moving repo from git to local repo
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9081_fmca_ebz_zcu102
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M_DEPS += timing_constr.xdc
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/data_offload_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
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M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
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M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_3w_spi.v
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M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += axi_tdd
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LIB_DEPS += data_offload
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/axi_jesd204_tx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += jesd204/jesd204_tx
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LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx
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LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_adcfifo
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LIB_DEPS += util_dacfifo
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LIB_DEPS += util_do_ram
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LIB_DEPS += util_hbm
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk
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@@ -0,0 +1,105 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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`timescale 1ns/100ps
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//
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// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves.
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// The expected transfer format is defined in ADI_SPI technical specification
|
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// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
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//
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// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the
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// instruction defines the direction of the SDIO during data transfer. (READ
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// is 1 and WRITE is 0)
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//
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||||
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module ad_3w_spi #(
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parameter NUM_OF_SLAVES = 8
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) (
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input [NUM_OF_SLAVES-1:0] spi_csn,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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inout spi_sdio,
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output spi_dir
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);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_dir = ~spi_enable_s;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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// io butter
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assign spi_miso = spi_sdio;
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assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
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endmodule
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@@ -0,0 +1,56 @@
|
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
|
||||
`timescale 1ns/100ps
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module ad_iobuf #(
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parameter DATA_WIDTH = 1
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) (
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input [(DATA_WIDTH-1):0] dio_t,
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input [(DATA_WIDTH-1):0] dio_i,
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output [(DATA_WIDTH-1):0] dio_o,
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inout [(DATA_WIDTH-1):0] dio_p
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);
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genvar n;
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generate
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
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assign dio_o[n] = dio_p[n];
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assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
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end
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endgenerate
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endmodule
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@@ -0,0 +1,93 @@
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###############################################################################
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||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
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||||
###############################################################################
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#
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## mxfe
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||||
#
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||||
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||||
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
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set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
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||||
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
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set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
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||||
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
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||||
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
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||||
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67
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||||
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67
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||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
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||||
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
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||||
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
|
||||
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
|
||||
set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229
|
||||
set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229
|
||||
set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66
|
||||
set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67
|
||||
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66
|
||||
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66
|
||||
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
|
||||
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
|
||||
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66
|
||||
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66
|
||||
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66
|
||||
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66
|
||||
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66
|
||||
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66
|
||||
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66
|
||||
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66
|
||||
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66
|
||||
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66
|
||||
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
|
||||
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
|
||||
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66
|
||||
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p]
|
||||
create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p]
|
||||
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
@@ -0,0 +1,34 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# constraints
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
|
||||
set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
|
||||
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
|
||||
set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4
|
||||
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6
|
||||
set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7
|
||||
|
||||
# Define SPI clock
|
||||
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
|
||||
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
|
||||
+2985
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,512 @@
|
||||
00000002
|
||||
00000010
|
||||
000001d0
|
||||
000001d8
|
||||
000001e0
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
63000000
|
||||
6e69616d
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
37656439
|
||||
30303939
|
||||
36643732
|
||||
38613839
|
||||
63653239
|
||||
62393030
|
||||
61333163
|
||||
34333835
|
||||
31326132
|
||||
39336363
|
||||
00000000
|
||||
00000074
|
||||
6a646176
|
||||
34313731
|
||||
31343537
|
||||
00003139
|
||||
00000000
|
||||
d0000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
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||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "afifo_32b_1024_pf512_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Independent_Clocks_Builtin_FIFO", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "511", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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||||
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|
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@@ -0,0 +1,467 @@
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{
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||||
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||||
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||||
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||||
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||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
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||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
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||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
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||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
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||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
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||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
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||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEMORY_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "992", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "991", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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File diff suppressed because it is too large
Load Diff
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"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "511", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,154 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 1 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 3 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
constant dds_command_set : dds_command_list(0 to 3) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"010624DD", --PHASE_INC (~1 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
1 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000050", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
2 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
x"00000050", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
-- x"000FFFFF", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
3 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000050", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
)
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
if (rst_in = '1') then
|
||||
cmd_idx_r <= 0;
|
||||
cmd_send_r <= '0';
|
||||
fifo_wr_en_r <= '0';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= IDLE;
|
||||
else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,365 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
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"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "aclken" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,419 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
holdoff_r <= holdoff_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,415 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_latency10
|
||||
port(
|
||||
-- ce : in std_logic;
|
||||
-- clk : in std_logic;
|
||||
-- sclr : in std_logic;
|
||||
-- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- rdy : out std_logic;
|
||||
-- cosine : out std_logic_vector(15 downto 0);
|
||||
-- sine : out std_logic_vector(15 downto 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0);
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0);
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0);
|
||||
signal phase_offset_r : std_logic_vector(31 downto 0);
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
phase_offset_r <= fifo_data_r(223 downto 192);
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
phase_inc_r1 <= phase_inc_r;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data(31 downto 0)
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,222 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_pulse_wrapper is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
|
||||
m_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m_axis_tvalid_out : out std_logic;
|
||||
m_axis_tready_in : in std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper;
|
||||
|
||||
architecture imp of dds_pulse_wrapper is
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001";
|
||||
|
||||
signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_r : std_logic := '0';
|
||||
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
signal cmd_idx : std_logic_vector( 1 downto 0) := "00";
|
||||
signal cmd_send : std_logic := '0';
|
||||
|
||||
signal mode : std_logic := '0';
|
||||
signal scale : std_logic_vector(15 downto 0) := x"0000";
|
||||
signal dac_holdoff : std_logic := '1';
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
reset_n <= not rst_in;
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_vio_0 : entity work.vio_0
|
||||
port map (
|
||||
clk => clk_in,
|
||||
probe_out0(0) => mode, -- 1
|
||||
probe_out1 => scale, -- 16
|
||||
probe_out2 => cmd_idx, -- 2
|
||||
probe_out3(0) => cmd_send -- 1
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => rst_in
|
||||
);
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => rst_in,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_dout,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
pulse_i <= dds_pulse_dout(15 downto 0);
|
||||
pulse_q <= dds_pulse_dout(31 downto 16);
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
dds_pulse_dval_r <= '0';
|
||||
|
||||
if (dds_pulse_dval_r = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (dds_pulse_dval = '1') then
|
||||
s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3);
|
||||
|
||||
if (s_axis_keep_r = "0001") then
|
||||
dds_pulse_data_r(31 downto 0) <= dds_pulse_dout;
|
||||
elsif (s_axis_keep_r = "0010") then
|
||||
dds_pulse_data_r(63 downto 32) <= dds_pulse_dout;
|
||||
elsif (s_axis_keep_r = "0100") then
|
||||
dds_pulse_data_r(95 downto 64) <= dds_pulse_dout;
|
||||
elsif (s_axis_keep_r = "1000") then
|
||||
dds_pulse_data_r(127 downto 96) <= dds_pulse_dout;
|
||||
dds_pulse_dval_r <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
i_fifo : entity work.axis_data_fifo_512x128
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk_in,
|
||||
s_axis_aresetn => reset_n,
|
||||
|
||||
s_axis_tdata => dds_pulse_data_r,
|
||||
s_axis_tvalid => dds_pulse_dval_r,
|
||||
s_axis_tready => open,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_out,
|
||||
m_axis_tvalid => m_axis_tvalid_out,
|
||||
m_axis_tready => m_axis_tready_in
|
||||
);
|
||||
|
||||
sim_true : if (SIM_ENABLED = TRUE) generate
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait until rising_edge(clk_in);
|
||||
wait for 1 ns;
|
||||
mode <= '0';
|
||||
scale <= x"8000";
|
||||
dac_holdoff <= '0';
|
||||
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(clk_in);
|
||||
--dac_holdoff <= '0';
|
||||
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "00";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "01";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "10";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 4
|
||||
-- CW TONE
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "11";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end generate sim_true;
|
||||
|
||||
end architecture imp;
|
||||
+168
@@ -0,0 +1,168 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mult_16signed_x_16unsigned_latency3",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../sweep.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OutputWidthHigh": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutputWidthLow": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PipeStages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ClockEnable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SyncClear": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_HIGH": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_LOW": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sweep.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"SCLR": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "SCLR" } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,467 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "sfifo_32b_1024_pf992_latency1",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../sweep.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Builtin_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "992", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "991", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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"RD_EN": [ { "physical_name": "rd_en" } ]
|
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}
|
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}
|
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}
|
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}
|
||||
}
|
||||
@@ -0,0 +1,357 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top #(
|
||||
parameter TX_JESD_L = 8,
|
||||
parameter TX_NUM_LINKS = 1,
|
||||
parameter RX_JESD_L = 8,
|
||||
parameter RX_NUM_LINKS = 1,
|
||||
parameter SHARED_DEVCLK = 0,
|
||||
parameter JESD_MODE = "8B10B"
|
||||
) (
|
||||
input [12:0] gpio_bd_i,
|
||||
output [ 7:0] gpio_bd_o,
|
||||
|
||||
// FMC HPC IOs
|
||||
input [1:0] agc0,
|
||||
input [1:0] agc1,
|
||||
input [1:0] agc2,
|
||||
input [1:0] agc3,
|
||||
input clkin6_n,
|
||||
input clkin6_p,
|
||||
input clkin10_n,
|
||||
input clkin10_p,
|
||||
input fpga_refclk_in_n,
|
||||
input fpga_refclk_in_p,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
||||
input fpga_syncin_0_n,
|
||||
input fpga_syncin_0_p,
|
||||
inout fpga_syncin_1_n,
|
||||
inout fpga_syncin_1_p,
|
||||
output fpga_syncout_0_n,
|
||||
output fpga_syncout_0_p,
|
||||
inout fpga_syncout_1_n,
|
||||
inout fpga_syncout_1_p,
|
||||
inout [10:0] gpio,
|
||||
inout hmc_gpio1,
|
||||
output hmc_sync,
|
||||
input [1:0] irqb,
|
||||
output rstb,
|
||||
output [1:0] rxen,
|
||||
output spi0_csb,
|
||||
input spi0_miso,
|
||||
output spi0_mosi,
|
||||
output spi0_sclk,
|
||||
output spi1_csb,
|
||||
output spi1_sclk,
|
||||
inout spi1_sdio,
|
||||
input sysref2_n,
|
||||
input sysref2_p,
|
||||
output [1:0] txen
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [94:0] gpio_i;
|
||||
wire [94:0] gpio_o;
|
||||
wire [94:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
|
||||
wire ref_clk;
|
||||
wire sysref;
|
||||
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
||||
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
||||
|
||||
wire [7:0] rx_data_p_loc;
|
||||
wire [7:0] rx_data_n_loc;
|
||||
wire [7:0] tx_data_p_loc;
|
||||
wire [7:0] tx_data_n_loc;
|
||||
|
||||
wire clkin6;
|
||||
wire clkin10;
|
||||
wire tx_device_clk;
|
||||
wire rx_device_clk_internal;
|
||||
wire rx_device_clk;
|
||||
|
||||
wire dac_rst;
|
||||
wire tx_device_clk_div4;
|
||||
|
||||
wire [127:0] s_axis_tx_data_0_tdata;
|
||||
wire s_axis_tx_data_0_tready;
|
||||
wire s_axis_tx_data_0_tvalid;
|
||||
|
||||
assign iic_rstn = 1'b1;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fpga_refclk_in_p),
|
||||
.IB (fpga_refclk_in_n),
|
||||
.O (ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_sysref (
|
||||
.I (sysref2_p),
|
||||
.IB (sysref2_n),
|
||||
.O (sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_device_clk (
|
||||
.I (clkin6_p),
|
||||
.IB (clkin6_n),
|
||||
.O (clkin6));
|
||||
|
||||
IBUFDS i_ibufds_rx_device_clk (
|
||||
.I (clkin10_p),
|
||||
.IB (clkin10_n),
|
||||
.O (clkin10));
|
||||
|
||||
IBUFDS i_ibufds_syncin_0 (
|
||||
.I (fpga_syncin_0_p),
|
||||
.IB (fpga_syncin_0_n),
|
||||
.O (tx_syncin[0]));
|
||||
|
||||
OBUFDS i_obufds_syncout_0 (
|
||||
.I (rx_syncout[0]),
|
||||
.O (fpga_syncout_0_p),
|
||||
.OB (fpga_syncout_0_n));
|
||||
|
||||
BUFG i_tx_device_clk (
|
||||
.I (clkin6),
|
||||
.O (tx_device_clk));
|
||||
|
||||
|
||||
BUFGCE_DIV #(
|
||||
.BUFGCE_DIVIDE(4), // 1-8
|
||||
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
|
||||
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
|
||||
.IS_I_INVERTED(1'b0) // Optional inversion for I
|
||||
)
|
||||
BUFGCE_DIV_inst (
|
||||
.O(tx_device_clk_div4), // 1-bit output: Buffer
|
||||
.CE(1'b1), // 1-bit input: Buffer enable
|
||||
.CLR(1'b0), // 1-bit input: Asynchronous clear
|
||||
.I(clkin6) // 1-bit input: Buffer
|
||||
);
|
||||
// E
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG i_rx_device_clk (
|
||||
.I (clkin10),
|
||||
.O (rx_device_clk_internal));
|
||||
|
||||
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
|
||||
|
||||
// spi
|
||||
|
||||
assign spi0_csb = spi0_csn[0];
|
||||
assign spi1_csb = spi1_csn[0];
|
||||
|
||||
ad_3w_spi #(
|
||||
.NUM_OF_SLAVES(1)
|
||||
) i_spi (
|
||||
.spi_csn (spi1_csn[0]),
|
||||
.spi_clk (spi1_sclk),
|
||||
.spi_mosi (spi1_mosi),
|
||||
.spi_miso (spi1_miso),
|
||||
.spi_sdio (spi1_sdio),
|
||||
.spi_dir ());
|
||||
|
||||
// gpios
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(12)
|
||||
) i_iobuf (
|
||||
.dio_t (gpio_t[43:32]),
|
||||
.dio_i (gpio_o[43:32]),
|
||||
.dio_o (gpio_i[43:32]),
|
||||
.dio_p ({hmc_gpio1, // 43
|
||||
gpio[10:0]})); // 42-32
|
||||
|
||||
assign gpio_i[44] = agc0[0];
|
||||
assign gpio_i[45] = agc0[1];
|
||||
assign gpio_i[46] = agc1[0];
|
||||
assign gpio_i[47] = agc1[1];
|
||||
assign gpio_i[48] = agc2[0];
|
||||
assign gpio_i[49] = agc2[1];
|
||||
assign gpio_i[50] = agc3[0];
|
||||
assign gpio_i[51] = agc3[1];
|
||||
assign gpio_i[52] = irqb[0];
|
||||
assign gpio_i[53] = irqb[1];
|
||||
|
||||
assign hmc_sync = gpio_o[54];
|
||||
assign rstb = gpio_o[55];
|
||||
assign rxen[0] = gpio_o[56];
|
||||
assign rxen[1] = gpio_o[57];
|
||||
assign txen[0] = gpio_o[58];
|
||||
assign txen[1] = gpio_o[59];
|
||||
|
||||
generate
|
||||
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign tx_syncin[1] = fpga_syncin_1_p;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncin_iobuf (
|
||||
.dio_t (gpio_t[61:60]),
|
||||
.dio_i (gpio_o[61:60]),
|
||||
.dio_o (gpio_i[61:60]),
|
||||
.dio_p ({fpga_syncin_1_n, // 61
|
||||
fpga_syncin_1_p})); // 60
|
||||
end
|
||||
|
||||
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign fpga_syncout_1_p = rx_syncout[1];
|
||||
assign fpga_syncout_1_n = 0;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncout_iobuf (
|
||||
.dio_t (gpio_t[63:62]),
|
||||
.dio_i (gpio_o[63:62]),
|
||||
.dio_o (gpio_i[63:62]),
|
||||
.dio_p ({fpga_syncout_1_n, // 63
|
||||
fpga_syncout_1_p})); // 62
|
||||
end
|
||||
endgenerate
|
||||
/* Board GPIOS. Buttons, LEDs, etc... */
|
||||
assign gpio_i[20: 8] = gpio_bd_i;
|
||||
assign gpio_bd_o = gpio_o[7:0];
|
||||
|
||||
// Unused GPIOs
|
||||
assign gpio_i[59:54] = gpio_o[59:54];
|
||||
assign gpio_i[94:64] = gpio_o[94:64];
|
||||
assign gpio_i[31:21] = gpio_o[31:21];
|
||||
assign gpio_i[7:0] = gpio_o[7:0];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.spi0_csn (spi0_csn),
|
||||
.spi0_miso (spi0_miso),
|
||||
.spi0_mosi (spi0_mosi),
|
||||
.spi0_sclk (spi0_sclk),
|
||||
.spi1_csn (spi1_csn),
|
||||
.spi1_miso (spi1_miso),
|
||||
.spi1_mosi (spi1_mosi),
|
||||
.spi1_sclk (spi1_sclk),
|
||||
// FMC HPC
|
||||
.rx_data_0_n (rx_data_n_loc[0]),
|
||||
.rx_data_0_p (rx_data_p_loc[0]),
|
||||
.rx_data_1_n (rx_data_n_loc[1]),
|
||||
.rx_data_1_p (rx_data_p_loc[1]),
|
||||
.rx_data_2_n (rx_data_n_loc[2]),
|
||||
.rx_data_2_p (rx_data_p_loc[2]),
|
||||
.rx_data_3_n (rx_data_n_loc[3]),
|
||||
.rx_data_3_p (rx_data_p_loc[3]),
|
||||
.rx_data_4_n (rx_data_n_loc[4]),
|
||||
.rx_data_4_p (rx_data_p_loc[4]),
|
||||
.rx_data_5_n (rx_data_n_loc[5]),
|
||||
.rx_data_5_p (rx_data_p_loc[5]),
|
||||
.rx_data_6_n (rx_data_n_loc[6]),
|
||||
.rx_data_6_p (rx_data_p_loc[6]),
|
||||
.rx_data_7_n (rx_data_n_loc[7]),
|
||||
.rx_data_7_p (rx_data_p_loc[7]),
|
||||
.tx_data_0_n (tx_data_n_loc[0]),
|
||||
.tx_data_0_p (tx_data_p_loc[0]),
|
||||
.tx_data_1_n (tx_data_n_loc[1]),
|
||||
.tx_data_1_p (tx_data_p_loc[1]),
|
||||
.tx_data_2_n (tx_data_n_loc[2]),
|
||||
.tx_data_2_p (tx_data_p_loc[2]),
|
||||
.tx_data_3_n (tx_data_n_loc[3]),
|
||||
.tx_data_3_p (tx_data_p_loc[3]),
|
||||
.tx_data_4_n (tx_data_n_loc[4]),
|
||||
.tx_data_4_p (tx_data_p_loc[4]),
|
||||
.tx_data_5_n (tx_data_n_loc[5]),
|
||||
.tx_data_5_p (tx_data_p_loc[5]),
|
||||
.tx_data_6_n (tx_data_n_loc[6]),
|
||||
.tx_data_6_p (tx_data_p_loc[6]),
|
||||
.tx_data_7_n (tx_data_n_loc[7]),
|
||||
.tx_data_7_p (tx_data_p_loc[7]),
|
||||
.ref_clk_q0 (ref_clk),
|
||||
.ref_clk_q1 (ref_clk),
|
||||
.rx_device_clk (rx_device_clk),
|
||||
.tx_device_clk (tx_device_clk),
|
||||
// .dac_rst_out (dac_rst),
|
||||
|
||||
// .s_axis_tx_data_0_tdata (s_axis_tx_data_0_tdata),
|
||||
// .s_axis_tx_data_0_tvalid (s_axis_tx_data_0_tvalid),
|
||||
// .s_axis_tx_data_0_tready (s_axis_tx_data_0_tready),
|
||||
|
||||
.clk_in_1 (tx_device_clk_div4),
|
||||
.rx_sync_0 (rx_syncout),
|
||||
.tx_sync_0 (tx_syncin),
|
||||
.rx_sysref_0 (sysref),
|
||||
.tx_sysref_0 (sysref));
|
||||
|
||||
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
|
||||
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
/*
|
||||
dds_pulse_wrapper i_dds_pulse_wrapper (
|
||||
.clk_in (tx_device_clk_div4),
|
||||
|
||||
.m_axis_aclk_in (tx_device_clk),
|
||||
|
||||
.m_axis_tdata_out (s_axis_tx_data_0_tdata),
|
||||
.m_axis_tvalid_out (s_axis_tx_data_0_tvalid),
|
||||
.m_axis_tready_in (s_axis_tx_data_0_tready),
|
||||
|
||||
.rst_in (dac_rst)
|
||||
);
|
||||
|
||||
*/
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
+2971
File diff suppressed because it is too large
Load Diff
+3018
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,610 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>dds_pulse_wrapper</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_out</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata_out</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid_out</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>dds_pulse_wrapper</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4288e600</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
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|
||||
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|
||||
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|
||||
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo</spirit:userFileType>
|
||||
</spirit:file>
|
||||
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|
||||
<spirit:name>src/ila_2/ila_2.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../ip/vio_0/vio_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
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<spirit:userFileType>CELL_NAME_sim_false.i_vio_0</spirit:userFileType>
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|
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<spirit:name>dds_cmd_gen.vhd</spirit:name>
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|
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|
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|
||||
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|
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<spirit:file>
|
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|
||||
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|
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|
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<spirit:file>
|
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<spirit:name>dds_pulse_wrapper.vhd</spirit:name>
|
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="fifo_generator" xilinx:version="13.2">
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:description>dds_pulse_wrapper_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>SIM_ENABLED</spirit:name>
|
||||
<spirit:displayName>Sim Enabled</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SIM_ENABLED">FALSE</spirit:value>
|
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dds_pulse_wrapper_v1_0</spirit:value>
|
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FPGA_REVISION_DATE</spirit:name>
|
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<spirit:displayName>Fpga Revision Date</spirit:displayName>
|
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<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_REVISION_DATE" spirit:bitStringLength="32">0x09162023</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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<xilinx:displayName>dds_pulse_wrapper_v1_0</xilinx:displayName>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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|
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<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
|
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<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
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<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
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<xilinx:tag xilinx:name="nopcore"/>
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|
||||
@@ -0,0 +1,205 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
vio_reserv1_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
vio_idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
vio_phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
vio_phase_off_in : in std_logic_vector(31 downto 0);
|
||||
vio_swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 4 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
signal dds_command_set : dds_command_list(0 to 4) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) = 68719 = 0x00010C6F
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
1 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
2 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
-- x"000FFFFF", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
3 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 4
|
||||
-- ??????
|
||||
4 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"00000000", --DDS_SAMPLES (~5 us)
|
||||
x"00000000", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
)
|
||||
);
|
||||
|
||||
|
||||
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
dds_command_set(4)(0) <= vio_reserv1_in;
|
||||
dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in;
|
||||
dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in;
|
||||
dds_command_set(4)(3) <= vio_idle_samples_in;
|
||||
dds_command_set(4)(4) <= vio_dds_samples_in;
|
||||
dds_command_set(4)(5) <= vio_phase_inc_in;
|
||||
dds_command_set(4)(6) <= vio_phase_off_in;
|
||||
dds_command_set(4)(7) <= vio_swap_sf_in;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
if (rst_in = '1') then
|
||||
cmd_idx_r <= 0;
|
||||
cmd_send_r <= '0';
|
||||
fifo_wr_en_r <= '0';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= IDLE;
|
||||
else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state_r <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = DONE else
|
||||
"11";
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_1 : entity work.ila_2
|
||||
port map (
|
||||
clk => clk_in,
|
||||
probe0 => test_state_r, -- 2
|
||||
probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
|
||||
probe2 => fifo_wr_data_r, -- 32
|
||||
probe3(0) => fifo_wr_en_r, -- 1
|
||||
probe4(0) => cmd_send_in, -- 1
|
||||
probe5(0) => cmd_send_r -- 1
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,419 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
holdoff_r <= holdoff_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,415 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_latency10
|
||||
port(
|
||||
-- ce : in std_logic;
|
||||
-- clk : in std_logic;
|
||||
-- sclr : in std_logic;
|
||||
-- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- rdy : out std_logic;
|
||||
-- cosine : out std_logic_vector(15 downto 0);
|
||||
-- sine : out std_logic_vector(15 downto 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0);
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0);
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0);
|
||||
signal phase_offset_r : std_logic_vector(31 downto 0);
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
phase_offset_r <= fifo_data_r(223 downto 192);
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
phase_inc_r1 <= phase_inc_r;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data(31 downto 0)
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,346 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_pulse_wrapper is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE;
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0916_2023"
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
|
||||
m_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m_axis_tvalid_out : out std_logic;
|
||||
m_axis_tready_in : in std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper;
|
||||
|
||||
architecture imp of dds_pulse_wrapper is
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001";
|
||||
signal s_axis_tready : std_logic;
|
||||
|
||||
signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_r : std_logic := '0';
|
||||
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_cnt_r1 : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0) := "000";
|
||||
signal cmd_send : std_logic := '0';
|
||||
|
||||
signal mode : std_logic := '0';
|
||||
signal scale : std_logic_vector(15 downto 0) := x"0000";
|
||||
signal dac_holdoff : std_logic := '1';
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
signal m_axis_tdata : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid : std_logic;
|
||||
|
||||
signal pulse_data_word : std_logic_vector(127 downto 0);
|
||||
|
||||
signal vio_reserv1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_idle_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_dds_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_phase_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_phase_off : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal vio_swap_sf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
reset_n <= not rst_in;
|
||||
|
||||
-- process(clk_in)
|
||||
-- begin
|
||||
-- if (rising_edge(clk_in)) then
|
||||
-- fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_vio_0 : entity work.vio_0
|
||||
port map (
|
||||
clk => clk_in,
|
||||
-- probe_in0 => fpga_revison_r, -- 32
|
||||
|
||||
probe_out0(0) => mode, -- 1
|
||||
probe_out1 => scale, -- 16
|
||||
probe_out2 => cmd_idx, -- 3
|
||||
probe_out3(0) => cmd_send, -- 1
|
||||
probe_out4(0) => dac_holdoff, -- 1
|
||||
|
||||
probe_out5 => vio_reserv1, -- 32
|
||||
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
|
||||
probe_out7 => vio_dds_phase_inc_step_size, -- 32
|
||||
probe_out8 => vio_idle_samples, -- 32
|
||||
probe_out9 => vio_dds_samples, -- 32
|
||||
probe_out10 => vio_phase_inc, -- 32
|
||||
probe_out11 => vio_phase_off, -- 32
|
||||
probe_out12 => vio_swap_sf -- 32
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
generic map (
|
||||
SIM_ENABLED => SIM_ENABLED
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
vio_reserv1_in => vio_reserv1,
|
||||
vio_dds_phase_inc_dwell_time_in => vio_dds_phase_inc_dwell_time,
|
||||
vio_dds_phase_inc_step_size_in => vio_dds_phase_inc_step_size,
|
||||
vio_idle_samples_in => vio_idle_samples,
|
||||
vio_dds_samples_in => vio_dds_samples,
|
||||
vio_phase_inc_in => vio_phase_inc,
|
||||
vio_phase_off_in => vio_phase_off,
|
||||
vio_swap_sf_in => vio_swap_sf,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => rst_in
|
||||
);
|
||||
|
||||
sim_false1 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_4 : entity work.ila_4
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
);
|
||||
end generate sim_false1;
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => rst_in,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
pulse_i <= dds_pulse_data(15 downto 0);
|
||||
pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
dds_pulse_dval_r <= dds_pulse_dval;
|
||||
|
||||
if (dds_pulse_dval_r = '1' and dds_pulse_dval = '0') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
dds_pulse_data_cnt_r1 <= dds_pulse_data_cnt_r;
|
||||
elsif (dds_pulse_dval = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3);
|
||||
--
|
||||
-- if (s_axis_keep_r = "0001") then
|
||||
-- dds_pulse_data_r(31 downto 0) <= dds_pulse_data;
|
||||
-- elsif (s_axis_keep_r = "0010") then
|
||||
-- dds_pulse_data_r(63 downto 32) <= dds_pulse_data;
|
||||
-- elsif (s_axis_keep_r = "0100") then
|
||||
-- dds_pulse_data_r(95 downto 64) <= dds_pulse_data;
|
||||
-- elsif (s_axis_keep_r = "1000") then
|
||||
-- dds_pulse_data_r(127 downto 96) <= dds_pulse_data;
|
||||
-- dds_pulse_dval_r <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse_data_word <= dds_pulse_data & dds_pulse_data & dds_pulse_data & dds_pulse_data;
|
||||
|
||||
|
||||
sim_false2 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_3 : entity work.ila_3
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => dds_pulse_data(15 downto 0),
|
||||
probe1 => dds_pulse_data(31 downto 16),
|
||||
probe2(0) => dds_pulse_dval,
|
||||
probe3(0) => s_axis_tready
|
||||
);
|
||||
end generate sim_false2;
|
||||
|
||||
i_fifo : entity work.axis_data_fifo_512x128
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk_in,
|
||||
s_axis_aresetn => reset_n,
|
||||
|
||||
s_axis_tdata => pulse_data_word,
|
||||
s_axis_tvalid => dds_pulse_dval,
|
||||
s_axis_tready => s_axis_tready,
|
||||
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tready => m_axis_tready_in
|
||||
);
|
||||
|
||||
m_axis_tdata_out <= m_axis_tdata;
|
||||
m_axis_tvalid_out <= m_axis_tvalid;
|
||||
|
||||
sim_false3 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_2 : entity work.ila_0
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => m_axis_tdata(15 downto 0),
|
||||
probe1 => m_axis_tdata(31 downto 16),
|
||||
probe2 => m_axis_tdata(47 downto 32),
|
||||
probe3 => m_axis_tdata(63 downto 48),
|
||||
probe4 => m_axis_tdata(79 downto 64),
|
||||
probe5 => m_axis_tdata(95 downto 80),
|
||||
probe6 => m_axis_tdata(111 downto 96),
|
||||
probe7 => m_axis_tdata(127 downto 112),
|
||||
probe8(0) => m_axis_tvalid,
|
||||
probe9(0) => m_axis_tready_in
|
||||
);
|
||||
end generate sim_false3;
|
||||
|
||||
sim_true : if (SIM_ENABLED = TRUE) generate
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait until rising_edge(clk_in);
|
||||
wait for 1 ns;
|
||||
mode <= '0';
|
||||
scale <= x"8000";
|
||||
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(clk_in);
|
||||
-- dac_holdoff <= '0';
|
||||
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "000";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "000";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_idx <= "000";
|
||||
cmd_send <= '1';
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
wait until rising_edge(clk_in);
|
||||
cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- cmd_idx <= "011";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
-- wait for 100 ns;
|
||||
-- CW TONE
|
||||
-- vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
|
||||
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
|
||||
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
|
||||
-- vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- cmd_idx <= "100";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- wait until rising_edge(clk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for 5 us;
|
||||
dac_holdoff <= '0';
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end generate sim_true;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,227 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "adder_16signed_16signed_latency2",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ],
|
||||
"Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Add_Mode": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
|
||||
"Out_Width": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
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||||
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||||
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||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_RD_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "rd_clk" } ]
|
||||
}
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
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|
||||
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|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
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|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,365 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
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||||
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||||
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}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+168
@@ -0,0 +1,168 @@
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|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "SCLR" } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,467 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "sfifo_32b_1024_pf992_latency1",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../sweep.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Builtin_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "992", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "991", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
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||||
"C_PRIM_FIFO_TYPE_WDCH": [ { "value": "512x72", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_WRCH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_RACH": [ { "value": "512x36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_RDCH": [ { "value": "512x72", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE_AXIS": [ { "value": "1kx18", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ECC_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WACH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_WRCH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_RACH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_RDCH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DIN_WIDTH_AXIS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_WRCH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_RACH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_RDCH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../sweep.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"srst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"din": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"overflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"underflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"prog_full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"core_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,357 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top #(
|
||||
parameter TX_JESD_L = 8,
|
||||
parameter TX_NUM_LINKS = 1,
|
||||
parameter RX_JESD_L = 8,
|
||||
parameter RX_NUM_LINKS = 1,
|
||||
parameter SHARED_DEVCLK = 0,
|
||||
parameter JESD_MODE = "8B10B"
|
||||
) (
|
||||
input [12:0] gpio_bd_i,
|
||||
output [ 7:0] gpio_bd_o,
|
||||
|
||||
// FMC HPC IOs
|
||||
input [1:0] agc0,
|
||||
input [1:0] agc1,
|
||||
input [1:0] agc2,
|
||||
input [1:0] agc3,
|
||||
input clkin6_n,
|
||||
input clkin6_p,
|
||||
input clkin10_n,
|
||||
input clkin10_p,
|
||||
input fpga_refclk_in_n,
|
||||
input fpga_refclk_in_p,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
||||
input fpga_syncin_0_n,
|
||||
input fpga_syncin_0_p,
|
||||
inout fpga_syncin_1_n,
|
||||
inout fpga_syncin_1_p,
|
||||
output fpga_syncout_0_n,
|
||||
output fpga_syncout_0_p,
|
||||
inout fpga_syncout_1_n,
|
||||
inout fpga_syncout_1_p,
|
||||
inout [10:0] gpio,
|
||||
inout hmc_gpio1,
|
||||
output hmc_sync,
|
||||
input [1:0] irqb,
|
||||
output rstb,
|
||||
output [1:0] rxen,
|
||||
output spi0_csb,
|
||||
input spi0_miso,
|
||||
output spi0_mosi,
|
||||
output spi0_sclk,
|
||||
output spi1_csb,
|
||||
output spi1_sclk,
|
||||
inout spi1_sdio,
|
||||
input sysref2_n,
|
||||
input sysref2_p,
|
||||
output [1:0] txen
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [94:0] gpio_i;
|
||||
wire [94:0] gpio_o;
|
||||
wire [94:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
|
||||
wire ref_clk;
|
||||
wire sysref;
|
||||
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
||||
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
||||
|
||||
wire [7:0] rx_data_p_loc;
|
||||
wire [7:0] rx_data_n_loc;
|
||||
wire [7:0] tx_data_p_loc;
|
||||
wire [7:0] tx_data_n_loc;
|
||||
|
||||
wire clkin6;
|
||||
wire clkin10;
|
||||
wire tx_device_clk;
|
||||
wire rx_device_clk_internal;
|
||||
wire rx_device_clk;
|
||||
|
||||
wire dac_rst;
|
||||
wire tx_device_clk_div4;
|
||||
|
||||
wire [127:0] s_axis_tx_data_0_tdata;
|
||||
wire s_axis_tx_data_0_tready;
|
||||
wire s_axis_tx_data_0_tvalid;
|
||||
|
||||
assign iic_rstn = 1'b1;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fpga_refclk_in_p),
|
||||
.IB (fpga_refclk_in_n),
|
||||
.O (ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_sysref (
|
||||
.I (sysref2_p),
|
||||
.IB (sysref2_n),
|
||||
.O (sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_device_clk (
|
||||
.I (clkin6_p),
|
||||
.IB (clkin6_n),
|
||||
.O (clkin6));
|
||||
|
||||
IBUFDS i_ibufds_rx_device_clk (
|
||||
.I (clkin10_p),
|
||||
.IB (clkin10_n),
|
||||
.O (clkin10));
|
||||
|
||||
IBUFDS i_ibufds_syncin_0 (
|
||||
.I (fpga_syncin_0_p),
|
||||
.IB (fpga_syncin_0_n),
|
||||
.O (tx_syncin[0]));
|
||||
|
||||
OBUFDS i_obufds_syncout_0 (
|
||||
.I (rx_syncout[0]),
|
||||
.O (fpga_syncout_0_p),
|
||||
.OB (fpga_syncout_0_n));
|
||||
|
||||
BUFG i_tx_device_clk (
|
||||
.I (clkin6),
|
||||
.O (tx_device_clk));
|
||||
|
||||
|
||||
BUFGCE_DIV #(
|
||||
.BUFGCE_DIVIDE(4), // 1-8
|
||||
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
|
||||
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
|
||||
.IS_I_INVERTED(1'b0) // Optional inversion for I
|
||||
)
|
||||
BUFGCE_DIV_inst (
|
||||
.O(tx_device_clk_div4), // 1-bit output: Buffer
|
||||
.CE(1'b1), // 1-bit input: Buffer enable
|
||||
.CLR(1'b0), // 1-bit input: Asynchronous clear
|
||||
.I(clkin6) // 1-bit input: Buffer
|
||||
);
|
||||
// E
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG i_rx_device_clk (
|
||||
.I (clkin10),
|
||||
.O (rx_device_clk_internal));
|
||||
|
||||
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
|
||||
|
||||
// spi
|
||||
|
||||
assign spi0_csb = spi0_csn[0];
|
||||
assign spi1_csb = spi1_csn[0];
|
||||
|
||||
ad_3w_spi #(
|
||||
.NUM_OF_SLAVES(1)
|
||||
) i_spi (
|
||||
.spi_csn (spi1_csn[0]),
|
||||
.spi_clk (spi1_sclk),
|
||||
.spi_mosi (spi1_mosi),
|
||||
.spi_miso (spi1_miso),
|
||||
.spi_sdio (spi1_sdio),
|
||||
.spi_dir ());
|
||||
|
||||
// gpios
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(12)
|
||||
) i_iobuf (
|
||||
.dio_t (gpio_t[43:32]),
|
||||
.dio_i (gpio_o[43:32]),
|
||||
.dio_o (gpio_i[43:32]),
|
||||
.dio_p ({hmc_gpio1, // 43
|
||||
gpio[10:0]})); // 42-32
|
||||
|
||||
assign gpio_i[44] = agc0[0];
|
||||
assign gpio_i[45] = agc0[1];
|
||||
assign gpio_i[46] = agc1[0];
|
||||
assign gpio_i[47] = agc1[1];
|
||||
assign gpio_i[48] = agc2[0];
|
||||
assign gpio_i[49] = agc2[1];
|
||||
assign gpio_i[50] = agc3[0];
|
||||
assign gpio_i[51] = agc3[1];
|
||||
assign gpio_i[52] = irqb[0];
|
||||
assign gpio_i[53] = irqb[1];
|
||||
|
||||
assign hmc_sync = gpio_o[54];
|
||||
assign rstb = gpio_o[55];
|
||||
assign rxen[0] = gpio_o[56];
|
||||
assign rxen[1] = gpio_o[57];
|
||||
assign txen[0] = gpio_o[58];
|
||||
assign txen[1] = gpio_o[59];
|
||||
|
||||
generate
|
||||
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign tx_syncin[1] = fpga_syncin_1_p;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncin_iobuf (
|
||||
.dio_t (gpio_t[61:60]),
|
||||
.dio_i (gpio_o[61:60]),
|
||||
.dio_o (gpio_i[61:60]),
|
||||
.dio_p ({fpga_syncin_1_n, // 61
|
||||
fpga_syncin_1_p})); // 60
|
||||
end
|
||||
|
||||
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign fpga_syncout_1_p = rx_syncout[1];
|
||||
assign fpga_syncout_1_n = 0;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncout_iobuf (
|
||||
.dio_t (gpio_t[63:62]),
|
||||
.dio_i (gpio_o[63:62]),
|
||||
.dio_o (gpio_i[63:62]),
|
||||
.dio_p ({fpga_syncout_1_n, // 63
|
||||
fpga_syncout_1_p})); // 62
|
||||
end
|
||||
endgenerate
|
||||
/* Board GPIOS. Buttons, LEDs, etc... */
|
||||
assign gpio_i[20: 8] = gpio_bd_i;
|
||||
assign gpio_bd_o = gpio_o[7:0];
|
||||
|
||||
// Unused GPIOs
|
||||
assign gpio_i[59:54] = gpio_o[59:54];
|
||||
assign gpio_i[94:64] = gpio_o[94:64];
|
||||
assign gpio_i[31:21] = gpio_o[31:21];
|
||||
assign gpio_i[7:0] = gpio_o[7:0];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.spi0_csn (spi0_csn),
|
||||
.spi0_miso (spi0_miso),
|
||||
.spi0_mosi (spi0_mosi),
|
||||
.spi0_sclk (spi0_sclk),
|
||||
.spi1_csn (spi1_csn),
|
||||
.spi1_miso (spi1_miso),
|
||||
.spi1_mosi (spi1_mosi),
|
||||
.spi1_sclk (spi1_sclk),
|
||||
// FMC HPC
|
||||
.rx_data_0_n (rx_data_n_loc[0]),
|
||||
.rx_data_0_p (rx_data_p_loc[0]),
|
||||
.rx_data_1_n (rx_data_n_loc[1]),
|
||||
.rx_data_1_p (rx_data_p_loc[1]),
|
||||
.rx_data_2_n (rx_data_n_loc[2]),
|
||||
.rx_data_2_p (rx_data_p_loc[2]),
|
||||
.rx_data_3_n (rx_data_n_loc[3]),
|
||||
.rx_data_3_p (rx_data_p_loc[3]),
|
||||
.rx_data_4_n (rx_data_n_loc[4]),
|
||||
.rx_data_4_p (rx_data_p_loc[4]),
|
||||
.rx_data_5_n (rx_data_n_loc[5]),
|
||||
.rx_data_5_p (rx_data_p_loc[5]),
|
||||
.rx_data_6_n (rx_data_n_loc[6]),
|
||||
.rx_data_6_p (rx_data_p_loc[6]),
|
||||
.rx_data_7_n (rx_data_n_loc[7]),
|
||||
.rx_data_7_p (rx_data_p_loc[7]),
|
||||
.tx_data_0_n (tx_data_n_loc[0]),
|
||||
.tx_data_0_p (tx_data_p_loc[0]),
|
||||
.tx_data_1_n (tx_data_n_loc[1]),
|
||||
.tx_data_1_p (tx_data_p_loc[1]),
|
||||
.tx_data_2_n (tx_data_n_loc[2]),
|
||||
.tx_data_2_p (tx_data_p_loc[2]),
|
||||
.tx_data_3_n (tx_data_n_loc[3]),
|
||||
.tx_data_3_p (tx_data_p_loc[3]),
|
||||
.tx_data_4_n (tx_data_n_loc[4]),
|
||||
.tx_data_4_p (tx_data_p_loc[4]),
|
||||
.tx_data_5_n (tx_data_n_loc[5]),
|
||||
.tx_data_5_p (tx_data_p_loc[5]),
|
||||
.tx_data_6_n (tx_data_n_loc[6]),
|
||||
.tx_data_6_p (tx_data_p_loc[6]),
|
||||
.tx_data_7_n (tx_data_n_loc[7]),
|
||||
.tx_data_7_p (tx_data_p_loc[7]),
|
||||
.ref_clk_q0 (ref_clk),
|
||||
.ref_clk_q1 (ref_clk),
|
||||
.rx_device_clk (rx_device_clk),
|
||||
.tx_device_clk (tx_device_clk),
|
||||
// .dac_rst_out (dac_rst),
|
||||
|
||||
// .s_axis_tx_data_0_tdata (s_axis_tx_data_0_tdata),
|
||||
// .s_axis_tx_data_0_tvalid (s_axis_tx_data_0_tvalid),
|
||||
// .s_axis_tx_data_0_tready (s_axis_tx_data_0_tready),
|
||||
|
||||
.clk_in_1 (tx_device_clk_div4),
|
||||
.rx_sync_0 (rx_syncout),
|
||||
.tx_sync_0 (tx_syncin),
|
||||
.rx_sysref_0 (sysref),
|
||||
.tx_sysref_0 (sysref));
|
||||
|
||||
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
|
||||
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
/*
|
||||
dds_pulse_wrapper i_dds_pulse_wrapper (
|
||||
.clk_in (tx_device_clk_div4),
|
||||
|
||||
.m_axis_aclk_in (tx_device_clk),
|
||||
|
||||
.m_axis_tdata_out (s_axis_tx_data_0_tdata),
|
||||
.m_axis_tvalid_out (s_axis_tx_data_0_tvalid),
|
||||
.m_axis_tready_in (s_axis_tx_data_0_tready),
|
||||
|
||||
.rst_in (dac_rst)
|
||||
);
|
||||
|
||||
*/
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "SIM_ENABLED" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to update SIM_ENABLED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to validate SIM_ENABLED
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.SIM_ENABLED { MODELPARAM_VALUE.SIM_ENABLED PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SIM_ENABLED}] ${MODELPARAM_VALUE.SIM_ENABLED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
## ADC FIFO depth in samples per converter
|
||||
set adc_fifo_samples_per_converter [expr 64*1024]
|
||||
## DAC FIFO depth in samples per converter
|
||||
set dac_fifo_samples_per_converter [expr 64*1024]
|
||||
|
||||
|
||||
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||
|
||||
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
|
||||
|
||||
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
|
||||
|
||||
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
|
||||
|
||||
#system ID
|
||||
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
|
||||
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
|
||||
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
|
||||
|
||||
sysid_gen_sys_init_file
|
||||
|
||||
# Parameters for 15.5Gpbs lane rate
|
||||
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3
|
||||
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF
|
||||
|
||||
# Overwrite parameter for lower lane rates which use CPLL
|
||||
if {$ad_project_params(RX_LANE_RATE) < 12} {
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x0
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x200
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0xFD
|
||||
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x12
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12
|
||||
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
|
||||
}
|
||||
|
||||
@@ -0,0 +1,93 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
#
|
||||
## mxfe
|
||||
#
|
||||
|
||||
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
|
||||
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
|
||||
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
|
||||
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
|
||||
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
|
||||
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
|
||||
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67
|
||||
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67
|
||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
|
||||
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
|
||||
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
|
||||
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
|
||||
set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229
|
||||
set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229
|
||||
set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66
|
||||
set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67
|
||||
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66
|
||||
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66
|
||||
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
|
||||
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
|
||||
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66
|
||||
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66
|
||||
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66
|
||||
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66
|
||||
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66
|
||||
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66
|
||||
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66
|
||||
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66
|
||||
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66
|
||||
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66
|
||||
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
|
||||
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
|
||||
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66
|
||||
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
# get_env_param retrieves parameter value from the environment if exists,
|
||||
# other case use the default value
|
||||
#
|
||||
# Use over-writable parameters from the environment.
|
||||
#
|
||||
# e.g.
|
||||
# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
|
||||
# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
|
||||
|
||||
#
|
||||
# Parameter description:
|
||||
# JESD_MODE : Used link layer encoder mode
|
||||
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
|
||||
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
|
||||
#
|
||||
# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA )
|
||||
# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE )
|
||||
# [RX/TX]_JESD_M : Number of converters per link
|
||||
# [RX/TX]_JESD_L : Number of lanes per link
|
||||
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
|
||||
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
|
||||
#
|
||||
|
||||
adi_project ad9081_fmca_ebz_zcu102 0 [list \
|
||||
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
|
||||
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
|
||||
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \
|
||||
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
|
||||
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
|
||||
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
|
||||
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
|
||||
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
|
||||
RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \
|
||||
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
|
||||
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
|
||||
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
|
||||
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
|
||||
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
|
||||
TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \
|
||||
TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \
|
||||
SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \
|
||||
TDD_CHANNEL_CNT [get_env_param TDD_CHANNEL_CNT 2 ] \
|
||||
TDD_SYNC_WIDTH [get_env_param TDD_SYNC_WIDTH 32 ] \
|
||||
TDD_SYNC_INT [get_env_param TDD_SYNC_INT 1 ] \
|
||||
TDD_SYNC_EXT [get_env_param TDD_SYNC_EXT 0 ] \
|
||||
TDD_SYNC_EXT_CDC [get_env_param TDD_SYNC_EXT_CDC 0 ] \
|
||||
]
|
||||
|
||||
adi_project_files ad9081_fmca_ebz_zcu102 [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"timing_constr.xdc"\
|
||||
"../../../library/common/ad_3w_spi.v"\
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
|
||||
|
||||
|
||||
adi_project_run ad9081_fmca_ebz_zcu102
|
||||
|
||||
+305
@@ -0,0 +1,305 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top #(
|
||||
parameter TX_JESD_L = 8,
|
||||
parameter TX_NUM_LINKS = 1,
|
||||
parameter RX_JESD_L = 8,
|
||||
parameter RX_NUM_LINKS = 1,
|
||||
parameter SHARED_DEVCLK = 0,
|
||||
parameter JESD_MODE = "8B10B"
|
||||
) (
|
||||
input [12:0] gpio_bd_i,
|
||||
output [ 7:0] gpio_bd_o,
|
||||
|
||||
// FMC HPC IOs
|
||||
input [1:0] agc0,
|
||||
input [1:0] agc1,
|
||||
input [1:0] agc2,
|
||||
input [1:0] agc3,
|
||||
input clkin6_n,
|
||||
input clkin6_p,
|
||||
input clkin10_n,
|
||||
input clkin10_p,
|
||||
input fpga_refclk_in_n,
|
||||
input fpga_refclk_in_p,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
||||
input fpga_syncin_0_n,
|
||||
input fpga_syncin_0_p,
|
||||
inout fpga_syncin_1_n,
|
||||
inout fpga_syncin_1_p,
|
||||
output fpga_syncout_0_n,
|
||||
output fpga_syncout_0_p,
|
||||
inout fpga_syncout_1_n,
|
||||
inout fpga_syncout_1_p,
|
||||
inout [10:0] gpio,
|
||||
inout hmc_gpio1,
|
||||
output hmc_sync,
|
||||
input [1:0] irqb,
|
||||
output rstb,
|
||||
output [1:0] rxen,
|
||||
output spi0_csb,
|
||||
input spi0_miso,
|
||||
output spi0_mosi,
|
||||
output spi0_sclk,
|
||||
output spi1_csb,
|
||||
output spi1_sclk,
|
||||
inout spi1_sdio,
|
||||
input sysref2_n,
|
||||
input sysref2_p,
|
||||
output [1:0] txen
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [94:0] gpio_i;
|
||||
wire [94:0] gpio_o;
|
||||
wire [94:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
|
||||
wire ref_clk;
|
||||
wire sysref;
|
||||
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
||||
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
||||
|
||||
wire [7:0] rx_data_p_loc;
|
||||
wire [7:0] rx_data_n_loc;
|
||||
wire [7:0] tx_data_p_loc;
|
||||
wire [7:0] tx_data_n_loc;
|
||||
|
||||
wire clkin6;
|
||||
wire clkin10;
|
||||
wire tx_device_clk;
|
||||
wire rx_device_clk_internal;
|
||||
wire rx_device_clk;
|
||||
|
||||
assign iic_rstn = 1'b1;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fpga_refclk_in_p),
|
||||
.IB (fpga_refclk_in_n),
|
||||
.O (ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_sysref (
|
||||
.I (sysref2_p),
|
||||
.IB (sysref2_n),
|
||||
.O (sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_device_clk (
|
||||
.I (clkin6_p),
|
||||
.IB (clkin6_n),
|
||||
.O (clkin6));
|
||||
|
||||
IBUFDS i_ibufds_rx_device_clk (
|
||||
.I (clkin10_p),
|
||||
.IB (clkin10_n),
|
||||
.O (clkin10));
|
||||
|
||||
IBUFDS i_ibufds_syncin_0 (
|
||||
.I (fpga_syncin_0_p),
|
||||
.IB (fpga_syncin_0_n),
|
||||
.O (tx_syncin[0]));
|
||||
|
||||
OBUFDS i_obufds_syncout_0 (
|
||||
.I (rx_syncout[0]),
|
||||
.O (fpga_syncout_0_p),
|
||||
.OB (fpga_syncout_0_n));
|
||||
|
||||
BUFG i_tx_device_clk (
|
||||
.I (clkin6),
|
||||
.O (tx_device_clk));
|
||||
|
||||
BUFG i_rx_device_clk (
|
||||
.I (clkin10),
|
||||
.O (rx_device_clk_internal));
|
||||
|
||||
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
|
||||
|
||||
// spi
|
||||
|
||||
assign spi0_csb = spi0_csn[0];
|
||||
assign spi1_csb = spi1_csn[0];
|
||||
|
||||
ad_3w_spi #(
|
||||
.NUM_OF_SLAVES(1)
|
||||
) i_spi (
|
||||
.spi_csn (spi1_csn[0]),
|
||||
.spi_clk (spi1_sclk),
|
||||
.spi_mosi (spi1_mosi),
|
||||
.spi_miso (spi1_miso),
|
||||
.spi_sdio (spi1_sdio),
|
||||
.spi_dir ());
|
||||
|
||||
// gpios
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(12)
|
||||
) i_iobuf (
|
||||
.dio_t (gpio_t[43:32]),
|
||||
.dio_i (gpio_o[43:32]),
|
||||
.dio_o (gpio_i[43:32]),
|
||||
.dio_p ({hmc_gpio1, // 43
|
||||
gpio[10:0]})); // 42-32
|
||||
|
||||
assign gpio_i[44] = agc0[0];
|
||||
assign gpio_i[45] = agc0[1];
|
||||
assign gpio_i[46] = agc1[0];
|
||||
assign gpio_i[47] = agc1[1];
|
||||
assign gpio_i[48] = agc2[0];
|
||||
assign gpio_i[49] = agc2[1];
|
||||
assign gpio_i[50] = agc3[0];
|
||||
assign gpio_i[51] = agc3[1];
|
||||
assign gpio_i[52] = irqb[0];
|
||||
assign gpio_i[53] = irqb[1];
|
||||
|
||||
assign hmc_sync = gpio_o[54];
|
||||
assign rstb = gpio_o[55];
|
||||
assign rxen[0] = gpio_o[56];
|
||||
assign rxen[1] = gpio_o[57];
|
||||
assign txen[0] = gpio_o[58];
|
||||
assign txen[1] = gpio_o[59];
|
||||
|
||||
generate
|
||||
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign tx_syncin[1] = fpga_syncin_1_p;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncin_iobuf (
|
||||
.dio_t (gpio_t[61:60]),
|
||||
.dio_i (gpio_o[61:60]),
|
||||
.dio_o (gpio_i[61:60]),
|
||||
.dio_p ({fpga_syncin_1_n, // 61
|
||||
fpga_syncin_1_p})); // 60
|
||||
end
|
||||
|
||||
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign fpga_syncout_1_p = rx_syncout[1];
|
||||
assign fpga_syncout_1_n = 0;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncout_iobuf (
|
||||
.dio_t (gpio_t[63:62]),
|
||||
.dio_i (gpio_o[63:62]),
|
||||
.dio_o (gpio_i[63:62]),
|
||||
.dio_p ({fpga_syncout_1_n, // 63
|
||||
fpga_syncout_1_p})); // 62
|
||||
end
|
||||
endgenerate
|
||||
/* Board GPIOS. Buttons, LEDs, etc... */
|
||||
assign gpio_i[20: 8] = gpio_bd_i;
|
||||
assign gpio_bd_o = gpio_o[7:0];
|
||||
|
||||
// Unused GPIOs
|
||||
assign gpio_i[59:54] = gpio_o[59:54];
|
||||
assign gpio_i[94:64] = gpio_o[94:64];
|
||||
assign gpio_i[31:21] = gpio_o[31:21];
|
||||
assign gpio_i[7:0] = gpio_o[7:0];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.spi0_csn (spi0_csn),
|
||||
.spi0_miso (spi0_miso),
|
||||
.spi0_mosi (spi0_mosi),
|
||||
.spi0_sclk (spi0_sclk),
|
||||
.spi1_csn (spi1_csn),
|
||||
.spi1_miso (spi1_miso),
|
||||
.spi1_mosi (spi1_mosi),
|
||||
.spi1_sclk (spi1_sclk),
|
||||
// FMC HPC
|
||||
.rx_data_0_n (rx_data_n_loc[0]),
|
||||
.rx_data_0_p (rx_data_p_loc[0]),
|
||||
.rx_data_1_n (rx_data_n_loc[1]),
|
||||
.rx_data_1_p (rx_data_p_loc[1]),
|
||||
.rx_data_2_n (rx_data_n_loc[2]),
|
||||
.rx_data_2_p (rx_data_p_loc[2]),
|
||||
.rx_data_3_n (rx_data_n_loc[3]),
|
||||
.rx_data_3_p (rx_data_p_loc[3]),
|
||||
.rx_data_4_n (rx_data_n_loc[4]),
|
||||
.rx_data_4_p (rx_data_p_loc[4]),
|
||||
.rx_data_5_n (rx_data_n_loc[5]),
|
||||
.rx_data_5_p (rx_data_p_loc[5]),
|
||||
.rx_data_6_n (rx_data_n_loc[6]),
|
||||
.rx_data_6_p (rx_data_p_loc[6]),
|
||||
.rx_data_7_n (rx_data_n_loc[7]),
|
||||
.rx_data_7_p (rx_data_p_loc[7]),
|
||||
.tx_data_0_n (tx_data_n_loc[0]),
|
||||
.tx_data_0_p (tx_data_p_loc[0]),
|
||||
.tx_data_1_n (tx_data_n_loc[1]),
|
||||
.tx_data_1_p (tx_data_p_loc[1]),
|
||||
.tx_data_2_n (tx_data_n_loc[2]),
|
||||
.tx_data_2_p (tx_data_p_loc[2]),
|
||||
.tx_data_3_n (tx_data_n_loc[3]),
|
||||
.tx_data_3_p (tx_data_p_loc[3]),
|
||||
.tx_data_4_n (tx_data_n_loc[4]),
|
||||
.tx_data_4_p (tx_data_p_loc[4]),
|
||||
.tx_data_5_n (tx_data_n_loc[5]),
|
||||
.tx_data_5_p (tx_data_p_loc[5]),
|
||||
.tx_data_6_n (tx_data_n_loc[6]),
|
||||
.tx_data_6_p (tx_data_p_loc[6]),
|
||||
.tx_data_7_n (tx_data_n_loc[7]),
|
||||
.tx_data_7_p (tx_data_p_loc[7]),
|
||||
.ref_clk_q0 (ref_clk),
|
||||
.ref_clk_q1 (ref_clk),
|
||||
.rx_device_clk (rx_device_clk),
|
||||
.tx_device_clk (tx_device_clk),
|
||||
.rx_sync_0 (rx_syncout),
|
||||
.tx_sync_0 (tx_syncin),
|
||||
.rx_sysref_0 (sysref),
|
||||
.tx_sysref_0 (sysref));
|
||||
|
||||
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
|
||||
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,33 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p]
|
||||
create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p]
|
||||
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
Reference in New Issue
Block a user