From 55cdbdb59c53fb4793b5419605be26b310c10a36 Mon Sep 17 00:00:00 2001 From: Nick Santana Date: Fri, 29 May 2026 13:36:02 -0700 Subject: [PATCH] moving repo from git to local repo --- Makefile | 46 + common/ad_3w_spi.v | 105 + common/ad_iobuf.v | 56 + constraints/system_constr.xdc | 93 + constraints/timing_constr.xdc | 33 + constraints/zcu102_system_constr.xdc | 34 + create_proj.tcl | 2985 ++++++++ mem_init_sys.txt | 512 ++ my_source/component.xml | 111 + .../adder_16signed_16signed_latency2.xci | 227 + my_source/ip/addsub/addsub.xci | 215 + .../afifo_32b_1024_pf512_latency1.xci | 485 ++ .../axis_data_fifo_512x128.xci | 175 + my_source/ip/dds_latency10/dds_latency10.xci | 365 + .../mult_16signed_x_16unsigned_latency3.xci | 168 + .../sfifo_32b_1024_pf992_latency1.xci | 467 ++ my_source/ip/vio_0/vio_0.xci | 1632 +++++ .../adder_16signed_16signed_latency2.xci | 227 + my_source/src/addsub/addsub.xci | 215 + .../afifo_32b_1024_pf512_latency1.xci | 485 ++ .../axis_data_fifo_512x128.xci | 175 + my_source/src/dds_cmd_gen.vhd | 154 + my_source/src/dds_latency10/dds_latency10.xci | 365 + my_source/src/dds_pulse_2x_top.vhd | 419 ++ my_source/src/dds_pulse_gen.vhd | 415 ++ my_source/src/dds_pulse_wrapper.vhd | 222 + .../mult_16signed_x_16unsigned_latency3.xci | 168 + .../sfifo_32b_1024_pf992_latency1.xci | 467 ++ my_source/src/system_top.v | 357 + my_source/src/vio_0/vio_0.xci | 1632 +++++ recreate.tcl | 2971 ++++++++ script/recreate.tcl | 3018 ++++++++ script/recreate_bd.tcl | 2231 ++++++ source/component.xml | 610 ++ source/dds_cmd_gen.vhd | 205 + source/dds_pulse_2x_top.vhd | 419 ++ source/dds_pulse_gen.vhd | 415 ++ source/dds_pulse_wrapper.vhd | 346 + .../adder_16signed_16signed_latency2.xci | 227 + source/src/addsub/addsub.xci | 215 + .../afifo_32b_1024_pf512_latency1.xci | 486 ++ .../axis_data_fifo_512x128.xci | 175 + source/src/dds_latency10/dds_latency10.xci | 365 + source/src/ila_0/ila_0.xci | 6310 +++++++++++++++++ source/src/ila_2/ila_2.xci | 6306 ++++++++++++++++ source/src/ila_3/ila_3.xci | 6303 ++++++++++++++++ source/src/ila_4/ila_4.xci | 6304 ++++++++++++++++ .../mult_16signed_x_16unsigned_latency3.xci | 168 + .../sfifo_32b_1024_pf992_latency1.xci | 467 ++ source/src/vio_0/vio_0.xci | 1632 +++++ source/system_top.v | 357 + source/xgui/dds_pulse_wrapper_v1_0.tcl | 40 + system_bd.tcl | 74 + system_constr.xdc | 93 + system_project.tcl | 68 + system_top.v | 305 + timing_constr.xdc | 33 + 57 files changed, 53153 insertions(+) create mode 100644 Makefile create mode 100644 common/ad_3w_spi.v create mode 100644 common/ad_iobuf.v create mode 100644 constraints/system_constr.xdc create mode 100644 constraints/timing_constr.xdc create mode 100644 constraints/zcu102_system_constr.xdc create mode 100644 create_proj.tcl create mode 100644 mem_init_sys.txt create mode 100644 my_source/component.xml create mode 100644 my_source/ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci create mode 100644 my_source/ip/addsub/addsub.xci create mode 100644 my_source/ip/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci create mode 100644 my_source/ip/axis_data_fifo_512x128/axis_data_fifo_512x128.xci create mode 100644 my_source/ip/dds_latency10/dds_latency10.xci create mode 100644 my_source/ip/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci create mode 100644 my_source/ip/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci create mode 100644 my_source/ip/vio_0/vio_0.xci create mode 100644 my_source/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci create mode 100644 my_source/src/addsub/addsub.xci create mode 100644 my_source/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci create mode 100644 my_source/src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci create mode 100644 my_source/src/dds_cmd_gen.vhd create mode 100644 my_source/src/dds_latency10/dds_latency10.xci create mode 100644 my_source/src/dds_pulse_2x_top.vhd create mode 100644 my_source/src/dds_pulse_gen.vhd create mode 100644 my_source/src/dds_pulse_wrapper.vhd create mode 100644 my_source/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci create mode 100644 my_source/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci create mode 100644 my_source/src/system_top.v create mode 100644 my_source/src/vio_0/vio_0.xci create mode 100644 recreate.tcl create mode 100644 script/recreate.tcl create mode 100644 script/recreate_bd.tcl create mode 100644 source/component.xml create mode 100644 source/dds_cmd_gen.vhd create mode 100644 source/dds_pulse_2x_top.vhd create mode 100644 source/dds_pulse_gen.vhd create mode 100644 source/dds_pulse_wrapper.vhd create mode 100644 source/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci create mode 100644 source/src/addsub/addsub.xci create mode 100644 source/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci create mode 100644 source/src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci create mode 100644 source/src/dds_latency10/dds_latency10.xci create mode 100644 source/src/ila_0/ila_0.xci create mode 100644 source/src/ila_2/ila_2.xci create mode 100644 source/src/ila_3/ila_3.xci create mode 100644 source/src/ila_4/ila_4.xci create mode 100644 source/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci create mode 100644 source/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci create mode 100644 source/src/vio_0/vio_0.xci create mode 100644 source/system_top.v create mode 100644 source/xgui/dds_pulse_wrapper_v1_0.tcl create mode 100644 system_bd.tcl create mode 100644 system_constr.xdc create mode 100644 system_project.tcl create mode 100644 system_top.v create mode 100644 timing_constr.xdc diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..14f4a9a --- /dev/null +++ b/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_zcu102 + +M_DEPS += timing_constr.xdc +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v +M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/common/ad_3w_spi.v b/common/ad_3w_spi.v new file mode 100644 index 0000000..bd7cb4b --- /dev/null +++ b/common/ad_3w_spi.v @@ -0,0 +1,105 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// +// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves. +// The expected transfer format is defined in ADI_SPI technical specification +// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf) +// +// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the +// instruction defines the direction of the SDIO during data transfer. (READ +// is 1 and WRITE is 0) +// + +module ad_3w_spi #( + + parameter NUM_OF_SLAVES = 8 +) ( + input [NUM_OF_SLAVES-1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, + + inout spi_sdio, + output spi_dir +); + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_dir = ~spi_enable_s; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; + +endmodule diff --git a/common/ad_iobuf.v b/common/ad_iobuf.v new file mode 100644 index 0000000..c097a3f --- /dev/null +++ b/common/ad_iobuf.v @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_iobuf #( + + parameter DATA_WIDTH = 1 +) ( + input [(DATA_WIDTH-1):0] dio_t, + input [(DATA_WIDTH-1):0] dio_i, + output [(DATA_WIDTH-1):0] dio_o, + inout [(DATA_WIDTH-1):0] dio_p +); + + genvar n; + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf + assign dio_o[n] = dio_p[n]; + assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n]; + end + endgenerate + +endmodule diff --git a/constraints/system_constr.xdc b/constraints/system_constr.xdc new file mode 100644 index 0000000..7985529 --- /dev/null +++ b/constraints/system_constr.xdc @@ -0,0 +1,93 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## mxfe +# + +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229 +set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229 +set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N +set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P +set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N +set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P +set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N +set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P +set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N +set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P +set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N +set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P +set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N +set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P +set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N +set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P +set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N +set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P +set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N +set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P +set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N +set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P +set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N +set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P +set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N +set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P +set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N +set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P +set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N +set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P +set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N +set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P +set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N +set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P +set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66 +set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66 +set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66 + diff --git a/constraints/timing_constr.xdc b/constraints/timing_constr.xdc new file mode 100644 index 0000000..0285b04 --- /dev/null +++ b/constraints/timing_constr.xdc @@ -0,0 +1,33 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Primary clock definitions +create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p] + +# device clock +create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p] +create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p] + + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks tx_device_clk] \ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref2_*}] + +# For transceiver output clocks use reference clock divided by two +# This will help autoderive the clocks correcly +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]] diff --git a/constraints/zcu102_system_constr.xdc b/constraints/zcu102_system_constr.xdc new file mode 100644 index 0000000..e81ece4 --- /dev/null +++ b/constraints/zcu102_system_constr.xdc @@ -0,0 +1,34 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# constraints +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4 +set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5 +set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6 +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7 +set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W +set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C + +set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0 +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1 +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2 +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3 +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4 +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5 +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6 +set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7 + +# Define SPI clock +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] +create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO] diff --git a/create_proj.tcl b/create_proj.tcl new file mode 100644 index 0000000..91634ff --- /dev/null +++ b/create_proj.tcl @@ -0,0 +1,2985 @@ +#***************************************************************************************** +# Vivado (TM) v2023.2 (64-bit) +# +# create_proj.tcl: Tcl script for re-creating project 'ad9081_fmca_ebz_zcu102' +# +# Generated by Vivado on Thu Apr 24 21:11:47 EDT 2025 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (create_proj.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/system_top.v" +# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/system_constr.xdc" +# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/timing_constr.xdc" +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/nsantana/adi/hdl/library/common/ad_3w_spi.v" +# "/home/nsantana/adi/hdl/library/common/ad_iobuf.v" +# "/home/nsantana/adi/hdl/projects/common/zcu102/zcu102_system_constr.xdc" +# +#***************************************************************************************** + +# Check file required for this script exists +proc checkRequiredFiles { origin_dir} { + set status true + set files [list \ + "[file normalize "$origin_dir/system_top.v"]"\ + "[file normalize "$origin_dir/system_constr.xdc"]"\ + "[file normalize "$origin_dir/timing_constr.xdc"]"\ + ] + foreach ifile $files { + if { ![file isfile $ifile] } { + puts " Could not find local file $ifile " + set status false + } + } + + set files [list \ + "[file normalize "$origin_dir/../../../library/common/ad_3w_spi.v"]"\ + "[file normalize "$origin_dir/../../../library/common/ad_iobuf.v"]"\ + "[file normalize "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc"]"\ + ] + foreach ifile $files { + if { ![file isfile $ifile] } { + puts " Could not find remote file $ifile " + set status false + } + } + + set paths [list \ + "[file normalize "$origin_dir/[file normalize "$origin_dir/../../../library"]"]"\ + ] + foreach ipath $paths { + if { ![file isdirectory $ipath] } { + puts " Could not access $ipath " + set status false + } + } + + return $status +} +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "ad9081_fmca_ebz_zcu102" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "create_proj.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Check for paths and files needed for project creation +set validate_required 0 +if { $validate_required } { + if { [checkRequiredFiles $origin_dir] } { + puts "Tcl file $script_file is valid. All files required for project creation is accesable. " + } else { + puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. " + return + } +} + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu9eg-ffvb1156-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {1} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {10} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {11} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {12} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {13} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {14} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {15} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {16} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {17} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {18} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {19} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {2} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {20} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {21} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {22} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {23} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {24} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {25} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {26} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {27} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {28} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {3} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {4} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {5} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {6} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {7} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2 + + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.4" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_resource_estimation" -value "0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "feature_set" -value "FeatureSet_Classic" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "/home/nsantana/adi/hdl/ipcache" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "zcu102" -objects $obj +set_property -name "revised_directory_structure" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "sim_compile_state" -value "1" -objects $obj +set_property -name "xpm_libraries" -value "XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +if { $obj != {} } { + set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../library"]" $obj + + # Rebuild user ip_repo's index before adding any source files + update_ip_catalog -rebuild +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../../library/common/ad_3w_spi.v"] \ + [file normalize "${origin_dir}/../../../library/common/ad_iobuf.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/system_top.v" ]\ +] +set imported_files "" +foreach f $files { + lappend imported_files [import_files -fileset sources_1 $f] +} + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj +set_property -name "generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/system_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "zcu102_orig/system_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/timing_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "zcu102_orig/timing_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD system +proc cr_bd_system { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name system + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:zynq_ultra_ps_e:3.5\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:xlconstant:1.1\ + analog.com:user:axi_sysid:1.0\ + analog.com:user:sysid_rom:1.0\ + xilinx.com:ip:smartconnect:1.0\ + analog.com:user:util_adxcvr:1.0\ + analog.com:user:axi_adxcvr:1.0\ + analog.com:user:util_cpack2:1.0\ + analog.com:user:axi_dmac:1.0\ + analog.com:user:util_upack2:1.0\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:util_reduced_logic:2.0\ + analog.com:user:axi_jesd204_rx:1.0\ + analog.com:user:jesd204_rx:1.0\ + analog.com:user:ad_ip_jesd204_tpl_adc:1.0\ + xilinx.com:ip:xlslice:1.0\ + analog.com:user:data_offload:1.0\ + analog.com:user:util_do_ram:1.0\ + analog.com:user:axi_jesd204_tx:1.0\ + analog.com:user:jesd204_tx:1.0\ + analog.com:user:ad_ip_jesd204_tpl_dac:1.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +# Hierarchical cell: mxfe_tx_data_offload +proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I init_req + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_CYCLIC_EN {true} \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {1} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: tx_mxfe_tpl_core +proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I dac_dunf + create_bd_pin -dir O -from 0 -to 0 dac_enable_0 + create_bd_pin -dir O -from 0 -to 0 dac_valid_0 + create_bd_pin -dir I -from 15 -to 0 dac_data_0 + create_bd_pin -dir O -from 0 -to 0 dac_enable_1 + create_bd_pin -dir O -from 0 -to 0 dac_valid_1 + create_bd_pin -dir I -from 15 -to 0 dac_data_1 + create_bd_pin -dir O -from 0 -to 0 dac_enable_2 + create_bd_pin -dir O -from 0 -to 0 dac_valid_2 + create_bd_pin -dir I -from 15 -to 0 dac_data_2 + create_bd_pin -dir O -from 0 -to 0 dac_enable_3 + create_bd_pin -dir O -from 0 -to 0 dac_valid_3 + create_bd_pin -dir I -from 15 -to 0 dac_data_3 + create_bd_pin -dir O -from 0 -to 0 dac_enable_4 + create_bd_pin -dir O -from 0 -to 0 dac_valid_4 + create_bd_pin -dir I -from 15 -to 0 dac_data_4 + create_bd_pin -dir O -from 0 -to 0 dac_enable_5 + create_bd_pin -dir O -from 0 -to 0 dac_valid_5 + create_bd_pin -dir I -from 15 -to 0 dac_data_5 + create_bd_pin -dir O -from 0 -to 0 dac_enable_6 + create_bd_pin -dir O -from 0 -to 0 dac_valid_6 + create_bd_pin -dir I -from 15 -to 0 dac_data_6 + create_bd_pin -dir O -from 0 -to 0 dac_enable_7 + create_bd_pin -dir O -from 0 -to 0 dac_valid_7 + create_bd_pin -dir I -from 15 -to 0 dac_data_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir O dac_sync_manual_req_out + create_bd_pin -dir I dac_sync_manual_req_in + create_bd_pin -dir O dac_rst + + # Create instance: dac_tpl_core, and set properties + set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.IQCORRECTION_DISABLE {0} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $dac_tpl_core + + + # Create instance: data_concat0, and set properties + set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ] + set_property CONFIG.NUM_PORTS {8} $data_concat0 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins dac_tpl_core/link] [get_bd_intf_pins link] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0] + connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1] + connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2] + connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3] + connect_bd_net -net dac_data_4_1 [get_bd_pins dac_data_4] [get_bd_pins data_concat0/In4] + connect_bd_net -net dac_data_5_1 [get_bd_pins dac_data_5] [get_bd_pins data_concat0/In5] + connect_bd_net -net dac_data_6_1 [get_bd_pins dac_data_6] [get_bd_pins data_concat0/In6] + connect_bd_net -net dac_data_7_1 [get_bd_pins dac_data_7] [get_bd_pins data_concat0/In7] + connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf] + connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_tpl_core/dac_rst] [get_bd_pins dac_rst] + connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] [get_bd_pins dac_sync_manual_req_out] + connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_concat0_dout [get_bd_pins data_concat0/dout] [get_bd_pins dac_tpl_core/dac_ddata] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins dac_enable_0] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins dac_enable_1] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins dac_enable_2] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins dac_enable_3] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins enable_slice_4/Dout] [get_bd_pins dac_enable_4] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins enable_slice_5/Dout] [get_bd_pins dac_enable_5] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins enable_slice_6/Dout] [get_bd_pins dac_enable_6] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins enable_slice_7/Dout] [get_bd_pins dac_enable_7] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins dac_valid_0] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins dac_valid_1] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins dac_valid_2] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins dac_valid_3] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins valid_slice_4/Dout] [get_bd_pins dac_valid_4] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins valid_slice_5/Dout] [get_bd_pins dac_valid_5] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins valid_slice_6/Dout] [get_bd_pins dac_valid_6] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins valid_slice_7/Dout] [get_bd_pins dac_valid_7] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_tx_jesd +proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3 + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir I -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: tx_axi, and set properties + set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $tx_axi + + + # Create instance: tx, and set properties + set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $tx + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi] + connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx_axi/tx_cfg] [get_bd_intf_pins tx/tx_cfg] + connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx_axi/tx_ctrl] [get_bd_intf_pins tx/tx_ctrl] + connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data] + connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event] + connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config] + connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx/tx_phy0] [get_bd_intf_pins tx_phy0] + connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx/tx_phy1] [get_bd_intf_pins tx_phy1] + connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx/tx_phy2] [get_bd_intf_pins tx_phy2] + connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx/tx_phy3] [get_bd_intf_pins tx_phy3] + connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx_axi/device_clk] [get_bd_pins tx/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx_axi/core_clk] [get_bd_pins tx/clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn] + connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref] + connect_bd_net -net tx_axi_core_reset [get_bd_pins tx_axi/core_reset] [get_bd_pins tx/reset] + connect_bd_net -net tx_axi_device_reset [get_bd_pins tx_axi/device_reset] [get_bd_pins tx/device_reset] + connect_bd_net -net tx_axi_irq [get_bd_pins tx_axi/irq] [get_bd_pins irq] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_rx_data_offload +proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I init_req + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {0} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx_mxfe_tpl_core +proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -from 3 -to 0 link_sof + create_bd_pin -dir I link_valid + create_bd_pin -dir I -from 127 -to 0 link_data + create_bd_pin -dir I adc_dovf + create_bd_pin -dir O -from 0 -to 0 adc_enable_0 + create_bd_pin -dir O -from 0 -to 0 adc_valid_0 + create_bd_pin -dir O -from 15 -to 0 adc_data_0 + create_bd_pin -dir O -from 0 -to 0 adc_enable_1 + create_bd_pin -dir O -from 0 -to 0 adc_valid_1 + create_bd_pin -dir O -from 15 -to 0 adc_data_1 + create_bd_pin -dir O -from 0 -to 0 adc_enable_2 + create_bd_pin -dir O -from 0 -to 0 adc_valid_2 + create_bd_pin -dir O -from 15 -to 0 adc_data_2 + create_bd_pin -dir O -from 0 -to 0 adc_enable_3 + create_bd_pin -dir O -from 0 -to 0 adc_valid_3 + create_bd_pin -dir O -from 15 -to 0 adc_data_3 + create_bd_pin -dir O -from 0 -to 0 adc_enable_4 + create_bd_pin -dir O -from 0 -to 0 adc_valid_4 + create_bd_pin -dir O -from 15 -to 0 adc_data_4 + create_bd_pin -dir O -from 0 -to 0 adc_enable_5 + create_bd_pin -dir O -from 0 -to 0 adc_valid_5 + create_bd_pin -dir O -from 15 -to 0 adc_data_5 + create_bd_pin -dir O -from 0 -to 0 adc_enable_6 + create_bd_pin -dir O -from 0 -to 0 adc_valid_6 + create_bd_pin -dir O -from 15 -to 0 adc_data_6 + create_bd_pin -dir O -from 0 -to 0 adc_enable_7 + create_bd_pin -dir O -from 0 -to 0 adc_valid_7 + create_bd_pin -dir O -from 15 -to 0 adc_data_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir O adc_sync_manual_req_out + create_bd_pin -dir I adc_sync_manual_req_in + create_bd_pin -dir O adc_rst + + # Create instance: adc_tpl_core, and set properties + set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $adc_tpl_core + + + # Create instance: data_slice_0, and set properties + set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_0 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: data_slice_1, and set properties + set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {16} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_1 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: data_slice_2, and set properties + set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {47} \ + CONFIG.DIN_TO {32} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_2 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: data_slice_3, and set properties + set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {48} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_3 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: data_slice_4, and set properties + set data_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {79} \ + CONFIG.DIN_TO {64} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_4 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: data_slice_5, and set properties + set data_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {95} \ + CONFIG.DIN_TO {80} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_5 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: data_slice_6, and set properties + set data_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {111} \ + CONFIG.DIN_TO {96} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_6 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: data_slice_7, and set properties + set data_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {127} \ + CONFIG.DIN_TO {112} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_7 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf] + connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in] + connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din] [get_bd_pins data_slice_4/Din] [get_bd_pins data_slice_5/Din] [get_bd_pins data_slice_6/Din] [get_bd_pins data_slice_7/Din] + connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_tpl_core/adc_rst] [get_bd_pins adc_rst] + connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] [get_bd_pins adc_sync_manual_req_out] + connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_slice_0_Dout [get_bd_pins data_slice_0/Dout] [get_bd_pins adc_data_0] + connect_bd_net -net data_slice_1_Dout [get_bd_pins data_slice_1/Dout] [get_bd_pins adc_data_1] + connect_bd_net -net data_slice_2_Dout [get_bd_pins data_slice_2/Dout] [get_bd_pins adc_data_2] + connect_bd_net -net data_slice_3_Dout [get_bd_pins data_slice_3/Dout] [get_bd_pins adc_data_3] + connect_bd_net -net data_slice_4_Dout [get_bd_pins data_slice_4/Dout] [get_bd_pins adc_data_4] + connect_bd_net -net data_slice_5_Dout [get_bd_pins data_slice_5/Dout] [get_bd_pins adc_data_5] + connect_bd_net -net data_slice_6_Dout [get_bd_pins data_slice_6/Dout] [get_bd_pins adc_data_6] + connect_bd_net -net data_slice_7_Dout [get_bd_pins data_slice_7/Dout] [get_bd_pins adc_data_7] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins adc_enable_0] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins adc_enable_1] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins adc_enable_2] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins adc_enable_3] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins enable_slice_4/Dout] [get_bd_pins adc_enable_4] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins enable_slice_5/Dout] [get_bd_pins adc_enable_5] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins enable_slice_6/Dout] [get_bd_pins adc_enable_6] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins enable_slice_7/Dout] [get_bd_pins adc_enable_7] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk] + connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data] + connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof] + connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins adc_valid_0] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins adc_valid_1] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins adc_valid_2] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins adc_valid_3] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins valid_slice_4/Dout] [get_bd_pins adc_valid_4] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins valid_slice_5/Dout] [get_bd_pins adc_valid_5] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins valid_slice_6/Dout] [get_bd_pins adc_valid_6] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins valid_slice_7/Dout] [get_bd_pins adc_valid_7] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_rx_jesd +proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3 + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -from 0 -to 0 sync + create_bd_pin -dir I sysref + create_bd_pin -dir O phy_en_char_align + create_bd_pin -dir O -from 3 -to 0 rx_eof + create_bd_pin -dir O -from 3 -to 0 rx_sof + create_bd_pin -dir O rx_data_tvalid + create_bd_pin -dir O -from 127 -to 0 rx_data_tdata + + # Create instance: rx_axi, and set properties + set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $rx_axi + + + # Create instance: rx, and set properties + set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_INPUT_PIPELINE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $rx + + + # Create interface connections + connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx_axi/rx_cfg] [get_bd_intf_pins rx/rx_cfg] + connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx/rx_phy0] [get_bd_intf_pins rx_phy0] + connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx/rx_phy1] [get_bd_intf_pins rx_phy1] + connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx/rx_phy2] [get_bd_intf_pins rx_phy2] + connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx/rx_phy3] [get_bd_intf_pins rx_phy3] + connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event] + connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config] + connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx_axi/device_clk] [get_bd_pins rx/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx_axi/core_clk] [get_bd_pins rx/clk] + connect_bd_net -net rx_axi_core_reset [get_bd_pins rx_axi/core_reset] [get_bd_pins rx/reset] + connect_bd_net -net rx_axi_device_reset [get_bd_pins rx_axi/device_reset] [get_bd_pins rx/device_reset] + connect_bd_net -net rx_axi_irq [get_bd_pins rx_axi/irq] [get_bd_pins irq] + connect_bd_net -net rx_phy_en_char_align [get_bd_pins rx/phy_en_char_align] [get_bd_pins phy_en_char_align] + connect_bd_net -net rx_rx_data [get_bd_pins rx/rx_data] [get_bd_pins rx_data_tdata] + connect_bd_net -net rx_rx_eof [get_bd_pins rx/rx_eof] [get_bd_pins rx_eof] + connect_bd_net -net rx_rx_sof [get_bd_pins rx/rx_sof] [get_bd_pins rx_sof] + connect_bd_net -net rx_rx_valid [get_bd_pins rx/rx_valid] [get_bd_pins rx_data_tvalid] + connect_bd_net -net rx_sync [get_bd_pins rx/sync] [get_bd_pins sync] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] + set spi0_sclk [ create_bd_port -dir O spi0_sclk ] + set spi0_mosi [ create_bd_port -dir O spi0_mosi ] + set spi0_miso [ create_bd_port -dir I spi0_miso ] + set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ] + set spi1_sclk [ create_bd_port -dir O spi1_sclk ] + set spi1_mosi [ create_bd_port -dir O spi1_mosi ] + set spi1_miso [ create_bd_port -dir I spi1_miso ] + set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ] + set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ] + set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ] + set rx_device_clk [ create_bd_port -dir I rx_device_clk ] + set tx_device_clk [ create_bd_port -dir I tx_device_clk ] + set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ] + set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ] + set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ] + set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ] + set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ] + set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ] + set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ] + set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ] + set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ] + set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ] + set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ] + set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ] + set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ] + set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ] + set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ] + set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ] + set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ] + set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ] + set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ] + set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ] + set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ] + set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ] + set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ] + set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ] + set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ] + set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ] + set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ] + set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ] + set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ] + set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ] + set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ] + set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ] + set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ] + set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ] + set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ] + set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ] + set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ] + set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ] + set ext_sync_in [ create_bd_port -dir I ext_sync_in ] + + # Create instance: sys_ps8, and set properties + set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 sys_ps8 ] + set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\ +GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ +\ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Single Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {0x0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {1} \ + CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \ + CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \ + CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ +\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ +\ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {0} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {1} \ + CONFIG.PSU__USE__S_AXI_GP4 {1} \ + ] $sys_ps8 + + + # Create instance: sys_rstgen, and set properties + set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen + + + # Create instance: sys_250m_rstgen, and set properties + set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen + + + # Create instance: sys_500m_rstgen, and set properties + set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen + + + # Create instance: spi0_csn_concat, and set properties + set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat + + + # Create instance: VCC_1, and set properties + set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $VCC_1 + + + # Create instance: GND_1, and set properties + set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $GND_1 + + + # Create instance: spi1_csn_concat, and set properties + set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat + + + # Create instance: axi_sysid_0, and set properties + set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ] + set_property CONFIG.ROM_ADDR_BITS {9} $axi_sysid_0 + + + # Create instance: rom_sys_0, and set properties + set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ] + set_property -dict [list \ + CONFIG.PATH_TO_FILE {/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102/mem_init_sys.txt} \ + CONFIG.ROM_ADDR_BITS {9} \ + ] $rom_sys_0 + + + # Create instance: axi_cpu_interconnect, and set properties + set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {11} \ + CONFIG.NUM_SI {1} \ + ] $axi_cpu_interconnect + + + # Create instance: sys_concat_intc_0, and set properties + set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0 + + + # Create instance: sys_concat_intc_1, and set properties + set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1 + + + # Create instance: axi_hp0_interconnect, and set properties + set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp0_interconnect + + + # Create instance: util_mxfe_xcvr, and set properties + set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ] + set_property -dict [list \ + CONFIG.A_TXDIFFCTRL {0x0C} \ + CONFIG.CH_HSPMUX {0x6868} \ + CONFIG.CPLL_CFG0 {0x01FA} \ + CONFIG.CPLL_CFG1 {0x0023} \ + CONFIG.CPLL_CFG2 {0x0002} \ + CONFIG.CPLL_FBDIV {2} \ + CONFIG.CPLL_FBDIV_4_5 {5} \ + CONFIG.LINK_MODE {1} \ + CONFIG.POR_CFG {0x0000} \ + CONFIG.PPF0_CFG {0x0F00} \ + CONFIG.PREIQ_FREQ_BST {1} \ + CONFIG.QPLL_CFG0 {0x333c} \ + CONFIG.QPLL_CFG4 {0x0045} \ + CONFIG.QPLL_CP {0x0FF} \ + CONFIG.QPLL_CP_G3 {0x00F} \ + CONFIG.QPLL_FBDIV {"0000010100"} \ + CONFIG.QPLL_LPF {0x2FF} \ + CONFIG.QPLL_REFCLK_DIV {1} \ + CONFIG.RXCDR_CFG0 {0x0003} \ + CONFIG.RXCDR_CFG2_GEN2 {0x265} \ + CONFIG.RXCDR_CFG2_GEN4 {0x0164} \ + CONFIG.RXCDR_CFG3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN2 {0x12} \ + CONFIG.RXCDR_CFG3_GEN3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN4 {0x0012} \ + CONFIG.RXPI_CFG0 {0x0200} \ + CONFIG.RXPI_CFG1 {0x00FD} \ + CONFIG.RX_CLK25_DIV {31} \ + CONFIG.RX_LANE_RATE {10} \ + CONFIG.RX_NUM_OF_LANES {4} \ + CONFIG.RX_OUT_DIV {1} \ + CONFIG.RX_WIDEMODE_CDR {0x0} \ + CONFIG.TXPI_CFG {0x0000} \ + CONFIG.TX_CLK25_DIV {31} \ + CONFIG.TX_LANE_RATE {10} \ + CONFIG.TX_NUM_OF_LANES {4} \ + CONFIG.TX_PI_BIASSET {3} \ + ] $util_mxfe_xcvr + + + # Create instance: axi_mxfe_rx_xcvr, and set properties + set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.LPM_OR_DFE_N {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {0} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {0} \ + ] $axi_mxfe_rx_xcvr + + + # Create instance: axi_mxfe_rx_jesd + create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd + + # Create instance: rx_mxfe_tpl_core + create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core + + # Create instance: util_mxfe_cpack, and set properties + set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_cpack + + + # Create instance: mxfe_rx_data_offload + create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload + + # Create instance: axi_mxfe_rx_dma, and set properties + set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {false} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {0} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_mxfe_rx_dma + + + # Create instance: axi_mxfe_tx_xcvr, and set properties + set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {1} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {1} \ + ] $axi_mxfe_tx_xcvr + + + # Create instance: axi_mxfe_tx_jesd + create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd + + # Create instance: tx_mxfe_tpl_core + create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core + + # Create instance: util_mxfe_upack, and set properties + set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_upack + + + # Create instance: mxfe_tx_data_offload + create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload + + # Create instance: axi_mxfe_tx_dma, and set properties + set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {true} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + ] $axi_mxfe_tx_dma + + + # Create instance: rx_device_clk_rstgen, and set properties + set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ] + + # Create instance: tx_device_clk_rstgen, and set properties + set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ] + + # Create instance: axi_hp1_interconnect, and set properties + set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp1_interconnect + + + # Create instance: axi_hp2_interconnect, and set properties + set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp2_interconnect + + + # Create instance: manual_sync_or, and set properties + set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $manual_sync_or + + + # Create instance: cpack_rst_logic, and set properties + set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {3} \ + ] $cpack_rst_logic + + + # Create instance: rx_do_rstout_logic, and set properties + set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rx_do_rstout_logic + + + # Create instance: cpack_reset_sources, and set properties + set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ] + set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources + + + # Create instance: upack_rst_logic, and set properties + set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {2} \ + ] $upack_rst_logic + + + # Create instance: upack_reset_sources, and set properties + set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ] + set_property CONFIG.NUM_PORTS {2} $upack_reset_sources + + + # Create interface connections + connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] + connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] + connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins util_mxfe_xcvr/tx_0] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins util_mxfe_xcvr/tx_1] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins util_mxfe_xcvr/tx_2] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins util_mxfe_xcvr/tx_3] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0] + connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins mxfe_rx_data_offload/m_axis] [get_bd_intf_pins axi_mxfe_rx_dma/s_axis] + connect_bd_intf_net -intf_net mxfe_tx_data_offload_m_axis [get_bd_intf_pins util_mxfe_upack/s_axis] [get_bd_intf_pins mxfe_tx_data_offload/m_axis] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins mxfe_tx_data_offload/s_axis] [get_bd_intf_pins axi_mxfe_tx_dma/m_axis] + connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD] + connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins tx_mxfe_tpl_core/link] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins util_mxfe_xcvr/rx_0] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins util_mxfe_xcvr/rx_1] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins util_mxfe_xcvr/rx_2] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins util_mxfe_xcvr/rx_3] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3] + + # Create port connections + connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] + connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] + connect_bd_net -net adc_dovf_1 [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] [get_bd_pins rx_mxfe_tpl_core/adc_dovf] + connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5] + connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3] + connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid] + connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof] + connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_pins axi_mxfe_rx_jesd/sync] [get_bd_ports rx_sync_0] + connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3] + connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4] + connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2] + connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0] + connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr] + connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1] + connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset] + connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in] + connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i] + connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req] + connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req] + connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1] + connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3] + connect_bd_net -net rom_sys_0_rom_data [get_bd_pins rom_sys_0/rom_data] [get_bd_pins axi_sysid_0/sys_rom_data] + connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n] + connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p] + connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n] + connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p] + connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n] + connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p] + connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n] + connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p] + connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_cpack/clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] + connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] + connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins rx_device_clk_rstgen/peripheral_reset] [get_bd_pins cpack_reset_sources/In0] + connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins rx_do_rstout_logic/Res] [get_bd_pins cpack_reset_sources/In2] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_4 [get_bd_pins rx_mxfe_tpl_core/adc_data_4] [get_bd_pins util_mxfe_cpack/fifo_wr_data_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_5 [get_bd_pins rx_mxfe_tpl_core/adc_data_5] [get_bd_pins util_mxfe_cpack/fifo_wr_data_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_6 [get_bd_pins rx_mxfe_tpl_core/adc_data_6] [get_bd_pins util_mxfe_cpack/fifo_wr_data_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_7 [get_bd_pins rx_mxfe_tpl_core/adc_data_7] [get_bd_pins util_mxfe_cpack/fifo_wr_data_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_4 [get_bd_pins rx_mxfe_tpl_core/adc_enable_4] [get_bd_pins util_mxfe_cpack/enable_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_5 [get_bd_pins rx_mxfe_tpl_core/adc_enable_5] [get_bd_pins util_mxfe_cpack/enable_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_6 [get_bd_pins rx_mxfe_tpl_core/adc_enable_6] [get_bd_pins util_mxfe_cpack/enable_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_7 [get_bd_pins rx_mxfe_tpl_core/adc_enable_7] [get_bd_pins util_mxfe_cpack/enable_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins rx_mxfe_tpl_core/adc_rst] [get_bd_pins cpack_reset_sources/In1] + connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] [get_bd_pins manual_sync_or/Op1] + connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en] + connect_bd_net -net spi0_csn_concat_dout [get_bd_pins spi0_csn_concat/dout] [get_bd_ports spi0_csn] + connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i] + connect_bd_net -net spi1_csn_concat_dout [get_bd_pins spi1_csn_concat/dout] [get_bd_ports spi1_csn] + connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i] + connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync] + connect_bd_net -net sys_250m_clk [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] + connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset] + connect_bd_net -net sys_250m_resetn [get_bd_pins sys_250m_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_pins axi_hp2_interconnect/aresetn] + connect_bd_net -net sys_500m_clk [get_bd_pins sys_ps8/pl_clk2] [get_bd_pins sys_500m_rstgen/slowest_sync_clk] + connect_bd_net -net sys_500m_reset [get_bd_pins sys_500m_rstgen/peripheral_reset] + connect_bd_net -net sys_500m_resetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0] + connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1] + connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins rom_sys_0/clk] [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins util_mxfe_xcvr/up_clk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] + connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins util_mxfe_xcvr/up_rstn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] + connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_pins sys_ps8/emio_gpio_o] [get_bd_ports gpio_o] + connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_pins sys_ps8/emio_gpio_t] [get_bd_ports gpio_t] + connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_pins sys_ps8/emio_spi0_m_o] [get_bd_ports spi0_mosi] + connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_pins sys_ps8/emio_spi0_sclk_o] [get_bd_ports spi0_sclk] + connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] [get_bd_pins spi0_csn_concat/In1] + connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] [get_bd_pins spi0_csn_concat/In2] + connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins sys_ps8/emio_spi0_ss_o_n] [get_bd_pins spi0_csn_concat/In0] + connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_pins sys_ps8/emio_spi1_m_o] [get_bd_ports spi1_mosi] + connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_pins sys_ps8/emio_spi1_sclk_o] [get_bd_ports spi1_sclk] + connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] [get_bd_pins spi1_csn_concat/In1] + connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] [get_bd_pins spi1_csn_concat/In2] + connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins sys_ps8/emio_spi1_ss_o_n] [get_bd_pins spi1_csn_concat/In0] + connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in] + connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref] + connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref] + connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_upack/clk] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] + connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] + connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_4 [get_bd_pins tx_mxfe_tpl_core/dac_enable_4] [get_bd_pins util_mxfe_upack/enable_4] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_5 [get_bd_pins tx_mxfe_tpl_core/dac_enable_5] [get_bd_pins util_mxfe_upack/enable_5] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_6 [get_bd_pins tx_mxfe_tpl_core/dac_enable_6] [get_bd_pins util_mxfe_upack/enable_6] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_7 [get_bd_pins tx_mxfe_tpl_core/dac_enable_7] [get_bd_pins util_mxfe_upack/enable_7] + connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1] + connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] [get_bd_pins manual_sync_or/Op2] + connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en] + connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1] + connect_bd_net -net upack_rst_logic_Res [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins util_mxfe_upack/fifo_rd_data_0] [get_bd_pins tx_mxfe_tpl_core/dac_data_0] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins util_mxfe_upack/fifo_rd_data_1] [get_bd_pins tx_mxfe_tpl_core/dac_data_1] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins util_mxfe_upack/fifo_rd_data_2] [get_bd_pins tx_mxfe_tpl_core/dac_data_2] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins util_mxfe_upack/fifo_rd_data_3] [get_bd_pins tx_mxfe_tpl_core/dac_data_3] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_4 [get_bd_pins util_mxfe_upack/fifo_rd_data_4] [get_bd_pins tx_mxfe_tpl_core/dac_data_4] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_5 [get_bd_pins util_mxfe_upack/fifo_rd_data_5] [get_bd_pins tx_mxfe_tpl_core/dac_data_5] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_6 [get_bd_pins util_mxfe_upack/fifo_rd_data_6] [get_bd_pins tx_mxfe_tpl_core/dac_data_6] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_7 [get_bd_pins util_mxfe_upack/fifo_rd_data_7] [get_bd_pins tx_mxfe_tpl_core/dac_data_7] + connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins axi_mxfe_rx_jesd/link_clk] + connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_pins util_mxfe_xcvr/tx_0_n] [get_bd_ports tx_data_0_n] + connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_pins util_mxfe_xcvr/tx_0_p] [get_bd_ports tx_data_0_p] + connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_pins util_mxfe_xcvr/tx_1_n] [get_bd_ports tx_data_1_n] + connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_pins util_mxfe_xcvr/tx_1_p] [get_bd_ports tx_data_1_p] + connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_pins util_mxfe_xcvr/tx_2_n] [get_bd_ports tx_data_2_n] + connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_pins util_mxfe_xcvr/tx_2_p] [get_bd_ports tx_data_2_p] + connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_pins util_mxfe_xcvr/tx_3_n] [get_bd_ports tx_data_3_n] + connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_pins util_mxfe_xcvr/tx_3_p] [get_bd_ports tx_data_3_p] + connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins axi_mxfe_tx_jesd/link_clk] + + # Create address segments + assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C430000 -range 0x00001000 -with_name SEG_data_axi_mxfe_tx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_tx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_tx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x85000000 -range 0x00010000 -with_name SEG_data_axi_sysid_0 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C450000 -range 0x00010000 -with_name SEG_data_mxfe_rx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C440000 -range 0x00010000 -with_name SEG_data_mxfe_tx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A10000 -range 0x00002000 -with_name SEG_data_rx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B10000 -range 0x00002000 -with_name SEG_data_tx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.17607", + "Default View_TopLeft":"-165,464", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port port-id_spi0_sclk -pg 1 -lvl 15 -x 6170 -y 2770 -defaultsOSRD +preplace port port-id_spi0_mosi -pg 1 -lvl 15 -x 6170 -y 2810 -defaultsOSRD +preplace port port-id_spi0_miso -pg 1 -lvl 0 -x 0 -y 3200 -defaultsOSRD +preplace port port-id_spi1_sclk -pg 1 -lvl 15 -x 6170 -y 2970 -defaultsOSRD +preplace port port-id_spi1_mosi -pg 1 -lvl 15 -x 6170 -y 3170 -defaultsOSRD +preplace port port-id_spi1_miso -pg 1 -lvl 0 -x 0 -y 3260 -defaultsOSRD +preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x 0 -y 1490 -defaultsOSRD +preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x 0 -y 1720 -defaultsOSRD +preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x 0 -y 2450 -defaultsOSRD +preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD +preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x 0 -y 3180 -defaultsOSRD +preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x 0 -y 1700 -defaultsOSRD +preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x 0 -y 2470 -defaultsOSRD +preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x 0 -y 2510 -defaultsOSRD +preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x 0 -y 2490 -defaultsOSRD +preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x 0 -y 3080 -defaultsOSRD +preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x 0 -y 3060 -defaultsOSRD +preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x 0 -y 3100 -defaultsOSRD +preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x 0 -y 3120 -defaultsOSRD +preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x 0 -y 3140 -defaultsOSRD +preplace port port-id_tx_data_0_p -pg 1 -lvl 15 -x 6170 -y 2090 -defaultsOSRD +preplace port port-id_tx_data_0_n -pg 1 -lvl 15 -x 6170 -y 2110 -defaultsOSRD +preplace port port-id_tx_data_1_p -pg 1 -lvl 15 -x 6170 -y 2130 -defaultsOSRD +preplace port port-id_tx_data_1_n -pg 1 -lvl 15 -x 6170 -y 2150 -defaultsOSRD +preplace port port-id_tx_data_2_p -pg 1 -lvl 15 -x 6170 -y 2170 -defaultsOSRD +preplace port port-id_tx_data_2_n -pg 1 -lvl 15 -x 6170 -y 2190 -defaultsOSRD +preplace port port-id_tx_data_3_p -pg 1 -lvl 15 -x 6170 -y 2230 -defaultsOSRD +preplace port port-id_tx_data_3_n -pg 1 -lvl 15 -x 6170 -y 2250 -defaultsOSRD +preplace port port-id_rx_data_4_n -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD +preplace port port-id_rx_data_4_p -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port port-id_rx_data_5_n -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD +preplace port port-id_rx_data_5_p -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD +preplace port port-id_rx_data_6_n -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD +preplace port port-id_rx_data_6_p -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD +preplace port port-id_rx_data_7_n -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD +preplace port port-id_rx_data_7_p -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD +preplace port port-id_tx_data_4_n -pg 1 -lvl 15 -x 6170 -y 20 -defaultsOSRD +preplace port port-id_tx_data_4_p -pg 1 -lvl 15 -x 6170 -y 40 -defaultsOSRD +preplace port port-id_tx_data_5_n -pg 1 -lvl 15 -x 6170 -y 60 -defaultsOSRD +preplace port port-id_tx_data_5_p -pg 1 -lvl 15 -x 6170 -y 80 -defaultsOSRD +preplace port port-id_tx_data_6_n -pg 1 -lvl 15 -x 6170 -y 100 -defaultsOSRD +preplace port port-id_tx_data_6_p -pg 1 -lvl 15 -x 6170 -y 120 -defaultsOSRD +preplace port port-id_tx_data_7_n -pg 1 -lvl 15 -x 6170 -y 140 -defaultsOSRD +preplace port port-id_tx_data_7_p -pg 1 -lvl 15 -x 6170 -y 160 -defaultsOSRD +preplace port port-id_ext_sync_in -pg 1 -lvl 0 -x 0 -y 1270 -defaultsOSRD +preplace portBus spi0_csn -pg 1 -lvl 15 -x 6170 -y 2890 -defaultsOSRD +preplace portBus spi1_csn -pg 1 -lvl 15 -x 6170 -y 3090 -defaultsOSRD +preplace portBus gpio_i -pg 1 -lvl 0 -x 0 -y 2910 -defaultsOSRD +preplace portBus gpio_o -pg 1 -lvl 15 -x 6170 -y 2690 -defaultsOSRD +preplace portBus gpio_t -pg 1 -lvl 15 -x 6170 -y 2710 -defaultsOSRD +preplace portBus rx_sync_0 -pg 1 -lvl 15 -x 6170 -y 1920 -defaultsOSRD +preplace portBus tx_sync_0 -pg 1 -lvl 0 -x 0 -y 3160 -defaultsOSRD +preplace inst sys_ps8 -pg 1 -lvl 9 -x 3350 -y 2910 -defaultsOSRD +preplace inst sys_rstgen -pg 1 -lvl 1 -x 200 -y 2120 -defaultsOSRD +preplace inst sys_250m_rstgen -pg 1 -lvl 5 -x 1560 -y 2320 -defaultsOSRD +preplace inst sys_500m_rstgen -pg 1 -lvl 10 -x 3900 -y 3230 -defaultsOSRD +preplace inst spi0_csn_concat -pg 1 -lvl 14 -x 5960 -y 2890 -defaultsOSRD +preplace inst VCC_1 -pg 1 -lvl 5 -x 1560 -y 2110 -defaultsOSRD +preplace inst GND_1 -pg 1 -lvl 5 -x 1560 -y 2010 -defaultsOSRD +preplace inst spi1_csn_concat -pg 1 -lvl 14 -x 5960 -y 3090 -defaultsOSRD +preplace inst axi_sysid_0 -pg 1 -lvl 11 -x 4500 -y 2170 -defaultsOSRD +preplace inst rom_sys_0 -pg 1 -lvl 10 -x 3900 -y 2340 -defaultsOSRD +preplace inst axi_cpu_interconnect -pg 1 -lvl 10 -x 3900 -y 1770 -defaultsOSRD +preplace inst sys_concat_intc_0 -pg 1 -lvl 8 -x 2720 -y 2620 -defaultsOSRD +preplace inst sys_concat_intc_1 -pg 1 -lvl 8 -x 2720 -y 2150 -defaultsOSRD +preplace inst axi_hp0_interconnect -pg 1 -lvl 8 -x 2720 -y 2830 -defaultsOSRD +preplace inst util_mxfe_xcvr -pg 1 -lvl 13 -x 5570 -y 2080 -defaultsOSRD +preplace inst axi_mxfe_rx_xcvr -pg 1 -lvl 7 -x 2320 -y 1530 -defaultsOSRD +preplace inst axi_mxfe_rx_jesd -pg 1 -lvl 14 -x 5960 -y 1960 -defaultsOSRD +preplace inst rx_mxfe_tpl_core -pg 1 -lvl 11 -x 4500 -y 330 -defaultsOSRD +preplace inst util_mxfe_cpack -pg 1 -lvl 5 -x 1560 -y 1010 -defaultsOSRD +preplace inst mxfe_rx_data_offload -pg 1 -lvl 6 -x 1970 -y 2130 -defaultsOSRD +preplace inst axi_mxfe_rx_dma -pg 1 -lvl 7 -x 2320 -y 2300 -defaultsOSRD +preplace inst axi_mxfe_tx_xcvr -pg 1 -lvl 12 -x 5030 -y 1720 -defaultsOSRD +preplace inst axi_mxfe_tx_jesd -pg 1 -lvl 12 -x 5030 -y 1970 -defaultsOSRD +preplace inst tx_mxfe_tpl_core -pg 1 -lvl 11 -x 4500 -y 1060 -defaultsOSRD +preplace inst util_mxfe_upack -pg 1 -lvl 12 -x 5030 -y 1260 -defaultsOSRD +preplace inst mxfe_tx_data_offload -pg 1 -lvl 11 -x 4500 -y 1890 -defaultsOSRD +preplace inst axi_mxfe_tx_dma -pg 1 -lvl 7 -x 2320 -y 2050 -defaultsOSRD +preplace inst rx_device_clk_rstgen -pg 1 -lvl 2 -x 550 -y 1600 -defaultsOSRD +preplace inst tx_device_clk_rstgen -pg 1 -lvl 9 -x 3350 -y 1850 -defaultsOSRD +preplace inst axi_hp1_interconnect -pg 1 -lvl 8 -x 2720 -y 3000 -defaultsOSRD +preplace inst axi_hp2_interconnect -pg 1 -lvl 8 -x 2720 -y 2360 -defaultsOSRD +preplace inst manual_sync_or -pg 1 -lvl 10 -x 3900 -y 860 -defaultsOSRD +preplace inst cpack_rst_logic -pg 1 -lvl 4 -x 1060 -y 850 -defaultsOSRD +preplace inst rx_do_rstout_logic -pg 1 -lvl 2 -x 550 -y 1430 -defaultsOSRD +preplace inst cpack_reset_sources -pg 1 -lvl 3 -x 830 -y 1410 -defaultsOSRD +preplace inst upack_rst_logic -pg 1 -lvl 11 -x 4500 -y 1370 -defaultsOSRD +preplace inst upack_reset_sources -pg 1 -lvl 10 -x 3900 -y 1410 -defaultsOSRD +preplace netloc GND_1_dout 1 5 6 1760 2320 2150J 2180 2530 2440 2850J 2420 3720 2410 4220 +preplace netloc VCC_1_dout 1 5 5 1790 2450 NJ 2450 NJ 2450 2860J 2430 3670 +preplace netloc adc_dovf_1 1 5 6 NJ 1040 NJ 1040 NJ 1040 NJ 1040 3660J 780 4090 +preplace netloc axi_mxfe_rx_dma_irq 1 7 1 2540 2180n +preplace netloc axi_mxfe_rx_jesd_irq 1 7 8 2590 1970 NJ 1970 NJ 1970 4120J 2040 4730J 2100 5310J 1540 5800J 2100 6130 +preplace netloc axi_mxfe_rx_jesd_phy_en_char_align 1 12 3 5430 2660 NJ 2660 6120 +preplace netloc axi_mxfe_rx_jesd_rx_data_tdata 1 10 5 4260 1580 NJ 1580 5240J 1500 NJ 1500 6150 +preplace netloc axi_mxfe_rx_jesd_rx_data_tvalid 1 10 5 4250 1590 NJ 1590 5250J 1510 NJ 1510 6140 +preplace netloc axi_mxfe_rx_jesd_rx_sof 1 10 5 4240 1600 NJ 1600 5260J 1520 NJ 1520 6110 +preplace netloc axi_mxfe_rx_jesd_sync 1 14 1 NJ 1920 +preplace netloc axi_mxfe_rx_xcvr_up_pll_rst 1 7 6 2530J 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 5330 +preplace netloc axi_mxfe_tx_dma_irq 1 7 1 2560 2060n +preplace netloc axi_mxfe_tx_jesd_irq 1 7 6 2580 2280 NJ 2280 3700J 2270 NJ 2270 NJ 2270 5180 +preplace netloc axi_mxfe_tx_xcvr_up_pll_rst 1 12 1 5190 1780n +preplace netloc axi_sysid_0_rom_addr 1 9 3 3730 2420 NJ 2420 4690 +preplace netloc cpack_reset_sources_dout 1 3 1 930 850n +preplace netloc cpack_rst_logic_Res 1 4 1 NJ 850 +preplace netloc ext_sync_in_1 1 0 11 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 4110 +preplace netloc gpio_i_1 1 0 10 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 2940J 2480 3660 +preplace netloc init_req_1 1 5 3 1840 2430 NJ 2430 2480 +preplace netloc init_req_2 1 7 4 2490J 2010 NJ 2010 NJ 2010 4290 +preplace netloc manual_sync_or_Res 1 10 1 4230 420n +preplace netloc mxfe_rx_data_offload_s_axis_tready 1 1 5 380 1500 NJ 1500 NJ 1500 NJ 1500 1810J +preplace netloc ref_clk_q0_1 1 0 13 NJ 2450 NJ 2450 NJ 2450 NJ 2450 NJ 2450 1760J 2460 NJ 2460 NJ 2460 2870J 2440 NJ 2440 NJ 2440 NJ 2440 5360 +preplace netloc rom_sys_0_rom_data 1 10 1 4310 2190n +preplace netloc rx_data_0_n_1 1 0 13 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 2890J 2450 NJ 2450 NJ 2450 NJ 2450 5340J +preplace netloc rx_data_0_p_1 1 0 13 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 2100J 1690 NJ 1690 2880J 1580 NJ 1580 4190J 1610 4750J 1840 5200J +preplace netloc rx_data_1_n_1 1 0 13 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 2540J 2480 2900J 2460 NJ 2460 NJ 2460 NJ 2460 5240J +preplace netloc rx_data_1_p_1 1 0 13 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 2580J 2490 2910J 2470 NJ 2470 NJ 2470 NJ 2470 5350J +preplace netloc rx_data_2_n_1 1 0 13 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 2500J 3090 2950J 2490 NJ 2490 NJ 2490 NJ 2490 5390J +preplace netloc rx_data_2_p_1 1 0 13 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 2480J 3100 2960J 2500 NJ 2500 NJ 2500 NJ 2500 5380J +preplace netloc rx_data_3_n_1 1 0 13 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 2980J 2520 NJ 2520 NJ 2520 NJ 2520 5420J +preplace netloc rx_data_3_p_1 1 0 13 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 2470J 3110 2970J 2510 NJ 2510 NJ 2510 NJ 2510 5410J +preplace netloc rx_device_clk_1 1 0 14 NJ 1490 370 1490 NJ 1490 NJ 1490 1190 1260 1800 1710 NJ 1710 NJ 1710 2930J 1600 NJ 1600 4200 2050 4720J 2140 5170J 2620 5770J +preplace netloc rx_device_clk_rstgen_peripheral_aresetn 1 2 4 NJ 1640 NJ 1640 NJ 1640 1780 +preplace netloc rx_device_clk_rstgen_peripheral_reset 1 2 1 720 1390n +preplace netloc rx_do_rstout_logic_Res 1 2 1 NJ 1430 +preplace netloc rx_mxfe_tpl_core_adc_data_0 1 4 8 1220 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 4710 +preplace netloc rx_mxfe_tpl_core_adc_data_1 1 4 8 1250 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 4730 +preplace netloc rx_mxfe_tpl_core_adc_data_2 1 4 8 1210 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 4750 +preplace netloc rx_mxfe_tpl_core_adc_data_3 1 4 8 1240 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 4700 +preplace netloc rx_mxfe_tpl_core_adc_data_4 1 4 8 1200 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 4770 +preplace netloc rx_mxfe_tpl_core_adc_data_5 1 4 8 1230 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 4740 +preplace netloc rx_mxfe_tpl_core_adc_data_6 1 4 8 1260 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 4710 +preplace netloc rx_mxfe_tpl_core_adc_data_7 1 4 8 1340 750 NJ 750 NJ 750 NJ 750 NJ 750 NJ 750 NJ 750 4780 +preplace netloc rx_mxfe_tpl_core_adc_enable_0 1 4 8 1270 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 4870 +preplace netloc rx_mxfe_tpl_core_adc_enable_1 1 4 8 1290 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 4850 +preplace netloc rx_mxfe_tpl_core_adc_enable_2 1 4 8 1310 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 4830 +preplace netloc rx_mxfe_tpl_core_adc_enable_3 1 4 8 1280 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 4880 +preplace netloc rx_mxfe_tpl_core_adc_enable_4 1 4 8 1300 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 4860 +preplace netloc rx_mxfe_tpl_core_adc_enable_5 1 4 8 1320 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 4760 +preplace netloc rx_mxfe_tpl_core_adc_enable_6 1 4 8 1330 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 4690 +preplace netloc rx_mxfe_tpl_core_adc_enable_7 1 4 8 1350 760 NJ 760 NJ 760 NJ 760 NJ 760 NJ 760 NJ 760 4790 +preplace netloc rx_mxfe_tpl_core_adc_rst 1 2 10 730 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 4210J 1460 4730 +preplace netloc rx_mxfe_tpl_core_adc_sync_manual_req_out 1 9 3 3710 790 4130J 780 4720 +preplace netloc rx_mxfe_tpl_core_adc_valid_0 1 4 8 1360 770 NJ 770 NJ 770 NJ 770 NJ 770 NJ 770 NJ 770 4890 +preplace netloc spi0_csn_concat_dout 1 14 1 NJ 2890 +preplace netloc spi0_miso_1 1 0 10 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 2590J 3160 3030J 2560 3650 +preplace netloc spi1_csn_concat_dout 1 14 1 NJ 3090 +preplace netloc spi1_miso_1 1 0 10 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 3660 +preplace netloc sync_1 1 0 12 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 2560J 3140 3010J 2540 NJ 2540 NJ 2540 4860J +preplace netloc sys_250m_clk 1 4 7 1310 2210 1780 2350 2160 2440 2520 3180 3050 3250 3730 3120 4280 +preplace netloc sys_250m_reset 1 5 1 N 2320 +preplace netloc sys_250m_resetn 1 5 6 1800 2360 2140 2170 2570 1980 NJ 1980 NJ 1980 4110J +preplace netloc sys_500m_clk 1 9 1 N 3190 +preplace netloc sys_500m_reset 1 10 1 N 3230 +preplace netloc sys_500m_resetn 1 10 1 N 3270 +preplace netloc sys_concat_intc_0_dout 1 8 1 2910J 2620n +preplace netloc sys_concat_intc_1_dout 1 8 1 2920 2150n +preplace netloc sys_cpu_clk 1 0 14 30 2220 NJ 2220 NJ 2220 NJ 2220 NJ 2220 1820 2340 2130 2420 2490 3170 3040 2570 3710 1930 4170 2060 4850 2120 5400 2630 5750 +preplace netloc sys_cpu_reset 1 1 1 N 2120 +preplace netloc sys_cpu_resetn 1 1 13 380 2170 NJ 2170 NJ 2170 NJ 2170 1770 2330 2110 2530 2500 2750 2880 1950 3670 1940 4180 2070 4880 2110 5370 2640 5780 +preplace netloc sys_ps8_emio_gpio_o 1 9 6 NJ 2690 NJ 2690 NJ 2690 NJ 2690 NJ 2690 NJ +preplace netloc sys_ps8_emio_gpio_t 1 9 6 NJ 2710 NJ 2710 NJ 2710 NJ 2710 NJ 2710 NJ +preplace netloc sys_ps8_emio_spi0_m_o 1 9 6 NJ 2810 NJ 2810 NJ 2810 NJ 2810 NJ 2810 NJ +preplace netloc sys_ps8_emio_spi0_sclk_o 1 9 6 NJ 2770 NJ 2770 NJ 2770 NJ 2770 NJ 2770 NJ +preplace netloc sys_ps8_emio_spi0_ss1_o_n 1 9 5 NJ 2890 NJ 2890 NJ 2890 NJ 2890 N +preplace netloc sys_ps8_emio_spi0_ss2_o_n 1 9 5 NJ 2910 NJ 2910 NJ 2910 NJ 2910 N +preplace netloc sys_ps8_emio_spi0_ss_o_n 1 9 5 NJ 2870 NJ 2870 NJ 2870 NJ 2870 N +preplace netloc sys_ps8_emio_spi1_m_o 1 9 6 3690J 3130 4090J 3170 NJ 3170 NJ 3170 NJ 3170 NJ +preplace netloc sys_ps8_emio_spi1_sclk_o 1 9 6 NJ 2970 NJ 2970 NJ 2970 NJ 2970 NJ 2970 NJ +preplace netloc sys_ps8_emio_spi1_ss1_o_n 1 9 5 NJ 3090 NJ 3090 NJ 3090 NJ 3090 N +preplace netloc sys_ps8_emio_spi1_ss2_o_n 1 9 5 NJ 3110 NJ 3110 NJ 3110 NJ 3110 N +preplace netloc sys_ps8_emio_spi1_ss_o_n 1 9 5 NJ 3070 NJ 3070 NJ 3070 NJ 3070 N +preplace netloc sys_ps8_pl_resetn0 1 0 10 20 2230 NJ 2230 NJ 2230 NJ 2230 1190 3270 NJ 3270 NJ 3270 NJ 3270 NJ 3270 3670 +preplace netloc sysref_1 1 0 14 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 2470J 3150 3020J 2550 NJ 2550 NJ 2550 NJ 2550 5180J 2680 5790J +preplace netloc sysref_2 1 0 12 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 2500J 3130 2990J 2530 NJ 2530 NJ 2530 4870J +preplace netloc tx_device_clk_1 1 0 12 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 2940 1610 NJ 1610 4090 1310 4710 +preplace netloc tx_device_clk_rstgen_peripheral_aresetn 1 9 2 3680J 1950 4270 +preplace netloc tx_device_clk_rstgen_peripheral_reset 1 9 1 3660 1400n +preplace netloc tx_mxfe_tpl_core_dac_enable_0 1 11 1 4890 900n +preplace netloc tx_mxfe_tpl_core_dac_enable_1 1 11 1 4880 940n +preplace netloc tx_mxfe_tpl_core_dac_enable_2 1 11 1 4860 980n +preplace netloc tx_mxfe_tpl_core_dac_enable_3 1 11 1 4850 1020n +preplace netloc tx_mxfe_tpl_core_dac_enable_4 1 11 1 4810 1060n +preplace netloc tx_mxfe_tpl_core_dac_enable_5 1 11 1 4800 1100n +preplace netloc tx_mxfe_tpl_core_dac_enable_6 1 11 1 4790 1140n +preplace netloc tx_mxfe_tpl_core_dac_enable_7 1 11 1 4780 1180n +preplace netloc tx_mxfe_tpl_core_dac_rst 1 9 3 3710 1340 4190J 1470 4700 +preplace netloc tx_mxfe_tpl_core_dac_sync_manual_req_out 1 9 3 3710 930 4140J 790 4720 +preplace netloc tx_mxfe_tpl_core_dac_valid_0 1 11 1 4820 920n +preplace netloc upack_reset_sources_dout 1 10 1 4160 1370n +preplace netloc upack_rst_logic_Res 1 11 1 4770J 1190n +preplace netloc util_mxfe_cpack_packed_fifo_wr_data 1 5 1 1820 1020n +preplace netloc util_mxfe_cpack_packed_fifo_wr_en 1 5 1 1830 1000n +preplace netloc util_mxfe_upack_fifo_rd_data_0 1 10 3 4270 800 NJ 800 5170 +preplace netloc util_mxfe_upack_fifo_rd_data_1 1 10 3 4300 810 NJ 810 5200 +preplace netloc util_mxfe_upack_fifo_rd_data_2 1 10 3 4310 820 NJ 820 5220 +preplace netloc util_mxfe_upack_fifo_rd_data_3 1 10 3 4290 1290 4740J 1080 5180 +preplace netloc util_mxfe_upack_fifo_rd_data_4 1 10 3 4280 1300 4750J 1090 5210 +preplace netloc util_mxfe_upack_fifo_rd_data_5 1 10 3 4310 1430 NJ 1430 5220 +preplace netloc util_mxfe_upack_fifo_rd_data_6 1 10 3 4300 1440 NJ 1440 5200 +preplace netloc util_mxfe_upack_fifo_rd_data_7 1 10 3 4270 1450 NJ 1450 5170 +preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 12 2 5440 2650 5740 +preplace netloc util_mxfe_xcvr_tx_0_n 1 13 2 5710J 2120 6150J +preplace netloc util_mxfe_xcvr_tx_0_p 1 13 2 5720J 2110 6140J +preplace netloc util_mxfe_xcvr_tx_1_n 1 13 2 5730J 2150 NJ +preplace netloc util_mxfe_xcvr_tx_1_p 1 13 2 5760J 2130 NJ +preplace netloc util_mxfe_xcvr_tx_2_n 1 13 2 5710J 2190 NJ +preplace netloc util_mxfe_xcvr_tx_2_p 1 13 2 5720J 2170 NJ +preplace netloc util_mxfe_xcvr_tx_3_n 1 13 2 NJ 2250 NJ +preplace netloc util_mxfe_xcvr_tx_3_p 1 13 2 NJ 2230 NJ +preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 11 3 4890 2130 5250 2670 5700 +preplace netloc axi_cpu_interconnect_M00_AXI 1 10 1 4130 1670n +preplace netloc axi_cpu_interconnect_M01_AXI 1 6 5 2170 1700 NJ 1700 2920J 1590 NJ 1590 4080 +preplace netloc axi_cpu_interconnect_M02_AXI 1 10 1 4100 240n +preplace netloc axi_cpu_interconnect_M03_AXI 1 10 4 NJ 1730 4740J 2090 5290J 1530 5810 +preplace netloc axi_cpu_interconnect_M04_AXI 1 6 5 2170 2160 2510J 2020 NJ 2020 NJ 2020 4100 +preplace netloc axi_cpu_interconnect_M05_AXI 1 5 6 1840 1930 NJ 1930 NJ 1930 2940J 1960 NJ 1960 4080 +preplace netloc axi_cpu_interconnect_M06_AXI 1 10 2 4190J 1740 4790 +preplace netloc axi_cpu_interconnect_M07_AXI 1 10 1 4150 920n +preplace netloc axi_cpu_interconnect_M08_AXI 1 10 2 4140J 2030 4840 +preplace netloc axi_cpu_interconnect_M09_AXI 1 6 5 2170 1940 2560J 1990 NJ 1990 NJ 1990 4070 +preplace netloc axi_cpu_interconnect_M10_AXI 1 10 1 4190 1800n +preplace netloc axi_hp0_interconnect_M00_AXI 1 8 1 N 2830 +preplace netloc axi_hp1_interconnect_M00_AXI 1 8 1 3000 2850n +preplace netloc axi_hp2_interconnect_M00_AXI 1 8 1 2930 2360n +preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 7 1 2510 2280n +preplace netloc axi_mxfe_rx_xcvr_m_axi 1 7 1 2550 1430n +preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 7 6 NJ 1470 NJ 1470 3690J 1490 NJ 1490 NJ 1490 5400 +preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 7 6 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 5220 +preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 7 6 2480J 1540 NJ 1540 NJ 1540 NJ 1540 NJ 1540 5200 +preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 7 6 2510J 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 5350 +preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 7 6 NJ 1450 2880J 1460 3710J 1480 NJ 1480 NJ 1480 5440 +preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 7 6 NJ 1490 NJ 1490 3670J 1500 NJ 1500 NJ 1500 5230 +preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 7 6 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 5210 +preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 7 6 2490J 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 5370 +preplace netloc axi_mxfe_tx_dma_m_src_axi 1 7 1 2500 2020n +preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 12 1 5300 1680n +preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 12 1 5320 1760n +preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 12 1 5340 1840n +preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 12 1 5350 1920n +preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 12 1 5280 1660n +preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 12 1 5190 1700n +preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 12 1 5180 1720n +preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 12 1 5170 1740n +preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 12 1 5270 1600n +preplace netloc mxfe_rx_data_offload_m_axis 1 6 1 2120 2130n +preplace netloc mxfe_tx_data_offload_m_axis 1 11 1 4760 1150n +preplace netloc s_axis_1 1 7 4 2480J 2000 NJ 2000 NJ 2000 4250 +preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 9 1 3690 1750n +preplace netloc tx_mxfe_tpl_core_link 1 11 1 4830 880n +preplace netloc util_mxfe_xcvr_rx_0 1 13 1 N 1890 +preplace netloc util_mxfe_xcvr_rx_1 1 13 1 N 1910 +preplace netloc util_mxfe_xcvr_rx_2 1 13 1 N 1930 +preplace netloc util_mxfe_xcvr_rx_3 1 13 1 N 1950 +levelinfo -pg 1 0 200 550 830 1060 1560 1970 2320 2720 3350 3900 4500 5030 5570 5960 6170 +pagesize -pg 1 -db -bbox -sgen -150 0 6320 3320 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_system() + +cr_bd_system "" +set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] + +set idrFlowPropertiesConstraints "" +catch { + set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints] + set_param runs.disableIDRFlowPropertyConstraints 1 +} + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2023} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2023" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2023} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2023" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] +catch { + if { $idrFlowPropertiesConstraints != {} } { + set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints + } +} + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/mem_init_sys.txt b/mem_init_sys.txt new file mode 100644 index 0000000..0331a55 --- /dev/null +++ b/mem_init_sys.txt @@ -0,0 +1,512 @@ +00000002 +00000010 +000001d0 +000001d8 +000001e0 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +63000000 +6e69616d +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +37656439 +30303939 +36643732 +38613839 +63653239 +62393030 +61333163 +34333835 +31326132 +39336363 +00000000 +00000074 +6a646176 +34313731 +31343537 +00003139 +00000000 +d0000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 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xilinx_anylanguagesynthesis_view_fileset + + src/dds_cmd_gen.vhd + vhdlSource + my_source + + + src/dds_pulse_2x_top.vhd + vhdlSource + my_source + + + src/dds_pulse_gen.vhd + vhdlSource + my_source + + + src/dds_pulse_wrapper.vhd + vhdlSource + CHECKSUM_31bcb16e + my_source + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dds_cmd_gen.vhd + vhdlSource + my_source + + + src/dds_pulse_2x_top.vhd + vhdlSource + my_source + + + src/dds_pulse_gen.vhd + vhdlSource + my_source + + + src/dds_pulse_wrapper.vhd + vhdlSource + my_source + + + + xilinx.com:ip:my_source:1.0 + + + Component_Name + my_source_v1_0 + + + + + my_source_v1_0 + true + package_project + 2 + 2023-09-07T17:00:31Z + + + 2022.2 + + + + + diff --git a/my_source/ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci b/my_source/ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci new file mode 100644 index 0000000..737a9ac --- /dev/null +++ b/my_source/ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci @@ -0,0 +1,227 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "adder_16signed_16signed_latency2", + "component_reference": "xilinx.com:ip:c_addsub:12.0", + "ip_revision": "14", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ], + "Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ], + "A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], + "B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], + "A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Add_Mode": [ { "value": "Add", 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{ "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplus" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu9eg" } ], + "PACKAGE": [ { "value": "ffvb1156" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + 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"direction": "out", "size_left": "16", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "a_intf": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "slave", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "A" } ] + } + }, + "clk_intf": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "SCLR", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_CLKEN": [ { "value": "CE", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": 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file mode 100644 index 0000000..afd62d6 --- /dev/null +++ b/my_source/src/dds_cmd_gen.vhd @@ -0,0 +1,154 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity dds_cmd_gen is + port( + clk_in : in std_logic; + cmd_idx_in : in std_logic_vector( 1 downto 0); + cmd_send_in : in std_logic; + + fifo_rd_clk_in : in std_logic; + fifo_rd_data_out : out std_logic_vector(31 downto 0); + fifo_rd_dval_out : out std_logic; + fifo_rd_rd_en_in : in std_logic; + fifo_rd_empty_out : out std_logic; + + rst_in : in std_logic + ); +end entity dds_cmd_gen; + +architecture imp of dds_cmd_gen is + + signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0'); + signal fifo_wr_en_r : std_logic := '0'; + + signal cmd_idx_r : integer range 0 to 3 := 0; + signal cmd_send_r : std_logic := '0'; + + type fsm_state is (IDLE, SEND, DONE); + signal state_r : fsm_state := IDLE; + signal state_cnt_r : integer := 0; + + type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0); + type dds_command_list is array (integer range <>) of array_32b_type; + constant dds_command_set : dds_command_list(0 to 3) := + ( + -- WFM 0 + -- FREQUENCY SWEEP (UP-SWEEP) + 0 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000000", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) + x"010624DD", --PHASE_INC (~1 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 1 + -- FREQUENCY SWEEP (DOWN-SWEEP) + 1 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000050", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 2 + -- CW TONE + 2 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone) + x"00000050", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) +-- x"000FFFFF", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 3 + -- FREQUENCY SWEEP (DOWN-SWEEP) + 3 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000050", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ) + ); + +begin + + process(clk_in) + begin + if (rising_edge(clk_in)) then + if (rst_in = '1') then + cmd_idx_r <= 0; + cmd_send_r <= '0'; + fifo_wr_en_r <= '0'; + state_cnt_r <= 0; + state_r <= IDLE; + else + cmd_send_r <= cmd_send_in; + fifo_wr_en_r <= '0'; + + case (state_r) is + when IDLE => + if (cmd_send_in = '1' and cmd_send_r = '0') then + cmd_idx_r <= conv_integer(unsigned(cmd_idx_in)); + state_cnt_r <= 0; + state_r <= SEND; + else + state_r <= IDLE; + end if; + + when SEND => + if (state_cnt_r = 8) then + state_r <= DONE; + else + fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r); + fifo_wr_en_r <= '1'; + state_cnt_r <= state_cnt_r + 1; + state_r <= SEND; + end if; + + when DONE => + state_r <= IDLE; + + when others => + state_r <= IDLE; + + end case; + end if; + end if; + end process; + + + i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1 + port map( + wr_clk => clk_in, + din => fifo_wr_data_r, + wr_en => fifo_wr_en_r, + full => open, + overflow => open, + + + rd_clk => fifo_rd_clk_in, + dout => fifo_rd_data_out, + valid => fifo_rd_dval_out, + rd_en => fifo_rd_rd_en_in, + empty => fifo_rd_empty_out, + + underflow => open, + prog_full => open, + wr_rst_busy => open, + rd_rst_busy => open, + srst => rst_in + ); + +end architecture imp; diff --git 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"aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + }, + "port_maps": { + "CE": [ { "physical_name": "aclken" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/my_source/src/dds_pulse_2x_top.vhd b/my_source/src/dds_pulse_2x_top.vhd new file mode 100644 index 0000000..8e53f95 --- /dev/null +++ b/my_source/src/dds_pulse_2x_top.vhd @@ -0,0 +1,419 @@ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M. Blevins +-- +-- Create Date: 19:38:12 11/10/2016 +-- Design Name: +-- Module Name: dds_pulse_2x_top - behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- * All information is proprietary/confidential * +-- +-- Supports single channel mode or dual channel (summed) mode. +-- When using dual channel mode, the module hangs after the shortest of the +-- two pulse streams completes. Ideally, both streams will be equal length. +-- +-- For each channel: +-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO. +-- The control word contains all information needed to create a pulse +-- +-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits +-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies +-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000 +-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000 +-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits +-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits +-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits +-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit +-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!) +-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits +-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--Library UNIMACRO; +--use UNIMACRO.vcomponents.all; +USE IEEE.NUMERIC_STD.ALL; + +entity dds_pulse_2x_top is + port( + clk_in : in std_logic; + rst_in : in std_logic; + mode_in : in std_logic; -- 0=single, 1=dual + scale_in : in std_logic_vector(15 downto 0); + fifo1_data_in : in std_logic_vector(31 downto 0); + fifo1_dval_in : in std_logic; + fifo1_empty_in : in std_logic; + fifo1_rden_out : out std_logic; + fifo2_data_in : in std_logic_vector(31 downto 0); + fifo2_dval_in : in std_logic; + fifo2_empty_in : in std_logic; + fifo2_rden_out : out std_logic; + holdoff_in : in std_logic; + overflow_out : out std_logic_vector(1 downto 0); + underflow_out : out std_logic_vector(1 downto 0); + i_max_abs_out : out std_logic_vector(15 downto 0); + q_max_abs_out : out std_logic_vector(15 downto 0); + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); +end entity; + +architecture mixed of dds_pulse_2x_top is + + component mult_16signed_x_16unsigned_latency3 + port( + clk : in std_logic; + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + ce : in std_logic; + sclr : in std_logic; + p : out std_logic_vector(15 downto 0) + ); + end component; + + component dds_pulse_gen is + port( + clk_in : in std_logic; + rst_in : in std_logic; + fifo_data_in : in std_logic_vector(31 downto 0); + fifo_dval_in : in std_logic; + fifo_empty_in : in std_logic; + fifo_rden_out : out std_logic; + holdoff_in : in std_logic; + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); + end component; + + component sfifo_32b_1024_pf992_latency1 + port( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(31 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(31 downto 0); + full : out std_logic; + overflow : out std_logic; + empty : out std_logic; + underflow : out std_logic; + prog_full : out std_logic + ); + end component; + + component adder_16signed_16signed_latency2 + port( + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + clk : in std_logic; + ce : in std_logic; + bypass : in std_logic; + s : out std_logic_vector(16 downto 0) + ); + end component; + + signal rst_r : std_logic := '1'; + signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual + signal scale_r : std_logic_vector(15 downto 0) := x"8000"; + signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00"; + signal pulse_adder_dval_r : std_logic := '0'; + signal pulse_adder_ce : std_logic; + signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0'); + signal pulse_dval_r : std_logic := '0'; + signal adder_dval_r : std_logic := '0'; + signal holdoff_r : std_logic; + + signal pulse1_mult_dval_r : std_logic := '0'; + signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal pulse1_mult_ce : std_logic; + signal pulse1_data : std_logic_vector(31 downto 0); + signal pulse1_dval : std_logic; + signal pulse1_data_scaled : std_logic_vector(31 downto 0); + signal pulse1_fifo_overflow : std_logic; + signal pulse1_fifo_empty : std_logic; + signal pulse1_fifo_underflow : std_logic; + signal pulse1_fifo_progfull : std_logic; + signal pulse1_fifo_rden : std_logic; + signal pulse1_fifo_rden_r : std_logic := '0'; + signal pulse1_fifo_dout : std_logic_vector(31 downto 0); + signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0'); + signal adder1_s : std_logic_vector(16 downto 0); + signal adder1_s_r : std_logic_vector(16 downto 0); + signal adder1_s_r1 : std_logic_vector(15 downto 0); + signal i_abs_max_r : unsigned(15 downto 0); + signal fifo1_underflow_r : std_logic := '0'; + signal fifo1_overflow_r : std_logic := '0'; + + signal pulse2_mult_dval_r : std_logic := '0'; + signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal pulse2_mult_ce : std_logic; + signal pulse2_data : std_logic_vector(31 downto 0); + signal pulse2_dval : std_logic; + signal pulse2_data_scaled : std_logic_vector(31 downto 0); + signal pulse2_fifo_overflow : std_logic; + signal pulse2_fifo_empty : std_logic; + signal pulse2_fifo_underflow : std_logic; + signal pulse2_fifo_progfull : std_logic; + signal pulse2_fifo_rden : std_logic; + signal pulse2_fifo_dout : std_logic_vector(31 downto 0); + signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0); + signal adder2_s : std_logic_vector(16 downto 0); + signal adder2_s_r : std_logic_vector(16 downto 0); + signal adder2_s_r1 : std_logic_vector(15 downto 0); + signal q_abs_max_r : unsigned(15 downto 0); + signal fifo2_underflow_r : std_logic := '0'; + signal fifo2_overflow_r : std_logic := '0'; + +begin + + data_out <= pulse_data_r; + dval_out <= pulse_dval_r; + i_max_abs_out <= std_logic_vector(i_abs_max_r); + q_max_abs_out <= std_logic_vector(q_abs_max_r); + overflow_out <= fifo2_overflow_r & fifo1_overflow_r; + underflow_out <= fifo2_underflow_r & fifo1_underflow_r; + + process(clk_in) + begin + if(rising_edge(clk_in))then + rst_r <= rst_in; + scale_r <= scale_in; + mode_n_r <= not(mode_in); + holdoff_r <= holdoff_in; + end if; + end process; + + process(clk_in) + begin + if(rising_edge(clk_in))then + pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1); + pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval; + pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1); + pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval; + pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r; + pulse_adder_dval_r <= pulse_fifo_dval_r(1); + pulse1_fifo_rden_r <= pulse1_fifo_rden; + pulse1_fifo_dout_r <= pulse1_fifo_dout; + pulse2_fifo_dout_r <= pulse2_fifo_dout; + end if; + end process; + + pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval; + pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval; + + pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else + not(pulse1_fifo_empty) and not(holdoff_r); + + pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else + '0'; + + pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0); + + i_dds_pulse1_gen : dds_pulse_gen + port map( + clk_in => clk_in, + rst_in => rst_r, + fifo_data_in => fifo1_data_in, + fifo_dval_in => fifo1_dval_in, + fifo_empty_in => fifo1_empty_in, + fifo_rden_out => fifo1_rden_out, + holdoff_in => pulse1_fifo_progfull, + data_out => pulse1_data, + dval_out => pulse1_dval + ); + + i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse1_data(15 downto 0), + b => scale_r, + ce => pulse1_mult_ce, + sclr => '0', + p => pulse1_data_scaled(15 downto 0) + ); + + i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse1_data(31 downto 16), + b => scale_r, + ce => pulse1_mult_ce, + sclr => '0', + p => pulse1_data_scaled(31 downto 16) + ); + + i_pulse1_fifo : sfifo_32b_1024_pf992_latency1 + port map( + clk => clk_in, + srst => rst_r, + din => pulse1_data_scaled, + wr_en => pulse1_mult_dval_r, + rd_en => pulse1_fifo_rden, + dout => pulse1_fifo_dout, + full => open, + overflow => pulse1_fifo_overflow, + empty => pulse1_fifo_empty, + underflow => pulse1_fifo_underflow, + prog_full => pulse1_fifo_progfull + ); + + i_dds_pulse2_gen : dds_pulse_gen + port map( + clk_in => clk_in, + rst_in => rst_r, + fifo_data_in => fifo2_data_in, + fifo_dval_in => fifo2_dval_in, + fifo_empty_in => fifo2_empty_in, + fifo_rden_out => fifo2_rden_out, + holdoff_in => pulse2_fifo_progfull, + data_out => pulse2_data, + dval_out => pulse2_dval + ); + + i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse2_data(15 downto 0), + b => scale_r, + ce => pulse2_mult_ce, + sclr => '0', + p => pulse2_data_scaled(15 downto 0) + ); + + i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse2_data(31 downto 16), + b => scale_r, + ce => pulse2_mult_ce, + sclr => '0', + p => pulse2_data_scaled(31 downto 16) + ); + + i_pulse2_fifo : sfifo_32b_1024_pf992_latency1 + port map( + clk => clk_in, + srst => rst_r, + din => pulse2_data_scaled, + wr_en => pulse2_mult_dval_r, + rd_en => pulse2_fifo_rden, + dout => pulse2_fifo_dout, + full => open, + overflow => pulse2_fifo_overflow, + empty => pulse2_fifo_empty, + underflow => pulse2_fifo_underflow, + prog_full => pulse2_fifo_progfull + ); + + i_pulse_adder1 : adder_16signed_16signed_latency2 + port map( + a => pulse2_fifo_dout_r(15 downto 0), + b => pulse1_fifo_dout_r(15 downto 0), + clk => clk_in, + ce => pulse_adder_ce, + bypass => mode_n_r, -- when set to '1', b input proceeds to s output + s => adder1_s + ); + + i_pulse_adder2 : adder_16signed_16signed_latency2 + port map( + a => pulse2_fifo_dout_r(31 downto 16), + b => pulse1_fifo_dout_r(31 downto 16), + clk => clk_in, + ce => pulse_adder_ce, + bypass => mode_n_r, -- when set to '1', b input proceeds to s output + s => adder2_s + ); + + process(clk_in) + begin + if(rising_edge(clk_in))then + adder1_s_r <= adder1_s; + adder2_s_r <= adder2_s; + adder_dval_r <= pulse_adder_dval_r; + pulse_dval_r <= adder_dval_r; + if(adder_dval_r = '1')then + case adder1_s_r(16 downto 15) is + when "01" => --positive overflow + pulse_data_r(15 downto 0) <= x"7FFF"; + when "10" => --negative overflow + pulse_data_r(15 downto 0) <= x"8000"; + when others => + pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0); + end case; + case adder2_s_r(16 downto 15) is + when "01" => --positive overflow + pulse_data_r(31 downto 16) <= x"7FFF"; + when "10" => --negative overflow + pulse_data_r(31 downto 16) <= x"8000"; + when others => + pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0); + end case; + end if; + if(rst_r = '1')then + --adder_dval_r <= '0'; + --pulse_dval_r <= '0'; + i_abs_max_r <= (others => '0'); + q_abs_max_r <= (others => '0'); + fifo1_overflow_r <= '0'; + fifo1_underflow_r <= '0'; + fifo2_overflow_r <= '0'; + fifo2_underflow_r <= '0'; + else + --adder_dval_r <= pulse_adder_dval_r; + --pulse_dval_r <= adder_dval_r; + if(pulse1_fifo_overflow = '1')then + fifo1_overflow_r <= '1'; + end if; + if(pulse1_fifo_underflow = '1')then + fifo1_underflow_r <= '1'; + end if; + if(pulse2_fifo_overflow = '1')then + fifo2_overflow_r <= '1'; + end if; + if(pulse2_fifo_underflow = '1')then + fifo2_underflow_r <= '1'; + end if; + if(adder_dval_r = '1')then + -- if(abs(signed(adder1_s_r)) > i_abs_max_r)then + -- i_abs_max_r <= abs(signed(adder1_s_r)); + -- end if; + if(adder1_s_r(16) = '0')then + adder1_s_r1 <= adder1_s_r(15 downto 0); + else + adder1_s_r1 <= not(adder1_s_r(15 downto 0)); + end if; + + -- if(abs(signed(adder2_s_r)) > q_abs_max_r)then + -- q_abs_max_r <= abs(signed(adder2_s_r)); + -- end if; + if(adder2_s_r(16) = '0')then + adder2_s_r1 <= adder2_s_r(15 downto 0); + else + adder2_s_r1 <= not(adder2_s_r(15 downto 0)); + end if; + end if; + if(pulse_dval_r = '1')then + if(unsigned(adder1_s_r1) > i_abs_max_r)then + i_abs_max_r <= unsigned(adder1_s_r1); + end if; + if(unsigned(adder2_s_r1) > q_abs_max_r)then + q_abs_max_r <= unsigned(adder2_s_r1); + end if; + end if; + end if; + end if; + end process; + +end mixed; + \ No newline at end of file diff --git a/my_source/src/dds_pulse_gen.vhd b/my_source/src/dds_pulse_gen.vhd new file mode 100644 index 0000000..6291cf5 --- /dev/null +++ b/my_source/src/dds_pulse_gen.vhd @@ -0,0 +1,415 @@ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M. Blevins +-- +-- Create Date: 19:38:12 11/10/2016 +-- Design Name: +-- Module Name: dds_pulse_gen - behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - Added Sweep Functionality 10-17-2017 +-- Additional Comments: +-- * All information is proprietary/confidential * +-- +-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO. +-- The control word contains all information needed to create a pulse +-- +-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits +-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies +-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000 +-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000 +-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits +-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits +-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits +-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit +-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!) +-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits +-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits +-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--Library UNIMACRO; +--use UNIMACRO.vcomponents.all; +USE IEEE.NUMERIC_STD.ALL; + +entity dds_pulse_gen is + port( + clk_in : in std_logic; + rst_in : in std_logic; + fifo_data_in : in std_logic_vector(31 downto 0); + fifo_dval_in : in std_logic; + fifo_empty_in : in std_logic; + fifo_rden_out : out std_logic; + holdoff_in : in std_logic; + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); +end entity; + +architecture mixed of dds_pulse_gen is + + component mult_16signed_x_16unsigned_latency3 + port( + clk : in std_logic; + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + ce : in std_logic; + sclr : in std_logic; + p : out std_logic_vector(15 downto 0) + ); + end component; + + component dds_latency10 + port( + -- ce : in std_logic; + -- clk : in std_logic; + -- sclr : in std_logic; + -- pinc_in : in std_logic_vector(31 downto 0); + -- poff_in : in std_logic_vector(31 downto 0); + -- rdy : out std_logic; + -- cosine : out std_logic_vector(15 downto 0); + -- sine : out std_logic_vector(15 downto 0) + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + end component; + + component addsub + port ( + a : in std_logic_vector(31 downto 0); -- unsigned + b : in std_logic_vector(23 downto 0); -- signed + --clk : in std_logic; + s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency. + ); + end component; + + constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000"; + + type state_type is (s0, s0a, s0b, s0c, s1, s2, s3); + signal state : state_type; + signal state_r : state_type; + signal rst_r : std_logic := '1'; + signal rstn_r : std_logic := '0'; + + signal cnt1_r : unsigned(3 downto 0) := "0000"; + signal cnt1 : unsigned(3 downto 0); + signal cnt2_r : unsigned(2 downto 0) := "000"; + signal cnt2 : unsigned(2 downto 0); + signal cnt3_r : unsigned(31 downto 0) := x"00000000"; + signal cnt3 : unsigned(31 downto 0); + signal cnt4_r : unsigned(31 downto 0) := x"00000000"; + signal cnt4 : unsigned(31 downto 0); + signal cnt5_r : unsigned(3 downto 0) := "0000"; + signal cnt5 : unsigned(3 downto 0); + signal fifo_data_ce : std_logic; + signal fifo_data_r : std_logic_vector(255 downto 0); + signal fifo_rden : std_logic; + --signal fifo_rden_r : std_logic := '0'; + signal dval_r : std_logic := '0'; + signal dval : std_logic; + signal dds_data : std_logic_vector(31 downto 0); + signal data : std_logic_vector(31 downto 0); + signal data_r : std_logic_vector(31 downto 0); + signal idle_sample_cnt_r : unsigned(31 downto 0); + signal idle_sample_cnt_r1 : unsigned(31 downto 0); + signal dds_sample_cnt_r : unsigned(31 downto 0); + signal dds_sample_cnt_r1 : unsigned(31 downto 0); + signal phase_inc_init_r : std_logic_vector(31 downto 0); + signal phase_offset_r : std_logic_vector(31 downto 0); + signal swap_r : std_logic := '0'; + signal scale_r : std_logic_vector(15 downto 0); + signal mult_dval_r : std_logic := '0'; + signal data_swap_scaled : std_logic_vector(31 downto 0); + signal data_scaled : std_logic_vector(31 downto 0); + signal dds_ce : std_logic; + signal dds_rst : std_logic; + signal dds_rdy : std_logic; + signal mult_ce : std_logic; + signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal holdoff_r : std_logic; + + --signal phase_inc_mux_sel : std_logic; + signal phase_inc_update_en : std_logic; + --signal phase_inc_mux : std_logic_vector(31 downto 0); + signal phase_inc : std_logic_vector(31 downto 0); + signal phase_inc_r : std_logic_vector(31 downto 0); + signal phase_inc_r1 : std_logic_vector(31 downto 0); + signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0'); + signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000"; + signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000"; + signal phase_inc_dwell_cnt : unsigned(15 downto 0); + signal phase_inc_addsub : std_logic_vector(31 downto 0); + signal rstn : std_logic; + +begin + + + + i_addsub : addsub + port map( + a => phase_inc_r, + b => phase_inc_step_r, + --clk => clk_in, + s => phase_inc_addsub + ); + + fifo_rden_out <= fifo_rden;--fifo_rden_r; + data_out <= data_r; + dval_out <= dval_r; + + process(clk_in) + begin + if(rising_edge(clk_in))then + if(rst_r = '1')then + state_r <= s0; + cnt1_r <= (others => '0'); + cnt2_r <= (others => '0'); + cnt3_r <= (others => '0'); + cnt4_r <= (others => '0'); + cnt5_r <= (others => '0'); + phase_inc_dwell_cnt_r <= (others => '0'); + else + state_r <= state; + cnt1_r <= cnt1; + cnt2_r <= cnt2; + cnt3_r <= cnt3; + cnt4_r <= cnt4; + cnt5_r <= cnt5; + phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt; + end if; + if(fifo_data_ce = '1')then + fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in; + end if; + rst_r <= rst_in; + rstn_r <= not(rst_in); + dval_r <= dval; + phase_offset_r <= fifo_data_r(223 downto 192); + -- phase_inc_init_r <= fifo_data_r(191 downto 160); + dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128)); + dds_sample_cnt_r1 <= dds_sample_cnt_r; + swap_r <= fifo_data_r(240); + scale_r <= fifo_data_r(239 downto 224); + idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96)); + idle_sample_cnt_r1 <= idle_sample_cnt_r; + phase_inc_step_r <= fifo_data_r(87 downto 64); + phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32)); + data_r <= data; + holdoff_r <= holdoff_in; + phase_inc_r <= phase_inc; + + if(phase_inc_update_en = '1')then + phase_inc_r1 <= phase_inc_r; + end if; + + end if; + end process; + + + phase_inc_init_r <= fifo_data_r(191 downto 160); + + -- FSM next-state & output process + process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r, + mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub) + begin + --defaults + fifo_rden <= '0'; + cnt1 <= cnt1_r; + cnt2 <= cnt2_r; + cnt3 <= cnt3_r; + cnt4 <= cnt4_r; + cnt5 <= cnt5_r; + state <= state_r; + dds_ce <= '0'; + dds_rst <= '1'; + dval <= mult_dval_r; + data <= data_swap_scaled; + fifo_data_ce <= '0'; + phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r; + phase_inc <= phase_inc_r; + phase_inc_update_en <= '0'; + + case state_r is + + when s0 => + phase_inc_dwell_cnt <= (others => '0'); + if(fifo_empty_in = '0' and cnt1_r < 8)then + fifo_rden <= '1'; + cnt1 <= cnt1_r +1; + end if; + if(fifo_dval_in = '1')then + fifo_data_ce <= '1'; + if(cnt2_r < 7)then + cnt2 <= cnt2_r +1; + else + cnt2 <= (others => '0'); + cnt1 <= (others => '0'); + state <= s0a; + end if; + end if; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + when s0a => + state <= s0b;--s1; + phase_inc <= phase_inc_init_r; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + when s0b => + state <= s1; + phase_inc_update_en <= '1'; + phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + -- when s0c => + -- state <= s1; + -- phase_inc_update_en <= '1'; + -- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + + + -- Insert midpoint (idle) samples that preceed the pulse. + when s1 => + data <= MIDPOINT; + if(cnt3_r < idle_sample_cnt_r1)then + if(holdoff_r = '0')then + cnt3 <= cnt3_r +1; + dval <= '1'; + end if; + else + cnt3 <= (others => '0'); + if(dds_sample_cnt_r1 > 0)then + state <= s2; + else + state <= s0; + end if; + end if; + + -- Turn on DDS for requested number of samples. + when s2 => + dds_rst <= '0'; + + if(holdoff_r = '0')then + if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then + phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1; + else + phase_inc_dwell_cnt <= (others => '0'); + phase_inc_update_en <= '1'; + phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + end if; + end if; + + if(holdoff_r = '0')then + dds_ce <= '1'; + if(cnt4_r < dds_sample_cnt_r1)then + cnt4 <= cnt4_r +1; + else + cnt4 <= (others => '0'); + state <= s3; + end if; + end if; + + -- phase_inc_mux_sel <= '1'; + -- --phase_inc_en <= not(holdoff_r); + -- dds_rst <= '0'; + -- if(cnt4_r < dds_sample_cnt_r1)then + -- if(holdoff_r = '0')then + -- dds_ce <= '1'; + -- cnt4 <= cnt4_r +1; + -- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then + -- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1; + -- else + -- phase_inc_dwell_cnt <= x"00000"; + -- phase_inc_en <= '1'; + -- end if; + -- end if; + -- else + -- if(holdoff_r = '0')then + -- dds_ce <= '1'; + -- cnt4 <= (others => '0'); + -- state <= s3; + -- end if; + -- end if; + + -- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out). + when s3 => + dds_rst <= '0'; + if(cnt5_r < 9)then + if(holdoff_r = '0')then + dds_ce <= '1'; + cnt5 <= cnt5_r +1; + end if; + else + cnt5 <= (others => '0'); + state <= s0; + end if; + when others => + end case; + end process; + + process(clk_in) + begin + if(rising_edge(clk_in))then + mult_dval_r <= mult_ce_pipe_r(1); + mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce); + end if; + end process; + + data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16); + mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce); + + i_dds : dds_latency10 + port map( + -- ce => dds_ce, + -- clk => clk_in, + -- sclr => dds_rst, + -- pinc_in => phase_inc_r1, + -- poff_in => phase_offset_r, + -- rdy => dds_rdy, + -- cosine => dds_data(15 downto 0), + -- sine => dds_data(31 downto 16) + aclk => clk_in, + aclken => dds_ce, + aresetn => rstn_r, + s_axis_phase_tvalid => dds_ce, + s_axis_phase_tdata => phase_inc_r1, + m_axis_data_tvalid => dds_rdy, + m_axis_data_tdata => dds_data(31 downto 0) + ); + + i_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => dds_data(15 downto 0), + b => scale_r, + ce => mult_ce, + sclr => '0', + p => data_scaled(15 downto 0) + ); + + i_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => dds_data(31 downto 16), + b => scale_r, + ce => mult_ce, + sclr => '0', + p => data_scaled(31 downto 16) + ); + +end mixed; + \ No newline at end of file diff --git a/my_source/src/dds_pulse_wrapper.vhd b/my_source/src/dds_pulse_wrapper.vhd new file mode 100644 index 0000000..ebf7b98 --- /dev/null +++ b/my_source/src/dds_pulse_wrapper.vhd @@ -0,0 +1,222 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity dds_pulse_wrapper is + generic ( + SIM_ENABLED : boolean := FALSE + ); + port( + clk_in : in std_logic; + + m_axis_aclk_in : in std_logic; + + m_axis_tdata_out : out std_logic_vector(127 downto 0); + m_axis_tvalid_out : out std_logic; + m_axis_tready_in : in std_logic; + + rst_in : in std_logic + ); +end entity dds_pulse_wrapper; + +architecture imp of dds_pulse_wrapper is + + constant ok_clk_in_period : time := 10 ns; + + signal reset_n : std_logic; + signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001"; + + signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0'); + signal dds_pulse_dval_r : std_logic := '0'; + + signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0'); + + signal cmd_idx : std_logic_vector( 1 downto 0) := "00"; + signal cmd_send : std_logic := '0'; + + signal mode : std_logic := '0'; + signal scale : std_logic_vector(15 downto 0) := x"0000"; + signal dac_holdoff : std_logic := '1'; + + signal dds_pulse_dval : std_logic; + signal dds_pulse_dout : std_logic_vector(31 downto 0); + signal pulse_i : std_logic_vector(15 downto 0); + signal pulse_q : std_logic_vector(15 downto 0); + + signal pipe_in_ch1_fifo_rden : std_logic; + signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0); + signal pipe_in_ch1_fifo_rd_dval : std_logic; + signal pipe_in_ch1_fifo_empty : std_logic; + signal pipe_in_ch2_fifo_rden : std_logic; + +begin + + reset_n <= not rst_in; + + sim_false : if (SIM_ENABLED = FALSE) generate + i_vio_0 : entity work.vio_0 + port map ( + clk => clk_in, + probe_out0(0) => mode, -- 1 + probe_out1 => scale, -- 16 + probe_out2 => cmd_idx, -- 2 + probe_out3(0) => cmd_send -- 1 + ); + end generate sim_false; + + i_dds_cmd_gen : entity work.dds_cmd_gen + port map ( + clk_in => clk_in, + cmd_idx_in => cmd_idx, + cmd_send_in => cmd_send, + + fifo_rd_clk_in => m_axis_aclk_in, + fifo_rd_data_out => pipe_in_ch1_fifo_rd_data, + fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval, + fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden, + fifo_rd_empty_out => pipe_in_ch1_fifo_empty, + + rst_in => rst_in + ); + + i_dds_pulse_2x_top : entity work.dds_pulse_2x_top + port map( + clk_in => m_axis_aclk_in, + rst_in => rst_in, + mode_in => mode, -- 0=single, 1=dual + scale_in => scale, + fifo1_data_in => pipe_in_ch1_fifo_rd_data, + fifo1_dval_in => pipe_in_ch1_fifo_rd_dval, + fifo1_empty_in => pipe_in_ch1_fifo_empty, + fifo1_rden_out => pipe_in_ch1_fifo_rden, + fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data, + fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval, + fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty, + fifo2_rden_out => pipe_in_ch2_fifo_rden, + holdoff_in => dac_holdoff, + overflow_out => open, + underflow_out => open, + i_max_abs_out => open, + q_max_abs_out => open, + data_out => dds_pulse_dout, + dval_out => dds_pulse_dval + ); + + pulse_i <= dds_pulse_dout(15 downto 0); + pulse_q <= dds_pulse_dout(31 downto 16); + + process(m_axis_aclk_in) + begin + if (rising_edge(m_axis_aclk_in)) then + dds_pulse_dval_r <= '0'; + + if (dds_pulse_dval_r = '1') then + dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1; + end if; + + if (dds_pulse_dval = '1') then + s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3); + + if (s_axis_keep_r = "0001") then + dds_pulse_data_r(31 downto 0) <= dds_pulse_dout; + elsif (s_axis_keep_r = "0010") then + dds_pulse_data_r(63 downto 32) <= dds_pulse_dout; + elsif (s_axis_keep_r = "0100") then + dds_pulse_data_r(95 downto 64) <= dds_pulse_dout; + elsif (s_axis_keep_r = "1000") then + dds_pulse_data_r(127 downto 96) <= dds_pulse_dout; + dds_pulse_dval_r <= '1'; + end if; + end if; + end if; + end process; + + + i_fifo : entity work.axis_data_fifo_512x128 + port map ( + s_axis_aclk => m_axis_aclk_in, + s_axis_aresetn => reset_n, + + s_axis_tdata => dds_pulse_data_r, + s_axis_tvalid => dds_pulse_dval_r, + s_axis_tready => open, + + m_axis_tdata => m_axis_tdata_out, + m_axis_tvalid => m_axis_tvalid_out, + m_axis_tready => m_axis_tready_in + ); + + sim_true : if (SIM_ENABLED = TRUE) generate + -- Stimulus process + stim_proc: process + begin + + wait for 200 ns; + wait for 200 ns; + wait for 200 ns; + wait until rising_edge(clk_in); + wait for 1 ns; + mode <= '0'; + scale <= x"8000"; + dac_holdoff <= '0'; + + wait for ok_clk_in_period*10; + wait until rising_edge(clk_in); + --dac_holdoff <= '0'; + + -- WFM 0 + -- FREQUENCY SWEEP (UP-SWEEP) + wait until rising_edge(clk_in); + cmd_idx <= "00"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + + -- WFM 1 + -- FREQUENCY SWEEP (DOWN-SWEEP) + wait until rising_edge(clk_in); + cmd_idx <= "01"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + + + -- WFM 2 + -- CW TONE + wait until rising_edge(clk_in); + cmd_idx <= "10"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + + -- WFM 4 + -- CW TONE + wait until rising_edge(clk_in); + cmd_idx <= "11"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; 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newline at end of file diff --git a/my_source/src/system_top.v b/my_source/src/system_top.v new file mode 100644 index 0000000..46675dc --- /dev/null +++ b/my_source/src/system_top.v @@ -0,0 +1,357 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1, + parameter SHARED_DEVCLK = 0, + parameter JESD_MODE = "8B10B" +) ( + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire ref_clk; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk_internal; + wire rx_device_clk; + + wire dac_rst; + wire tx_device_clk_div4; + + wire [127:0] s_axis_tx_data_0_tdata; + wire s_axis_tx_data_0_tready; + wire s_axis_tx_data_0_tvalid; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + IBUFDS i_ibufds_syncin_0 ( + .I (fpga_syncin_0_p), + .IB (fpga_syncin_0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout_0 ( + .I (rx_syncout[0]), + .O (fpga_syncout_0_p), + .OB (fpga_syncout_0_n)); + + BUFG i_tx_device_clk ( + .I (clkin6), + .O (tx_device_clk)); + + +BUFGCE_DIV #( +.BUFGCE_DIVIDE(4), // 1-8 +// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins +.IS_CE_INVERTED(1'b0), // Optional inversion for CE +.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR +.IS_I_INVERTED(1'b0) // Optional inversion for I +) +BUFGCE_DIV_inst ( +.O(tx_device_clk_div4), // 1-bit output: Buffer +.CE(1'b1), // 1-bit input: Buffer enable +.CLR(1'b0), // 1-bit input: Asynchronous clear +.I(clkin6) // 1-bit input: Buffer +); +// E + + + + + + + + + + BUFG i_rx_device_clk ( + .I (clkin10), + .O (rx_device_clk_internal)); + + assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; + + // spi + + assign spi0_csb = spi0_csn[0]; + assign spi1_csb = spi1_csn[0]; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi ( + .spi_csn (spi1_csn[0]), + .spi_clk (spi1_sclk), + .spi_mosi (spi1_mosi), + .spi_miso (spi1_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + // gpios + + ad_iobuf #( + .DATA_WIDTH(12) + ) i_iobuf ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({hmc_gpio1, // 43 + gpio[10:0]})); // 42-32 + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + assign txen[0] = gpio_o[58]; + assign txen[1] = gpio_o[59]; + + generate + if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[7:0]; + + // Unused GPIOs + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[94:64] = gpio_o[94:64]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[7:0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_sclk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_sclk), + // FMC HPC + .rx_data_0_n (rx_data_n_loc[0]), + .rx_data_0_p (rx_data_p_loc[0]), + .rx_data_1_n (rx_data_n_loc[1]), + .rx_data_1_p (rx_data_p_loc[1]), + .rx_data_2_n (rx_data_n_loc[2]), + .rx_data_2_p (rx_data_p_loc[2]), + .rx_data_3_n (rx_data_n_loc[3]), + .rx_data_3_p (rx_data_p_loc[3]), + .rx_data_4_n (rx_data_n_loc[4]), + .rx_data_4_p (rx_data_p_loc[4]), + .rx_data_5_n (rx_data_n_loc[5]), + .rx_data_5_p (rx_data_p_loc[5]), + .rx_data_6_n (rx_data_n_loc[6]), + .rx_data_6_p (rx_data_p_loc[6]), + .rx_data_7_n (rx_data_n_loc[7]), + .rx_data_7_p (rx_data_p_loc[7]), + .tx_data_0_n (tx_data_n_loc[0]), + .tx_data_0_p (tx_data_p_loc[0]), + .tx_data_1_n (tx_data_n_loc[1]), + .tx_data_1_p (tx_data_p_loc[1]), + .tx_data_2_n (tx_data_n_loc[2]), + .tx_data_2_p (tx_data_p_loc[2]), + .tx_data_3_n (tx_data_n_loc[3]), + .tx_data_3_p (tx_data_p_loc[3]), + .tx_data_4_n (tx_data_n_loc[4]), + .tx_data_4_p (tx_data_p_loc[4]), + .tx_data_5_n (tx_data_n_loc[5]), + .tx_data_5_p (tx_data_p_loc[5]), + .tx_data_6_n (tx_data_n_loc[6]), + .tx_data_6_p (tx_data_p_loc[6]), + .tx_data_7_n (tx_data_n_loc[7]), + .tx_data_7_p (tx_data_p_loc[7]), + .ref_clk_q0 (ref_clk), + .ref_clk_q1 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), +// .dac_rst_out (dac_rst), + +// .s_axis_tx_data_0_tdata (s_axis_tx_data_0_tdata), +// .s_axis_tx_data_0_tvalid (s_axis_tx_data_0_tvalid), +// .s_axis_tx_data_0_tready (s_axis_tx_data_0_tready), + + .clk_in_1 (tx_device_clk_div4), + .rx_sync_0 (rx_syncout), + .tx_sync_0 (tx_syncin), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref)); + + assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0]; + assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0]; + + assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; +/* + dds_pulse_wrapper i_dds_pulse_wrapper ( + .clk_in (tx_device_clk_div4), + + .m_axis_aclk_in (tx_device_clk), + + .m_axis_tdata_out (s_axis_tx_data_0_tdata), + .m_axis_tvalid_out (s_axis_tx_data_0_tvalid), + .m_axis_tready_in (s_axis_tx_data_0_tready), + + .rst_in (dac_rst) + ); + +*/ + +endmodule diff --git a/my_source/src/vio_0/vio_0.xci b/my_source/src/vio_0/vio_0.xci new file mode 100644 index 0000000..8fce3b2 --- /dev/null +++ b/my_source/src/vio_0/vio_0.xci @@ -0,0 +1,1632 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "vio_0", + "component_reference": "xilinx.com:ip:vio:3.0", + "ip_revision": "23", + "gen_directory": "../../../../sweep.gen/sources_1/ip/vio_0", + "parameters": { + "component_parameters": { + "C_PROBE_OUT255_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT254_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT253_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT252_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT251_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT250_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT249_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT248_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT247_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT246_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT245_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT244_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT243_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT242_INIT_VAL": [ { "value": "0x0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT241_INIT_VAL": [ { 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"dependent", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT254_INIT_VAL": [ { "value": "0x0", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ], + "C_PROBE_OUT255_INIT_VAL": [ { "value": "0x0", "resolve_type": "dependent", "format": "bitString", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynquplus" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xczu9eg" } ], + "PACKAGE": [ { "value": "ffvb1156" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "23" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../sweep.gen/sources_1/ip/vio_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2022.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "clk": [ { "direction": "in" } ], + "probe_out0": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "probe_out1": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "probe_out2": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "probe_out3": [ { "direction": "out", "size_left": "0", "size_right": "0" } ] + }, + "interfaces": { + "signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "clk" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/recreate.tcl b/recreate.tcl new file mode 100644 index 0000000..9ce9ffd --- /dev/null +++ b/recreate.tcl @@ -0,0 +1,2971 @@ +#***************************************************************************************** +# Vivado (TM) v2022.2 (64-bit) +# +# recreate.tcl: Tcl script for re-creating project 'ad9081_fmca_ebz_zcu102' +# +# Generated by Vivado on Sun Oct 22 20:10:48 -0400 2023 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (recreate.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/common/ad_3w_spi.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/common/ad_iobuf.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/source/system_top.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/system_constr.xdc" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/timing_constr.xdc" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/zcu102_system_constr.xdc" +# +# 3. The following remote source files that were added to the original project:- +# +# +# +#***************************************************************************************** + +# Check file required for this script exists +proc checkRequiredFiles { origin_dir} { + set status true + set files [list \ + "[file normalize "$origin_dir/common/ad_3w_spi.v"]"\ + "[file normalize "$origin_dir/common/ad_iobuf.v"]"\ + "[file normalize "$origin_dir/source/system_top.v"]"\ + "[file normalize "$origin_dir/constraints/system_constr.xdc"]"\ + "[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\ + "[file normalize "$origin_dir/constraints/zcu102_system_constr.xdc"]"\ + ] + foreach ifile $files { + if { ![file isfile $ifile] } { + puts " Could not find local file $ifile " + set status false + } + } + + set paths [list \ + "[file normalize "$origin_dir/[file normalize "$origin_dir/my_source"]"]"\ + "[file normalize "$origin_dir/[file normalize "$origin_dir/../../../library"]"]"\ + "[file normalize "$origin_dir/[file normalize "$origin_dir/source"]"]"\ + ] + foreach ipath $paths { + if { ![file isdirectory $ipath] } { + puts " Could not access $ipath " + set status false + } + } + + return $status +} +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "ad9081_fmca_ebz_zcu102" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "recreate.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Check for paths and files needed for project creation +set validate_required 0 +if { $validate_required } { + if { [checkRequiredFiles $origin_dir] } { + puts "Tcl file $script_file is valid. All files required for project creation is accesable. " + } else { + puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. " + return + } +} + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu9eg-ffvb1156-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../Users/nicks/AppData/Roaming/Xilinx/Vivado/2019.2/xhub/board_store"]" -objects $obj +set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.4" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_resource_estimation" -value "0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "C:/ZCU102/hdl/ipcache" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "zcu102" -objects $obj +set_property -name "revised_directory_structure" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "sim_compile_state" -value "1" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "18" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "18" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "18" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "18" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "18" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "18" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +if { $obj != {} } { + set_property "ip_repo_paths" "[file normalize "$origin_dir/my_source"] [file normalize "$origin_dir/../../../library"] [file normalize "$origin_dir/source"]" $obj + + # Rebuild user ip_repo's index before adding any source files + update_ip_catalog -rebuild +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/common/ad_3w_spi.v" ]\ + [file normalize "${origin_dir}/common/ad_iobuf.v" ]\ + [file normalize "${origin_dir}/source/system_top.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj +set_property -name "generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj +set_property -name "top" -value "system_top" -objects $obj +set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/system_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/system_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/timing_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/timing_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/zcu102_system_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/zcu102_system_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD system +proc cr_bd_system { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name system + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:smartconnect:1.0\ + analog.com:user:axi_dmac:1.0\ + analog.com:user:axi_adxcvr:1.0\ + analog.com:user:axi_sysid:1.0\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:util_reduced_logic:2.0\ + xilinx.com:user:dds_pulse_wrapper:1.0\ + xilinx.com:ip:util_vector_logic:2.0\ + analog.com:user:sysid_rom:1.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:zynq_ultra_ps_e:3.4\ + analog.com:user:util_cpack2:1.0\ + analog.com:user:util_upack2:1.0\ + analog.com:user:util_adxcvr:1.0\ + analog.com:user:jesd204_rx:1.0\ + analog.com:user:axi_jesd204_rx:1.0\ + analog.com:user:jesd204_tx:1.0\ + analog.com:user:axi_jesd204_tx:1.0\ + analog.com:user:data_offload:1.0\ + analog.com:user:util_do_ram:1.0\ + analog.com:user:ad_ip_jesd204_tpl_adc:1.0\ + xilinx.com:ip:xlslice:1.0\ + analog.com:user:ad_ip_jesd204_tpl_dac:1.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +# Hierarchical cell: tx_mxfe_tpl_core +proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -from 15 -to 0 dac_data_0 + create_bd_pin -dir I -from 15 -to 0 dac_data_1 + create_bd_pin -dir I -from 15 -to 0 dac_data_2 + create_bd_pin -dir I -from 15 -to 0 dac_data_3 + create_bd_pin -dir I -from 15 -to 0 dac_data_4 + create_bd_pin -dir I -from 15 -to 0 dac_data_5 + create_bd_pin -dir I -from 15 -to 0 dac_data_6 + create_bd_pin -dir I -from 15 -to 0 dac_data_7 + create_bd_pin -dir I dac_dunf + create_bd_pin -dir O -from 0 -to 0 dac_enable_0 + create_bd_pin -dir O -from 0 -to 0 dac_enable_1 + create_bd_pin -dir O -from 0 -to 0 dac_enable_2 + create_bd_pin -dir O -from 0 -to 0 dac_enable_3 + create_bd_pin -dir O -from 0 -to 0 dac_enable_4 + create_bd_pin -dir O -from 0 -to 0 dac_enable_5 + create_bd_pin -dir O -from 0 -to 0 dac_enable_6 + create_bd_pin -dir O -from 0 -to 0 dac_enable_7 + create_bd_pin -dir O dac_rst + create_bd_pin -dir I dac_sync_manual_req_in + create_bd_pin -dir O dac_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 dac_valid_0 + create_bd_pin -dir O -from 0 -to 0 dac_valid_1 + create_bd_pin -dir O -from 0 -to 0 dac_valid_2 + create_bd_pin -dir O -from 0 -to 0 dac_valid_3 + create_bd_pin -dir O -from 0 -to 0 dac_valid_4 + create_bd_pin -dir O -from 0 -to 0 dac_valid_5 + create_bd_pin -dir O -from 0 -to 0 dac_valid_6 + create_bd_pin -dir O -from 0 -to 0 dac_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: dac_tpl_core, and set properties + set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.IQCORRECTION_DISABLE {0} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $dac_tpl_core + + + # Create instance: data_concat0, and set properties + set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ] + set_property CONFIG.NUM_PORTS {8} $data_concat0 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins link] [get_bd_intf_pins dac_tpl_core/link] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0] + connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1] + connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2] + connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3] + connect_bd_net -net dac_data_4_1 [get_bd_pins dac_data_4] [get_bd_pins data_concat0/In4] + connect_bd_net -net dac_data_5_1 [get_bd_pins dac_data_5] [get_bd_pins data_concat0/In5] + connect_bd_net -net dac_data_6_1 [get_bd_pins dac_data_6] [get_bd_pins data_concat0/In6] + connect_bd_net -net dac_data_7_1 [get_bd_pins dac_data_7] [get_bd_pins data_concat0/In7] + connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf] + connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_rst] [get_bd_pins dac_tpl_core/dac_rst] + connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_sync_manual_req_out] [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_concat0_dout [get_bd_pins dac_tpl_core/dac_ddata] [get_bd_pins data_concat0/dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins dac_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins dac_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins dac_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins dac_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins dac_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins dac_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins dac_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins dac_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins dac_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins dac_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins dac_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins dac_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins dac_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins dac_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins dac_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins dac_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx_mxfe_tpl_core +proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir O -from 15 -to 0 adc_data_0 + create_bd_pin -dir O -from 15 -to 0 adc_data_1 + create_bd_pin -dir O -from 15 -to 0 adc_data_2 + create_bd_pin -dir O -from 15 -to 0 adc_data_3 + create_bd_pin -dir O -from 15 -to 0 adc_data_4 + create_bd_pin -dir O -from 15 -to 0 adc_data_5 + create_bd_pin -dir O -from 15 -to 0 adc_data_6 + create_bd_pin -dir O -from 15 -to 0 adc_data_7 + create_bd_pin -dir I adc_dovf + create_bd_pin -dir O -from 0 -to 0 adc_enable_0 + create_bd_pin -dir O -from 0 -to 0 adc_enable_1 + create_bd_pin -dir O -from 0 -to 0 adc_enable_2 + create_bd_pin -dir O -from 0 -to 0 adc_enable_3 + create_bd_pin -dir O -from 0 -to 0 adc_enable_4 + create_bd_pin -dir O -from 0 -to 0 adc_enable_5 + create_bd_pin -dir O -from 0 -to 0 adc_enable_6 + create_bd_pin -dir O -from 0 -to 0 adc_enable_7 + create_bd_pin -dir O adc_rst + create_bd_pin -dir I adc_sync_manual_req_in + create_bd_pin -dir O adc_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 adc_valid_0 + create_bd_pin -dir O -from 0 -to 0 adc_valid_1 + create_bd_pin -dir O -from 0 -to 0 adc_valid_2 + create_bd_pin -dir O -from 0 -to 0 adc_valid_3 + create_bd_pin -dir O -from 0 -to 0 adc_valid_4 + create_bd_pin -dir O -from 0 -to 0 adc_valid_5 + create_bd_pin -dir O -from 0 -to 0 adc_valid_6 + create_bd_pin -dir O -from 0 -to 0 adc_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -from 127 -to 0 link_data + create_bd_pin -dir I -from 3 -to 0 link_sof + create_bd_pin -dir I link_valid + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: adc_tpl_core, and set properties + set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $adc_tpl_core + + + # Create instance: data_slice_0, and set properties + set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_0 + + + # Create instance: data_slice_1, and set properties + set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {16} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_1 + + + # Create instance: data_slice_2, and set properties + set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {47} \ + CONFIG.DIN_TO {32} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_2 + + + # Create instance: data_slice_3, and set properties + set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {48} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_3 + + + # Create instance: data_slice_4, and set properties + set data_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {79} \ + CONFIG.DIN_TO {64} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_4 + + + # Create instance: data_slice_5, and set properties + set data_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {95} \ + CONFIG.DIN_TO {80} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_5 + + + # Create instance: data_slice_6, and set properties + set data_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {111} \ + CONFIG.DIN_TO {96} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_6 + + + # Create instance: data_slice_7, and set properties + set data_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {127} \ + CONFIG.DIN_TO {112} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_7 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf] + connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in] + connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din] [get_bd_pins data_slice_4/Din] [get_bd_pins data_slice_5/Din] [get_bd_pins data_slice_6/Din] [get_bd_pins data_slice_7/Din] + connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_rst] [get_bd_pins adc_tpl_core/adc_rst] + connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_sync_manual_req_out] [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_slice_0_Dout [get_bd_pins adc_data_0] [get_bd_pins data_slice_0/Dout] + connect_bd_net -net data_slice_1_Dout [get_bd_pins adc_data_1] [get_bd_pins data_slice_1/Dout] + connect_bd_net -net data_slice_2_Dout [get_bd_pins adc_data_2] [get_bd_pins data_slice_2/Dout] + connect_bd_net -net data_slice_3_Dout [get_bd_pins adc_data_3] [get_bd_pins data_slice_3/Dout] + connect_bd_net -net data_slice_4_Dout [get_bd_pins adc_data_4] [get_bd_pins data_slice_4/Dout] + connect_bd_net -net data_slice_5_Dout [get_bd_pins adc_data_5] [get_bd_pins data_slice_5/Dout] + connect_bd_net -net data_slice_6_Dout [get_bd_pins adc_data_6] [get_bd_pins data_slice_6/Dout] + connect_bd_net -net data_slice_7_Dout [get_bd_pins adc_data_7] [get_bd_pins data_slice_7/Dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins adc_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins adc_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins adc_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins adc_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins adc_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins adc_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins adc_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins adc_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk] + connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data] + connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof] + connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins adc_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins adc_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins adc_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins adc_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins adc_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins adc_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins adc_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins adc_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_tx_data_offload +proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_CYCLIC_EN {true} \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {1} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_rx_data_offload +proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {0} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_tx_jesd +proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3 + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: tx, and set properties + set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $tx + + + # Create instance: tx_axi, and set properties + set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $tx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi] + connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx/tx_cfg] [get_bd_intf_pins tx_axi/tx_cfg] + connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx/tx_ctrl] [get_bd_intf_pins tx_axi/tx_ctrl] + connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data] + connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event] + connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config] + connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx_phy0] [get_bd_intf_pins tx/tx_phy0] + connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx_phy1] [get_bd_intf_pins tx/tx_phy1] + connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx_phy2] [get_bd_intf_pins tx/tx_phy2] + connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx_phy3] [get_bd_intf_pins tx/tx_phy3] + connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx/device_clk] [get_bd_pins tx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx/clk] [get_bd_pins tx_axi/core_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn] + connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref] + connect_bd_net -net tx_axi_core_reset [get_bd_pins tx/reset] [get_bd_pins tx_axi/core_reset] + connect_bd_net -net tx_axi_device_reset [get_bd_pins tx/device_reset] [get_bd_pins tx_axi/device_reset] + connect_bd_net -net tx_axi_irq [get_bd_pins irq] [get_bd_pins tx_axi/irq] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_rx_jesd +proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir O phy_en_char_align + create_bd_pin -dir O -from 127 -to 0 rx_data_tdata + create_bd_pin -dir O rx_data_tvalid + create_bd_pin -dir O -from 3 -to 0 rx_eof + create_bd_pin -dir O -from 3 -to 0 rx_sof + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: rx, and set properties + set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_INPUT_PIPELINE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $rx + + + # Create instance: rx_axi, and set properties + set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $rx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx/rx_cfg] [get_bd_intf_pins rx_axi/rx_cfg] + connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx_phy0] [get_bd_intf_pins rx/rx_phy0] + connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx_phy1] [get_bd_intf_pins rx/rx_phy1] + connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx_phy2] [get_bd_intf_pins rx/rx_phy2] + connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx_phy3] [get_bd_intf_pins rx/rx_phy3] + connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event] + connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config] + connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx/device_clk] [get_bd_pins rx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx/clk] [get_bd_pins rx_axi/core_clk] + connect_bd_net -net rx_axi_core_reset [get_bd_pins rx/reset] [get_bd_pins rx_axi/core_reset] + connect_bd_net -net rx_axi_device_reset [get_bd_pins rx/device_reset] [get_bd_pins rx_axi/device_reset] + connect_bd_net -net rx_axi_irq [get_bd_pins irq] [get_bd_pins rx_axi/irq] + connect_bd_net -net rx_phy_en_char_align [get_bd_pins phy_en_char_align] [get_bd_pins rx/phy_en_char_align] + connect_bd_net -net rx_rx_data [get_bd_pins rx_data_tdata] [get_bd_pins rx/rx_data] + connect_bd_net -net rx_rx_eof [get_bd_pins rx_eof] [get_bd_pins rx/rx_eof] + connect_bd_net -net rx_rx_sof [get_bd_pins rx_sof] [get_bd_pins rx/rx_sof] + connect_bd_net -net rx_rx_valid [get_bd_pins rx_data_tvalid] [get_bd_pins rx/rx_valid] + connect_bd_net -net rx_sync [get_bd_pins sync] [get_bd_pins rx/sync] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk_in_1 [ create_bd_port -dir I clk_in_1 ] + set ext_sync_in [ create_bd_port -dir I ext_sync_in ] + set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ] + set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ] + set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ] + set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ] + set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ] + set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ] + set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ] + set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ] + set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ] + set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ] + set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ] + set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ] + set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ] + set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ] + set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ] + set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ] + set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ] + set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ] + set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ] + set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ] + set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ] + set rx_device_clk [ create_bd_port -dir I rx_device_clk ] + set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ] + set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ] + set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] + set spi0_miso [ create_bd_port -dir I spi0_miso ] + set spi0_mosi [ create_bd_port -dir O spi0_mosi ] + set spi0_sclk [ create_bd_port -dir O spi0_sclk ] + set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ] + set spi1_miso [ create_bd_port -dir I spi1_miso ] + set spi1_mosi [ create_bd_port -dir O spi1_mosi ] + set spi1_sclk [ create_bd_port -dir O spi1_sclk ] + set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ] + set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ] + set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ] + set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ] + set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ] + set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ] + set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ] + set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ] + set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ] + set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ] + set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ] + set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ] + set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ] + set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ] + set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ] + set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ] + set tx_device_clk [ create_bd_port -dir I tx_device_clk ] + set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ] + set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ] + + # Create instance: GND_1, and set properties + set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $GND_1 + + + # Create instance: VCC_1, and set properties + set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $VCC_1 + + + # Create instance: axi_cpu_interconnect, and set properties + set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {11} \ + CONFIG.NUM_SI {1} \ + ] $axi_cpu_interconnect + + + # Create instance: axi_hp0_interconnect, and set properties + set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp0_interconnect + + + # Create instance: axi_hp1_interconnect, and set properties + set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp1_interconnect + + + # Create instance: axi_hp2_interconnect, and set properties + set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp2_interconnect + + + # Create instance: axi_mxfe_rx_dma, and set properties + set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {false} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {0} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_mxfe_rx_dma + + + # Create instance: axi_mxfe_rx_jesd + create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd + + # Create instance: axi_mxfe_rx_xcvr, and set properties + set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.LPM_OR_DFE_N {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {0} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {0} \ + ] $axi_mxfe_rx_xcvr + + + # Create instance: axi_mxfe_tx_dma, and set properties + set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {true} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + ] $axi_mxfe_tx_dma + + + # Create instance: axi_mxfe_tx_jesd + create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd + + # Create instance: axi_mxfe_tx_xcvr, and set properties + set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {1} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {1} \ + ] $axi_mxfe_tx_xcvr + + + # Create instance: axi_sysid_0, and set properties + set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ] + set_property CONFIG.ROM_ADDR_BITS {9} $axi_sysid_0 + + + # Create instance: cpack_reset_sources, and set properties + set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ] + set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources + + + # Create instance: cpack_rst_logic, and set properties + set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {3} \ + ] $cpack_rst_logic + + + # Create instance: dds_pulse_wrapper_0, and set properties + set dds_pulse_wrapper_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dds_pulse_wrapper:1.0 dds_pulse_wrapper_0 ] + set_property CONFIG.FPGA_REVISION_DATE {0x09112023} $dds_pulse_wrapper_0 + + + # Create instance: manual_sync_or, and set properties + set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $manual_sync_or + + + # Create instance: mxfe_rx_data_offload + create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload + + # Create instance: mxfe_tx_data_offload + create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload + + # Create instance: rom_sys_0, and set properties + set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ] + set_property -dict [list \ + CONFIG.PATH_TO_FILE {c:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/mem_init_sys.txt} \ + CONFIG.ROM_ADDR_BITS {9} \ + ] $rom_sys_0 + + + # Create instance: rx_device_clk_rstgen, and set properties + set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ] + + # Create instance: rx_do_rstout_logic, and set properties + set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rx_do_rstout_logic + + + # Create instance: rx_mxfe_tpl_core + create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core + + # Create instance: spi0_csn_concat, and set properties + set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat + + + # Create instance: spi1_csn_concat, and set properties + set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat + + + # Create instance: sys_250m_rstgen, and set properties + set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen + + + # Create instance: sys_500m_rstgen, and set properties + set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen + + + # Create instance: sys_concat_intc_0, and set properties + set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0 + + + # Create instance: sys_concat_intc_1, and set properties + set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1 + + + # Create instance: sys_ps8, and set properties + set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 sys_ps8 ] + set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\ +GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ +\ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Single Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {0x0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {1} \ + CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \ + CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \ + CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ +\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ +\ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {0} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {1} \ + CONFIG.PSU__USE__S_AXI_GP4 {1} \ + ] $sys_ps8 + + + # Create instance: sys_rstgen, and set properties + set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen + + + # Create instance: tx_device_clk_rstgen, and set properties + set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ] + + # Create instance: tx_mxfe_tpl_core + create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core + + # Create instance: upack_reset_sources, and set properties + set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ] + set_property CONFIG.NUM_PORTS {2} $upack_reset_sources + + + # Create instance: upack_rst_logic, and set properties + set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {2} \ + ] $upack_rst_logic + + + # Create instance: util_mxfe_cpack, and set properties + set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_cpack + + + # Create instance: util_mxfe_upack, and set properties + set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_upack + + + # Create instance: util_mxfe_xcvr, and set properties + set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ] + set_property -dict [list \ + CONFIG.A_TXDIFFCTRL {0x0C} \ + CONFIG.CH_HSPMUX {0x6868} \ + CONFIG.CPLL_CFG0 {0x01FA} \ + CONFIG.CPLL_CFG1 {0x0023} \ + CONFIG.CPLL_CFG2 {0x0002} \ + CONFIG.CPLL_FBDIV {2} \ + CONFIG.CPLL_FBDIV_4_5 {5} \ + CONFIG.LINK_MODE {1} \ + CONFIG.POR_CFG {0x0000} \ + CONFIG.PPF0_CFG {0x0F00} \ + CONFIG.PREIQ_FREQ_BST {1} \ + CONFIG.QPLL_CFG0 {0x333c} \ + CONFIG.QPLL_CFG4 {0x0045} \ + CONFIG.QPLL_CP {0x0FF} \ + CONFIG.QPLL_CP_G3 {0x00F} \ + CONFIG.QPLL_FBDIV {"0000010100"} \ + CONFIG.QPLL_LPF {0x2FF} \ + CONFIG.QPLL_REFCLK_DIV {1} \ + CONFIG.RXCDR_CFG0 {0x0003} \ + CONFIG.RXCDR_CFG2_GEN2 {0x265} \ + CONFIG.RXCDR_CFG2_GEN4 {0x0164} \ + CONFIG.RXCDR_CFG3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN2 {0x12} \ + CONFIG.RXCDR_CFG3_GEN3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN4 {0x0012} \ + CONFIG.RXPI_CFG0 {0x0200} \ + CONFIG.RXPI_CFG1 {0x00FD} \ + CONFIG.RX_CLK25_DIV {31} \ + CONFIG.RX_LANE_RATE {10} \ + CONFIG.RX_NUM_OF_LANES {4} \ + CONFIG.RX_OUT_DIV {1} \ + CONFIG.RX_WIDEMODE_CDR {0x0} \ + CONFIG.TXPI_CFG {0x0000} \ + CONFIG.TX_CLK25_DIV {31} \ + CONFIG.TX_LANE_RATE {10} \ + CONFIG.TX_NUM_OF_LANES {4} \ + CONFIG.TX_PI_BIASSET {3} \ + ] $util_mxfe_xcvr + + + # Create interface connections + connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] + connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] + connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0] [get_bd_intf_pins util_mxfe_xcvr/tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1] [get_bd_intf_pins util_mxfe_xcvr/tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2] [get_bd_intf_pins util_mxfe_xcvr/tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3] [get_bd_intf_pins util_mxfe_xcvr/tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0] + connect_bd_intf_net -intf_net dds_pulse_wrapper_0_m_axis_out [get_bd_intf_pins dds_pulse_wrapper_0/m_axis_out] [get_bd_intf_pins util_mxfe_upack/s_axis] + connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins axi_mxfe_rx_dma/s_axis] [get_bd_intf_pins mxfe_rx_data_offload/m_axis] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins axi_mxfe_tx_dma/m_axis] [get_bd_intf_pins mxfe_tx_data_offload/s_axis] + connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD] + connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data] [get_bd_intf_pins tx_mxfe_tpl_core/link] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0] [get_bd_intf_pins util_mxfe_xcvr/rx_0] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1] [get_bd_intf_pins util_mxfe_xcvr/rx_1] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2] [get_bd_intf_pins util_mxfe_xcvr/rx_2] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3] [get_bd_intf_pins util_mxfe_xcvr/rx_3] + + # Create port connections + connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] + connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n] + connect_bd_net -net adc_dovf_1 [get_bd_pins rx_mxfe_tpl_core/adc_dovf] [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] + connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5] + connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3] + connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid] + connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof] + connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_ports rx_sync_0] [get_bd_pins axi_mxfe_rx_jesd/sync] + connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3] + connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4] + connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2] + connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0] + connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr] + connect_bd_net -net clk_in_1_1 [get_bd_ports clk_in_1] [get_bd_pins dds_pulse_wrapper_0/clk_in] + connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1] + connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset] + connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in] + connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i] + connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req] + connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req] + connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1] + connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] + connect_bd_net -net rom_sys_0_rom_data [get_bd_pins axi_sysid_0/sys_rom_data] [get_bd_pins rom_sys_0/rom_data] + connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n] + connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p] + connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n] + connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p] + connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n] + connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p] + connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n] + connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p] + connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_cpack/clk] + connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins cpack_reset_sources/In0] [get_bd_pins rx_device_clk_rstgen/peripheral_reset] + connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins cpack_reset_sources/In2] [get_bd_pins rx_do_rstout_logic/Res] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_4 [get_bd_pins rx_mxfe_tpl_core/adc_data_4] [get_bd_pins util_mxfe_cpack/fifo_wr_data_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_5 [get_bd_pins rx_mxfe_tpl_core/adc_data_5] [get_bd_pins util_mxfe_cpack/fifo_wr_data_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_6 [get_bd_pins rx_mxfe_tpl_core/adc_data_6] [get_bd_pins util_mxfe_cpack/fifo_wr_data_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_7 [get_bd_pins rx_mxfe_tpl_core/adc_data_7] [get_bd_pins util_mxfe_cpack/fifo_wr_data_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_4 [get_bd_pins rx_mxfe_tpl_core/adc_enable_4] [get_bd_pins util_mxfe_cpack/enable_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_5 [get_bd_pins rx_mxfe_tpl_core/adc_enable_5] [get_bd_pins util_mxfe_cpack/enable_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_6 [get_bd_pins rx_mxfe_tpl_core/adc_enable_6] [get_bd_pins util_mxfe_cpack/enable_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_7 [get_bd_pins rx_mxfe_tpl_core/adc_enable_7] [get_bd_pins util_mxfe_cpack/enable_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins cpack_reset_sources/In1] [get_bd_pins rx_mxfe_tpl_core/adc_rst] + connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins manual_sync_or/Op1] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en] + connect_bd_net -net spi0_csn_concat_dout [get_bd_ports spi0_csn] [get_bd_pins spi0_csn_concat/dout] + connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i] + connect_bd_net -net spi1_csn_concat_dout [get_bd_ports spi1_csn] [get_bd_pins spi1_csn_concat/dout] + connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i] + connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync] + connect_bd_net -net sys_250m_clk [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] + connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset] + connect_bd_net -net sys_250m_resetn [get_bd_pins axi_hp2_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins sys_250m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_500m_clk [get_bd_pins sys_500m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk2] + connect_bd_net -net sys_500m_reset [get_bd_pins sys_500m_rstgen/peripheral_reset] + connect_bd_net -net sys_500m_resetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0] + connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins util_mxfe_xcvr/up_clk] + connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins util_mxfe_xcvr/up_rstn] + connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_ports gpio_o] [get_bd_pins sys_ps8/emio_gpio_o] + connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_ports gpio_t] [get_bd_pins sys_ps8/emio_gpio_t] + connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_ports spi0_mosi] [get_bd_pins sys_ps8/emio_spi0_m_o] + connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_ports spi0_sclk] [get_bd_pins sys_ps8/emio_spi0_sclk_o] + connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins spi0_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins spi0_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins spi0_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi0_ss_o_n] + connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_ports spi1_mosi] [get_bd_pins sys_ps8/emio_spi1_m_o] + connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_ports spi1_sclk] [get_bd_pins sys_ps8/emio_spi1_sclk_o] + connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins spi1_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins spi1_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins spi1_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi1_ss_o_n] + connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in] [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_rstgen/ext_reset_in] + connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref] + connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref] + connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins dds_pulse_wrapper_0/m_axis_aclk_in] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_upack/clk] + connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_4 [get_bd_pins tx_mxfe_tpl_core/dac_enable_4] [get_bd_pins util_mxfe_upack/enable_4] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_5 [get_bd_pins tx_mxfe_tpl_core/dac_enable_5] [get_bd_pins util_mxfe_upack/enable_5] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_6 [get_bd_pins tx_mxfe_tpl_core/dac_enable_6] [get_bd_pins util_mxfe_upack/enable_6] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_7 [get_bd_pins tx_mxfe_tpl_core/dac_enable_7] [get_bd_pins util_mxfe_upack/enable_7] + connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1] + connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins manual_sync_or/Op2] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en] + connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1] + connect_bd_net -net upack_rst_logic_Res [get_bd_pins dds_pulse_wrapper_0/rst_in] [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins tx_mxfe_tpl_core/dac_data_0] [get_bd_pins util_mxfe_upack/fifo_rd_data_0] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins tx_mxfe_tpl_core/dac_data_1] [get_bd_pins util_mxfe_upack/fifo_rd_data_1] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins tx_mxfe_tpl_core/dac_data_2] [get_bd_pins util_mxfe_upack/fifo_rd_data_2] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins tx_mxfe_tpl_core/dac_data_3] [get_bd_pins util_mxfe_upack/fifo_rd_data_3] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_4 [get_bd_pins tx_mxfe_tpl_core/dac_data_4] [get_bd_pins util_mxfe_upack/fifo_rd_data_4] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_5 [get_bd_pins tx_mxfe_tpl_core/dac_data_5] [get_bd_pins util_mxfe_upack/fifo_rd_data_5] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_6 [get_bd_pins tx_mxfe_tpl_core/dac_data_6] [get_bd_pins util_mxfe_upack/fifo_rd_data_6] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_7 [get_bd_pins tx_mxfe_tpl_core/dac_data_7] [get_bd_pins util_mxfe_upack/fifo_rd_data_7] + connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins axi_mxfe_rx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] + connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_ports tx_data_0_n] [get_bd_pins util_mxfe_xcvr/tx_0_n] + connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_ports tx_data_0_p] [get_bd_pins util_mxfe_xcvr/tx_0_p] + connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_ports tx_data_1_n] [get_bd_pins util_mxfe_xcvr/tx_1_n] + connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_ports tx_data_1_p] [get_bd_pins util_mxfe_xcvr/tx_1_p] + connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_ports tx_data_2_n] [get_bd_pins util_mxfe_xcvr/tx_2_n] + connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_ports tx_data_2_p] [get_bd_pins util_mxfe_xcvr/tx_2_p] + connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_ports tx_data_3_n] [get_bd_pins util_mxfe_xcvr/tx_3_n] + connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_ports tx_data_3_p] [get_bd_pins util_mxfe_xcvr/tx_3_p] + connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins axi_mxfe_tx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_LPS_OCM] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_PCIE_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force + assign_bd_address -offset 0x9C420000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C430000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x85000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_QSPI] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_QSPI] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.895069", + "Default View_TopLeft":"6246,428", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +preplace port port-id_spi0_sclk -pg 1 -lvl 13 -x 8460 -y 1200 -defaultsOSRD +preplace port port-id_spi0_mosi -pg 1 -lvl 13 -x 8460 -y 1230 -defaultsOSRD +preplace port port-id_spi0_miso -pg 1 -lvl 0 -x -70 -y 1570 -defaultsOSRD +preplace port port-id_spi1_sclk -pg 1 -lvl 13 -x 8460 -y 1350 -defaultsOSRD +preplace port port-id_spi1_mosi -pg 1 -lvl 13 -x 8460 -y 1380 -defaultsOSRD +preplace port port-id_spi1_miso -pg 1 -lvl 0 -x -70 -y 1600 -defaultsOSRD +preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x -70 -y 810 -defaultsOSRD +preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x -70 -y 2610 -defaultsOSRD +preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x -70 -y 2580 -defaultsOSRD +preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x -70 -y 20 -defaultsOSRD +preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x -70 -y 2490 -defaultsOSRD +preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x -70 -y 2460 -defaultsOSRD +preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x -70 -y 2430 -defaultsOSRD +preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x -70 -y 2520 -defaultsOSRD +preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x -70 -y 2550 -defaultsOSRD +preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x -70 -y 2700 -defaultsOSRD +preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x -70 -y 2730 -defaultsOSRD +preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x -70 -y 2790 -defaultsOSRD +preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x -70 -y 2760 -defaultsOSRD +preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x -70 -y 2360 -defaultsOSRD +preplace port port-id_tx_data_0_p -pg 1 -lvl 13 -x 8460 -y 2200 -defaultsOSRD +preplace port port-id_tx_data_0_n -pg 1 -lvl 13 -x 8460 -y 2230 -defaultsOSRD +preplace port port-id_tx_data_1_p -pg 1 -lvl 13 -x 8460 -y 2260 -defaultsOSRD +preplace port port-id_tx_data_1_n -pg 1 -lvl 13 -x 8460 -y 2290 -defaultsOSRD +preplace port port-id_tx_data_2_p -pg 1 -lvl 13 -x 8460 -y 2320 -defaultsOSRD +preplace port port-id_tx_data_2_n -pg 1 -lvl 13 -x 8460 -y 2350 -defaultsOSRD +preplace port port-id_tx_data_3_p -pg 1 -lvl 13 -x 8460 -y 2390 -defaultsOSRD +preplace port port-id_tx_data_3_n -pg 1 -lvl 13 -x 8460 -y 2420 -defaultsOSRD +preplace port port-id_rx_data_4_n -pg 1 -lvl 0 -x -70 -y 50 -defaultsOSRD +preplace port port-id_rx_data_4_p -pg 1 -lvl 0 -x -70 -y 80 -defaultsOSRD +preplace port port-id_rx_data_5_n -pg 1 -lvl 0 -x -70 -y 110 -defaultsOSRD +preplace port port-id_rx_data_5_p -pg 1 -lvl 0 -x -70 -y 140 -defaultsOSRD +preplace port port-id_rx_data_6_n -pg 1 -lvl 0 -x -70 -y 170 -defaultsOSRD +preplace port port-id_rx_data_6_p -pg 1 -lvl 0 -x -70 -y 200 -defaultsOSRD +preplace port port-id_rx_data_7_n -pg 1 -lvl 0 -x -70 -y 230 -defaultsOSRD +preplace port port-id_rx_data_7_p -pg 1 -lvl 0 -x -70 -y 260 -defaultsOSRD +preplace port port-id_tx_data_4_n -pg 1 -lvl 13 -x 8460 -y 200 -defaultsOSRD +preplace port port-id_tx_data_4_p -pg 1 -lvl 13 -x 8460 -y 170 -defaultsOSRD +preplace port port-id_tx_data_5_n -pg 1 -lvl 13 -x 8460 -y 140 -defaultsOSRD +preplace port port-id_tx_data_5_p -pg 1 -lvl 13 -x 8460 -y 110 -defaultsOSRD +preplace port port-id_tx_data_6_n -pg 1 -lvl 13 -x 8460 -y -10 -defaultsOSRD +preplace port port-id_tx_data_6_p -pg 1 -lvl 13 -x 8460 -y 80 -defaultsOSRD +preplace port port-id_tx_data_7_n -pg 1 -lvl 13 -x 8460 -y 50 -defaultsOSRD +preplace port port-id_tx_data_7_p -pg 1 -lvl 13 -x 8460 -y 20 -defaultsOSRD +preplace port port-id_ext_sync_in -pg 1 -lvl 0 -x -70 -y 730 -defaultsOSRD +preplace port port-id_clk_in_1 -pg 1 -lvl 0 -x -70 -y 780 -defaultsOSRD +preplace portBus spi0_csn -pg 1 -lvl 13 -x 8460 -y 1290 -defaultsOSRD +preplace portBus spi1_csn -pg 1 -lvl 13 -x 8460 -y 1570 -defaultsOSRD +preplace portBus gpio_i -pg 1 -lvl 0 -x -70 -y 1540 -defaultsOSRD +preplace portBus gpio_o -pg 1 -lvl 13 -x 8460 -y 1140 -defaultsOSRD +preplace portBus gpio_t -pg 1 -lvl 13 -x 8460 -y 1170 -defaultsOSRD +preplace portBus rx_sync_0 -pg 1 -lvl 13 -x 8460 -y 2060 -defaultsOSRD +preplace portBus tx_sync_0 -pg 1 -lvl 0 -x -70 -y 2030 -defaultsOSRD +preplace inst sys_ps8 -pg 1 -lvl 6 -x 2830 -y 1220 -defaultsOSRD +preplace inst sys_rstgen -pg 1 -lvl 1 -x 180 -y 2140 -defaultsOSRD +preplace inst sys_250m_rstgen -pg 1 -lvl 2 -x 740 -y 2140 -defaultsOSRD +preplace inst sys_500m_rstgen -pg 1 -lvl 7 -x 3480 -y 2260 -defaultsOSRD +preplace inst spi0_csn_concat -pg 1 -lvl 12 -x 8260 -y 1290 -defaultsOSRD +preplace inst VCC_1 -pg 1 -lvl 2 -x 740 -y 1740 -defaultsOSRD +preplace inst GND_1 -pg 1 -lvl 2 -x 740 -y 1640 -defaultsOSRD +preplace inst spi1_csn_concat -pg 1 -lvl 12 -x 8260 -y 1570 -defaultsOSRD +preplace inst axi_sysid_0 -pg 1 -lvl 8 -x 4650 -y 3080 -defaultsOSRD +preplace inst rom_sys_0 -pg 1 -lvl 7 -x 3480 -y 1440 -defaultsOSRD +preplace inst axi_cpu_interconnect -pg 1 -lvl 7 -x 3480 -y 1770 -defaultsOSRD +preplace inst sys_concat_intc_0 -pg 1 -lvl 5 -x 2320 -y 1190 -defaultsOSRD +preplace inst sys_concat_intc_1 -pg 1 -lvl 5 -x 2320 -y 1430 -defaultsOSRD +preplace inst axi_hp0_interconnect -pg 1 -lvl 5 -x 2320 -y 2030 -defaultsOSRD +preplace inst util_mxfe_xcvr -pg 1 -lvl 11 -x 7806 -y 2310 -defaultsOSRD +preplace inst axi_mxfe_rx_xcvr -pg 1 -lvl 4 -x 1862 -y 2090 -defaultsOSRD +preplace inst axi_mxfe_rx_jesd -pg 1 -lvl 12 -x 8260 -y 2100 -defaultsOSRD +preplace inst rx_mxfe_tpl_core -pg 1 -lvl 8 -x 4650 -y 300 -defaultsOSRD +preplace inst util_mxfe_cpack -pg 1 -lvl 2 -x 740 -y 970 -defaultsOSRD +preplace inst mxfe_rx_data_offload -pg 1 -lvl 3 -x 1420 -y 1790 -defaultsOSRD +preplace inst axi_mxfe_rx_dma -pg 1 -lvl 4 -x 1862 -y 1770 -defaultsOSRD +preplace inst axi_mxfe_tx_xcvr -pg 1 -lvl 9 -x 6290 -y 1120 -defaultsOSRD +preplace inst axi_mxfe_tx_jesd -pg 1 -lvl 9 -x 6290 -y 1380 -defaultsOSRD +preplace inst tx_mxfe_tpl_core -pg 1 -lvl 8 -x 4650 -y 980 -defaultsOSRD +preplace inst util_mxfe_upack -pg 1 -lvl 11 -x 7806 -y 1040 -defaultsOSRD +preplace inst mxfe_tx_data_offload -pg 1 -lvl 9 -x 6290 -y 1840 -defaultsOSRD +preplace inst axi_mxfe_tx_dma -pg 1 -lvl 8 -x 4650 -y 3914 -defaultsOSRD +preplace inst rx_device_clk_rstgen -pg 1 -lvl 2 -x 740 -y 1880 -defaultsOSRD +preplace inst tx_device_clk_rstgen -pg 1 -lvl 8 -x 4650 -y 4264 -defaultsOSRD +preplace inst axi_hp1_interconnect -pg 1 -lvl 5 -x 2320 -y 2260 -defaultsOSRD +preplace inst axi_hp2_interconnect -pg 1 -lvl 9 -x 6290 -y 1630 -defaultsOSRD +preplace inst manual_sync_or -pg 1 -lvl 9 -x 6290 -y 418 -defaultsOSRD +preplace inst cpack_rst_logic -pg 1 -lvl 11 -x 7806 -y 2910 -defaultsOSRD +preplace inst rx_do_rstout_logic -pg 1 -lvl 8 -x 4650 -y 4474 -defaultsOSRD +preplace inst cpack_reset_sources -pg 1 -lvl 9 -x 6290 -y 3074 -defaultsOSRD +preplace inst upack_rst_logic -pg 1 -lvl 11 -x 7806 -y 1470 -defaultsOSRD +preplace inst upack_reset_sources -pg 1 -lvl 9 -x 6290 -y 810 -defaultsOSRD +preplace inst dds_pulse_wrapper_0 -pg 1 -lvl 10 -x 7200 -y 800 -defaultsOSRD +preplace netloc GND_1_dout 1 2 7 1030 1500 NJ 1500 2050 810 NJ 810 3200 920 3890J 1500 5090 +preplace netloc VCC_1_dout 1 2 5 1020 800 NJ 800 NJ 800 NJ 800 3170 +preplace netloc adc_dovf_1 1 2 6 920J 590 NJ 590 NJ 590 NJ 590 NJ 590 3790 +preplace netloc axi_mxfe_rx_dma_irq 1 4 1 2010 1460n +preplace netloc axi_mxfe_rx_jesd_irq 1 4 9 2170 1870 2490J 2020 NJ 2020 NJ 2020 NJ 2020 6450J 1970 7390 1670 NJ 1670 8430 +preplace netloc axi_mxfe_rx_jesd_phy_en_char_align 1 10 3 7620 1690 NJ 1690 8410 +preplace netloc axi_mxfe_rx_jesd_rx_data_tdata 1 7 6 3950 2070 NJ 2070 6510J 1980 7400 1680 NJ 1680 8440 +preplace netloc axi_mxfe_rx_jesd_rx_data_tvalid 1 7 6 3960 2030 NJ 2030 6480J 1990 7350 1700 NJ 1700 8420 +preplace netloc axi_mxfe_rx_jesd_rx_sof 1 7 6 3940 2040 NJ 2040 6440J 2000 7450 1710 NJ 1710 8400 +preplace netloc axi_mxfe_rx_jesd_sync 1 12 1 NJ 2060 +preplace netloc axi_mxfe_rx_xcvr_up_pll_rst 1 4 7 2020 2420 NJ 2420 NJ 2420 3700J 2440 NJ 2440 N 2440 7600 +preplace netloc axi_mxfe_tx_dma_irq 1 4 5 2180 3230 NJ 3230 NJ 3230 NJ 3230 4830 +preplace netloc axi_mxfe_tx_jesd_irq 1 4 6 2180 -20 NJ -20 NJ -20 NJ -20 NJ -20 6440 +preplace netloc axi_mxfe_tx_xcvr_up_pll_rst 1 9 2 N 1180 7360 +preplace netloc axi_sysid_0_rom_addr 1 6 3 3240 1590 NJ 1590 4830 +preplace netloc clk_in_1_1 1 0 10 NJ 780 380J 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 6560J +preplace netloc cpack_reset_sources_dout 1 9 2 NJ 3074 7480 +preplace netloc cpack_rst_logic_Res 1 1 11 430 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 N 2850 7940 +preplace netloc ext_sync_in_1 1 0 8 NJ 730 350J 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 3930 +preplace netloc gpio_i_1 1 0 7 NJ 1540 NJ 1540 950J 820 NJ 820 NJ 820 NJ 820 3140 +preplace netloc init_req_1 1 2 3 1090 2300 NJ 2300 2010 +preplace netloc init_req_2 1 8 1 5310 1910n +preplace netloc manual_sync_or_Res 1 7 3 3970 680 NJ 680 6430 +preplace netloc mxfe_rx_data_offload_s_axis_tready 1 2 6 1080 4474 NJ 4474 NJ 4474 NJ 4474 NJ 4474 NJ +preplace netloc ref_clk_q0_1 1 0 11 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 N 2580 7590 +preplace netloc rom_sys_0_rom_data 1 7 1 3720 1440n +preplace netloc rx_data_0_n_1 1 0 11 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 7560 +preplace netloc rx_data_0_p_1 1 0 11 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 3890J 2420 NJ 2420 NJ 2420 7550 +preplace netloc rx_data_1_n_1 1 0 11 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 7580 +preplace netloc rx_data_1_p_1 1 0 11 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 7570 +preplace netloc rx_data_2_n_1 1 0 11 -20J 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 7610 +preplace netloc rx_data_2_p_1 1 0 11 -40J 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 N +preplace netloc rx_data_3_n_1 1 0 11 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 7610 +preplace netloc rx_data_3_p_1 1 0 11 -30J 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 7600 +preplace netloc rx_device_clk_1 1 0 12 NJ 810 380 1980 1020 1980 1560J 1910 NJ 1910 2480J 1940 NJ 1940 3900 1980 4850J 2010 NJ 2010 7340 1720 8020J +preplace netloc rx_device_clk_rstgen_peripheral_aresetn 1 2 1 970 1850n +preplace netloc rx_device_clk_rstgen_peripheral_reset 1 2 7 930J 2270 NJ 2270 2110J 1920 NJ 1920 3150J 1930 NJ 1930 4840 +preplace netloc rx_do_rstout_logic_Res 1 8 1 5330 3094n +preplace netloc rx_mxfe_tpl_core_adc_data_0 1 1 8 390 -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 4830 +preplace netloc rx_mxfe_tpl_core_adc_data_1 1 1 8 400 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 3790J 600 4860 +preplace netloc rx_mxfe_tpl_core_adc_data_2 1 1 8 410 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 4880 +preplace netloc rx_mxfe_tpl_core_adc_data_3 1 1 8 480 1210 930J 830 NJ 830 NJ 830 NJ 830 NJ 830 3920J 1210 4970 +preplace netloc rx_mxfe_tpl_core_adc_data_4 1 1 8 490 1220 940J 840 NJ 840 NJ 840 NJ 840 NJ 840 3810J 1220 4960 +preplace netloc rx_mxfe_tpl_core_adc_data_5 1 1 8 500 1230 960J 850 NJ 850 NJ 850 NJ 850 NJ 850 3910J 1230 4950 +preplace netloc rx_mxfe_tpl_core_adc_data_6 1 1 8 510 1550 NJ 1550 NJ 1550 2140J 1560 NJ 1560 NJ 1560 NJ 1560 4920 +preplace netloc rx_mxfe_tpl_core_adc_data_7 1 1 8 420 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 4830 +preplace netloc rx_mxfe_tpl_core_adc_enable_0 1 1 8 440 600 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 3780J 610 4940 +preplace netloc rx_mxfe_tpl_core_adc_enable_1 1 1 8 450 620 NJ 620 NJ 620 NJ 620 NJ 620 NJ 620 NJ 620 4910 +preplace netloc rx_mxfe_tpl_core_adc_enable_2 1 1 8 460 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 4930 +preplace netloc rx_mxfe_tpl_core_adc_enable_3 1 1 8 470 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 4900 +preplace netloc rx_mxfe_tpl_core_adc_enable_4 1 1 8 480 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 4890 +preplace netloc rx_mxfe_tpl_core_adc_enable_5 1 1 8 490 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 4870 +preplace netloc rx_mxfe_tpl_core_adc_enable_6 1 1 8 500 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 4850 +preplace netloc rx_mxfe_tpl_core_adc_enable_7 1 1 8 510 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 4840 +preplace netloc rx_mxfe_tpl_core_adc_rst 1 8 1 5160 550n +preplace netloc rx_mxfe_tpl_core_adc_sync_manual_req_out 1 8 1 4990 408n +preplace netloc rx_mxfe_tpl_core_adc_valid_0 1 1 8 470 1560 NJ 1560 NJ 1560 2050J 1570 NJ 1570 NJ 1570 NJ 1570 4980 +preplace netloc spi0_csn_concat_dout 1 12 1 NJ 1290 +preplace netloc spi0_miso_1 1 0 7 NJ 1570 NJ 1570 980J 860 NJ 860 NJ 860 NJ 860 3130 +preplace netloc spi1_csn_concat_dout 1 12 1 NJ 1570 +preplace netloc spi1_miso_1 1 0 7 NJ 1600 350J 2280 NJ 2280 NJ 2280 2070J 1880 NJ 1880 3130 +preplace netloc sync_1 1 0 9 -50J 1440 NJ 1440 970J 870 NJ 870 NJ 870 NJ 870 NJ 870 3860J 1480 5230J +preplace netloc sys_250m_clk 1 1 8 510 1990 1060 1990 1550 1650 2140 1590 2510J 1590 3180 1600 3680 1630 5210J +preplace netloc sys_250m_reset 1 2 1 N 2140 +preplace netloc sys_250m_resetn 1 2 7 1050 2000 1580 1900 NJ 1900 NJ 1900 3160J 1960 3920 1880 5290J +preplace netloc sys_500m_clk 1 6 1 3170 1500n +preplace netloc sys_500m_reset 1 7 1 N 2260 +preplace netloc sys_500m_resetn 1 7 1 N 2300 +preplace netloc sys_concat_intc_0_dout 1 5 1 2490J 1190n +preplace netloc sys_concat_intc_1_dout 1 5 1 2460 1300n +preplace netloc sys_cpu_clk 1 0 12 -30 2020 NJ 2020 1000 2020 1590 2250 2100 1580 2480 1580 3220 1550 3740 1440 5260 2080 6490 2100 7610 1740 8010J +preplace netloc sys_cpu_reset 1 1 1 N 2140 +preplace netloc sys_cpu_resetn 1 1 11 370 2000 1040 2010 1570 2290 2150 1890 NJ 1890 3180 1610 3800 1460 5270 2090 6440 2110 7520 1750 7980J +preplace netloc sys_ps8_emio_gpio_o 1 6 7 NJ 1000 3880J 1240 5110J 910 NJ 910 7600 860 NJ 860 8400J +preplace netloc sys_ps8_emio_gpio_t 1 6 7 NJ 1020 3870J 1250 5100J 890 NJ 890 7570 850 NJ 850 8430J +preplace netloc sys_ps8_emio_spi0_m_o 1 6 7 NJ 1120 3840J 1290 5150J 920 NJ 920 7590 840 NJ 840 8440J +preplace netloc sys_ps8_emio_spi0_sclk_o 1 6 7 NJ 1080 3780J 1550 NJ 1550 6450J 1250 7340 1220 8010J 1200 NJ +preplace netloc sys_ps8_emio_spi0_ss1_o_n 1 6 6 NJ 1200 3830J 1300 5190J 1250 6430J 1260 N 1260 8020 +preplace netloc sys_ps8_emio_spi0_ss2_o_n 1 6 6 NJ 1220 3750J 1510 5180J 1500 6480J 1480 7340 1370 8020 +preplace netloc sys_ps8_emio_spi0_ss_o_n 1 6 6 NJ 1180 3760J 1580 5240J 1540 6460J 1470 7330 1360 8010 +preplace netloc sys_ps8_emio_spi1_m_o 1 6 7 NJ 1320 3770J 1450 5210J 1510 NJ 1510 7350 1380 NJ 1380 NJ +preplace netloc sys_ps8_emio_spi1_sclk_o 1 6 7 NJ 1280 NJ 1280 5180J 1240 NJ 1240 7330 1210 NJ 1210 8400J +preplace netloc sys_ps8_emio_spi1_ss1_o_n 1 6 6 3200 1540 NJ 1540 5170J 710 NJ 710 7630 820 8030J +preplace netloc sys_ps8_emio_spi1_ss2_o_n 1 6 6 3190 1530 NJ 1530 NJ 1530 6470J 1540 N 1540 7980J +preplace netloc sys_ps8_emio_spi1_ss_o_n 1 6 6 3230 1520 NJ 1520 NJ 1520 6480J 1550 N 1550 NJ +preplace netloc sys_ps8_pl_resetn0 1 0 7 -20 2040 360 2040 NJ 2040 1550J 2260 2120J 1930 NJ 1930 3140 +preplace netloc sysref_1 1 0 12 NJ 2490 NJ 2490 NJ 2490 NJ 2490 2160J 1940 2460J 2050 NJ 2050 NJ 2050 NJ 2050 6460J 2020 7470 1730 7990J +preplace netloc sysref_2 1 0 9 -40J 1450 NJ 1450 990J 880 NJ 880 NJ 880 NJ 880 NJ 880 3790J 1490 5240J +preplace netloc tx_device_clk_1 1 0 11 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 3850 1470 5250 950 6450J 950 N +preplace netloc tx_device_clk_rstgen_peripheral_aresetn 1 8 1 5320 1890n +preplace netloc tx_device_clk_rstgen_peripheral_reset 1 8 1 5220 800n +preplace netloc tx_mxfe_tpl_core_dac_enable_0 1 8 3 4930 930 NJ 930 7600 +preplace netloc tx_mxfe_tpl_core_dac_enable_1 1 8 3 5200 880 6530J 1000 7580 +preplace netloc tx_mxfe_tpl_core_dac_enable_2 1 8 3 N 900 6510J 1010 7560 +preplace netloc tx_mxfe_tpl_core_dac_enable_3 1 8 3 N 940 6480J 1020 7500 +preplace netloc tx_mxfe_tpl_core_dac_enable_4 1 8 3 5040 970 NJ 970 7590 +preplace netloc tx_mxfe_tpl_core_dac_enable_5 1 8 3 5120 990 NJ 990 7520 +preplace netloc tx_mxfe_tpl_core_dac_enable_6 1 8 3 5140 1000 6450J 1110 N +preplace netloc tx_mxfe_tpl_core_dac_enable_7 1 8 3 5130 980 NJ 980 7540 +preplace netloc tx_mxfe_tpl_core_dac_rst 1 8 1 5030 820n +preplace netloc tx_mxfe_tpl_core_dac_sync_manual_req_out 1 8 1 5000 428n +preplace netloc tx_mxfe_tpl_core_dac_valid_0 1 8 3 5180 960 6460J 1150 N +preplace netloc upack_reset_sources_dout 1 9 2 6550J 940 7570 +preplace netloc upack_rst_logic_Res 1 9 3 6560 880 7630 870 7980J +preplace netloc util_mxfe_cpack_packed_fifo_wr_data 1 2 1 1000 980n +preplace netloc util_mxfe_cpack_packed_fifo_wr_en 1 2 1 1010 960n +preplace netloc util_mxfe_upack_fifo_rd_data_0 1 7 5 3980 1270 5090J 720 NJ 720 7620 830 7940 +preplace netloc util_mxfe_upack_fifo_rd_data_1 1 7 5 4040 1260 5020J 700 NJ 700 N 700 7950 +preplace netloc util_mxfe_upack_fifo_rd_data_2 1 7 5 3990 1310 5080J 670 NJ 670 N 670 7970 +preplace netloc util_mxfe_upack_fifo_rd_data_3 1 7 5 4020 720 5010J 690 NJ 690 N 690 7960 +preplace netloc util_mxfe_upack_fifo_rd_data_4 1 7 5 4000 1320 5070J 660 NJ 660 N 660 7990 +preplace netloc util_mxfe_upack_fifo_rd_data_5 1 7 5 4010 1330 5060J 650 NJ 650 N 650 8010 +preplace netloc util_mxfe_upack_fifo_rd_data_6 1 7 5 4020 1340 5050J 640 NJ 640 N 640 8020 +preplace netloc util_mxfe_upack_fifo_rd_data_7 1 7 5 4030 740 NJ 740 6450J 680 N 680 8000 +preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 10 2 7630 1760 7950 +preplace netloc util_mxfe_xcvr_tx_0_n 1 11 2 NJ 2240 8430J +preplace netloc util_mxfe_xcvr_tx_0_p 1 11 2 7990J 2250 8410J +preplace netloc util_mxfe_xcvr_tx_1_n 1 11 2 7980J 2290 NJ +preplace netloc util_mxfe_xcvr_tx_1_p 1 11 2 7960J 2260 NJ +preplace netloc util_mxfe_xcvr_tx_2_n 1 11 2 8010J 2350 NJ +preplace netloc util_mxfe_xcvr_tx_2_p 1 11 2 8000J 2320 NJ +preplace netloc util_mxfe_xcvr_tx_3_n 1 11 2 8030J 2420 NJ +preplace netloc util_mxfe_xcvr_tx_3_p 1 11 2 8020J 2390 NJ +preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 8 4 5330 2060 6500 2090 7540 1770 7940 +preplace netloc axi_cpu_interconnect_M00_AXI 1 7 1 3710 1670n +preplace netloc axi_cpu_interconnect_M01_AXI 1 3 5 1610 2350 NJ 2350 2510J 1990 NJ 1990 3670 +preplace netloc axi_cpu_interconnect_M02_AXI 1 7 1 3730 210n +preplace netloc axi_cpu_interconnect_M03_AXI 1 7 5 NJ 1730 4900J 1980 6440J 1960 7370 1660 8030 +preplace netloc axi_cpu_interconnect_M04_AXI 1 3 5 1600 2360 NJ 2360 NJ 2360 NJ 2360 3660 +preplace netloc axi_cpu_interconnect_M05_AXI 1 2 6 1070 2370 NJ 2370 NJ 2370 2530J 2350 3190J 2370 3650 +preplace netloc axi_cpu_interconnect_M06_AXI 1 7 2 3830J 1430 5200 +preplace netloc axi_cpu_interconnect_M07_AXI 1 7 1 3820 840n +preplace netloc axi_cpu_interconnect_M08_AXI 1 7 2 3840J 1420 5230 +preplace netloc axi_cpu_interconnect_M09_AXI 1 7 1 3690 1850n +preplace netloc axi_cpu_interconnect_M10_AXI 1 7 2 NJ 1870 5240 +preplace netloc axi_hp0_interconnect_M00_AXI 1 5 1 2450 1140n +preplace netloc axi_hp1_interconnect_M00_AXI 1 5 1 2470 1160n +preplace netloc axi_hp2_interconnect_M00_AXI 1 5 5 2520 2000 NJ 2000 NJ 2000 NJ 2000 6430 +preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 4 1 2050 1750n +preplace netloc axi_mxfe_rx_xcvr_m_axi 1 4 1 2170 1990n +preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 4 7 2060J 2110 2480J 2100 NJ 2100 NJ 2100 NJ 2100 6480 2040 7500 +preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 4 7 2080J 2120 2490J 2110 NJ 2110 NJ 2110 NJ 2110 6520 2060 7510 +preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 4 7 2040J 2130 2500J 2120 NJ 2120 NJ 2120 NJ 2120 6540 2080 7530 +preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 4 7 NJ 2150 2520J 2130 NJ 2130 NJ 2130 NJ 2130 6560 2120 7600 +preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 4 7 2090J 2140 NJ 2140 NJ 2140 NJ 2140 NJ 2140 6530 2030 7490 +preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 4 7 2130J 1950 NJ 1950 NJ 1950 3700J 1990 NJ 1990 6470 2050 7430 +preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 4 7 2030J 2160 2530J 2150 NJ 2150 NJ 2150 NJ 2150 6550 2070 7350 +preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 4 7 2020J 2170 NJ 2170 3230J 2160 NJ 2160 NJ 2160 N 2160 7590 +preplace netloc axi_mxfe_tx_dma_m_src_axi 1 8 1 5280 1610n +preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 9 2 6560 1490 7430 +preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 9 2 6550 1500 7410 +preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 9 2 6530 1520 7380 +preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 9 2 6510 1530 7330 +preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 9 2 N 1080 7480 +preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 9 2 N 1100 7460 +preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 9 2 N 1120 7440 +preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 9 2 N 1140 7420 +preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 9 2 N 1060 7500 +preplace netloc dds_pulse_wrapper_0_m_axis_out 1 10 1 7610 800n +preplace netloc mxfe_rx_data_offload_m_axis 1 3 1 1540 1730n +preplace netloc s_axis_1 1 8 1 5300 1770n +preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 6 1 3210 940n +preplace netloc tx_mxfe_tpl_core_link 1 8 1 5210 800n +preplace netloc util_mxfe_xcvr_rx_0 1 11 1 7960 2030n +preplace netloc util_mxfe_xcvr_rx_1 1 11 1 7970 2050n +preplace netloc util_mxfe_xcvr_rx_2 1 11 1 8000 2070n +preplace netloc util_mxfe_xcvr_rx_3 1 11 1 8030 2090n +levelinfo -pg 1 -70 180 740 1420 1862 2320 2830 3480 4650 6290 7200 7806 8260 8460 +pagesize -pg 1 -db -bbox -sgen -210 -30 8600 6480 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_system() +cr_bd_system "" +set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] + +#call make_wrapper to create wrapper files +if { [get_property IS_LOCKED [ get_files -norecurse system.bd] ] == 1 } { + import_files -fileset sources_1 [file normalize "${origin_dir}/ad9081_fmca_ebz_zcu102.gen/sources_1/bd/system/hdl/system_wrapper.v" ] +} else { + set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse system.bd] -top] + add_files -norecurse -fileset sources_1 $wrapper_path +} + + +set idrFlowPropertiesConstraints "" +catch { + set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints] + set_param runs.disableIDRFlowPropertyConstraints 1 +} + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2022" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2022" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] +catch { + if { $idrFlowPropertiesConstraints != {} } { + set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints + } +} + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/script/recreate.tcl b/script/recreate.tcl new file mode 100644 index 0000000..a106b4c --- /dev/null +++ b/script/recreate.tcl @@ -0,0 +1,3018 @@ +#***************************************************************************************** +# Vivado (TM) v2022.2 (64-bit) +# +# recreate.tcl: Tcl script for re-creating project 'ad9081_fmca_ebz_zcu102' +# +# Generated by Vivado on Sun Oct 22 15:33:56 -0400 2023 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (recreate.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/common/ad_3w_spi.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/common/ad_iobuf.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/my_source/src/system_top.v" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/system_constr.xdc" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/timing_constr.xdc" +# "C:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/constraints/zcu102_system_constr.xdc" +# +# 3. The following remote source files that were added to the original project:- +# +# +# +#***************************************************************************************** + +# Check file required for this script exists +proc checkRequiredFiles { origin_dir} { + set status true + set files [list \ + "[file normalize "$origin_dir/../common/ad_3w_spi.v"]"\ + "[file normalize "$origin_dir/../common/ad_iobuf.v"]"\ + "[file normalize "$origin_dir/../my_source/src/system_top.v"]"\ + "[file normalize "$origin_dir/../constraints/system_constr.xdc"]"\ + "[file normalize "$origin_dir/../constraints/timing_constr.xdc"]"\ + "[file normalize "$origin_dir/../constraints/zcu102_system_constr.xdc"]"\ + ] + foreach ifile $files { + if { ![file isfile $ifile] } { + puts " Could not find local file $ifile " + set status false + } + } + + set paths [list \ + "[file normalize "$origin_dir/../../../../../../Users/nicks/AppData/Roaming/Xilinx/Vivado/my_source"]"]"\ + "[file normalize "$origin_dir/../../../../../../Users/Projects/Erisys/sweep/sweep/source"]"]"\ + "[file normalize "$origin_dir/../../../../../../Users/nicks/AppData/library"]"]"\ + ] + foreach ipath $paths { + if { ![file isdirectory $ipath] } { + puts " Could not access $ipath " + set status false + } + } + + return $status +} +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "ad9081_fmca_ebz_zcu102" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "recreate.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/../"]" + +# Check for paths and files needed for project creation +set validate_required 0 +if { $validate_required } { + if { [checkRequiredFiles $origin_dir] } { + puts "Tcl file $script_file is valid. All files required for project creation is accesable. " + } else { + puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. " + return + } +} + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu9eg-ffvb1156-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../../../../../../Users/nicks/AppData/Roaming/Xilinx/Vivado/2019.2/xhub/board_store"]" -objects $obj +set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.4" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "enable_resource_estimation" -value "0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "C:/ZCU102/hdl/ipcache" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "platform.board_id" -value "zcu102" -objects $obj +set_property -name "revised_directory_structure" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "sim_compile_state" -value "1" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "18" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "18" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "18" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "18" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "18" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "18" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +if { $obj != {} } { + set_property "ip_repo_paths" "[file normalize "$origin_dir/../my_source"] [file normalize "$origin_dir/../../../../../../Projects/Erisys/sweep/sweep/source"] [file normalize "$origin_dir/../../../../library"]" $obj + + # Rebuild user ip_repo's index before adding any source files + update_ip_catalog -rebuild +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/../common/ad_3w_spi.v" ]\ + [file normalize "${origin_dir}/../common/ad_iobuf.v" ]\ + [file normalize "${origin_dir}/../my_source/src/system_top.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj +set_property -name "top" -value "system_top" -objects $obj +set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/../constraints/system_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/system_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/../constraints/timing_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/timing_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/../constraints/zcu102_system_constr.xdc"]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "constraints/zcu102_system_constr.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD system +proc cr_bd_system { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name system + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:xlconstant:1.1\ + xilinx.com:ip:smartconnect:1.0\ + analog.com:user:axi_dmac:1.0\ + analog.com:user:axi_adxcvr:1.0\ + analog.com:user:axi_sysid:1.0\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:util_reduced_logic:2.0\ + xilinx.com:user:dds_pulse_wrapper:1.0\ + xilinx.com:ip:util_vector_logic:2.0\ + analog.com:user:sysid_rom:1.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:zynq_ultra_ps_e:3.4\ + analog.com:user:util_cpack2:1.0\ + analog.com:user:util_upack2:1.0\ + analog.com:user:util_adxcvr:1.0\ + analog.com:user:jesd204_rx:1.0\ + analog.com:user:axi_jesd204_rx:1.0\ + analog.com:user:jesd204_tx:1.0\ + analog.com:user:axi_jesd204_tx:1.0\ + analog.com:user:data_offload:1.0\ + analog.com:user:util_do_ram:1.0\ + analog.com:user:ad_ip_jesd204_tpl_adc:1.0\ + xilinx.com:ip:xlslice:1.0\ + analog.com:user:ad_ip_jesd204_tpl_dac:1.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +# Hierarchical cell: tx_mxfe_tpl_core +proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -from 15 -to 0 dac_data_0 + create_bd_pin -dir I -from 15 -to 0 dac_data_1 + create_bd_pin -dir I -from 15 -to 0 dac_data_2 + create_bd_pin -dir I -from 15 -to 0 dac_data_3 + create_bd_pin -dir I -from 15 -to 0 dac_data_4 + create_bd_pin -dir I -from 15 -to 0 dac_data_5 + create_bd_pin -dir I -from 15 -to 0 dac_data_6 + create_bd_pin -dir I -from 15 -to 0 dac_data_7 + create_bd_pin -dir I dac_dunf + create_bd_pin -dir O -from 0 -to 0 dac_enable_0 + create_bd_pin -dir O -from 0 -to 0 dac_enable_1 + create_bd_pin -dir O -from 0 -to 0 dac_enable_2 + create_bd_pin -dir O -from 0 -to 0 dac_enable_3 + create_bd_pin -dir O -from 0 -to 0 dac_enable_4 + create_bd_pin -dir O -from 0 -to 0 dac_enable_5 + create_bd_pin -dir O -from 0 -to 0 dac_enable_6 + create_bd_pin -dir O -from 0 -to 0 dac_enable_7 + create_bd_pin -dir O dac_rst + create_bd_pin -dir I dac_sync_manual_req_in + create_bd_pin -dir O dac_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 dac_valid_0 + create_bd_pin -dir O -from 0 -to 0 dac_valid_1 + create_bd_pin -dir O -from 0 -to 0 dac_valid_2 + create_bd_pin -dir O -from 0 -to 0 dac_valid_3 + create_bd_pin -dir O -from 0 -to 0 dac_valid_4 + create_bd_pin -dir O -from 0 -to 0 dac_valid_5 + create_bd_pin -dir O -from 0 -to 0 dac_valid_6 + create_bd_pin -dir O -from 0 -to 0 dac_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: dac_tpl_core, and set properties + set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.IQCORRECTION_DISABLE {0} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $dac_tpl_core + + + # Create instance: data_concat0, and set properties + set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ] + set_property CONFIG.NUM_PORTS {8} $data_concat0 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins link] [get_bd_intf_pins dac_tpl_core/link] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0] + connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1] + connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2] + connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3] + connect_bd_net -net dac_data_4_1 [get_bd_pins dac_data_4] [get_bd_pins data_concat0/In4] + connect_bd_net -net dac_data_5_1 [get_bd_pins dac_data_5] [get_bd_pins data_concat0/In5] + connect_bd_net -net dac_data_6_1 [get_bd_pins dac_data_6] [get_bd_pins data_concat0/In6] + connect_bd_net -net dac_data_7_1 [get_bd_pins dac_data_7] [get_bd_pins data_concat0/In7] + connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf] + connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_rst] [get_bd_pins dac_tpl_core/dac_rst] + connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_sync_manual_req_out] [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_concat0_dout [get_bd_pins dac_tpl_core/dac_ddata] [get_bd_pins data_concat0/dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins dac_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins dac_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins dac_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins dac_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins dac_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins dac_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins dac_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins dac_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins dac_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins dac_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins dac_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins dac_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins dac_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins dac_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins dac_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins dac_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx_mxfe_tpl_core +proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir O -from 15 -to 0 adc_data_0 + create_bd_pin -dir O -from 15 -to 0 adc_data_1 + create_bd_pin -dir O -from 15 -to 0 adc_data_2 + create_bd_pin -dir O -from 15 -to 0 adc_data_3 + create_bd_pin -dir O -from 15 -to 0 adc_data_4 + create_bd_pin -dir O -from 15 -to 0 adc_data_5 + create_bd_pin -dir O -from 15 -to 0 adc_data_6 + create_bd_pin -dir O -from 15 -to 0 adc_data_7 + create_bd_pin -dir I adc_dovf + create_bd_pin -dir O -from 0 -to 0 adc_enable_0 + create_bd_pin -dir O -from 0 -to 0 adc_enable_1 + create_bd_pin -dir O -from 0 -to 0 adc_enable_2 + create_bd_pin -dir O -from 0 -to 0 adc_enable_3 + create_bd_pin -dir O -from 0 -to 0 adc_enable_4 + create_bd_pin -dir O -from 0 -to 0 adc_enable_5 + create_bd_pin -dir O -from 0 -to 0 adc_enable_6 + create_bd_pin -dir O -from 0 -to 0 adc_enable_7 + create_bd_pin -dir O adc_rst + create_bd_pin -dir I adc_sync_manual_req_in + create_bd_pin -dir O adc_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 adc_valid_0 + create_bd_pin -dir O -from 0 -to 0 adc_valid_1 + create_bd_pin -dir O -from 0 -to 0 adc_valid_2 + create_bd_pin -dir O -from 0 -to 0 adc_valid_3 + create_bd_pin -dir O -from 0 -to 0 adc_valid_4 + create_bd_pin -dir O -from 0 -to 0 adc_valid_5 + create_bd_pin -dir O -from 0 -to 0 adc_valid_6 + create_bd_pin -dir O -from 0 -to 0 adc_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -from 127 -to 0 link_data + create_bd_pin -dir I -from 3 -to 0 link_sof + create_bd_pin -dir I link_valid + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: adc_tpl_core, and set properties + set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $adc_tpl_core + + + # Create instance: data_slice_0, and set properties + set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_0 + + + # Create instance: data_slice_1, and set properties + set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {16} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_1 + + + # Create instance: data_slice_2, and set properties + set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {47} \ + CONFIG.DIN_TO {32} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_2 + + + # Create instance: data_slice_3, and set properties + set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {48} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_3 + + + # Create instance: data_slice_4, and set properties + set data_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {79} \ + CONFIG.DIN_TO {64} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_4 + + + # Create instance: data_slice_5, and set properties + set data_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {95} \ + CONFIG.DIN_TO {80} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_5 + + + # Create instance: data_slice_6, and set properties + set data_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {111} \ + CONFIG.DIN_TO {96} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_6 + + + # Create instance: data_slice_7, and set properties + set data_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {127} \ + CONFIG.DIN_TO {112} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_7 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf] + connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in] + connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din] [get_bd_pins data_slice_4/Din] [get_bd_pins data_slice_5/Din] [get_bd_pins data_slice_6/Din] [get_bd_pins data_slice_7/Din] + connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_rst] [get_bd_pins adc_tpl_core/adc_rst] + connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_sync_manual_req_out] [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_slice_0_Dout [get_bd_pins adc_data_0] [get_bd_pins data_slice_0/Dout] + connect_bd_net -net data_slice_1_Dout [get_bd_pins adc_data_1] [get_bd_pins data_slice_1/Dout] + connect_bd_net -net data_slice_2_Dout [get_bd_pins adc_data_2] [get_bd_pins data_slice_2/Dout] + connect_bd_net -net data_slice_3_Dout [get_bd_pins adc_data_3] [get_bd_pins data_slice_3/Dout] + connect_bd_net -net data_slice_4_Dout [get_bd_pins adc_data_4] [get_bd_pins data_slice_4/Dout] + connect_bd_net -net data_slice_5_Dout [get_bd_pins adc_data_5] [get_bd_pins data_slice_5/Dout] + connect_bd_net -net data_slice_6_Dout [get_bd_pins adc_data_6] [get_bd_pins data_slice_6/Dout] + connect_bd_net -net data_slice_7_Dout [get_bd_pins adc_data_7] [get_bd_pins data_slice_7/Dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins adc_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins adc_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins adc_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins adc_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins adc_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins adc_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins adc_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins adc_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk] + connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data] + connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof] + connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins adc_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins adc_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins adc_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins adc_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins adc_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins adc_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins adc_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins adc_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_tx_data_offload +proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_CYCLIC_EN {true} \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {1} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_rx_data_offload +proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {0} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_tx_jesd +proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3 + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: tx, and set properties + set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $tx + + + # Create instance: tx_axi, and set properties + set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $tx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi] + connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx/tx_cfg] [get_bd_intf_pins tx_axi/tx_cfg] + connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx/tx_ctrl] [get_bd_intf_pins tx_axi/tx_ctrl] + connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data] + connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event] + connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config] + connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx_phy0] [get_bd_intf_pins tx/tx_phy0] + connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx_phy1] [get_bd_intf_pins tx/tx_phy1] + connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx_phy2] [get_bd_intf_pins tx/tx_phy2] + connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx_phy3] [get_bd_intf_pins tx/tx_phy3] + connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx/device_clk] [get_bd_pins tx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx/clk] [get_bd_pins tx_axi/core_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn] + connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref] + connect_bd_net -net tx_axi_core_reset [get_bd_pins tx/reset] [get_bd_pins tx_axi/core_reset] + connect_bd_net -net tx_axi_device_reset [get_bd_pins tx/device_reset] [get_bd_pins tx_axi/device_reset] + connect_bd_net -net tx_axi_irq [get_bd_pins irq] [get_bd_pins tx_axi/irq] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_rx_jesd +proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir O phy_en_char_align + create_bd_pin -dir O -from 127 -to 0 rx_data_tdata + create_bd_pin -dir O rx_data_tvalid + create_bd_pin -dir O -from 3 -to 0 rx_eof + create_bd_pin -dir O -from 3 -to 0 rx_sof + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: rx, and set properties + set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_INPUT_PIPELINE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $rx + + + # Create instance: rx_axi, and set properties + set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $rx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx/rx_cfg] [get_bd_intf_pins rx_axi/rx_cfg] + connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx_phy0] [get_bd_intf_pins rx/rx_phy0] + connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx_phy1] [get_bd_intf_pins rx/rx_phy1] + connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx_phy2] [get_bd_intf_pins rx/rx_phy2] + connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx_phy3] [get_bd_intf_pins rx/rx_phy3] + connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event] + connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config] + connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx/device_clk] [get_bd_pins rx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx/clk] [get_bd_pins rx_axi/core_clk] + connect_bd_net -net rx_axi_core_reset [get_bd_pins rx/reset] [get_bd_pins rx_axi/core_reset] + connect_bd_net -net rx_axi_device_reset [get_bd_pins rx/device_reset] [get_bd_pins rx_axi/device_reset] + connect_bd_net -net rx_axi_irq [get_bd_pins irq] [get_bd_pins rx_axi/irq] + connect_bd_net -net rx_phy_en_char_align [get_bd_pins phy_en_char_align] [get_bd_pins rx/phy_en_char_align] + connect_bd_net -net rx_rx_data [get_bd_pins rx_data_tdata] [get_bd_pins rx/rx_data] + connect_bd_net -net rx_rx_eof [get_bd_pins rx_eof] [get_bd_pins rx/rx_eof] + connect_bd_net -net rx_rx_sof [get_bd_pins rx_sof] [get_bd_pins rx/rx_sof] + connect_bd_net -net rx_rx_valid [get_bd_pins rx_data_tvalid] [get_bd_pins rx/rx_valid] + connect_bd_net -net rx_sync [get_bd_pins sync] [get_bd_pins rx/sync] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk_in_1 [ create_bd_port -dir I clk_in_1 ] + set ext_sync_in [ create_bd_port -dir I ext_sync_in ] + set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ] + set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ] + set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ] + set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ] + set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ] + set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ] + set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ] + set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ] + set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ] + set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ] + set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ] + set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ] + set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ] + set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ] + set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ] + set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ] + set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ] + set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ] + set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ] + set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ] + set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ] + set rx_device_clk [ create_bd_port -dir I rx_device_clk ] + set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ] + set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ] + set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] + set spi0_miso [ create_bd_port -dir I spi0_miso ] + set spi0_mosi [ create_bd_port -dir O spi0_mosi ] + set spi0_sclk [ create_bd_port -dir O spi0_sclk ] + set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ] + set spi1_miso [ create_bd_port -dir I spi1_miso ] + set spi1_mosi [ create_bd_port -dir O spi1_mosi ] + set spi1_sclk [ create_bd_port -dir O spi1_sclk ] + set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ] + set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ] + set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ] + set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ] + set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ] + set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ] + set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ] + set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ] + set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ] + set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ] + set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ] + set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ] + set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ] + set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ] + set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ] + set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ] + set tx_device_clk [ create_bd_port -dir I tx_device_clk ] + set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ] + set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ] + + # Create instance: GND_1, and set properties + set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $GND_1 + + + # Create instance: VCC_1, and set properties + set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $VCC_1 + + + # Create instance: axi_cpu_interconnect, and set properties + set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {11} \ + CONFIG.NUM_SI {1} \ + ] $axi_cpu_interconnect + + + # Create instance: axi_hp0_interconnect, and set properties + set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp0_interconnect + + + # Create instance: axi_hp1_interconnect, and set properties + set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp1_interconnect + + + # Create instance: axi_hp2_interconnect, and set properties + set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp2_interconnect + + + # Create instance: axi_mxfe_rx_dma, and set properties + set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {false} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {0} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_mxfe_rx_dma + + + # Create instance: axi_mxfe_rx_jesd + create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd + + # Create instance: axi_mxfe_rx_xcvr, and set properties + set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.LPM_OR_DFE_N {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {0} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {0} \ + ] $axi_mxfe_rx_xcvr + + + # Create instance: axi_mxfe_tx_dma, and set properties + set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {true} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + ] $axi_mxfe_tx_dma + + + # Create instance: axi_mxfe_tx_jesd + create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd + + # Create instance: axi_mxfe_tx_xcvr, and set properties + set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {1} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {1} \ + ] $axi_mxfe_tx_xcvr + + + # Create instance: axi_sysid_0, and set properties + set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ] + set_property CONFIG.ROM_ADDR_BITS {9} $axi_sysid_0 + + + # Create instance: cpack_reset_sources, and set properties + set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ] + set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources + + + # Create instance: cpack_rst_logic, and set properties + set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {3} \ + ] $cpack_rst_logic + + + # Create instance: dds_pulse_wrapper_0, and set properties + set dds_pulse_wrapper_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dds_pulse_wrapper:1.0 dds_pulse_wrapper_0 ] + set_property CONFIG.FPGA_REVISION_DATE {0x09112023} $dds_pulse_wrapper_0 + + + # Create instance: manual_sync_or, and set properties + set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $manual_sync_or + + + # Create instance: mxfe_rx_data_offload + create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload + + # Create instance: mxfe_tx_data_offload + create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload + + # Create instance: rom_sys_0, and set properties + set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ] + set_property -dict [list \ + CONFIG.PATH_TO_FILE {c:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/mem_init_sys.txt} \ + CONFIG.ROM_ADDR_BITS {9} \ + ] $rom_sys_0 + + + # Create instance: rx_device_clk_rstgen, and set properties + set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ] + + # Create instance: rx_do_rstout_logic, and set properties + set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rx_do_rstout_logic + + + # Create instance: rx_mxfe_tpl_core + create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core + + # Create instance: spi0_csn_concat, and set properties + set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat + + + # Create instance: spi1_csn_concat, and set properties + set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat + + + # Create instance: sys_250m_rstgen, and set properties + set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen + + + # Create instance: sys_500m_rstgen, and set properties + set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen + + + # Create instance: sys_concat_intc_0, and set properties + set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0 + + + # Create instance: sys_concat_intc_1, and set properties + set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1 + + + # Create instance: sys_ps8, and set properties + set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 sys_ps8 ] + set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\ +GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ +\ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Single Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {0x0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {1} \ + CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \ + CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \ + CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ +\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ +\ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {0} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {1} \ + CONFIG.PSU__USE__S_AXI_GP4 {1} \ + ] $sys_ps8 + + + # Create instance: sys_rstgen, and set properties + set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen + + + # Create instance: tx_device_clk_rstgen, and set properties + set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ] + + # Create instance: tx_mxfe_tpl_core + create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core + + # Create instance: upack_reset_sources, and set properties + set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ] + set_property CONFIG.NUM_PORTS {2} $upack_reset_sources + + + # Create instance: upack_rst_logic, and set properties + set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {2} \ + ] $upack_rst_logic + + + # Create instance: util_mxfe_cpack, and set properties + set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_cpack + + + # Create instance: util_mxfe_upack, and set properties + set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_upack + + + # Create instance: util_mxfe_xcvr, and set properties + set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ] + set_property -dict [list \ + CONFIG.A_TXDIFFCTRL {0x0C} \ + CONFIG.CH_HSPMUX {0x6868} \ + CONFIG.CPLL_CFG0 {0x01FA} \ + CONFIG.CPLL_CFG1 {0x0023} \ + CONFIG.CPLL_CFG2 {0x0002} \ + CONFIG.CPLL_FBDIV {2} \ + CONFIG.CPLL_FBDIV_4_5 {5} \ + CONFIG.LINK_MODE {1} \ + CONFIG.POR_CFG {0x0000} \ + CONFIG.PPF0_CFG {0x0F00} \ + CONFIG.PREIQ_FREQ_BST {1} \ + CONFIG.QPLL_CFG0 {0x333c} \ + CONFIG.QPLL_CFG4 {0x0045} \ + CONFIG.QPLL_CP {0x0FF} \ + CONFIG.QPLL_CP_G3 {0x00F} \ + CONFIG.QPLL_FBDIV {"0000010100"} \ + CONFIG.QPLL_LPF {0x2FF} \ + CONFIG.QPLL_REFCLK_DIV {1} \ + CONFIG.RXCDR_CFG0 {0x0003} \ + CONFIG.RXCDR_CFG2_GEN2 {0x265} \ + CONFIG.RXCDR_CFG2_GEN4 {0x0164} \ + CONFIG.RXCDR_CFG3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN2 {0x12} \ + CONFIG.RXCDR_CFG3_GEN3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN4 {0x0012} \ + CONFIG.RXPI_CFG0 {0x0200} \ + CONFIG.RXPI_CFG1 {0x00FD} \ + CONFIG.RX_CLK25_DIV {31} \ + CONFIG.RX_LANE_RATE {10} \ + CONFIG.RX_NUM_OF_LANES {4} \ + CONFIG.RX_OUT_DIV {1} \ + CONFIG.RX_WIDEMODE_CDR {0x0} \ + CONFIG.TXPI_CFG {0x0000} \ + CONFIG.TX_CLK25_DIV {31} \ + CONFIG.TX_LANE_RATE {10} \ + CONFIG.TX_NUM_OF_LANES {4} \ + CONFIG.TX_PI_BIASSET {3} \ + ] $util_mxfe_xcvr + + + # Create interface connections + connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] + connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] + connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0] [get_bd_intf_pins util_mxfe_xcvr/tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1] [get_bd_intf_pins util_mxfe_xcvr/tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2] [get_bd_intf_pins util_mxfe_xcvr/tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3] [get_bd_intf_pins util_mxfe_xcvr/tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0] + connect_bd_intf_net -intf_net dds_pulse_wrapper_0_m_axis_out [get_bd_intf_pins dds_pulse_wrapper_0/m_axis_out] [get_bd_intf_pins util_mxfe_upack/s_axis] + connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins axi_mxfe_rx_dma/s_axis] [get_bd_intf_pins mxfe_rx_data_offload/m_axis] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins axi_mxfe_tx_dma/m_axis] [get_bd_intf_pins mxfe_tx_data_offload/s_axis] + connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD] + connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data] [get_bd_intf_pins tx_mxfe_tpl_core/link] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0] [get_bd_intf_pins util_mxfe_xcvr/rx_0] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1] [get_bd_intf_pins util_mxfe_xcvr/rx_1] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2] [get_bd_intf_pins util_mxfe_xcvr/rx_2] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3] [get_bd_intf_pins util_mxfe_xcvr/rx_3] + + # Create port connections + connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] + connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n] + connect_bd_net -net adc_dovf_1 [get_bd_pins rx_mxfe_tpl_core/adc_dovf] [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] + connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5] + connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3] + connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid] + connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof] + connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_ports rx_sync_0] [get_bd_pins axi_mxfe_rx_jesd/sync] + connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3] + connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4] + connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2] + connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0] + connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr] + connect_bd_net -net clk_in_1_1 [get_bd_ports clk_in_1] [get_bd_pins dds_pulse_wrapper_0/clk_in] + connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1] + connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset] + connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in] + connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i] + connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req] + connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req] + connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1] + connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] + connect_bd_net -net rom_sys_0_rom_data [get_bd_pins axi_sysid_0/sys_rom_data] [get_bd_pins rom_sys_0/rom_data] + connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n] + connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p] + connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n] + connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p] + connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n] + connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p] + connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n] + connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p] + connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_cpack/clk] + connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins cpack_reset_sources/In0] [get_bd_pins rx_device_clk_rstgen/peripheral_reset] + connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins cpack_reset_sources/In2] [get_bd_pins rx_do_rstout_logic/Res] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_4 [get_bd_pins rx_mxfe_tpl_core/adc_data_4] [get_bd_pins util_mxfe_cpack/fifo_wr_data_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_5 [get_bd_pins rx_mxfe_tpl_core/adc_data_5] [get_bd_pins util_mxfe_cpack/fifo_wr_data_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_6 [get_bd_pins rx_mxfe_tpl_core/adc_data_6] [get_bd_pins util_mxfe_cpack/fifo_wr_data_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_7 [get_bd_pins rx_mxfe_tpl_core/adc_data_7] [get_bd_pins util_mxfe_cpack/fifo_wr_data_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_4 [get_bd_pins rx_mxfe_tpl_core/adc_enable_4] [get_bd_pins util_mxfe_cpack/enable_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_5 [get_bd_pins rx_mxfe_tpl_core/adc_enable_5] [get_bd_pins util_mxfe_cpack/enable_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_6 [get_bd_pins rx_mxfe_tpl_core/adc_enable_6] [get_bd_pins util_mxfe_cpack/enable_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_7 [get_bd_pins rx_mxfe_tpl_core/adc_enable_7] [get_bd_pins util_mxfe_cpack/enable_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins cpack_reset_sources/In1] [get_bd_pins rx_mxfe_tpl_core/adc_rst] + connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins manual_sync_or/Op1] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en] + connect_bd_net -net spi0_csn_concat_dout [get_bd_ports spi0_csn] [get_bd_pins spi0_csn_concat/dout] + connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i] + connect_bd_net -net spi1_csn_concat_dout [get_bd_ports spi1_csn] [get_bd_pins spi1_csn_concat/dout] + connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i] + connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync] + connect_bd_net -net sys_250m_clk [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] + connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset] + connect_bd_net -net sys_250m_resetn [get_bd_pins axi_hp2_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins sys_250m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_500m_clk [get_bd_pins sys_500m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk2] + connect_bd_net -net sys_500m_reset [get_bd_pins sys_500m_rstgen/peripheral_reset] + connect_bd_net -net sys_500m_resetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0] + connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins util_mxfe_xcvr/up_clk] + connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins util_mxfe_xcvr/up_rstn] + connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_ports gpio_o] [get_bd_pins sys_ps8/emio_gpio_o] + connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_ports gpio_t] [get_bd_pins sys_ps8/emio_gpio_t] + connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_ports spi0_mosi] [get_bd_pins sys_ps8/emio_spi0_m_o] + connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_ports spi0_sclk] [get_bd_pins sys_ps8/emio_spi0_sclk_o] + connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins spi0_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins spi0_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins spi0_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi0_ss_o_n] + connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_ports spi1_mosi] [get_bd_pins sys_ps8/emio_spi1_m_o] + connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_ports spi1_sclk] [get_bd_pins sys_ps8/emio_spi1_sclk_o] + connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins spi1_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins spi1_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins spi1_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi1_ss_o_n] + connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in] [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_rstgen/ext_reset_in] + connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref] + connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref] + connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins dds_pulse_wrapper_0/m_axis_aclk_in] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_upack/clk] + connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_4 [get_bd_pins tx_mxfe_tpl_core/dac_enable_4] [get_bd_pins util_mxfe_upack/enable_4] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_5 [get_bd_pins tx_mxfe_tpl_core/dac_enable_5] [get_bd_pins util_mxfe_upack/enable_5] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_6 [get_bd_pins tx_mxfe_tpl_core/dac_enable_6] [get_bd_pins util_mxfe_upack/enable_6] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_7 [get_bd_pins tx_mxfe_tpl_core/dac_enable_7] [get_bd_pins util_mxfe_upack/enable_7] + connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1] + connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins manual_sync_or/Op2] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en] + connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1] + connect_bd_net -net upack_rst_logic_Res [get_bd_pins dds_pulse_wrapper_0/rst_in] [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins tx_mxfe_tpl_core/dac_data_0] [get_bd_pins util_mxfe_upack/fifo_rd_data_0] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins tx_mxfe_tpl_core/dac_data_1] [get_bd_pins util_mxfe_upack/fifo_rd_data_1] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins tx_mxfe_tpl_core/dac_data_2] [get_bd_pins util_mxfe_upack/fifo_rd_data_2] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins tx_mxfe_tpl_core/dac_data_3] [get_bd_pins util_mxfe_upack/fifo_rd_data_3] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_4 [get_bd_pins tx_mxfe_tpl_core/dac_data_4] [get_bd_pins util_mxfe_upack/fifo_rd_data_4] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_5 [get_bd_pins tx_mxfe_tpl_core/dac_data_5] [get_bd_pins util_mxfe_upack/fifo_rd_data_5] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_6 [get_bd_pins tx_mxfe_tpl_core/dac_data_6] [get_bd_pins util_mxfe_upack/fifo_rd_data_6] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_7 [get_bd_pins tx_mxfe_tpl_core/dac_data_7] [get_bd_pins util_mxfe_upack/fifo_rd_data_7] + connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins axi_mxfe_rx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] + connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_ports tx_data_0_n] [get_bd_pins util_mxfe_xcvr/tx_0_n] + connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_ports tx_data_0_p] [get_bd_pins util_mxfe_xcvr/tx_0_p] + connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_ports tx_data_1_n] [get_bd_pins util_mxfe_xcvr/tx_1_n] + connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_ports tx_data_1_p] [get_bd_pins util_mxfe_xcvr/tx_1_p] + connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_ports tx_data_2_n] [get_bd_pins util_mxfe_xcvr/tx_2_n] + connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_ports tx_data_2_p] [get_bd_pins util_mxfe_xcvr/tx_2_p] + connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_ports tx_data_3_n] [get_bd_pins util_mxfe_xcvr/tx_3_n] + connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_ports tx_data_3_p] [get_bd_pins util_mxfe_xcvr/tx_3_p] + connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins axi_mxfe_tx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_LPS_OCM] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_PCIE_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force + assign_bd_address -offset 0x9C420000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C430000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x85000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_QSPI] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_QSPI] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.18105", + "Default View_TopLeft":"4062,2416", + "ExpandedHierarchyInLayout":"/tx_mxfe_tpl_core", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +preplace port port-id_spi0_sclk -pg 1 -lvl 13 -x 8950 -y 1200 -defaultsOSRD +preplace port port-id_spi0_mosi -pg 1 -lvl 13 -x 8950 -y 1230 -defaultsOSRD +preplace port port-id_spi0_miso -pg 1 -lvl 0 -x -70 -y 1570 -defaultsOSRD +preplace port port-id_spi1_sclk -pg 1 -lvl 13 -x 8950 -y 1350 -defaultsOSRD +preplace port port-id_spi1_mosi -pg 1 -lvl 13 -x 8950 -y 1380 -defaultsOSRD +preplace port port-id_spi1_miso -pg 1 -lvl 0 -x -70 -y 1600 -defaultsOSRD +preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x -70 -y 810 -defaultsOSRD +preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x -70 -y 2610 -defaultsOSRD +preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x -70 -y 2580 -defaultsOSRD +preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x -70 -y 20 -defaultsOSRD +preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x -70 -y 2490 -defaultsOSRD +preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x -70 -y 2460 -defaultsOSRD +preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x -70 -y 2430 -defaultsOSRD +preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x -70 -y 2520 -defaultsOSRD +preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x -70 -y 2550 -defaultsOSRD +preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x -70 -y 2700 -defaultsOSRD +preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x -70 -y 2730 -defaultsOSRD +preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x -70 -y 2790 -defaultsOSRD +preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x -70 -y 2760 -defaultsOSRD +preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x -70 -y 2360 -defaultsOSRD +preplace port port-id_tx_data_0_p -pg 1 -lvl 13 -x 8950 -y 2200 -defaultsOSRD +preplace port port-id_tx_data_0_n -pg 1 -lvl 13 -x 8950 -y 2230 -defaultsOSRD +preplace port port-id_tx_data_1_p -pg 1 -lvl 13 -x 8950 -y 2260 -defaultsOSRD +preplace port port-id_tx_data_1_n -pg 1 -lvl 13 -x 8950 -y 2290 -defaultsOSRD +preplace port port-id_tx_data_2_p -pg 1 -lvl 13 -x 8950 -y 2320 -defaultsOSRD +preplace port port-id_tx_data_2_n -pg 1 -lvl 13 -x 8950 -y 2350 -defaultsOSRD +preplace port port-id_tx_data_3_p -pg 1 -lvl 13 -x 8950 -y 2390 -defaultsOSRD +preplace port port-id_tx_data_3_n -pg 1 -lvl 13 -x 8950 -y 2420 -defaultsOSRD +preplace port port-id_rx_data_4_n -pg 1 -lvl 0 -x -70 -y 50 -defaultsOSRD +preplace port port-id_rx_data_4_p -pg 1 -lvl 0 -x -70 -y 80 -defaultsOSRD +preplace port port-id_rx_data_5_n -pg 1 -lvl 0 -x -70 -y 110 -defaultsOSRD +preplace port port-id_rx_data_5_p -pg 1 -lvl 0 -x -70 -y 140 -defaultsOSRD +preplace port port-id_rx_data_6_n -pg 1 -lvl 0 -x -70 -y 170 -defaultsOSRD +preplace port port-id_rx_data_6_p -pg 1 -lvl 0 -x -70 -y 200 -defaultsOSRD +preplace port port-id_rx_data_7_n -pg 1 -lvl 0 -x -70 -y 230 -defaultsOSRD +preplace port port-id_rx_data_7_p -pg 1 -lvl 0 -x -70 -y 260 -defaultsOSRD +preplace port port-id_tx_data_4_n -pg 1 -lvl 13 -x 8950 -y 200 -defaultsOSRD +preplace port port-id_tx_data_4_p -pg 1 -lvl 13 -x 8950 -y 170 -defaultsOSRD +preplace port port-id_tx_data_5_n -pg 1 -lvl 13 -x 8950 -y 140 -defaultsOSRD +preplace port port-id_tx_data_5_p -pg 1 -lvl 13 -x 8950 -y 110 -defaultsOSRD +preplace port port-id_tx_data_6_n -pg 1 -lvl 13 -x 8950 -y -10 -defaultsOSRD +preplace port port-id_tx_data_6_p -pg 1 -lvl 13 -x 8950 -y 80 -defaultsOSRD +preplace port port-id_tx_data_7_n -pg 1 -lvl 13 -x 8950 -y 50 -defaultsOSRD +preplace port port-id_tx_data_7_p -pg 1 -lvl 13 -x 8950 -y 20 -defaultsOSRD +preplace port port-id_ext_sync_in -pg 1 -lvl 0 -x -70 -y 730 -defaultsOSRD +preplace port port-id_clk_in_1 -pg 1 -lvl 0 -x -70 -y 780 -defaultsOSRD +preplace portBus spi0_csn -pg 1 -lvl 13 -x 8950 -y 1290 -defaultsOSRD +preplace portBus spi1_csn -pg 1 -lvl 13 -x 8950 -y 1570 -defaultsOSRD +preplace portBus gpio_i -pg 1 -lvl 0 -x -70 -y 1540 -defaultsOSRD +preplace portBus gpio_o -pg 1 -lvl 13 -x 8950 -y 1140 -defaultsOSRD +preplace portBus gpio_t -pg 1 -lvl 13 -x 8950 -y 1170 -defaultsOSRD +preplace portBus rx_sync_0 -pg 1 -lvl 13 -x 8950 -y 2060 -defaultsOSRD +preplace portBus tx_sync_0 -pg 1 -lvl 0 -x -70 -y 2030 -defaultsOSRD +preplace inst sys_ps8 -pg 1 -lvl 6 -x 2830 -y 1220 -defaultsOSRD +preplace inst sys_rstgen -pg 1 -lvl 1 -x 180 -y 2140 -defaultsOSRD +preplace inst sys_250m_rstgen -pg 1 -lvl 2 -x 740 -y 2140 -defaultsOSRD +preplace inst sys_500m_rstgen -pg 1 -lvl 7 -x 3480 -y 2260 -defaultsOSRD +preplace inst spi0_csn_concat -pg 1 -lvl 12 -x 8744 -y 1290 -defaultsOSRD +preplace inst VCC_1 -pg 1 -lvl 2 -x 740 -y 1740 -defaultsOSRD +preplace inst GND_1 -pg 1 -lvl 2 -x 740 -y 1640 -defaultsOSRD +preplace inst spi1_csn_concat -pg 1 -lvl 12 -x 8744 -y 1570 -defaultsOSRD +preplace inst axi_sysid_0 -pg 1 -lvl 8 -x 4650 -y 4704 -defaultsOSRD +preplace inst rom_sys_0 -pg 1 -lvl 7 -x 3480 -y 1440 -defaultsOSRD +preplace inst axi_cpu_interconnect -pg 1 -lvl 7 -x 3480 -y 1770 -defaultsOSRD +preplace inst sys_concat_intc_0 -pg 1 -lvl 5 -x 2320 -y 1190 -defaultsOSRD +preplace inst sys_concat_intc_1 -pg 1 -lvl 5 -x 2320 -y 1430 -defaultsOSRD +preplace inst axi_hp0_interconnect -pg 1 -lvl 5 -x 2320 -y 2030 -defaultsOSRD +preplace inst util_mxfe_xcvr -pg 1 -lvl 11 -x 8290 -y 2310 -defaultsOSRD +preplace inst axi_mxfe_rx_xcvr -pg 1 -lvl 4 -x 1862 -y 2090 -defaultsOSRD +preplace inst axi_mxfe_rx_jesd -pg 1 -lvl 12 -x 8744 -y 2100 -defaultsOSRD +preplace inst rx_mxfe_tpl_core -pg 1 -lvl 8 -x 4650 -y 300 -defaultsOSRD +preplace inst util_mxfe_cpack -pg 1 -lvl 2 -x 740 -y 970 -defaultsOSRD +preplace inst mxfe_rx_data_offload -pg 1 -lvl 3 -x 1420 -y 1790 -defaultsOSRD +preplace inst axi_mxfe_rx_dma -pg 1 -lvl 4 -x 1862 -y 1770 -defaultsOSRD +preplace inst axi_mxfe_tx_xcvr -pg 1 -lvl 9 -x 6774 -y 1120 -defaultsOSRD +preplace inst axi_mxfe_tx_jesd -pg 1 -lvl 9 -x 6774 -y 1380 -defaultsOSRD +preplace inst tx_mxfe_tpl_core -pg 1 -lvl 8 -x 4650 -y 982 -defaultsOSRD +preplace inst util_mxfe_upack -pg 1 -lvl 11 -x 8290 -y 1040 -defaultsOSRD +preplace inst mxfe_tx_data_offload -pg 1 -lvl 9 -x 6774 -y 1840 -defaultsOSRD +preplace inst axi_mxfe_tx_dma -pg 1 -lvl 8 -x 4650 -y 5538 -defaultsOSRD +preplace inst rx_device_clk_rstgen -pg 1 -lvl 2 -x 740 -y 1880 -defaultsOSRD +preplace inst tx_device_clk_rstgen -pg 1 -lvl 8 -x 4650 -y 5888 -defaultsOSRD +preplace inst axi_hp1_interconnect -pg 1 -lvl 5 -x 2320 -y 2260 -defaultsOSRD +preplace inst axi_hp2_interconnect -pg 1 -lvl 9 -x 6774 -y 1630 -defaultsOSRD +preplace inst manual_sync_or -pg 1 -lvl 9 -x 6774 -y 418 -defaultsOSRD +preplace inst cpack_rst_logic -pg 1 -lvl 11 -x 8290 -y 2910 -defaultsOSRD +preplace inst rx_do_rstout_logic -pg 1 -lvl 8 -x 4650 -y 6098 -defaultsOSRD +preplace inst cpack_reset_sources -pg 1 -lvl 9 -x 6774 -y 3074 -defaultsOSRD +preplace inst upack_rst_logic -pg 1 -lvl 11 -x 8290 -y 1470 -defaultsOSRD +preplace inst upack_reset_sources -pg 1 -lvl 9 -x 6774 -y 810 -defaultsOSRD +preplace inst dds_pulse_wrapper_0 -pg 1 -lvl 10 -x 7684 -y 800 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|dac_tpl_core -pg 1 -lvl 2 -x 4960 -y 2532 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|data_concat0 -pg 1 -lvl 1 -x 4640 -y 2672 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_0 -pg 1 -lvl 2 -x 4960 -y 832 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_0 -pg 1 -lvl 2 -x 4960 -y 932 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_1 -pg 1 -lvl 2 -x 4960 -y 1032 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_1 -pg 1 -lvl 2 -x 4960 -y 1132 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_2 -pg 1 -lvl 2 -x 4960 -y 1232 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_2 -pg 1 -lvl 2 -x 4960 -y 1332 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_3 -pg 1 -lvl 2 -x 4960 -y 1432 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_3 -pg 1 -lvl 2 -x 4960 -y 1532 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_4 -pg 1 -lvl 2 -x 4960 -y 1632 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_4 -pg 1 -lvl 2 -x 4960 -y 1732 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_5 -pg 1 -lvl 2 -x 4960 -y 1832 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_5 -pg 1 -lvl 2 -x 4960 -y 1932 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_6 -pg 1 -lvl 2 -x 4960 -y 2032 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_6 -pg 1 -lvl 2 -x 4960 -y 2132 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|enable_slice_7 -pg 1 -lvl 2 -x 4960 -y 2232 -defaultsOSRD +preplace inst tx_mxfe_tpl_core|valid_slice_7 -pg 1 -lvl 2 -x 4960 -y 2332 -defaultsOSRD +preplace netloc GND_1_dout 1 2 7 1030 1500 NJ 1500 2050 810 NJ 810 3200 920 4170J 3124 5850 +preplace netloc VCC_1_dout 1 2 5 1020 800 NJ 800 NJ 800 NJ 800 3170 +preplace netloc adc_dovf_1 1 2 6 920J 590 NJ 590 NJ 590 NJ 590 NJ 590 3930 +preplace netloc axi_mxfe_rx_dma_irq 1 4 1 2010 1460n +preplace netloc axi_mxfe_rx_jesd_irq 1 4 9 2170 1870 2490J 2020 NJ 2020 3910J 3644 5940J 2020 6940J 1970 7880 1670 NJ 1670 8920 +preplace netloc axi_mxfe_rx_jesd_phy_en_char_align 1 10 3 8110 1690 NJ 1690 8900 +preplace netloc axi_mxfe_rx_jesd_rx_data_tdata 1 7 6 4280 3694 5980J 2070 7000J 1980 7890 1680 NJ 1680 8930 +preplace netloc axi_mxfe_rx_jesd_rx_data_tvalid 1 7 6 4290 3654 5950J 2030 6970J 1990 7840 1700 NJ 1700 8910 +preplace netloc axi_mxfe_rx_jesd_rx_sof 1 7 6 4270 3664 5960J 2040 6930J 2000 7940 1710 NJ 1710 8890 +preplace netloc axi_mxfe_rx_jesd_sync 1 12 1 NJ 2060 +preplace netloc axi_mxfe_rx_xcvr_up_pll_rst 1 4 7 2020 2420 NJ 2420 NJ 2420 3780J 4064 6130J 2440 N 2440 8090 +preplace netloc axi_mxfe_tx_dma_irq 1 4 5 2180 3230 NJ 3230 NJ 3230 3660J 4854 5320 +preplace netloc axi_mxfe_tx_jesd_irq 1 4 6 2180 -20 NJ -20 NJ -20 NJ -20 NJ -20 6930 +preplace netloc axi_mxfe_tx_xcvr_up_pll_rst 1 9 2 N 1180 7850 +preplace netloc axi_sysid_0_rom_addr 1 6 3 3240 1590 4010J 3214 5320 +preplace netloc clk_in_1_1 1 0 10 NJ 780 380J 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 7050J +preplace netloc cpack_reset_sources_dout 1 9 2 NJ 3074 7970 +preplace netloc cpack_rst_logic_Res 1 1 11 430 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 NJ 2850 3670J 4474 6210J 2850 NJ 2850 N 2850 8420 +preplace netloc ext_sync_in_1 1 0 8 NJ 730 350J 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 4260 +preplace netloc gpio_i_1 1 0 7 NJ 1540 NJ 1540 950J 820 NJ 820 NJ 820 NJ 820 3140 +preplace netloc init_req_1 1 2 3 1090 2300 NJ 2300 2010 +preplace netloc init_req_2 1 8 1 6060 1910n +preplace netloc manual_sync_or_Res 1 7 3 4300 680 NJ 680 6920 +preplace netloc mxfe_rx_data_offload_s_axis_tready 1 2 6 1080 4474 NJ 4474 NJ 4474 NJ 4474 NJ 4474 3650J +preplace netloc ref_clk_q0_1 1 0 11 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 NJ 2580 3710J 4204 6170J 2580 N 2580 8080 +preplace netloc rom_sys_0_rom_data 1 7 1 3900 1440n +preplace netloc rx_data_0_n_1 1 0 11 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 3770J 4054 6120J 2430 NJ 2430 8050 +preplace netloc rx_data_0_p_1 1 0 11 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 3760J 4044 6110J 2420 NJ 2420 8040 +preplace netloc rx_data_1_n_1 1 0 11 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 NJ 2550 3730J 4174 6150J 2550 NJ 2550 8070 +preplace netloc rx_data_1_p_1 1 0 11 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 NJ 2520 3740J 4144 6140J 2520 NJ 2520 8060 +preplace netloc rx_data_2_n_1 1 0 11 -20J 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 NJ 2600 3700J 4224 6180J 2600 NJ 2600 8100 +preplace netloc rx_data_2_p_1 1 0 11 -40J 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 NJ 2570 3720J 4194 6160J 2570 NJ 2570 N +preplace netloc rx_data_3_n_1 1 0 11 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 NJ 2760 3680J 4384 6200J 2760 NJ 2760 8100 +preplace netloc rx_data_3_p_1 1 0 11 -30J 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 NJ 2750 3690J 4374 6190J 2750 NJ 2750 8090 +preplace netloc rx_device_clk_1 1 0 12 NJ 810 380 1980 1020 1980 1560J 1910 NJ 1910 2480J 1940 NJ 1940 4140 3604 5920J 2010 NJ 2010 7830 1720 8500J +preplace netloc rx_device_clk_rstgen_peripheral_aresetn 1 2 1 970 1850n +preplace netloc rx_device_clk_rstgen_peripheral_reset 1 2 7 930J 2270 NJ 2270 2110J 1920 NJ 1920 3150J 1930 3940J 3554 6070 +preplace netloc rx_do_rstout_logic_Res 1 8 1 6220 3094n +preplace netloc rx_mxfe_tpl_core_adc_data_0 1 1 8 390 -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 NJ -10 5320 +preplace netloc rx_mxfe_tpl_core_adc_data_1 1 1 8 400 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 3970J 600 5350 +preplace netloc rx_mxfe_tpl_core_adc_data_2 1 1 8 410 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 5370 +preplace netloc rx_mxfe_tpl_core_adc_data_3 1 1 8 480 1210 930J 830 NJ 830 NJ 830 NJ 830 NJ 830 4250J 2834 5460 +preplace netloc rx_mxfe_tpl_core_adc_data_4 1 1 8 490 1220 940J 840 NJ 840 NJ 840 NJ 840 NJ 840 4240J 2844 5450 +preplace netloc rx_mxfe_tpl_core_adc_data_5 1 1 8 500 1230 960J 850 NJ 850 NJ 850 NJ 850 NJ 850 4230J 2854 5440 +preplace netloc rx_mxfe_tpl_core_adc_data_6 1 1 8 510 1550 NJ 1550 NJ 1550 2140J 1560 NJ 1560 NJ 1560 4030J 3184 5410 +preplace netloc rx_mxfe_tpl_core_adc_data_7 1 1 8 420 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 5320 +preplace netloc rx_mxfe_tpl_core_adc_enable_0 1 1 8 440 600 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 3930J 610 5430 +preplace netloc rx_mxfe_tpl_core_adc_enable_1 1 1 8 450 620 NJ 620 NJ 620 NJ 620 NJ 620 NJ 620 NJ 620 5400 +preplace netloc rx_mxfe_tpl_core_adc_enable_2 1 1 8 460 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 5420 +preplace netloc rx_mxfe_tpl_core_adc_enable_3 1 1 8 470 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 5390 +preplace netloc rx_mxfe_tpl_core_adc_enable_4 1 1 8 480 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 5380 +preplace netloc rx_mxfe_tpl_core_adc_enable_5 1 1 8 490 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 5360 +preplace netloc rx_mxfe_tpl_core_adc_enable_6 1 1 8 500 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 5340 +preplace netloc rx_mxfe_tpl_core_adc_enable_7 1 1 8 510 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 5330 +preplace netloc rx_mxfe_tpl_core_adc_rst 1 8 1 5840 550n +preplace netloc rx_mxfe_tpl_core_adc_sync_manual_req_out 1 8 1 5480 408n +preplace netloc rx_mxfe_tpl_core_adc_valid_0 1 1 8 470 1560 NJ 1560 NJ 1560 2050J 1570 NJ 1570 NJ 1570 4020J 3194 5470 +preplace netloc spi0_csn_concat_dout 1 12 1 NJ 1290 +preplace netloc spi0_miso_1 1 0 7 NJ 1570 NJ 1570 980J 860 NJ 860 NJ 860 NJ 860 3130 +preplace netloc spi1_csn_concat_dout 1 12 1 NJ 1570 +preplace netloc spi1_miso_1 1 0 7 NJ 1600 350J 2280 NJ 2280 NJ 2280 2070J 1880 NJ 1880 3130 +preplace netloc sync_1 1 0 9 -50J 1440 NJ 1440 970J 870 NJ 870 NJ 870 NJ 870 NJ 870 4200J 3104 5760J +preplace netloc sys_250m_clk 1 1 8 510 1990 1060 1990 1550 1650 2140 1590 2510J 1590 3180 1600 3820 3254 5860J +preplace netloc sys_250m_reset 1 2 1 N 2140 +preplace netloc sys_250m_resetn 1 2 7 1050 2000 1580 1900 NJ 1900 NJ 1900 3160J 1960 3750 3504 5870J +preplace netloc sys_500m_clk 1 6 1 3170 1500n +preplace netloc sys_500m_reset 1 7 1 N 2260 +preplace netloc sys_500m_resetn 1 7 1 N 2300 +preplace netloc sys_concat_intc_0_dout 1 5 1 2490J 1190n +preplace netloc sys_concat_intc_1_dout 1 5 1 2460 1300n +preplace netloc sys_cpu_clk 1 0 12 -30 2020 NJ 2020 1000 2020 1590 2250 2100 1580 2480 1580 3220 1550 3980 3064 5730 2080 6980 2100 8100 1740 8490J +preplace netloc sys_cpu_reset 1 1 1 N 2140 +preplace netloc sys_cpu_resetn 1 1 11 370 2000 1040 2010 1570 2290 2150 1890 NJ 1890 3180 1610 3960 3084 5750 2090 6930 2110 8010 1750 8460J +preplace netloc sys_ps8_emio_gpio_o 1 6 7 NJ 1000 4220J 2864 5630J 910 NJ 910 8090 860 NJ 860 8890J +preplace netloc sys_ps8_emio_gpio_t 1 6 7 NJ 1020 4210J 2874 5620J 890 NJ 890 8060 850 NJ 850 8920J +preplace netloc sys_ps8_emio_spi0_m_o 1 6 7 NJ 1120 4190J 2914 5670J 920 NJ 920 8080 840 NJ 840 8930J +preplace netloc sys_ps8_emio_spi0_sclk_o 1 6 7 NJ 1080 4110J 3174 5830J 1550 6940J 1250 7830 1220 8490J 1200 NJ +preplace netloc sys_ps8_emio_spi0_ss1_o_n 1 6 6 NJ 1200 4160J 2924 5700J 1250 6920J 1260 N 1260 8500 +preplace netloc sys_ps8_emio_spi0_ss2_o_n 1 6 6 NJ 1220 4100J 3134 5790J 1500 6970J 1480 7830 1370 8500 +preplace netloc sys_ps8_emio_spi0_ss_o_n 1 6 6 NJ 1180 4090J 3204 5820J 1540 6950J 1470 7820 1360 8490 +preplace netloc sys_ps8_emio_spi1_m_o 1 6 7 NJ 1320 4130J 3074 5770J 1510 NJ 1510 7840 1380 NJ 1380 NJ +preplace netloc sys_ps8_emio_spi1_sclk_o 1 6 7 NJ 1280 4150J 2904 5680J 1240 NJ 1240 7820 1210 NJ 1210 8890J +preplace netloc sys_ps8_emio_spi1_ss1_o_n 1 6 6 3200 1540 4050J 3164 5690J 710 NJ 710 8120 820 8510J +preplace netloc sys_ps8_emio_spi1_ss2_o_n 1 6 6 3190 1530 4070J 3154 5810J 1530 6960J 1540 N 1540 8460J +preplace netloc sys_ps8_emio_spi1_ss_o_n 1 6 6 3230 1520 4080J 3144 5800J 1520 6970J 1550 N 1550 NJ +preplace netloc sys_ps8_pl_resetn0 1 0 7 -20 2040 360 2040 NJ 2040 1550J 2260 2120J 1930 NJ 1930 3140 +preplace netloc sysref_1 1 0 12 NJ 2490 NJ 2490 NJ 2490 NJ 2490 2160J 1940 2460J 2050 NJ 2050 3890J 3674 5970J 2050 6950J 2020 7960 1730 8470J +preplace netloc sysref_2 1 0 9 -40J 1450 NJ 1450 990J 880 NJ 880 NJ 880 NJ 880 NJ 880 4180J 3114 5780J +preplace netloc tx_device_clk_1 1 0 11 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 NJ 2610 4000 3094 5710 950 6940J 950 N +preplace netloc tx_device_clk_rstgen_peripheral_aresetn 1 8 1 6080 1890n +preplace netloc tx_device_clk_rstgen_peripheral_reset 1 8 1 5890 800n +preplace netloc tx_mxfe_tpl_core_dac_enable_0 1 8 3 5860 930 NJ 930 8090 +preplace netloc tx_mxfe_tpl_core_dac_enable_1 1 8 3 5510 880 7020J 1000 8070 +preplace netloc tx_mxfe_tpl_core_dac_enable_2 1 8 3 5520 900 7000J 1010 8050 +preplace netloc tx_mxfe_tpl_core_dac_enable_3 1 8 3 5550 940 6970J 1020 7990 +preplace netloc tx_mxfe_tpl_core_dac_enable_4 1 8 3 5610 970 NJ 970 8080 +preplace netloc tx_mxfe_tpl_core_dac_enable_5 1 8 3 5640 990 NJ 990 8010 +preplace netloc tx_mxfe_tpl_core_dac_enable_6 1 8 3 5660 1000 6940J 1110 N +preplace netloc tx_mxfe_tpl_core_dac_enable_7 1 8 3 5650 980 NJ 980 8030 +preplace netloc tx_mxfe_tpl_core_dac_rst 1 8 1 5540 820n +preplace netloc tx_mxfe_tpl_core_dac_sync_manual_req_out 1 8 1 5500 428n +preplace netloc tx_mxfe_tpl_core_dac_valid_0 1 8 3 5480 960 6950J 1150 N +preplace netloc upack_reset_sources_dout 1 9 2 7040J 940 8060 +preplace netloc upack_rst_logic_Res 1 9 3 7050 880 8120 870 8460J +preplace netloc util_mxfe_cpack_packed_fifo_wr_data 1 2 1 1000 980n +preplace netloc util_mxfe_cpack_packed_fifo_wr_en 1 2 1 1010 960n +preplace netloc util_mxfe_upack_fifo_rd_data_0 1 7 5 4310 2894 5600J 720 NJ 720 8110 830 8420 +preplace netloc util_mxfe_upack_fifo_rd_data_1 1 7 5 4370 2884 5530J 700 NJ 700 N 700 8430 +preplace netloc util_mxfe_upack_fifo_rd_data_2 1 7 5 4320 2934 5590J 670 NJ 670 N 670 8450 +preplace netloc util_mxfe_upack_fifo_rd_data_3 1 7 5 4350 720 5480J 690 NJ 690 N 690 8440 +preplace netloc util_mxfe_upack_fifo_rd_data_4 1 7 5 4330 2944 5580J 660 NJ 660 N 660 8470 +preplace netloc util_mxfe_upack_fifo_rd_data_5 1 7 5 4340 2954 5570J 650 NJ 650 N 650 8490 +preplace netloc util_mxfe_upack_fifo_rd_data_6 1 7 5 4350 2964 5560J 640 NJ 640 N 640 8500 +preplace netloc util_mxfe_upack_fifo_rd_data_7 1 7 5 4360 740 NJ 740 6940J 680 N 680 8480 +preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 10 2 8120 1760 8430 +preplace netloc util_mxfe_xcvr_tx_0_n 1 11 2 NJ 2240 8920J +preplace netloc util_mxfe_xcvr_tx_0_p 1 11 2 8470J 2250 8900J +preplace netloc util_mxfe_xcvr_tx_1_n 1 11 2 8460J 2290 NJ +preplace netloc util_mxfe_xcvr_tx_1_p 1 11 2 8440J 2260 NJ +preplace netloc util_mxfe_xcvr_tx_2_n 1 11 2 8490J 2350 NJ +preplace netloc util_mxfe_xcvr_tx_2_p 1 11 2 8480J 2320 NJ +preplace netloc util_mxfe_xcvr_tx_3_n 1 11 2 8510J 2420 NJ +preplace netloc util_mxfe_xcvr_tx_3_p 1 11 2 8500J 2390 NJ +preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 8 4 6100 2060 6990 2090 8030 1770 8420 +preplace netloc axi_cpu_interconnect_M00_AXI 1 7 1 3850 1670n +preplace netloc axi_cpu_interconnect_M01_AXI 1 3 5 1610 2350 NJ 2350 2510J 1990 NJ 1990 3700 +preplace netloc axi_cpu_interconnect_M02_AXI 1 7 1 3910 210n +preplace netloc axi_cpu_interconnect_M03_AXI 1 7 5 3990J 3354 5900J 1980 6930J 1960 7860 1660 8510 +preplace netloc axi_cpu_interconnect_M04_AXI 1 3 5 1600 2360 NJ 2360 NJ 2360 NJ 2360 3690 +preplace netloc axi_cpu_interconnect_M05_AXI 1 2 6 1070 2370 NJ 2370 NJ 2370 2530J 2350 3190J 2370 3680 +preplace netloc axi_cpu_interconnect_M06_AXI 1 7 2 4060J 3054 5720 +preplace netloc axi_cpu_interconnect_M07_AXI 1 7 1 4120 1810n +preplace netloc axi_cpu_interconnect_M08_AXI 1 7 2 4040J 3044 5740 +preplace netloc axi_cpu_interconnect_M09_AXI 1 7 1 3790 1850n +preplace netloc axi_cpu_interconnect_M10_AXI 1 7 2 3950J 3494 5880 +preplace netloc axi_hp0_interconnect_M00_AXI 1 5 1 2450 1140n +preplace netloc axi_hp1_interconnect_M00_AXI 1 5 1 2470 1160n +preplace netloc axi_hp2_interconnect_M00_AXI 1 5 5 2520 2000 NJ 2000 3920J 3624 5930J 2000 6920 +preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 4 1 2050 1750n +preplace netloc axi_mxfe_rx_xcvr_m_axi 1 4 1 2170 1990n +preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 4 7 2060J 2110 2480J 2100 NJ 2100 3880J 3724 5990J 2100 6970 2040 7990 +preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 4 7 2080J 2120 2490J 2110 NJ 2110 3870J 3734 6010J 2110 7010 2060 8000 +preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 4 7 2040J 2130 2500J 2120 NJ 2120 3860J 3744 6020J 2120 7030 2080 8020 +preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 4 7 NJ 2150 2520J 2130 NJ 2130 3840J 3754 6040J 2130 7050 2120 8090 +preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 4 7 2090J 2140 NJ 2140 NJ 2140 3830J 3764 6050J 2140 7020 2030 7980 +preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 4 7 2130J 1950 NJ 1950 NJ 1950 3930J 3614 5910J 1990 6960 2050 7920 +preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 4 7 2030J 2160 2530J 2150 NJ 2150 3810J 3774 6090J 2150 7040 2070 7840 +preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 4 7 2020J 2170 NJ 2170 3230J 2160 3800J 3784 6100J 2160 N 2160 8080 +preplace netloc axi_mxfe_tx_dma_m_src_axi 1 8 1 6000 1610n +preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 9 2 7050 1490 7920 +preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 9 2 7040 1500 7900 +preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 9 2 7020 1520 7870 +preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 9 2 7000 1530 7820 +preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 9 2 N 1080 7970 +preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 9 2 N 1100 7950 +preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 9 2 N 1120 7930 +preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 9 2 N 1140 7910 +preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 9 2 N 1060 7990 +preplace netloc dds_pulse_wrapper_0_m_axis_out 1 10 1 8100 800n +preplace netloc mxfe_rx_data_offload_m_axis 1 3 1 1540 1730n +preplace netloc s_axis_1 1 8 1 6030 1770n +preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 6 1 3210 940n +preplace netloc tx_mxfe_tpl_core_link 1 8 1 5490 812n +preplace netloc util_mxfe_xcvr_rx_0 1 11 1 8440 2030n +preplace netloc util_mxfe_xcvr_rx_1 1 11 1 8450 2050n +preplace netloc util_mxfe_xcvr_rx_2 1 11 1 8480 2070n +preplace netloc util_mxfe_xcvr_rx_3 1 11 1 8510 2090n +preplace netloc tx_mxfe_tpl_core|dac_data_0_1 1 0 1 N 2602 +preplace netloc tx_mxfe_tpl_core|dac_data_1_1 1 0 1 N 2622 +preplace netloc tx_mxfe_tpl_core|dac_data_2_1 1 0 1 N 2642 +preplace netloc tx_mxfe_tpl_core|dac_data_3_1 1 0 1 N 2662 +preplace netloc tx_mxfe_tpl_core|dac_data_4_1 1 0 1 N 2682 +preplace netloc tx_mxfe_tpl_core|dac_data_5_1 1 0 1 N 2702 +preplace netloc tx_mxfe_tpl_core|dac_data_6_1 1 0 1 N 2722 +preplace netloc tx_mxfe_tpl_core|dac_data_7_1 1 0 1 N 2742 +preplace netloc tx_mxfe_tpl_core|dac_dunf_1 1 0 2 4530J 2532 4780 +preplace netloc tx_mxfe_tpl_core|dac_sync_manual_req_in_1 1 0 2 NJ 2802 4780 +preplace netloc tx_mxfe_tpl_core|dac_tpl_core_dac_rst 1 2 1 N 2552 +preplace netloc tx_mxfe_tpl_core|dac_tpl_core_dac_sync_manual_req_out 1 2 1 5160 2532n +preplace netloc tx_mxfe_tpl_core|dac_tpl_core_dac_valid 1 1 2 4780 2402 5140 +preplace netloc tx_mxfe_tpl_core|dac_tpl_core_enable 1 1 2 4740 2392 5150 +preplace netloc tx_mxfe_tpl_core|data_concat0_dout 1 1 1 4770 2502n +preplace netloc tx_mxfe_tpl_core|enable_slice_0_Dout 1 2 1 NJ 832 +preplace netloc tx_mxfe_tpl_core|enable_slice_1_Dout 1 2 1 NJ 1032 +preplace netloc tx_mxfe_tpl_core|enable_slice_2_Dout 1 2 1 NJ 1232 +preplace netloc tx_mxfe_tpl_core|enable_slice_3_Dout 1 2 1 NJ 1432 +preplace netloc tx_mxfe_tpl_core|enable_slice_4_Dout 1 2 1 NJ 1632 +preplace netloc tx_mxfe_tpl_core|enable_slice_5_Dout 1 2 1 NJ 1832 +preplace netloc tx_mxfe_tpl_core|enable_slice_6_Dout 1 2 1 NJ 2032 +preplace netloc tx_mxfe_tpl_core|enable_slice_7_Dout 1 2 1 NJ 2232 +preplace netloc tx_mxfe_tpl_core|ext_sync_in_1 1 0 2 4540J 2542 N +preplace netloc tx_mxfe_tpl_core|link_clk_1 1 0 2 NJ 2522 4750 +preplace netloc tx_mxfe_tpl_core|s_axi_aclk_1 1 0 2 NJ 2482 4740 +preplace netloc tx_mxfe_tpl_core|s_axi_aresetn_1 1 0 2 NJ 2502 4760 +preplace netloc tx_mxfe_tpl_core|valid_slice_0_Dout 1 2 1 NJ 932 +preplace netloc tx_mxfe_tpl_core|valid_slice_1_Dout 1 2 1 NJ 1132 +preplace netloc tx_mxfe_tpl_core|valid_slice_2_Dout 1 2 1 NJ 1332 +preplace netloc tx_mxfe_tpl_core|valid_slice_3_Dout 1 2 1 NJ 1532 +preplace netloc tx_mxfe_tpl_core|valid_slice_4_Dout 1 2 1 NJ 1732 +preplace netloc tx_mxfe_tpl_core|valid_slice_5_Dout 1 2 1 NJ 1932 +preplace netloc tx_mxfe_tpl_core|valid_slice_6_Dout 1 2 1 NJ 2132 +preplace netloc tx_mxfe_tpl_core|valid_slice_7_Dout 1 2 1 NJ 2332 +preplace netloc tx_mxfe_tpl_core|dac_tpl_core_link 1 2 1 5160 812n +preplace netloc tx_mxfe_tpl_core|s_axi_1 1 0 2 NJ 2462 N +levelinfo -pg 1 -70 180 740 1420 1862 2320 2830 3480 4650 6774 7684 8290 8744 8950 +levelinfo -hier tx_mxfe_tpl_core * 4640 4960 * +pagesize -pg 1 -db -bbox -sgen -210 -30 9090 6480 +pagesize -hier tx_mxfe_tpl_core -db -bbox -sgen 4500 772 5190 2812 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_system() +cr_bd_system "" +set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] + +set idrFlowPropertiesConstraints "" +catch { + set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints] + set_param runs.disableIDRFlowPropertyConstraints 1 +} + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2022" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2022" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.report_unconstrained" -value "1" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] +catch { + if { $idrFlowPropertiesConstraints != {} } { + set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints + } +} + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/script/recreate_bd.tcl b/script/recreate_bd.tcl new file mode 100644 index 0000000..88d78c4 --- /dev/null +++ b/script/recreate_bd.tcl @@ -0,0 +1,2231 @@ + +################################################################ +# This is a generated script based on design: system +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source system_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu9eg-ffvb1156-2-e + set_property BOARD_PART xilinx.com:zcu102:part0:3.4 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name system + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:smartconnect:1.0\ +analog.com:user:axi_dmac:1.0\ +analog.com:user:axi_adxcvr:1.0\ +analog.com:user:axi_sysid:1.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:util_reduced_logic:2.0\ +xilinx.com:user:dds_pulse_wrapper:1.0\ +xilinx.com:ip:util_vector_logic:2.0\ +analog.com:user:sysid_rom:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:zynq_ultra_ps_e:3.4\ +analog.com:user:util_cpack2:1.0\ +analog.com:user:util_upack2:1.0\ +analog.com:user:util_adxcvr:1.0\ +analog.com:user:jesd204_rx:1.0\ +analog.com:user:axi_jesd204_rx:1.0\ +analog.com:user:jesd204_tx:1.0\ +analog.com:user:axi_jesd204_tx:1.0\ +analog.com:user:data_offload:1.0\ +analog.com:user:util_do_ram:1.0\ +analog.com:user:ad_ip_jesd204_tpl_adc:1.0\ +xilinx.com:ip:xlslice:1.0\ +analog.com:user:ad_ip_jesd204_tpl_dac:1.0\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: tx_mxfe_tpl_core +proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -from 15 -to 0 dac_data_0 + create_bd_pin -dir I -from 15 -to 0 dac_data_1 + create_bd_pin -dir I -from 15 -to 0 dac_data_2 + create_bd_pin -dir I -from 15 -to 0 dac_data_3 + create_bd_pin -dir I -from 15 -to 0 dac_data_4 + create_bd_pin -dir I -from 15 -to 0 dac_data_5 + create_bd_pin -dir I -from 15 -to 0 dac_data_6 + create_bd_pin -dir I -from 15 -to 0 dac_data_7 + create_bd_pin -dir I dac_dunf + create_bd_pin -dir O -from 0 -to 0 dac_enable_0 + create_bd_pin -dir O -from 0 -to 0 dac_enable_1 + create_bd_pin -dir O -from 0 -to 0 dac_enable_2 + create_bd_pin -dir O -from 0 -to 0 dac_enable_3 + create_bd_pin -dir O -from 0 -to 0 dac_enable_4 + create_bd_pin -dir O -from 0 -to 0 dac_enable_5 + create_bd_pin -dir O -from 0 -to 0 dac_enable_6 + create_bd_pin -dir O -from 0 -to 0 dac_enable_7 + create_bd_pin -dir O dac_rst + create_bd_pin -dir I dac_sync_manual_req_in + create_bd_pin -dir O dac_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 dac_valid_0 + create_bd_pin -dir O -from 0 -to 0 dac_valid_1 + create_bd_pin -dir O -from 0 -to 0 dac_valid_2 + create_bd_pin -dir O -from 0 -to 0 dac_valid_3 + create_bd_pin -dir O -from 0 -to 0 dac_valid_4 + create_bd_pin -dir O -from 0 -to 0 dac_valid_5 + create_bd_pin -dir O -from 0 -to 0 dac_valid_6 + create_bd_pin -dir O -from 0 -to 0 dac_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: dac_tpl_core, and set properties + set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.IQCORRECTION_DISABLE {0} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $dac_tpl_core + + + # Create instance: data_concat0, and set properties + set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ] + set_property CONFIG.NUM_PORTS {8} $data_concat0 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins link] [get_bd_intf_pins dac_tpl_core/link] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0] + connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1] + connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2] + connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3] + connect_bd_net -net dac_data_4_1 [get_bd_pins dac_data_4] [get_bd_pins data_concat0/In4] + connect_bd_net -net dac_data_5_1 [get_bd_pins dac_data_5] [get_bd_pins data_concat0/In5] + connect_bd_net -net dac_data_6_1 [get_bd_pins dac_data_6] [get_bd_pins data_concat0/In6] + connect_bd_net -net dac_data_7_1 [get_bd_pins dac_data_7] [get_bd_pins data_concat0/In7] + connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf] + connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_rst] [get_bd_pins dac_tpl_core/dac_rst] + connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_sync_manual_req_out] [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_concat0_dout [get_bd_pins dac_tpl_core/dac_ddata] [get_bd_pins data_concat0/dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins dac_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins dac_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins dac_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins dac_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins dac_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins dac_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins dac_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins dac_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins dac_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins dac_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins dac_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins dac_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins dac_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins dac_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins dac_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins dac_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx_mxfe_tpl_core +proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir O -from 15 -to 0 adc_data_0 + create_bd_pin -dir O -from 15 -to 0 adc_data_1 + create_bd_pin -dir O -from 15 -to 0 adc_data_2 + create_bd_pin -dir O -from 15 -to 0 adc_data_3 + create_bd_pin -dir O -from 15 -to 0 adc_data_4 + create_bd_pin -dir O -from 15 -to 0 adc_data_5 + create_bd_pin -dir O -from 15 -to 0 adc_data_6 + create_bd_pin -dir O -from 15 -to 0 adc_data_7 + create_bd_pin -dir I adc_dovf + create_bd_pin -dir O -from 0 -to 0 adc_enable_0 + create_bd_pin -dir O -from 0 -to 0 adc_enable_1 + create_bd_pin -dir O -from 0 -to 0 adc_enable_2 + create_bd_pin -dir O -from 0 -to 0 adc_enable_3 + create_bd_pin -dir O -from 0 -to 0 adc_enable_4 + create_bd_pin -dir O -from 0 -to 0 adc_enable_5 + create_bd_pin -dir O -from 0 -to 0 adc_enable_6 + create_bd_pin -dir O -from 0 -to 0 adc_enable_7 + create_bd_pin -dir O adc_rst + create_bd_pin -dir I adc_sync_manual_req_in + create_bd_pin -dir O adc_sync_manual_req_out + create_bd_pin -dir O -from 0 -to 0 adc_valid_0 + create_bd_pin -dir O -from 0 -to 0 adc_valid_1 + create_bd_pin -dir O -from 0 -to 0 adc_valid_2 + create_bd_pin -dir O -from 0 -to 0 adc_valid_3 + create_bd_pin -dir O -from 0 -to 0 adc_valid_4 + create_bd_pin -dir O -from 0 -to 0 adc_valid_5 + create_bd_pin -dir O -from 0 -to 0 adc_valid_6 + create_bd_pin -dir O -from 0 -to 0 adc_valid_7 + create_bd_pin -dir I ext_sync_in + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -from 127 -to 0 link_data + create_bd_pin -dir I -from 3 -to 0 link_sof + create_bd_pin -dir I link_valid + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + + # Create instance: adc_tpl_core, and set properties + set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ] + set_property -dict [list \ + CONFIG.BITS_PER_SAMPLE {16} \ + CONFIG.CONVERTER_RESOLUTION {16} \ + CONFIG.DMA_BITS_PER_SAMPLE {16} \ + CONFIG.EXT_SYNC {1} \ + CONFIG.NUM_CHANNELS {8} \ + CONFIG.NUM_LANES {4} \ + CONFIG.OCTETS_PER_BEAT {4} \ + CONFIG.SAMPLES_PER_FRAME {1} \ + ] $adc_tpl_core + + + # Create instance: data_slice_0, and set properties + set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_0 + + + # Create instance: data_slice_1, and set properties + set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {31} \ + CONFIG.DIN_TO {16} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_1 + + + # Create instance: data_slice_2, and set properties + set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {47} \ + CONFIG.DIN_TO {32} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_2 + + + # Create instance: data_slice_3, and set properties + set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {63} \ + CONFIG.DIN_TO {48} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_3 + + + # Create instance: data_slice_4, and set properties + set data_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {79} \ + CONFIG.DIN_TO {64} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_4 + + + # Create instance: data_slice_5, and set properties + set data_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {95} \ + CONFIG.DIN_TO {80} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_5 + + + # Create instance: data_slice_6, and set properties + set data_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {111} \ + CONFIG.DIN_TO {96} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_6 + + + # Create instance: data_slice_7, and set properties + set data_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {127} \ + CONFIG.DIN_TO {112} \ + CONFIG.DIN_WIDTH {128} \ + ] $data_slice_7 + + + # Create instance: enable_slice_0, and set properties + set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_0 + + + # Create instance: enable_slice_1, and set properties + set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_1 + + + # Create instance: enable_slice_2, and set properties + set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_2 + + + # Create instance: enable_slice_3, and set properties + set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_3 + + + # Create instance: enable_slice_4, and set properties + set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_4 + + + # Create instance: enable_slice_5, and set properties + set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_5 + + + # Create instance: enable_slice_6, and set properties + set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_6 + + + # Create instance: enable_slice_7, and set properties + set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $enable_slice_7 + + + # Create instance: valid_slice_0, and set properties + set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_0 + + + # Create instance: valid_slice_1, and set properties + set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_1 + + + # Create instance: valid_slice_2, and set properties + set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ] + set_property -dict [list \ + CONFIG.DIN_FROM {2} \ + CONFIG.DIN_TO {2} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_2 + + + # Create instance: valid_slice_3, and set properties + set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ] + set_property -dict [list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DIN_TO {3} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_3 + + + # Create instance: valid_slice_4, and set properties + set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ] + set_property -dict [list \ + CONFIG.DIN_FROM {4} \ + CONFIG.DIN_TO {4} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_4 + + + # Create instance: valid_slice_5, and set properties + set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ] + set_property -dict [list \ + CONFIG.DIN_FROM {5} \ + CONFIG.DIN_TO {5} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_5 + + + # Create instance: valid_slice_6, and set properties + set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ] + set_property -dict [list \ + CONFIG.DIN_FROM {6} \ + CONFIG.DIN_TO {6} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_6 + + + # Create instance: valid_slice_7, and set properties + set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {7} \ + CONFIG.DIN_WIDTH {8} \ + ] $valid_slice_7 + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi] + + # Create port connections + connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf] + connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in] + connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din] [get_bd_pins data_slice_4/Din] [get_bd_pins data_slice_5/Din] [get_bd_pins data_slice_6/Din] [get_bd_pins data_slice_7/Din] + connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_rst] [get_bd_pins adc_tpl_core/adc_rst] + connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_sync_manual_req_out] [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din] + connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din] + connect_bd_net -net data_slice_0_Dout [get_bd_pins adc_data_0] [get_bd_pins data_slice_0/Dout] + connect_bd_net -net data_slice_1_Dout [get_bd_pins adc_data_1] [get_bd_pins data_slice_1/Dout] + connect_bd_net -net data_slice_2_Dout [get_bd_pins adc_data_2] [get_bd_pins data_slice_2/Dout] + connect_bd_net -net data_slice_3_Dout [get_bd_pins adc_data_3] [get_bd_pins data_slice_3/Dout] + connect_bd_net -net data_slice_4_Dout [get_bd_pins adc_data_4] [get_bd_pins data_slice_4/Dout] + connect_bd_net -net data_slice_5_Dout [get_bd_pins adc_data_5] [get_bd_pins data_slice_5/Dout] + connect_bd_net -net data_slice_6_Dout [get_bd_pins adc_data_6] [get_bd_pins data_slice_6/Dout] + connect_bd_net -net data_slice_7_Dout [get_bd_pins adc_data_7] [get_bd_pins data_slice_7/Dout] + connect_bd_net -net enable_slice_0_Dout [get_bd_pins adc_enable_0] [get_bd_pins enable_slice_0/Dout] + connect_bd_net -net enable_slice_1_Dout [get_bd_pins adc_enable_1] [get_bd_pins enable_slice_1/Dout] + connect_bd_net -net enable_slice_2_Dout [get_bd_pins adc_enable_2] [get_bd_pins enable_slice_2/Dout] + connect_bd_net -net enable_slice_3_Dout [get_bd_pins adc_enable_3] [get_bd_pins enable_slice_3/Dout] + connect_bd_net -net enable_slice_4_Dout [get_bd_pins adc_enable_4] [get_bd_pins enable_slice_4/Dout] + connect_bd_net -net enable_slice_5_Dout [get_bd_pins adc_enable_5] [get_bd_pins enable_slice_5/Dout] + connect_bd_net -net enable_slice_6_Dout [get_bd_pins adc_enable_6] [get_bd_pins enable_slice_6/Dout] + connect_bd_net -net enable_slice_7_Dout [get_bd_pins adc_enable_7] [get_bd_pins enable_slice_7/Dout] + connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk] + connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data] + connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof] + connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn] + connect_bd_net -net valid_slice_0_Dout [get_bd_pins adc_valid_0] [get_bd_pins valid_slice_0/Dout] + connect_bd_net -net valid_slice_1_Dout [get_bd_pins adc_valid_1] [get_bd_pins valid_slice_1/Dout] + connect_bd_net -net valid_slice_2_Dout [get_bd_pins adc_valid_2] [get_bd_pins valid_slice_2/Dout] + connect_bd_net -net valid_slice_3_Dout [get_bd_pins adc_valid_3] [get_bd_pins valid_slice_3/Dout] + connect_bd_net -net valid_slice_4_Dout [get_bd_pins adc_valid_4] [get_bd_pins valid_slice_4/Dout] + connect_bd_net -net valid_slice_5_Dout [get_bd_pins adc_valid_5] [get_bd_pins valid_slice_5/Dout] + connect_bd_net -net valid_slice_6_Dout [get_bd_pins adc_valid_6] [get_bd_pins valid_slice_6/Dout] + connect_bd_net -net valid_slice_7_Dout [get_bd_pins adc_valid_7] [get_bd_pins valid_slice_7/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_tx_data_offload +proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_CYCLIC_EN {true} \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {1} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: mxfe_rx_data_offload +proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + + # Create pins + create_bd_pin -dir I init_req + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst m_axis_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + create_bd_pin -dir I -type rst s_axis_aresetn + create_bd_pin -dir I sync_ext + + # Create instance: i_data_offload, and set properties + set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.MEM_SIZE_LOG2 {20} \ + CONFIG.MEM_TYPE {0} \ + CONFIG.SRC_DATA_WIDTH {128} \ + CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \ + CONFIG.TX_OR_RXN_PATH {0} \ + ] $i_data_offload + + + # Create instance: storage_unit, and set properties + set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ] + set_property -dict [list \ + CONFIG.DST_DATA_WIDTH {128} \ + CONFIG.LENGTH_WIDTH {20} \ + CONFIG.SRC_DATA_WIDTH {128} \ + ] $storage_unit + + + # Create interface connections + connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis] + connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins i_data_offload/m_storage_axis] [get_bd_intf_pins storage_unit/s_axis] + connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins i_data_offload/rd_ctrl] [get_bd_intf_pins storage_unit/rd_ctrl] + connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins i_data_offload/wr_ctrl] [get_bd_intf_pins storage_unit/wr_ctrl] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis] + connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins i_data_offload/s_storage_axis] [get_bd_intf_pins storage_unit/m_axis] + + # Create port connections + connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] + connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] + connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_tx_jesd +proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3 + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: tx, and set properties + set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $tx + + + # Create instance: tx_axi, and set properties + set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $tx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi] + connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx/tx_cfg] [get_bd_intf_pins tx_axi/tx_cfg] + connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx/tx_ctrl] [get_bd_intf_pins tx_axi/tx_ctrl] + connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data] + connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event] + connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config] + connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx_phy0] [get_bd_intf_pins tx/tx_phy0] + connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx_phy1] [get_bd_intf_pins tx/tx_phy1] + connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx_phy2] [get_bd_intf_pins tx/tx_phy2] + connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx_phy3] [get_bd_intf_pins tx/tx_phy3] + connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx/device_clk] [get_bd_pins tx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx/clk] [get_bd_pins tx_axi/core_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn] + connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref] + connect_bd_net -net tx_axi_core_reset [get_bd_pins tx/reset] [get_bd_pins tx_axi/core_reset] + connect_bd_net -net tx_axi_device_reset [get_bd_pins tx/device_reset] [get_bd_pins tx_axi/device_reset] + connect_bd_net -net tx_axi_irq [get_bd_pins irq] [get_bd_pins tx_axi/irq] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_mxfe_rx_jesd +proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + + # Create pins + create_bd_pin -dir I -type clk device_clk + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type clk link_clk + create_bd_pin -dir O phy_en_char_align + create_bd_pin -dir O -from 127 -to 0 rx_data_tdata + create_bd_pin -dir O rx_data_tvalid + create_bd_pin -dir O -from 3 -to 0 rx_eof + create_bd_pin -dir O -from 3 -to 0 rx_sof + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O -from 0 -to 0 sync + create_bd_pin -dir I sysref + + # Create instance: rx, and set properties + set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_INPUT_PIPELINE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + CONFIG.SYSREF_IOB {false} \ + CONFIG.TPL_DATA_PATH_WIDTH {4} \ + ] $rx + + + # Create instance: rx_axi, and set properties + set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ] + set_property -dict [list \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LINKS {1} \ + ] $rx_axi + + + # Create interface connections + connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx/rx_cfg] [get_bd_intf_pins rx_axi/rx_cfg] + connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx_phy0] [get_bd_intf_pins rx/rx_phy0] + connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx_phy1] [get_bd_intf_pins rx/rx_phy1] + connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx_phy2] [get_bd_intf_pins rx/rx_phy2] + connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx_phy3] [get_bd_intf_pins rx/rx_phy3] + connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event] + connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config] + connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi] + + # Create port connections + connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx/device_clk] [get_bd_pins rx_axi/device_clk] + connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx/clk] [get_bd_pins rx_axi/core_clk] + connect_bd_net -net rx_axi_core_reset [get_bd_pins rx/reset] [get_bd_pins rx_axi/core_reset] + connect_bd_net -net rx_axi_device_reset [get_bd_pins rx/device_reset] [get_bd_pins rx_axi/device_reset] + connect_bd_net -net rx_axi_irq [get_bd_pins irq] [get_bd_pins rx_axi/irq] + connect_bd_net -net rx_phy_en_char_align [get_bd_pins phy_en_char_align] [get_bd_pins rx/phy_en_char_align] + connect_bd_net -net rx_rx_data [get_bd_pins rx_data_tdata] [get_bd_pins rx/rx_data] + connect_bd_net -net rx_rx_eof [get_bd_pins rx_eof] [get_bd_pins rx/rx_eof] + connect_bd_net -net rx_rx_sof [get_bd_pins rx_sof] [get_bd_pins rx/rx_sof] + connect_bd_net -net rx_rx_valid [get_bd_pins rx_data_tvalid] [get_bd_pins rx/rx_valid] + connect_bd_net -net rx_sync [get_bd_pins sync] [get_bd_pins rx/sync] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn] + connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk_in_1 [ create_bd_port -dir I clk_in_1 ] + set ext_sync_in [ create_bd_port -dir I ext_sync_in ] + set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ] + set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ] + set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ] + set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ] + set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ] + set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ] + set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ] + set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ] + set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ] + set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ] + set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ] + set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ] + set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ] + set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ] + set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ] + set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ] + set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ] + set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ] + set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ] + set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ] + set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ] + set rx_device_clk [ create_bd_port -dir I rx_device_clk ] + set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ] + set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ] + set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] + set spi0_miso [ create_bd_port -dir I spi0_miso ] + set spi0_mosi [ create_bd_port -dir O spi0_mosi ] + set spi0_sclk [ create_bd_port -dir O spi0_sclk ] + set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ] + set spi1_miso [ create_bd_port -dir I spi1_miso ] + set spi1_mosi [ create_bd_port -dir O spi1_mosi ] + set spi1_sclk [ create_bd_port -dir O spi1_sclk ] + set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ] + set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ] + set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ] + set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ] + set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ] + set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ] + set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ] + set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ] + set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ] + set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ] + set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ] + set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ] + set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ] + set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ] + set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ] + set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ] + set tx_device_clk [ create_bd_port -dir I tx_device_clk ] + set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ] + set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ] + + # Create instance: GND_1, and set properties + set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {1} \ + ] $GND_1 + + + # Create instance: VCC_1, and set properties + set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {1} \ + CONFIG.CONST_WIDTH {1} \ + ] $VCC_1 + + + # Create instance: axi_cpu_interconnect, and set properties + set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {11} \ + CONFIG.NUM_SI {1} \ + ] $axi_cpu_interconnect + + + # Create instance: axi_hp0_interconnect, and set properties + set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp0_interconnect + + + # Create instance: axi_hp1_interconnect, and set properties + set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp1_interconnect + + + # Create instance: axi_hp2_interconnect, and set properties + set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ] + set_property -dict [list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {1} \ + ] $axi_hp2_interconnect + + + # Create instance: axi_mxfe_rx_dma, and set properties + set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {false} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {0} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_mxfe_rx_dma + + + # Create instance: axi_mxfe_rx_jesd + create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd + + # Create instance: axi_mxfe_rx_xcvr, and set properties + set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.LPM_OR_DFE_N {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {0} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {0} \ + ] $axi_mxfe_rx_xcvr + + + # Create instance: axi_mxfe_tx_dma, and set properties + set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ] + set_property -dict [list \ + CONFIG.AXI_SLICE_DEST {true} \ + CONFIG.AXI_SLICE_SRC {true} \ + CONFIG.CYCLIC {true} \ + CONFIG.DMA_2D_TRANSFER {false} \ + CONFIG.DMA_DATA_WIDTH_DEST {128} \ + CONFIG.DMA_DATA_WIDTH_SRC {128} \ + CONFIG.DMA_LENGTH_WIDTH {24} \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + CONFIG.ID {0} \ + CONFIG.MAX_BYTES_PER_BURST {4096} \ + ] $axi_mxfe_tx_dma + + + # Create instance: axi_mxfe_tx_jesd + create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd + + # Create instance: axi_mxfe_tx_xcvr, and set properties + set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ] + set_property -dict [list \ + CONFIG.ID {0} \ + CONFIG.LINK_MODE {1} \ + CONFIG.NUM_OF_LANES {4} \ + CONFIG.QPLL_ENABLE {1} \ + CONFIG.SYS_CLK_SEL {0x3} \ + CONFIG.TX_OR_RX_N {1} \ + ] $axi_mxfe_tx_xcvr + + + # Create instance: axi_sysid_0, and set properties + set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ] + set_property CONFIG.ROM_ADDR_BITS {9} $axi_sysid_0 + + + # Create instance: cpack_reset_sources, and set properties + set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ] + set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources + + + # Create instance: cpack_rst_logic, and set properties + set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {3} \ + ] $cpack_rst_logic + + + # Create instance: dds_pulse_wrapper_0, and set properties + set dds_pulse_wrapper_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dds_pulse_wrapper:1.0 dds_pulse_wrapper_0 ] + set_property CONFIG.FPGA_REVISION_DATE {0x09112023} $dds_pulse_wrapper_0 + + + # Create instance: manual_sync_or, and set properties + set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $manual_sync_or + + + # Create instance: mxfe_rx_data_offload + create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload + + # Create instance: mxfe_tx_data_offload + create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload + + # Create instance: rom_sys_0, and set properties + set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ] + set_property -dict [list \ + CONFIG.PATH_TO_FILE {c:/ZCU102/hdl/projects/ad9081_fmca_ebz/zcu102/mem_init_sys.txt} \ + CONFIG.ROM_ADDR_BITS {9} \ + ] $rom_sys_0 + + + # Create instance: rx_device_clk_rstgen, and set properties + set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ] + + # Create instance: rx_do_rstout_logic, and set properties + set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rx_do_rstout_logic + + + # Create instance: rx_mxfe_tpl_core + create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core + + # Create instance: spi0_csn_concat, and set properties + set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat + + + # Create instance: spi1_csn_concat, and set properties + set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ] + set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat + + + # Create instance: sys_250m_rstgen, and set properties + set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen + + + # Create instance: sys_500m_rstgen, and set properties + set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen + + + # Create instance: sys_concat_intc_0, and set properties + set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0 + + + # Create instance: sys_concat_intc_1, and set properties + set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ] + set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1 + + + # Create instance: sys_ps8, and set properties + set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 sys_ps8 ] + set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ +SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\ +GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ +\ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {500.000000} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {15} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ + CONFIG.PSU__DDRC__CWL {14} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {47.06} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ + CONFIG.PSU__DP__LANE_SEL {Single Lower} \ + CONFIG.PSU__DP__REF_CLK_FREQ {27} \ + CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {0x0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {1} \ + CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \ + CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \ + CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {low} \ + CONFIG.PSU__PMU__GPO4__ENABLE {1} \ + CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ + CONFIG.PSU__PMU__GPO4__POLARITY {low} \ + CONFIG.PSU__PMU__GPO5__ENABLE {1} \ + CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ + CONFIG.PSU__PMU__GPO5__POLARITY {low} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ +\ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ +\ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ + CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {0} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {1} \ + CONFIG.PSU__USE__S_AXI_GP4 {1} \ + ] $sys_ps8 + + + # Create instance: sys_rstgen, and set properties + set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ] + set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen + + + # Create instance: tx_device_clk_rstgen, and set properties + set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ] + + # Create instance: tx_mxfe_tpl_core + create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core + + # Create instance: upack_reset_sources, and set properties + set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ] + set_property CONFIG.NUM_PORTS {2} $upack_reset_sources + + + # Create instance: upack_rst_logic, and set properties + set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {2} \ + ] $upack_rst_logic + + + # Create instance: util_mxfe_cpack, and set properties + set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_cpack + + + # Create instance: util_mxfe_upack, and set properties + set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ] + set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS {8} \ + CONFIG.SAMPLES_PER_CHANNEL {1} \ + CONFIG.SAMPLE_DATA_WIDTH {16} \ + ] $util_mxfe_upack + + + # Create instance: util_mxfe_xcvr, and set properties + set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ] + set_property -dict [list \ + CONFIG.A_TXDIFFCTRL {0x0C} \ + CONFIG.CH_HSPMUX {0x6868} \ + CONFIG.CPLL_CFG0 {0x01FA} \ + CONFIG.CPLL_CFG1 {0x0023} \ + CONFIG.CPLL_CFG2 {0x0002} \ + CONFIG.CPLL_FBDIV {2} \ + CONFIG.CPLL_FBDIV_4_5 {5} \ + CONFIG.LINK_MODE {1} \ + CONFIG.POR_CFG {0x0000} \ + CONFIG.PPF0_CFG {0x0F00} \ + CONFIG.PREIQ_FREQ_BST {1} \ + CONFIG.QPLL_CFG0 {0x333c} \ + CONFIG.QPLL_CFG4 {0x0045} \ + CONFIG.QPLL_CP {0x0FF} \ + CONFIG.QPLL_CP_G3 {0x00F} \ + CONFIG.QPLL_FBDIV {"0000010100"} \ + CONFIG.QPLL_LPF {0x2FF} \ + CONFIG.QPLL_REFCLK_DIV {1} \ + CONFIG.RXCDR_CFG0 {0x0003} \ + CONFIG.RXCDR_CFG2_GEN2 {0x265} \ + CONFIG.RXCDR_CFG2_GEN4 {0x0164} \ + CONFIG.RXCDR_CFG3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN2 {0x12} \ + CONFIG.RXCDR_CFG3_GEN3 {0x0012} \ + CONFIG.RXCDR_CFG3_GEN4 {0x0012} \ + CONFIG.RXPI_CFG0 {0x0200} \ + CONFIG.RXPI_CFG1 {0x00FD} \ + CONFIG.RX_CLK25_DIV {31} \ + CONFIG.RX_LANE_RATE {10} \ + CONFIG.RX_NUM_OF_LANES {4} \ + CONFIG.RX_OUT_DIV {1} \ + CONFIG.RX_WIDEMODE_CDR {0x0} \ + CONFIG.TXPI_CFG {0x0000} \ + CONFIG.TX_CLK25_DIV {31} \ + CONFIG.TX_LANE_RATE {10} \ + CONFIG.TX_NUM_OF_LANES {4} \ + CONFIG.TX_PI_BIASSET {3} \ + ] $util_mxfe_xcvr + + + # Create interface connections + connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] + connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] + connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] + connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2] + connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0] [get_bd_intf_pins util_mxfe_xcvr/tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1] [get_bd_intf_pins util_mxfe_xcvr/tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2] [get_bd_intf_pins util_mxfe_xcvr/tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3] [get_bd_intf_pins util_mxfe_xcvr/tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3] + connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0] + connect_bd_intf_net -intf_net dds_pulse_wrapper_0_m_axis_out [get_bd_intf_pins dds_pulse_wrapper_0/m_axis_out] [get_bd_intf_pins util_mxfe_upack/s_axis] + connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins axi_mxfe_rx_dma/s_axis] [get_bd_intf_pins mxfe_rx_data_offload/m_axis] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins axi_mxfe_tx_dma/m_axis] [get_bd_intf_pins mxfe_tx_data_offload/s_axis] + connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD] + connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data] [get_bd_intf_pins tx_mxfe_tpl_core/link] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0] [get_bd_intf_pins util_mxfe_xcvr/rx_0] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1] [get_bd_intf_pins util_mxfe_xcvr/rx_1] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2] [get_bd_intf_pins util_mxfe_xcvr/rx_2] + connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3] [get_bd_intf_pins util_mxfe_xcvr/rx_3] + + # Create port connections + connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] + connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n] + connect_bd_net -net adc_dovf_1 [get_bd_pins rx_mxfe_tpl_core/adc_dovf] [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] + connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5] + connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3] + connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data] + connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid] + connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof] + connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_ports rx_sync_0] [get_bd_pins axi_mxfe_rx_jesd/sync] + connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3] + connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4] + connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2] + connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0] + connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr] + connect_bd_net -net clk_in_1_1 [get_bd_ports clk_in_1] [get_bd_pins dds_pulse_wrapper_0/clk_in] + connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1] + connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset] + connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in] + connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i] + connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req] + connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req] + connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in] + connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1] + connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] + connect_bd_net -net rom_sys_0_rom_data [get_bd_pins axi_sysid_0/sys_rom_data] [get_bd_pins rom_sys_0/rom_data] + connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n] + connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p] + connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n] + connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p] + connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n] + connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p] + connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n] + connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p] + connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_cpack/clk] + connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins cpack_reset_sources/In0] [get_bd_pins rx_device_clk_rstgen/peripheral_reset] + connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins cpack_reset_sources/In2] [get_bd_pins rx_do_rstout_logic/Res] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_4 [get_bd_pins rx_mxfe_tpl_core/adc_data_4] [get_bd_pins util_mxfe_cpack/fifo_wr_data_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_5 [get_bd_pins rx_mxfe_tpl_core/adc_data_5] [get_bd_pins util_mxfe_cpack/fifo_wr_data_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_6 [get_bd_pins rx_mxfe_tpl_core/adc_data_6] [get_bd_pins util_mxfe_cpack/fifo_wr_data_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_data_7 [get_bd_pins rx_mxfe_tpl_core/adc_data_7] [get_bd_pins util_mxfe_cpack/fifo_wr_data_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_4 [get_bd_pins rx_mxfe_tpl_core/adc_enable_4] [get_bd_pins util_mxfe_cpack/enable_4] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_5 [get_bd_pins rx_mxfe_tpl_core/adc_enable_5] [get_bd_pins util_mxfe_cpack/enable_5] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_6 [get_bd_pins rx_mxfe_tpl_core/adc_enable_6] [get_bd_pins util_mxfe_cpack/enable_6] + connect_bd_net -net rx_mxfe_tpl_core_adc_enable_7 [get_bd_pins rx_mxfe_tpl_core/adc_enable_7] [get_bd_pins util_mxfe_cpack/enable_7] + connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins cpack_reset_sources/In1] [get_bd_pins rx_mxfe_tpl_core/adc_rst] + connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins manual_sync_or/Op1] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] + connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en] + connect_bd_net -net spi0_csn_concat_dout [get_bd_ports spi0_csn] [get_bd_pins spi0_csn_concat/dout] + connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i] + connect_bd_net -net spi1_csn_concat_dout [get_bd_ports spi1_csn] [get_bd_pins spi1_csn_concat/dout] + connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i] + connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync] + connect_bd_net -net sys_250m_clk [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] + connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset] + connect_bd_net -net sys_250m_resetn [get_bd_pins axi_hp2_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins sys_250m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_500m_clk [get_bd_pins sys_500m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/pl_clk2] + connect_bd_net -net sys_500m_reset [get_bd_pins sys_500m_rstgen/peripheral_reset] + connect_bd_net -net sys_500m_resetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn] + connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0] + connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins util_mxfe_xcvr/up_clk] + connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins util_mxfe_xcvr/up_rstn] + connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_ports gpio_o] [get_bd_pins sys_ps8/emio_gpio_o] + connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_ports gpio_t] [get_bd_pins sys_ps8/emio_gpio_t] + connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_ports spi0_mosi] [get_bd_pins sys_ps8/emio_spi0_m_o] + connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_ports spi0_sclk] [get_bd_pins sys_ps8/emio_spi0_sclk_o] + connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins spi0_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins spi0_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins spi0_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi0_ss_o_n] + connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_ports spi1_mosi] [get_bd_pins sys_ps8/emio_spi1_m_o] + connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_ports spi1_sclk] [get_bd_pins sys_ps8/emio_spi1_sclk_o] + connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins spi1_csn_concat/In1] [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins spi1_csn_concat/In2] [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] + connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins spi1_csn_concat/In0] [get_bd_pins sys_ps8/emio_spi1_ss_o_n] + connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in] [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_rstgen/ext_reset_in] + connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref] + connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref] + connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins dds_pulse_wrapper_0/m_axis_aclk_in] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_upack/clk] + connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] + connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_4 [get_bd_pins tx_mxfe_tpl_core/dac_enable_4] [get_bd_pins util_mxfe_upack/enable_4] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_5 [get_bd_pins tx_mxfe_tpl_core/dac_enable_5] [get_bd_pins util_mxfe_upack/enable_5] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_6 [get_bd_pins tx_mxfe_tpl_core/dac_enable_6] [get_bd_pins util_mxfe_upack/enable_6] + connect_bd_net -net tx_mxfe_tpl_core_dac_enable_7 [get_bd_pins tx_mxfe_tpl_core/dac_enable_7] [get_bd_pins util_mxfe_upack/enable_7] + connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1] + connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins manual_sync_or/Op2] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] + connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en] + connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1] + connect_bd_net -net upack_rst_logic_Res [get_bd_pins dds_pulse_wrapper_0/rst_in] [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] + connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins tx_mxfe_tpl_core/dac_data_0] [get_bd_pins util_mxfe_upack/fifo_rd_data_0] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins tx_mxfe_tpl_core/dac_data_1] [get_bd_pins util_mxfe_upack/fifo_rd_data_1] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins tx_mxfe_tpl_core/dac_data_2] [get_bd_pins util_mxfe_upack/fifo_rd_data_2] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins tx_mxfe_tpl_core/dac_data_3] [get_bd_pins util_mxfe_upack/fifo_rd_data_3] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_4 [get_bd_pins tx_mxfe_tpl_core/dac_data_4] [get_bd_pins util_mxfe_upack/fifo_rd_data_4] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_5 [get_bd_pins tx_mxfe_tpl_core/dac_data_5] [get_bd_pins util_mxfe_upack/fifo_rd_data_5] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_6 [get_bd_pins tx_mxfe_tpl_core/dac_data_6] [get_bd_pins util_mxfe_upack/fifo_rd_data_6] + connect_bd_net -net util_mxfe_upack_fifo_rd_data_7 [get_bd_pins tx_mxfe_tpl_core/dac_data_7] [get_bd_pins util_mxfe_upack/fifo_rd_data_7] + connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins axi_mxfe_rx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] + connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_ports tx_data_0_n] [get_bd_pins util_mxfe_xcvr/tx_0_n] + connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_ports tx_data_0_p] [get_bd_pins util_mxfe_xcvr/tx_0_p] + connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_ports tx_data_1_n] [get_bd_pins util_mxfe_xcvr/tx_1_n] + connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_ports tx_data_1_p] [get_bd_pins util_mxfe_xcvr/tx_1_p] + connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_ports tx_data_2_n] [get_bd_pins util_mxfe_xcvr/tx_2_n] + connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_ports tx_data_2_p] [get_bd_pins util_mxfe_xcvr/tx_2_p] + connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_ports tx_data_3_n] [get_bd_pins util_mxfe_xcvr/tx_3_n] + connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_ports tx_data_3_p] [get_bd_pins util_mxfe_xcvr/tx_3_p] + connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins axi_mxfe_tx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_LPS_OCM] -force + assign_bd_address -offset 0xE0000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_PCIE_LOW] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_QSPI] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force + assign_bd_address -offset 0x9C420000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C430000 -range 0x00001000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B90000 -range 0x00004000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B60000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force + assign_bd_address -offset 0x85000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C450000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x9C440000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force + assign_bd_address -offset 0x84A10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force + assign_bd_address -offset 0x84B10000 -range 0x00002000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force + + # Exclude Address Segments + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_QSPI] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_LPS_OCM] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_PCIE_LOW] + exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_QSPI] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/source/component.xml b/source/component.xml new file mode 100644 index 0000000..6d1fce9 --- /dev/null +++ b/source/component.xml @@ -0,0 +1,610 @@ + + + xilinx.com + user + dds_pulse_wrapper + 1.0 + + + m_axis_out + + + + + + + TDATA + + + m_axis_tdata_out + + + + + TVALID + + + m_axis_tvalid_out + + + + + TREADY + + + m_axis_tready_in + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + dds_pulse_wrapper + + xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4288e600 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + dds_pulse_wrapper + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4288e600 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c12c7cc7 + + + + + + + clk_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aclk_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tdata_out + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tvalid_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tready_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + SIM_ENABLED + Sim Enabled + FALSE + + + FPGA_REVISION_DATE + Fpga Revision Date + 0x09162023 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1 + + + ../ip/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo + + + ../ip/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1 + + + ../ip/dds_latency10/dds_latency10.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds + + + ../ip/addsub/addsub.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub + + + src/ila_0/ila_0.xci + xci + CELL_NAME_sim_false3.i_ila_2 + + + ../ip/axis_data_fifo_512x128/axis_data_fifo_512x128.xci + xci + CELL_NAME_i_fifo + + + src/ila_3/ila_3.xci + xci + CELL_NAME_sim_false2.i_ila_3 + + + src/ila_4/ila_4.xci + xci + CELL_NAME_sim_false1.i_ila_4 + + + src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci + xci + CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo + + + src/ila_2/ila_2.xci + xci + CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1 + + + ../ip/vio_0/vio_0.xci + xci + CELL_NAME_sim_false.i_vio_0 + + + dds_cmd_gen.vhd + vhdlSource + + + dds_pulse_2x_top.vhd + vhdlSource + + + dds_pulse_gen.vhd + vhdlSource + + + dds_pulse_wrapper.vhd + vhdlSource + CHECKSUM_bb6db1b1 + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1 + + + ../ip/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo + + + ../ip/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1 + + + ../ip/dds_latency10/dds_latency10.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds + + + ../ip/addsub/addsub.xci + xci + CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub + + + src/ila_0/ila_0.xci + xci + CELL_NAME_sim_false3.i_ila_2 + + + ../ip/axis_data_fifo_512x128/axis_data_fifo_512x128.xci + xci + CELL_NAME_i_fifo + + + src/ila_3/ila_3.xci + xci + CELL_NAME_sim_false2.i_ila_3 + + + src/ila_4/ila_4.xci + xci + CELL_NAME_sim_false1.i_ila_4 + + + src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci + xci + CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo + + + src/ila_2/ila_2.xci + xci + CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1 + + + ../ip/vio_0/vio_0.xci + xci + CELL_NAME_sim_false.i_vio_0 + + + dds_cmd_gen.vhd + vhdlSource + + + dds_pulse_2x_top.vhd + vhdlSource + + + dds_pulse_gen.vhd + vhdlSource + + + dds_pulse_wrapper.vhd + vhdlSource + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/dds_pulse_wrapper_v1_0.tcl + tclSource + CHECKSUM_c12c7cc7 + XGUI_VERSION_2 + + + + dds_pulse_wrapper_v1_0 + + + SIM_ENABLED + Sim Enabled + FALSE + + + Component_Name + dds_pulse_wrapper_v1_0 + + + FPGA_REVISION_DATE + Fpga Revision Date + 0x09162023 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + dds_pulse_wrapper_v1_0 + package_project + + XPM_CDC + XPM_FIFO + XPM_MEMORY + + 15 + 2023-09-17T19:46:14Z + + + + + + 2022.2 + + + + + + + + diff --git a/source/dds_cmd_gen.vhd b/source/dds_cmd_gen.vhd new file mode 100644 index 0000000..e4042fe --- /dev/null +++ b/source/dds_cmd_gen.vhd @@ -0,0 +1,205 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity dds_cmd_gen is + generic ( + SIM_ENABLED : boolean := FALSE + ); + port( + clk_in : in std_logic; + cmd_idx_in : in std_logic_vector( 2 downto 0); + cmd_send_in : in std_logic; + + vio_reserv1_in : in std_logic_vector(31 downto 0); + vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0); + vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0); + vio_idle_samples_in : in std_logic_vector(31 downto 0); + vio_dds_samples_in : in std_logic_vector(31 downto 0); + vio_phase_inc_in : in std_logic_vector(31 downto 0); + vio_phase_off_in : in std_logic_vector(31 downto 0); + vio_swap_sf_in : in std_logic_vector(31 downto 0); + + fifo_rd_clk_in : in std_logic; + fifo_rd_data_out : out std_logic_vector(31 downto 0); + fifo_rd_dval_out : out std_logic; + fifo_rd_rd_en_in : in std_logic; + fifo_rd_empty_out : out std_logic; + + rst_in : in std_logic + ); +end entity dds_cmd_gen; + +architecture imp of dds_cmd_gen is + + signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0'); + signal fifo_wr_en_r : std_logic := '0'; + + signal cmd_idx_r : integer range 0 to 4 := 0; + signal cmd_send_r : std_logic := '0'; + + type fsm_state is (IDLE, SEND, DONE); + signal state_r : fsm_state := IDLE; + signal state_cnt_r : integer := 0; + + type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0); + type dds_command_list is array (integer range <>) of array_32b_type; + signal dds_command_set : dds_command_list(0 to 4) := + ( + -- WFM 0 + -- FREQUENCY SWEEP (UP-SWEEP) + 0 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) = 68719 = 0x00010C6F + x"00000000", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2 + x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 1 + -- FREQUENCY SWEEP (DOWN-SWEEP) + 1 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000000", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 2 + -- CW TONE + 2 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone) + x"00000000", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) +-- x"000FFFFF", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 3 + -- FREQUENCY SWEEP (DOWN-SWEEP) + 3 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000000", --IDLE_SAMPLES + x"000004E2", --DDS_SAMPLES (~5 us) + x"0624DD2F", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ), + -- WFM 4 + -- ?????? + 4 => (x"00000000", --RESERVED1 + x"00000000", --DDS_PHASE_INC_DWELL_TIME + x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) + x"00000000", --IDLE_SAMPLES + x"00000000", --DDS_SAMPLES (~5 us) + x"00000000", --PHASE_INC (~6 MHz) + x"00000000", --PHASE_OFF + x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 + ) + ); + + + signal test_state_r : std_logic_vector(1 downto 0) := (others => '0'); + +begin + + dds_command_set(4)(0) <= vio_reserv1_in; + dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in; + dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in; + dds_command_set(4)(3) <= vio_idle_samples_in; + dds_command_set(4)(4) <= vio_dds_samples_in; + dds_command_set(4)(5) <= vio_phase_inc_in; + dds_command_set(4)(6) <= vio_phase_off_in; + dds_command_set(4)(7) <= vio_swap_sf_in; + + process(clk_in) + begin + if (rising_edge(clk_in)) then + if (rst_in = '1') then + cmd_idx_r <= 0; + cmd_send_r <= '0'; + fifo_wr_en_r <= '0'; + state_cnt_r <= 0; + state_r <= IDLE; + else + cmd_send_r <= cmd_send_in; + fifo_wr_en_r <= '0'; + + case (state_r) is + when IDLE => + if (cmd_send_in = '1' and cmd_send_r = '0') then + cmd_idx_r <= conv_integer(unsigned(cmd_idx_in)); + state_cnt_r <= 0; + state_r <= SEND; + else + state_r <= IDLE; + end if; + + when SEND => + if (state_cnt_r = 8) then + state_r <= DONE; + else + fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r); + fifo_wr_en_r <= '1'; + state_cnt_r <= state_cnt_r + 1; + state_r <= SEND; + end if; + + when DONE => + state_r <= IDLE; + + when others => + state_r <= IDLE; + + end case; + end if; + end if; + end process; + + test_state_r <= "00" when state_r = IDLE else + "01" when state_r = SEND else + "10" when state_r = DONE else + "11"; + + sim_false : if (SIM_ENABLED = FALSE) generate + i_ila_1 : entity work.ila_2 + port map ( + clk => clk_in, + probe0 => test_state_r, -- 2 + probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4 + probe2 => fifo_wr_data_r, -- 32 + probe3(0) => fifo_wr_en_r, -- 1 + probe4(0) => cmd_send_in, -- 1 + probe5(0) => cmd_send_r -- 1 + ); + end generate sim_false; + + i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1 + port map( + wr_clk => clk_in, + din => fifo_wr_data_r, + wr_en => fifo_wr_en_r, + full => open, + overflow => open, + + rd_clk => fifo_rd_clk_in, + dout => fifo_rd_data_out, + valid => fifo_rd_dval_out, + rd_en => fifo_rd_rd_en_in, + empty => fifo_rd_empty_out, + + underflow => open, + prog_full => open, + wr_rst_busy => open, + rd_rst_busy => open, + srst => rst_in + ); + +end architecture imp; diff --git a/source/dds_pulse_2x_top.vhd b/source/dds_pulse_2x_top.vhd new file mode 100644 index 0000000..8e53f95 --- /dev/null +++ b/source/dds_pulse_2x_top.vhd @@ -0,0 +1,419 @@ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M. Blevins +-- +-- Create Date: 19:38:12 11/10/2016 +-- Design Name: +-- Module Name: dds_pulse_2x_top - behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- * All information is proprietary/confidential * +-- +-- Supports single channel mode or dual channel (summed) mode. +-- When using dual channel mode, the module hangs after the shortest of the +-- two pulse streams completes. Ideally, both streams will be equal length. +-- +-- For each channel: +-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO. +-- The control word contains all information needed to create a pulse +-- +-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits +-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies +-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000 +-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000 +-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits +-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits +-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits +-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit +-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!) +-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits +-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--Library UNIMACRO; +--use UNIMACRO.vcomponents.all; +USE IEEE.NUMERIC_STD.ALL; + +entity dds_pulse_2x_top is + port( + clk_in : in std_logic; + rst_in : in std_logic; + mode_in : in std_logic; -- 0=single, 1=dual + scale_in : in std_logic_vector(15 downto 0); + fifo1_data_in : in std_logic_vector(31 downto 0); + fifo1_dval_in : in std_logic; + fifo1_empty_in : in std_logic; + fifo1_rden_out : out std_logic; + fifo2_data_in : in std_logic_vector(31 downto 0); + fifo2_dval_in : in std_logic; + fifo2_empty_in : in std_logic; + fifo2_rden_out : out std_logic; + holdoff_in : in std_logic; + overflow_out : out std_logic_vector(1 downto 0); + underflow_out : out std_logic_vector(1 downto 0); + i_max_abs_out : out std_logic_vector(15 downto 0); + q_max_abs_out : out std_logic_vector(15 downto 0); + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); +end entity; + +architecture mixed of dds_pulse_2x_top is + + component mult_16signed_x_16unsigned_latency3 + port( + clk : in std_logic; + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + ce : in std_logic; + sclr : in std_logic; + p : out std_logic_vector(15 downto 0) + ); + end component; + + component dds_pulse_gen is + port( + clk_in : in std_logic; + rst_in : in std_logic; + fifo_data_in : in std_logic_vector(31 downto 0); + fifo_dval_in : in std_logic; + fifo_empty_in : in std_logic; + fifo_rden_out : out std_logic; + holdoff_in : in std_logic; + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); + end component; + + component sfifo_32b_1024_pf992_latency1 + port( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(31 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(31 downto 0); + full : out std_logic; + overflow : out std_logic; + empty : out std_logic; + underflow : out std_logic; + prog_full : out std_logic + ); + end component; + + component adder_16signed_16signed_latency2 + port( + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + clk : in std_logic; + ce : in std_logic; + bypass : in std_logic; + s : out std_logic_vector(16 downto 0) + ); + end component; + + signal rst_r : std_logic := '1'; + signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual + signal scale_r : std_logic_vector(15 downto 0) := x"8000"; + signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00"; + signal pulse_adder_dval_r : std_logic := '0'; + signal pulse_adder_ce : std_logic; + signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0'); + signal pulse_dval_r : std_logic := '0'; + signal adder_dval_r : std_logic := '0'; + signal holdoff_r : std_logic; + + signal pulse1_mult_dval_r : std_logic := '0'; + signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal pulse1_mult_ce : std_logic; + signal pulse1_data : std_logic_vector(31 downto 0); + signal pulse1_dval : std_logic; + signal pulse1_data_scaled : std_logic_vector(31 downto 0); + signal pulse1_fifo_overflow : std_logic; + signal pulse1_fifo_empty : std_logic; + signal pulse1_fifo_underflow : std_logic; + signal pulse1_fifo_progfull : std_logic; + signal pulse1_fifo_rden : std_logic; + signal pulse1_fifo_rden_r : std_logic := '0'; + signal pulse1_fifo_dout : std_logic_vector(31 downto 0); + signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0'); + signal adder1_s : std_logic_vector(16 downto 0); + signal adder1_s_r : std_logic_vector(16 downto 0); + signal adder1_s_r1 : std_logic_vector(15 downto 0); + signal i_abs_max_r : unsigned(15 downto 0); + signal fifo1_underflow_r : std_logic := '0'; + signal fifo1_overflow_r : std_logic := '0'; + + signal pulse2_mult_dval_r : std_logic := '0'; + signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal pulse2_mult_ce : std_logic; + signal pulse2_data : std_logic_vector(31 downto 0); + signal pulse2_dval : std_logic; + signal pulse2_data_scaled : std_logic_vector(31 downto 0); + signal pulse2_fifo_overflow : std_logic; + signal pulse2_fifo_empty : std_logic; + signal pulse2_fifo_underflow : std_logic; + signal pulse2_fifo_progfull : std_logic; + signal pulse2_fifo_rden : std_logic; + signal pulse2_fifo_dout : std_logic_vector(31 downto 0); + signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0); + signal adder2_s : std_logic_vector(16 downto 0); + signal adder2_s_r : std_logic_vector(16 downto 0); + signal adder2_s_r1 : std_logic_vector(15 downto 0); + signal q_abs_max_r : unsigned(15 downto 0); + signal fifo2_underflow_r : std_logic := '0'; + signal fifo2_overflow_r : std_logic := '0'; + +begin + + data_out <= pulse_data_r; + dval_out <= pulse_dval_r; + i_max_abs_out <= std_logic_vector(i_abs_max_r); + q_max_abs_out <= std_logic_vector(q_abs_max_r); + overflow_out <= fifo2_overflow_r & fifo1_overflow_r; + underflow_out <= fifo2_underflow_r & fifo1_underflow_r; + + process(clk_in) + begin + if(rising_edge(clk_in))then + rst_r <= rst_in; + scale_r <= scale_in; + mode_n_r <= not(mode_in); + holdoff_r <= holdoff_in; + end if; + end process; + + process(clk_in) + begin + if(rising_edge(clk_in))then + pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1); + pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval; + pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1); + pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval; + pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r; + pulse_adder_dval_r <= pulse_fifo_dval_r(1); + pulse1_fifo_rden_r <= pulse1_fifo_rden; + pulse1_fifo_dout_r <= pulse1_fifo_dout; + pulse2_fifo_dout_r <= pulse2_fifo_dout; + end if; + end process; + + pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval; + pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval; + + pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else + not(pulse1_fifo_empty) and not(holdoff_r); + + pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else + '0'; + + pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0); + + i_dds_pulse1_gen : dds_pulse_gen + port map( + clk_in => clk_in, + rst_in => rst_r, + fifo_data_in => fifo1_data_in, + fifo_dval_in => fifo1_dval_in, + fifo_empty_in => fifo1_empty_in, + fifo_rden_out => fifo1_rden_out, + holdoff_in => pulse1_fifo_progfull, + data_out => pulse1_data, + dval_out => pulse1_dval + ); + + i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse1_data(15 downto 0), + b => scale_r, + ce => pulse1_mult_ce, + sclr => '0', + p => pulse1_data_scaled(15 downto 0) + ); + + i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse1_data(31 downto 16), + b => scale_r, + ce => pulse1_mult_ce, + sclr => '0', + p => pulse1_data_scaled(31 downto 16) + ); + + i_pulse1_fifo : sfifo_32b_1024_pf992_latency1 + port map( + clk => clk_in, + srst => rst_r, + din => pulse1_data_scaled, + wr_en => pulse1_mult_dval_r, + rd_en => pulse1_fifo_rden, + dout => pulse1_fifo_dout, + full => open, + overflow => pulse1_fifo_overflow, + empty => pulse1_fifo_empty, + underflow => pulse1_fifo_underflow, + prog_full => pulse1_fifo_progfull + ); + + i_dds_pulse2_gen : dds_pulse_gen + port map( + clk_in => clk_in, + rst_in => rst_r, + fifo_data_in => fifo2_data_in, + fifo_dval_in => fifo2_dval_in, + fifo_empty_in => fifo2_empty_in, + fifo_rden_out => fifo2_rden_out, + holdoff_in => pulse2_fifo_progfull, + data_out => pulse2_data, + dval_out => pulse2_dval + ); + + i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse2_data(15 downto 0), + b => scale_r, + ce => pulse2_mult_ce, + sclr => '0', + p => pulse2_data_scaled(15 downto 0) + ); + + i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => pulse2_data(31 downto 16), + b => scale_r, + ce => pulse2_mult_ce, + sclr => '0', + p => pulse2_data_scaled(31 downto 16) + ); + + i_pulse2_fifo : sfifo_32b_1024_pf992_latency1 + port map( + clk => clk_in, + srst => rst_r, + din => pulse2_data_scaled, + wr_en => pulse2_mult_dval_r, + rd_en => pulse2_fifo_rden, + dout => pulse2_fifo_dout, + full => open, + overflow => pulse2_fifo_overflow, + empty => pulse2_fifo_empty, + underflow => pulse2_fifo_underflow, + prog_full => pulse2_fifo_progfull + ); + + i_pulse_adder1 : adder_16signed_16signed_latency2 + port map( + a => pulse2_fifo_dout_r(15 downto 0), + b => pulse1_fifo_dout_r(15 downto 0), + clk => clk_in, + ce => pulse_adder_ce, + bypass => mode_n_r, -- when set to '1', b input proceeds to s output + s => adder1_s + ); + + i_pulse_adder2 : adder_16signed_16signed_latency2 + port map( + a => pulse2_fifo_dout_r(31 downto 16), + b => pulse1_fifo_dout_r(31 downto 16), + clk => clk_in, + ce => pulse_adder_ce, + bypass => mode_n_r, -- when set to '1', b input proceeds to s output + s => adder2_s + ); + + process(clk_in) + begin + if(rising_edge(clk_in))then + adder1_s_r <= adder1_s; + adder2_s_r <= adder2_s; + adder_dval_r <= pulse_adder_dval_r; + pulse_dval_r <= adder_dval_r; + if(adder_dval_r = '1')then + case adder1_s_r(16 downto 15) is + when "01" => --positive overflow + pulse_data_r(15 downto 0) <= x"7FFF"; + when "10" => --negative overflow + pulse_data_r(15 downto 0) <= x"8000"; + when others => + pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0); + end case; + case adder2_s_r(16 downto 15) is + when "01" => --positive overflow + pulse_data_r(31 downto 16) <= x"7FFF"; + when "10" => --negative overflow + pulse_data_r(31 downto 16) <= x"8000"; + when others => + pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0); + end case; + end if; + if(rst_r = '1')then + --adder_dval_r <= '0'; + --pulse_dval_r <= '0'; + i_abs_max_r <= (others => '0'); + q_abs_max_r <= (others => '0'); + fifo1_overflow_r <= '0'; + fifo1_underflow_r <= '0'; + fifo2_overflow_r <= '0'; + fifo2_underflow_r <= '0'; + else + --adder_dval_r <= pulse_adder_dval_r; + --pulse_dval_r <= adder_dval_r; + if(pulse1_fifo_overflow = '1')then + fifo1_overflow_r <= '1'; + end if; + if(pulse1_fifo_underflow = '1')then + fifo1_underflow_r <= '1'; + end if; + if(pulse2_fifo_overflow = '1')then + fifo2_overflow_r <= '1'; + end if; + if(pulse2_fifo_underflow = '1')then + fifo2_underflow_r <= '1'; + end if; + if(adder_dval_r = '1')then + -- if(abs(signed(adder1_s_r)) > i_abs_max_r)then + -- i_abs_max_r <= abs(signed(adder1_s_r)); + -- end if; + if(adder1_s_r(16) = '0')then + adder1_s_r1 <= adder1_s_r(15 downto 0); + else + adder1_s_r1 <= not(adder1_s_r(15 downto 0)); + end if; + + -- if(abs(signed(adder2_s_r)) > q_abs_max_r)then + -- q_abs_max_r <= abs(signed(adder2_s_r)); + -- end if; + if(adder2_s_r(16) = '0')then + adder2_s_r1 <= adder2_s_r(15 downto 0); + else + adder2_s_r1 <= not(adder2_s_r(15 downto 0)); + end if; + end if; + if(pulse_dval_r = '1')then + if(unsigned(adder1_s_r1) > i_abs_max_r)then + i_abs_max_r <= unsigned(adder1_s_r1); + end if; + if(unsigned(adder2_s_r1) > q_abs_max_r)then + q_abs_max_r <= unsigned(adder2_s_r1); + end if; + end if; + end if; + end if; + end process; + +end mixed; + \ No newline at end of file diff --git a/source/dds_pulse_gen.vhd b/source/dds_pulse_gen.vhd new file mode 100644 index 0000000..6291cf5 --- /dev/null +++ b/source/dds_pulse_gen.vhd @@ -0,0 +1,415 @@ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M. Blevins +-- +-- Create Date: 19:38:12 11/10/2016 +-- Design Name: +-- Module Name: dds_pulse_gen - behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - Added Sweep Functionality 10-17-2017 +-- Additional Comments: +-- * All information is proprietary/confidential * +-- +-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO. +-- The control word contains all information needed to create a pulse +-- +-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits +-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies +-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000 +-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000 +-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits +-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits +-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits +-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit +-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!) +-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits +-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits +-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--Library UNIMACRO; +--use UNIMACRO.vcomponents.all; +USE IEEE.NUMERIC_STD.ALL; + +entity dds_pulse_gen is + port( + clk_in : in std_logic; + rst_in : in std_logic; + fifo_data_in : in std_logic_vector(31 downto 0); + fifo_dval_in : in std_logic; + fifo_empty_in : in std_logic; + fifo_rden_out : out std_logic; + holdoff_in : in std_logic; + data_out : out std_logic_vector(31 downto 0); + dval_out : out std_logic + ); +end entity; + +architecture mixed of dds_pulse_gen is + + component mult_16signed_x_16unsigned_latency3 + port( + clk : in std_logic; + a : in std_logic_vector(15 downto 0); + b : in std_logic_vector(15 downto 0); + ce : in std_logic; + sclr : in std_logic; + p : out std_logic_vector(15 downto 0) + ); + end component; + + component dds_latency10 + port( + -- ce : in std_logic; + -- clk : in std_logic; + -- sclr : in std_logic; + -- pinc_in : in std_logic_vector(31 downto 0); + -- poff_in : in std_logic_vector(31 downto 0); + -- rdy : out std_logic; + -- cosine : out std_logic_vector(15 downto 0); + -- sine : out std_logic_vector(15 downto 0) + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + end component; + + component addsub + port ( + a : in std_logic_vector(31 downto 0); -- unsigned + b : in std_logic_vector(23 downto 0); -- signed + --clk : in std_logic; + s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency. + ); + end component; + + constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000"; + + type state_type is (s0, s0a, s0b, s0c, s1, s2, s3); + signal state : state_type; + signal state_r : state_type; + signal rst_r : std_logic := '1'; + signal rstn_r : std_logic := '0'; + + signal cnt1_r : unsigned(3 downto 0) := "0000"; + signal cnt1 : unsigned(3 downto 0); + signal cnt2_r : unsigned(2 downto 0) := "000"; + signal cnt2 : unsigned(2 downto 0); + signal cnt3_r : unsigned(31 downto 0) := x"00000000"; + signal cnt3 : unsigned(31 downto 0); + signal cnt4_r : unsigned(31 downto 0) := x"00000000"; + signal cnt4 : unsigned(31 downto 0); + signal cnt5_r : unsigned(3 downto 0) := "0000"; + signal cnt5 : unsigned(3 downto 0); + signal fifo_data_ce : std_logic; + signal fifo_data_r : std_logic_vector(255 downto 0); + signal fifo_rden : std_logic; + --signal fifo_rden_r : std_logic := '0'; + signal dval_r : std_logic := '0'; + signal dval : std_logic; + signal dds_data : std_logic_vector(31 downto 0); + signal data : std_logic_vector(31 downto 0); + signal data_r : std_logic_vector(31 downto 0); + signal idle_sample_cnt_r : unsigned(31 downto 0); + signal idle_sample_cnt_r1 : unsigned(31 downto 0); + signal dds_sample_cnt_r : unsigned(31 downto 0); + signal dds_sample_cnt_r1 : unsigned(31 downto 0); + signal phase_inc_init_r : std_logic_vector(31 downto 0); + signal phase_offset_r : std_logic_vector(31 downto 0); + signal swap_r : std_logic := '0'; + signal scale_r : std_logic_vector(15 downto 0); + signal mult_dval_r : std_logic := '0'; + signal data_swap_scaled : std_logic_vector(31 downto 0); + signal data_scaled : std_logic_vector(31 downto 0); + signal dds_ce : std_logic; + signal dds_rst : std_logic; + signal dds_rdy : std_logic; + signal mult_ce : std_logic; + signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00"; + signal holdoff_r : std_logic; + + --signal phase_inc_mux_sel : std_logic; + signal phase_inc_update_en : std_logic; + --signal phase_inc_mux : std_logic_vector(31 downto 0); + signal phase_inc : std_logic_vector(31 downto 0); + signal phase_inc_r : std_logic_vector(31 downto 0); + signal phase_inc_r1 : std_logic_vector(31 downto 0); + signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0'); + signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000"; + signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000"; + signal phase_inc_dwell_cnt : unsigned(15 downto 0); + signal phase_inc_addsub : std_logic_vector(31 downto 0); + signal rstn : std_logic; + +begin + + + + i_addsub : addsub + port map( + a => phase_inc_r, + b => phase_inc_step_r, + --clk => clk_in, + s => phase_inc_addsub + ); + + fifo_rden_out <= fifo_rden;--fifo_rden_r; + data_out <= data_r; + dval_out <= dval_r; + + process(clk_in) + begin + if(rising_edge(clk_in))then + if(rst_r = '1')then + state_r <= s0; + cnt1_r <= (others => '0'); + cnt2_r <= (others => '0'); + cnt3_r <= (others => '0'); + cnt4_r <= (others => '0'); + cnt5_r <= (others => '0'); + phase_inc_dwell_cnt_r <= (others => '0'); + else + state_r <= state; + cnt1_r <= cnt1; + cnt2_r <= cnt2; + cnt3_r <= cnt3; + cnt4_r <= cnt4; + cnt5_r <= cnt5; + phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt; + end if; + if(fifo_data_ce = '1')then + fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in; + end if; + rst_r <= rst_in; + rstn_r <= not(rst_in); + dval_r <= dval; + phase_offset_r <= fifo_data_r(223 downto 192); + -- phase_inc_init_r <= fifo_data_r(191 downto 160); + dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128)); + dds_sample_cnt_r1 <= dds_sample_cnt_r; + swap_r <= fifo_data_r(240); + scale_r <= fifo_data_r(239 downto 224); + idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96)); + idle_sample_cnt_r1 <= idle_sample_cnt_r; + phase_inc_step_r <= fifo_data_r(87 downto 64); + phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32)); + data_r <= data; + holdoff_r <= holdoff_in; + phase_inc_r <= phase_inc; + + if(phase_inc_update_en = '1')then + phase_inc_r1 <= phase_inc_r; + end if; + + end if; + end process; + + + phase_inc_init_r <= fifo_data_r(191 downto 160); + + -- FSM next-state & output process + process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r, + mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub) + begin + --defaults + fifo_rden <= '0'; + cnt1 <= cnt1_r; + cnt2 <= cnt2_r; + cnt3 <= cnt3_r; + cnt4 <= cnt4_r; + cnt5 <= cnt5_r; + state <= state_r; + dds_ce <= '0'; + dds_rst <= '1'; + dval <= mult_dval_r; + data <= data_swap_scaled; + fifo_data_ce <= '0'; + phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r; + phase_inc <= phase_inc_r; + phase_inc_update_en <= '0'; + + case state_r is + + when s0 => + phase_inc_dwell_cnt <= (others => '0'); + if(fifo_empty_in = '0' and cnt1_r < 8)then + fifo_rden <= '1'; + cnt1 <= cnt1_r +1; + end if; + if(fifo_dval_in = '1')then + fifo_data_ce <= '1'; + if(cnt2_r < 7)then + cnt2 <= cnt2_r +1; + else + cnt2 <= (others => '0'); + cnt1 <= (others => '0'); + state <= s0a; + end if; + end if; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + when s0a => + state <= s0b;--s1; + phase_inc <= phase_inc_init_r; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + when s0b => + state <= s1; + phase_inc_update_en <= '1'; + phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + + -- This state is needed to clock the input shift reg data into next set of regs. + -- Possibly can be removed to decrease pulse param processing cycles. + -- when s0c => + -- state <= s1; + -- phase_inc_update_en <= '1'; + -- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + + + -- Insert midpoint (idle) samples that preceed the pulse. + when s1 => + data <= MIDPOINT; + if(cnt3_r < idle_sample_cnt_r1)then + if(holdoff_r = '0')then + cnt3 <= cnt3_r +1; + dval <= '1'; + end if; + else + cnt3 <= (others => '0'); + if(dds_sample_cnt_r1 > 0)then + state <= s2; + else + state <= s0; + end if; + end if; + + -- Turn on DDS for requested number of samples. + when s2 => + dds_rst <= '0'; + + if(holdoff_r = '0')then + if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then + phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1; + else + phase_inc_dwell_cnt <= (others => '0'); + phase_inc_update_en <= '1'; + phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r; + end if; + end if; + + if(holdoff_r = '0')then + dds_ce <= '1'; + if(cnt4_r < dds_sample_cnt_r1)then + cnt4 <= cnt4_r +1; + else + cnt4 <= (others => '0'); + state <= s3; + end if; + end if; + + -- phase_inc_mux_sel <= '1'; + -- --phase_inc_en <= not(holdoff_r); + -- dds_rst <= '0'; + -- if(cnt4_r < dds_sample_cnt_r1)then + -- if(holdoff_r = '0')then + -- dds_ce <= '1'; + -- cnt4 <= cnt4_r +1; + -- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then + -- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1; + -- else + -- phase_inc_dwell_cnt <= x"00000"; + -- phase_inc_en <= '1'; + -- end if; + -- end if; + -- else + -- if(holdoff_r = '0')then + -- dds_ce <= '1'; + -- cnt4 <= (others => '0'); + -- state <= s3; + -- end if; + -- end if; + + -- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out). + when s3 => + dds_rst <= '0'; + if(cnt5_r < 9)then + if(holdoff_r = '0')then + dds_ce <= '1'; + cnt5 <= cnt5_r +1; + end if; + else + cnt5 <= (others => '0'); + state <= s0; + end if; + when others => + end case; + end process; + + process(clk_in) + begin + if(rising_edge(clk_in))then + mult_dval_r <= mult_ce_pipe_r(1); + mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce); + end if; + end process; + + data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16); + mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce); + + i_dds : dds_latency10 + port map( + -- ce => dds_ce, + -- clk => clk_in, + -- sclr => dds_rst, + -- pinc_in => phase_inc_r1, + -- poff_in => phase_offset_r, + -- rdy => dds_rdy, + -- cosine => dds_data(15 downto 0), + -- sine => dds_data(31 downto 16) + aclk => clk_in, + aclken => dds_ce, + aresetn => rstn_r, + s_axis_phase_tvalid => dds_ce, + s_axis_phase_tdata => phase_inc_r1, + m_axis_data_tvalid => dds_rdy, + m_axis_data_tdata => dds_data(31 downto 0) + ); + + i_mult1 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => dds_data(15 downto 0), + b => scale_r, + ce => mult_ce, + sclr => '0', + p => data_scaled(15 downto 0) + ); + + i_mult2 : mult_16signed_x_16unsigned_latency3 + port map( + clk => clk_in, + a => dds_data(31 downto 16), + b => scale_r, + ce => mult_ce, + sclr => '0', + p => data_scaled(31 downto 16) + ); + +end mixed; + \ No newline at end of file diff --git a/source/dds_pulse_wrapper.vhd b/source/dds_pulse_wrapper.vhd new file mode 100644 index 0000000..986a92a --- /dev/null +++ b/source/dds_pulse_wrapper.vhd @@ -0,0 +1,346 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity dds_pulse_wrapper is + generic ( + SIM_ENABLED : boolean := FALSE; + FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0916_2023" + ); + port( + clk_in : in std_logic; + + m_axis_aclk_in : in std_logic; + + m_axis_tdata_out : out std_logic_vector(127 downto 0); + m_axis_tvalid_out : out std_logic; + m_axis_tready_in : in std_logic; + + rst_in : in std_logic + ); +end entity dds_pulse_wrapper; + +architecture imp of dds_pulse_wrapper is + + constant ok_clk_in_period : time := 10 ns; + + signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0'); + attribute keep : string; + attribute keep of fpga_revision_date_r : signal is "true"; + + signal reset_n : std_logic; + signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001"; + signal s_axis_tready : std_logic; + + signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0'); + signal dds_pulse_dval_r : std_logic := '0'; + + signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0'); + signal dds_pulse_data_cnt_r1 : std_logic_vector(15 downto 0) := (others => '0'); + + signal cmd_idx : std_logic_vector( 2 downto 0) := "000"; + signal cmd_send : std_logic := '0'; + + signal mode : std_logic := '0'; + signal scale : std_logic_vector(15 downto 0) := x"0000"; + signal dac_holdoff : std_logic := '1'; + + signal dds_pulse_dval : std_logic; + signal dds_pulse_data : std_logic_vector(31 downto 0); + signal pulse_i : std_logic_vector(15 downto 0); + signal pulse_q : std_logic_vector(15 downto 0); + + signal pipe_in_ch1_fifo_rden : std_logic; + signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0); + signal pipe_in_ch1_fifo_rd_dval : std_logic; + signal pipe_in_ch1_fifo_empty : std_logic; + signal pipe_in_ch2_fifo_rden : std_logic; + + signal m_axis_tdata : std_logic_vector(127 downto 0); + signal m_axis_tvalid : std_logic; + + signal pulse_data_word : std_logic_vector(127 downto 0); + + signal vio_reserv1 : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_idle_samples : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_dds_samples : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_phase_inc : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_phase_off : std_logic_vector(31 downto 0) := (others => '0'); + signal vio_swap_sf : std_logic_vector(31 downto 0) := (others => '0'); + +begin + + reset_n <= not rst_in; + +-- process(clk_in) +-- begin +-- if (rising_edge(clk_in)) then +-- fpga_revision_date_r <= FPGA_REVISION_DATE; +-- end if; +-- end process; + + sim_false : if (SIM_ENABLED = FALSE) generate + i_vio_0 : entity work.vio_0 + port map ( + clk => clk_in, +-- probe_in0 => fpga_revison_r, -- 32 + + probe_out0(0) => mode, -- 1 + probe_out1 => scale, -- 16 + probe_out2 => cmd_idx, -- 3 + probe_out3(0) => cmd_send, -- 1 + probe_out4(0) => dac_holdoff, -- 1 + + probe_out5 => vio_reserv1, -- 32 + probe_out6 => vio_dds_phase_inc_dwell_time, -- 32 + probe_out7 => vio_dds_phase_inc_step_size, -- 32 + probe_out8 => vio_idle_samples, -- 32 + probe_out9 => vio_dds_samples, -- 32 + probe_out10 => vio_phase_inc, -- 32 + probe_out11 => vio_phase_off, -- 32 + probe_out12 => vio_swap_sf -- 32 + ); + end generate sim_false; + + i_dds_cmd_gen : entity work.dds_cmd_gen + generic map ( + SIM_ENABLED => SIM_ENABLED + ) + port map ( + clk_in => clk_in, + cmd_idx_in => cmd_idx, + cmd_send_in => cmd_send, + + vio_reserv1_in => vio_reserv1, + vio_dds_phase_inc_dwell_time_in => vio_dds_phase_inc_dwell_time, + vio_dds_phase_inc_step_size_in => vio_dds_phase_inc_step_size, + vio_idle_samples_in => vio_idle_samples, + vio_dds_samples_in => vio_dds_samples, + vio_phase_inc_in => vio_phase_inc, + vio_phase_off_in => vio_phase_off, + vio_swap_sf_in => vio_swap_sf, + + fifo_rd_clk_in => m_axis_aclk_in, + fifo_rd_data_out => pipe_in_ch1_fifo_rd_data, + fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval, + fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden, + fifo_rd_empty_out => pipe_in_ch1_fifo_empty, + + rst_in => rst_in + ); + + sim_false1 : if (SIM_ENABLED = FALSE) generate + i_ila_4 : entity work.ila_4 + port map ( + clk => m_axis_aclk_in, + probe0 => pipe_in_ch1_fifo_rd_data, --32 + probe1(0) => pipe_in_ch1_fifo_rd_dval, --1 + probe2(0) => pipe_in_ch1_fifo_rden, --1 + probe3(0) => pipe_in_ch1_fifo_empty --1 + ); + end generate sim_false1; + + i_dds_pulse_2x_top : entity work.dds_pulse_2x_top + port map( + clk_in => m_axis_aclk_in, + rst_in => rst_in, + mode_in => mode, -- 0=single, 1=dual + scale_in => scale, + fifo1_data_in => pipe_in_ch1_fifo_rd_data, + fifo1_dval_in => pipe_in_ch1_fifo_rd_dval, + fifo1_empty_in => pipe_in_ch1_fifo_empty, + fifo1_rden_out => pipe_in_ch1_fifo_rden, + fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data, + fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval, + fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty, + fifo2_rden_out => pipe_in_ch2_fifo_rden, + holdoff_in => dac_holdoff, + overflow_out => open, + underflow_out => open, + i_max_abs_out => open, + q_max_abs_out => open, + data_out => dds_pulse_data, + dval_out => dds_pulse_dval + ); + + pulse_i <= dds_pulse_data(15 downto 0); + pulse_q <= dds_pulse_data(31 downto 16); + + + + + + process(m_axis_aclk_in) + begin + if (rising_edge(m_axis_aclk_in)) then + dds_pulse_dval_r <= dds_pulse_dval; + + if (dds_pulse_dval_r = '1' and dds_pulse_dval = '0') then + dds_pulse_data_cnt_r <= (others => '0'); + dds_pulse_data_cnt_r1 <= dds_pulse_data_cnt_r; + elsif (dds_pulse_dval = '1') then + dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1; + end if; + +-- if (dds_pulse_dval = '1') then +-- s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3); +-- +-- if (s_axis_keep_r = "0001") then +-- dds_pulse_data_r(31 downto 0) <= dds_pulse_data; +-- elsif (s_axis_keep_r = "0010") then +-- dds_pulse_data_r(63 downto 32) <= dds_pulse_data; +-- elsif (s_axis_keep_r = "0100") then +-- dds_pulse_data_r(95 downto 64) <= dds_pulse_data; +-- elsif (s_axis_keep_r = "1000") then +-- dds_pulse_data_r(127 downto 96) <= dds_pulse_data; +-- dds_pulse_dval_r <= '1'; +-- end if; +-- end if; + end if; + end process; + + pulse_data_word <= dds_pulse_data & dds_pulse_data & dds_pulse_data & dds_pulse_data; + + + sim_false2 : if (SIM_ENABLED = FALSE) generate + i_ila_3 : entity work.ila_3 + port map ( + clk => m_axis_aclk_in, + probe0 => dds_pulse_data(15 downto 0), + probe1 => dds_pulse_data(31 downto 16), + probe2(0) => dds_pulse_dval, + probe3(0) => s_axis_tready + ); + end generate sim_false2; + + i_fifo : entity work.axis_data_fifo_512x128 + port map ( + s_axis_aclk => m_axis_aclk_in, + s_axis_aresetn => reset_n, + + s_axis_tdata => pulse_data_word, + s_axis_tvalid => dds_pulse_dval, + s_axis_tready => s_axis_tready, + + m_axis_tdata => m_axis_tdata, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready_in + ); + + m_axis_tdata_out <= m_axis_tdata; + m_axis_tvalid_out <= m_axis_tvalid; + + sim_false3 : if (SIM_ENABLED = FALSE) generate + i_ila_2 : entity work.ila_0 + port map ( + clk => m_axis_aclk_in, + probe0 => m_axis_tdata(15 downto 0), + probe1 => m_axis_tdata(31 downto 16), + probe2 => m_axis_tdata(47 downto 32), + probe3 => m_axis_tdata(63 downto 48), + probe4 => m_axis_tdata(79 downto 64), + probe5 => m_axis_tdata(95 downto 80), + probe6 => m_axis_tdata(111 downto 96), + probe7 => m_axis_tdata(127 downto 112), + probe8(0) => m_axis_tvalid, + probe9(0) => m_axis_tready_in + ); + end generate sim_false3; + + sim_true : if (SIM_ENABLED = TRUE) generate + -- Stimulus process + stim_proc: process + begin + + wait for 200 ns; + wait for 200 ns; + wait for 200 ns; + wait until rising_edge(clk_in); + wait for 1 ns; + mode <= '0'; + scale <= x"8000"; + + wait for ok_clk_in_period*10; + wait until rising_edge(clk_in); +-- dac_holdoff <= '0'; + + -- WFM 0 + -- FREQUENCY SWEEP (UP-SWEEP) + wait until rising_edge(clk_in); + cmd_idx <= "000"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + + -- WFM 1 + -- FREQUENCY SWEEP (DOWN-SWEEP) + wait until rising_edge(clk_in); + cmd_idx <= "000"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + + + -- WFM 2 + -- CW TONE + wait until rising_edge(clk_in); + cmd_idx <= "000"; + cmd_send <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + cmd_send <= '0'; + wait for 100 ns; + +-- -- WFM 3 +-- -- FREQUENCY SWEEP (DOWN-SWEEP) +-- wait until rising_edge(clk_in); +-- cmd_idx <= "011"; +-- cmd_send <= '1'; +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- wait until rising_edge(clk_in); +-- cmd_send <= '0'; +-- wait for 100 ns; +-- wait for 100 ns; + -- CW TONE +-- vio_reserv1 <= x"00000000"; --RESERVED1 +-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME +-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) +-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES +-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us) 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All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1, + parameter SHARED_DEVCLK = 0, + parameter JESD_MODE = "8B10B" +) ( + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire ref_clk; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk_internal; + wire rx_device_clk; + + wire dac_rst; + wire tx_device_clk_div4; + + wire [127:0] s_axis_tx_data_0_tdata; + wire s_axis_tx_data_0_tready; + wire s_axis_tx_data_0_tvalid; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + IBUFDS i_ibufds_syncin_0 ( + .I (fpga_syncin_0_p), + .IB (fpga_syncin_0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout_0 ( + .I (rx_syncout[0]), + .O (fpga_syncout_0_p), + .OB (fpga_syncout_0_n)); + + BUFG i_tx_device_clk ( + .I (clkin6), + .O (tx_device_clk)); + + +BUFGCE_DIV #( +.BUFGCE_DIVIDE(4), // 1-8 +// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins +.IS_CE_INVERTED(1'b0), // Optional inversion for CE +.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR +.IS_I_INVERTED(1'b0) // Optional inversion for I +) +BUFGCE_DIV_inst ( +.O(tx_device_clk_div4), // 1-bit output: Buffer +.CE(1'b1), // 1-bit input: Buffer enable +.CLR(1'b0), // 1-bit input: Asynchronous clear +.I(clkin6) // 1-bit input: Buffer +); +// E + + + + + + + + + + BUFG i_rx_device_clk ( + .I (clkin10), + .O (rx_device_clk_internal)); + + assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; + + // spi + + assign spi0_csb = spi0_csn[0]; + assign spi1_csb = spi1_csn[0]; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi ( + .spi_csn (spi1_csn[0]), + .spi_clk (spi1_sclk), + .spi_mosi (spi1_mosi), + .spi_miso (spi1_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + // gpios + + ad_iobuf #( + .DATA_WIDTH(12) + ) i_iobuf ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({hmc_gpio1, // 43 + gpio[10:0]})); // 42-32 + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + assign txen[0] = gpio_o[58]; + assign txen[1] = gpio_o[59]; + + generate + if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[7:0]; + + // Unused GPIOs + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[94:64] = gpio_o[94:64]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[7:0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_sclk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_sclk), + // FMC HPC + .rx_data_0_n (rx_data_n_loc[0]), + .rx_data_0_p (rx_data_p_loc[0]), + .rx_data_1_n (rx_data_n_loc[1]), + .rx_data_1_p (rx_data_p_loc[1]), + .rx_data_2_n (rx_data_n_loc[2]), + .rx_data_2_p (rx_data_p_loc[2]), + .rx_data_3_n (rx_data_n_loc[3]), + .rx_data_3_p (rx_data_p_loc[3]), + .rx_data_4_n (rx_data_n_loc[4]), + .rx_data_4_p (rx_data_p_loc[4]), + .rx_data_5_n (rx_data_n_loc[5]), + .rx_data_5_p (rx_data_p_loc[5]), + .rx_data_6_n (rx_data_n_loc[6]), + .rx_data_6_p (rx_data_p_loc[6]), + .rx_data_7_n (rx_data_n_loc[7]), + .rx_data_7_p (rx_data_p_loc[7]), + .tx_data_0_n (tx_data_n_loc[0]), + .tx_data_0_p (tx_data_p_loc[0]), + .tx_data_1_n (tx_data_n_loc[1]), + .tx_data_1_p (tx_data_p_loc[1]), + .tx_data_2_n (tx_data_n_loc[2]), + .tx_data_2_p (tx_data_p_loc[2]), + .tx_data_3_n (tx_data_n_loc[3]), + .tx_data_3_p (tx_data_p_loc[3]), + .tx_data_4_n (tx_data_n_loc[4]), + .tx_data_4_p (tx_data_p_loc[4]), + .tx_data_5_n (tx_data_n_loc[5]), + .tx_data_5_p (tx_data_p_loc[5]), + .tx_data_6_n (tx_data_n_loc[6]), + .tx_data_6_p (tx_data_p_loc[6]), + .tx_data_7_n (tx_data_n_loc[7]), + .tx_data_7_p (tx_data_p_loc[7]), + .ref_clk_q0 (ref_clk), + .ref_clk_q1 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), +// .dac_rst_out (dac_rst), + +// .s_axis_tx_data_0_tdata (s_axis_tx_data_0_tdata), +// .s_axis_tx_data_0_tvalid (s_axis_tx_data_0_tvalid), +// .s_axis_tx_data_0_tready (s_axis_tx_data_0_tready), + + .clk_in_1 (tx_device_clk_div4), + .rx_sync_0 (rx_syncout), + .tx_sync_0 (tx_syncin), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref)); + + assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0]; + assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0]; + + assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; +/* + dds_pulse_wrapper i_dds_pulse_wrapper ( + .clk_in (tx_device_clk_div4), + + .m_axis_aclk_in (tx_device_clk), + + .m_axis_tdata_out (s_axis_tx_data_0_tdata), + .m_axis_tvalid_out (s_axis_tx_data_0_tvalid), + .m_axis_tready_in (s_axis_tx_data_0_tready), + + .rst_in (dac_rst) + ); + +*/ + +endmodule diff --git a/source/xgui/dds_pulse_wrapper_v1_0.tcl b/source/xgui/dds_pulse_wrapper_v1_0.tcl new file mode 100644 index 0000000..08e2bd4 --- /dev/null +++ b/source/xgui/dds_pulse_wrapper_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "SIM_ENABLED" -parent ${Page_0} + + ipgui::add_param $IPINST -name "FPGA_REVISION_DATE" + +} + +proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } { + # Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } { + # Procedure called to validate FPGA_REVISION_DATE + return true +} + +proc update_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } { + # Procedure called to update SIM_ENABLED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } { + # Procedure called to validate SIM_ENABLED + return true +} + + +proc update_MODELPARAM_VALUE.SIM_ENABLED { MODELPARAM_VALUE.SIM_ENABLED PARAM_VALUE.SIM_ENABLED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIM_ENABLED}] ${MODELPARAM_VALUE.SIM_ENABLED} +} + +proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE} +} + diff --git a/system_bd.tcl b/system_bd.tcl new file mode 100644 index 0000000..6b47843 --- /dev/null +++ b/system_bd.tcl @@ -0,0 +1,74 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 64*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 64*1024] + + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0 + +source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Parameters for 15.5Gpbs lane rate + +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868 +ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3 + +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF + +# Overwrite parameter for lower lane rates which use CPLL +if {$ad_project_params(RX_LANE_RATE) < 12} { + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x0 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x200 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0xFD + + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +} + diff --git a/system_constr.xdc b/system_constr.xdc new file mode 100644 index 0000000..7985529 --- /dev/null +++ b/system_constr.xdc @@ -0,0 +1,93 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## mxfe +# + +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229 +set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229 +set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N +set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P +set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N +set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P +set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N +set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P +set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N +set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P +set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N +set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P +set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N +set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P +set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N +set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P +set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N +set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P +set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N +set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P +set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N +set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P +set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N +set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P +set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N +set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P +set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N +set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P +set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N +set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P +set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N +set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P +set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N +set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P +set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66 +set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66 +set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66 + diff --git a/system_project.tcl b/system_project.tcl new file mode 100644 index 0000000..cdaae69 --- /dev/null +++ b/system_project.tcl @@ -0,0 +1,68 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported +# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices +# + +adi_project ad9081_fmca_ebz_zcu102 0 [list \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + RX_TPL_WIDTH [get_env_param RX_TPL_WIDTH {} ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + TX_TPL_WIDTH [get_env_param TX_TPL_WIDTH {} ] \ + TDD_SUPPORT [get_env_param TDD_SUPPORT 0 ] \ + SHARED_DEVCLK [get_env_param SHARED_DEVCLK 0 ] \ + TDD_CHANNEL_CNT [get_env_param TDD_CHANNEL_CNT 2 ] \ + TDD_SYNC_WIDTH [get_env_param TDD_SYNC_WIDTH 32 ] \ + TDD_SYNC_INT [get_env_param TDD_SYNC_INT 1 ] \ + TDD_SYNC_EXT [get_env_param TDD_SYNC_EXT 0 ] \ + TDD_SYNC_EXT_CDC [get_env_param TDD_SYNC_EXT_CDC 0 ] \ +] + +adi_project_files ad9081_fmca_ebz_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../../../library/common/ad_3w_spi.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + + +adi_project_run ad9081_fmca_ebz_zcu102 + diff --git a/system_top.v b/system_top.v new file mode 100644 index 0000000..51a7124 --- /dev/null +++ b/system_top.v @@ -0,0 +1,305 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1, + parameter SHARED_DEVCLK = 0, + parameter JESD_MODE = "8B10B" +) ( + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire ref_clk; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk_internal; + wire rx_device_clk; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + IBUFDS i_ibufds_syncin_0 ( + .I (fpga_syncin_0_p), + .IB (fpga_syncin_0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout_0 ( + .I (rx_syncout[0]), + .O (fpga_syncout_0_p), + .OB (fpga_syncout_0_n)); + + BUFG i_tx_device_clk ( + .I (clkin6), + .O (tx_device_clk)); + + BUFG i_rx_device_clk ( + .I (clkin10), + .O (rx_device_clk_internal)); + + assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; + + // spi + + assign spi0_csb = spi0_csn[0]; + assign spi1_csb = spi1_csn[0]; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi ( + .spi_csn (spi1_csn[0]), + .spi_clk (spi1_sclk), + .spi_mosi (spi1_mosi), + .spi_miso (spi1_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + // gpios + + ad_iobuf #( + .DATA_WIDTH(12) + ) i_iobuf ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({hmc_gpio1, // 43 + gpio[10:0]})); // 42-32 + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + assign txen[0] = gpio_o[58]; + assign txen[1] = gpio_o[59]; + + generate + if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[7:0]; + + // Unused GPIOs + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[94:64] = gpio_o[94:64]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[7:0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_sclk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_sclk), + // FMC HPC + .rx_data_0_n (rx_data_n_loc[0]), + .rx_data_0_p (rx_data_p_loc[0]), + .rx_data_1_n (rx_data_n_loc[1]), + .rx_data_1_p (rx_data_p_loc[1]), + .rx_data_2_n (rx_data_n_loc[2]), + .rx_data_2_p (rx_data_p_loc[2]), + .rx_data_3_n (rx_data_n_loc[3]), + .rx_data_3_p (rx_data_p_loc[3]), + .rx_data_4_n (rx_data_n_loc[4]), + .rx_data_4_p (rx_data_p_loc[4]), + .rx_data_5_n (rx_data_n_loc[5]), + .rx_data_5_p (rx_data_p_loc[5]), + .rx_data_6_n (rx_data_n_loc[6]), + .rx_data_6_p (rx_data_p_loc[6]), + .rx_data_7_n (rx_data_n_loc[7]), + .rx_data_7_p (rx_data_p_loc[7]), + .tx_data_0_n (tx_data_n_loc[0]), + .tx_data_0_p (tx_data_p_loc[0]), + .tx_data_1_n (tx_data_n_loc[1]), + .tx_data_1_p (tx_data_p_loc[1]), + .tx_data_2_n (tx_data_n_loc[2]), + .tx_data_2_p (tx_data_p_loc[2]), + .tx_data_3_n (tx_data_n_loc[3]), + .tx_data_3_p (tx_data_p_loc[3]), + .tx_data_4_n (tx_data_n_loc[4]), + .tx_data_4_p (tx_data_p_loc[4]), + .tx_data_5_n (tx_data_n_loc[5]), + .tx_data_5_p (tx_data_p_loc[5]), + .tx_data_6_n (tx_data_n_loc[6]), + .tx_data_6_p (tx_data_p_loc[6]), + .tx_data_7_n (tx_data_n_loc[7]), + .tx_data_7_p (tx_data_p_loc[7]), + .ref_clk_q0 (ref_clk), + .ref_clk_q1 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_sync_0 (rx_syncout), + .tx_sync_0 (tx_syncin), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref)); + + assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0]; + assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0]; + + assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + +endmodule diff --git a/timing_constr.xdc b/timing_constr.xdc new file mode 100644 index 0000000..0285b04 --- /dev/null +++ b/timing_constr.xdc @@ -0,0 +1,33 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Primary clock definitions +create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p] + +# device clock +create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p] +create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p] + + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks tx_device_clk] \ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref2_*}] + +# For transceiver output clocks use reference clock divided by two +# This will help autoderive the clocks correcly +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]