346 lines
13 KiB
VHDL
346 lines
13 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity dds_pulse_wrapper is
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generic (
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SIM_ENABLED : boolean := FALSE;
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FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0916_2023"
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);
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port(
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clk_in : in std_logic;
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m_axis_aclk_in : in std_logic;
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m_axis_tdata_out : out std_logic_vector(127 downto 0);
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m_axis_tvalid_out : out std_logic;
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m_axis_tready_in : in std_logic;
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rst_in : in std_logic
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);
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end entity dds_pulse_wrapper;
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architecture imp of dds_pulse_wrapper is
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constant ok_clk_in_period : time := 10 ns;
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signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
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attribute keep : string;
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attribute keep of fpga_revision_date_r : signal is "true";
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signal reset_n : std_logic;
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signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001";
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signal s_axis_tready : std_logic;
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signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0');
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signal dds_pulse_dval_r : std_logic := '0';
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signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0');
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signal dds_pulse_data_cnt_r1 : std_logic_vector(15 downto 0) := (others => '0');
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signal cmd_idx : std_logic_vector( 2 downto 0) := "000";
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signal cmd_send : std_logic := '0';
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signal mode : std_logic := '0';
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signal scale : std_logic_vector(15 downto 0) := x"0000";
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signal dac_holdoff : std_logic := '1';
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signal dds_pulse_dval : std_logic;
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signal dds_pulse_data : std_logic_vector(31 downto 0);
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signal pulse_i : std_logic_vector(15 downto 0);
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signal pulse_q : std_logic_vector(15 downto 0);
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signal pipe_in_ch1_fifo_rden : std_logic;
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signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
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signal pipe_in_ch1_fifo_rd_dval : std_logic;
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signal pipe_in_ch1_fifo_empty : std_logic;
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signal pipe_in_ch2_fifo_rden : std_logic;
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signal m_axis_tdata : std_logic_vector(127 downto 0);
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signal m_axis_tvalid : std_logic;
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signal pulse_data_word : std_logic_vector(127 downto 0);
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signal vio_reserv1 : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_idle_samples : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_dds_samples : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_phase_inc : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_phase_off : std_logic_vector(31 downto 0) := (others => '0');
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signal vio_swap_sf : std_logic_vector(31 downto 0) := (others => '0');
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begin
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reset_n <= not rst_in;
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-- process(clk_in)
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-- begin
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-- if (rising_edge(clk_in)) then
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-- fpga_revision_date_r <= FPGA_REVISION_DATE;
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-- end if;
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-- end process;
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sim_false : if (SIM_ENABLED = FALSE) generate
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i_vio_0 : entity work.vio_0
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port map (
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clk => clk_in,
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-- probe_in0 => fpga_revison_r, -- 32
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probe_out0(0) => mode, -- 1
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probe_out1 => scale, -- 16
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probe_out2 => cmd_idx, -- 3
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probe_out3(0) => cmd_send, -- 1
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probe_out4(0) => dac_holdoff, -- 1
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probe_out5 => vio_reserv1, -- 32
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probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
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probe_out7 => vio_dds_phase_inc_step_size, -- 32
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probe_out8 => vio_idle_samples, -- 32
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probe_out9 => vio_dds_samples, -- 32
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probe_out10 => vio_phase_inc, -- 32
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probe_out11 => vio_phase_off, -- 32
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probe_out12 => vio_swap_sf -- 32
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);
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end generate sim_false;
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i_dds_cmd_gen : entity work.dds_cmd_gen
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generic map (
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SIM_ENABLED => SIM_ENABLED
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)
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port map (
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clk_in => clk_in,
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cmd_idx_in => cmd_idx,
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cmd_send_in => cmd_send,
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vio_reserv1_in => vio_reserv1,
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vio_dds_phase_inc_dwell_time_in => vio_dds_phase_inc_dwell_time,
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vio_dds_phase_inc_step_size_in => vio_dds_phase_inc_step_size,
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vio_idle_samples_in => vio_idle_samples,
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vio_dds_samples_in => vio_dds_samples,
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vio_phase_inc_in => vio_phase_inc,
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vio_phase_off_in => vio_phase_off,
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vio_swap_sf_in => vio_swap_sf,
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fifo_rd_clk_in => m_axis_aclk_in,
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fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
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fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
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fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
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fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
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rst_in => rst_in
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);
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sim_false1 : if (SIM_ENABLED = FALSE) generate
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i_ila_4 : entity work.ila_4
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port map (
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clk => m_axis_aclk_in,
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probe0 => pipe_in_ch1_fifo_rd_data, --32
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probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
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probe2(0) => pipe_in_ch1_fifo_rden, --1
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probe3(0) => pipe_in_ch1_fifo_empty --1
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);
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end generate sim_false1;
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i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
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port map(
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clk_in => m_axis_aclk_in,
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rst_in => rst_in,
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mode_in => mode, -- 0=single, 1=dual
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scale_in => scale,
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fifo1_data_in => pipe_in_ch1_fifo_rd_data,
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fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
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fifo1_empty_in => pipe_in_ch1_fifo_empty,
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fifo1_rden_out => pipe_in_ch1_fifo_rden,
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fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
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fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
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fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
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fifo2_rden_out => pipe_in_ch2_fifo_rden,
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holdoff_in => dac_holdoff,
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overflow_out => open,
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underflow_out => open,
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i_max_abs_out => open,
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q_max_abs_out => open,
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data_out => dds_pulse_data,
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dval_out => dds_pulse_dval
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);
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pulse_i <= dds_pulse_data(15 downto 0);
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pulse_q <= dds_pulse_data(31 downto 16);
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process(m_axis_aclk_in)
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begin
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if (rising_edge(m_axis_aclk_in)) then
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dds_pulse_dval_r <= dds_pulse_dval;
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if (dds_pulse_dval_r = '1' and dds_pulse_dval = '0') then
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dds_pulse_data_cnt_r <= (others => '0');
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dds_pulse_data_cnt_r1 <= dds_pulse_data_cnt_r;
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elsif (dds_pulse_dval = '1') then
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dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
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end if;
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-- if (dds_pulse_dval = '1') then
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-- s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3);
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--
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-- if (s_axis_keep_r = "0001") then
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-- dds_pulse_data_r(31 downto 0) <= dds_pulse_data;
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-- elsif (s_axis_keep_r = "0010") then
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-- dds_pulse_data_r(63 downto 32) <= dds_pulse_data;
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-- elsif (s_axis_keep_r = "0100") then
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-- dds_pulse_data_r(95 downto 64) <= dds_pulse_data;
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-- elsif (s_axis_keep_r = "1000") then
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-- dds_pulse_data_r(127 downto 96) <= dds_pulse_data;
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-- dds_pulse_dval_r <= '1';
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-- end if;
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-- end if;
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end if;
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end process;
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pulse_data_word <= dds_pulse_data & dds_pulse_data & dds_pulse_data & dds_pulse_data;
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sim_false2 : if (SIM_ENABLED = FALSE) generate
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i_ila_3 : entity work.ila_3
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port map (
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clk => m_axis_aclk_in,
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probe0 => dds_pulse_data(15 downto 0),
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probe1 => dds_pulse_data(31 downto 16),
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probe2(0) => dds_pulse_dval,
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probe3(0) => s_axis_tready
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);
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end generate sim_false2;
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i_fifo : entity work.axis_data_fifo_512x128
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port map (
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s_axis_aclk => m_axis_aclk_in,
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s_axis_aresetn => reset_n,
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s_axis_tdata => pulse_data_word,
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s_axis_tvalid => dds_pulse_dval,
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s_axis_tready => s_axis_tready,
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m_axis_tdata => m_axis_tdata,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tready => m_axis_tready_in
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);
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m_axis_tdata_out <= m_axis_tdata;
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m_axis_tvalid_out <= m_axis_tvalid;
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sim_false3 : if (SIM_ENABLED = FALSE) generate
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i_ila_2 : entity work.ila_0
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port map (
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clk => m_axis_aclk_in,
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probe0 => m_axis_tdata(15 downto 0),
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probe1 => m_axis_tdata(31 downto 16),
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probe2 => m_axis_tdata(47 downto 32),
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probe3 => m_axis_tdata(63 downto 48),
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probe4 => m_axis_tdata(79 downto 64),
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probe5 => m_axis_tdata(95 downto 80),
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probe6 => m_axis_tdata(111 downto 96),
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probe7 => m_axis_tdata(127 downto 112),
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probe8(0) => m_axis_tvalid,
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probe9(0) => m_axis_tready_in
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);
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end generate sim_false3;
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sim_true : if (SIM_ENABLED = TRUE) generate
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-- Stimulus process
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stim_proc: process
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begin
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wait for 200 ns;
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wait for 200 ns;
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wait for 200 ns;
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wait until rising_edge(clk_in);
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wait for 1 ns;
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mode <= '0';
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scale <= x"8000";
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wait for ok_clk_in_period*10;
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wait until rising_edge(clk_in);
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-- dac_holdoff <= '0';
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-- WFM 0
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-- FREQUENCY SWEEP (UP-SWEEP)
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wait until rising_edge(clk_in);
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cmd_idx <= "000";
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cmd_send <= '1';
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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cmd_send <= '0';
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wait for 100 ns;
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-- WFM 1
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-- FREQUENCY SWEEP (DOWN-SWEEP)
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wait until rising_edge(clk_in);
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cmd_idx <= "000";
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cmd_send <= '1';
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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cmd_send <= '0';
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wait for 100 ns;
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-- WFM 2
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-- CW TONE
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wait until rising_edge(clk_in);
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cmd_idx <= "000";
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cmd_send <= '1';
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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wait until rising_edge(clk_in);
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cmd_send <= '0';
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wait for 100 ns;
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-- -- WFM 3
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-- -- FREQUENCY SWEEP (DOWN-SWEEP)
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-- wait until rising_edge(clk_in);
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-- cmd_idx <= "011";
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-- cmd_send <= '1';
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- cmd_send <= '0';
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-- wait for 100 ns;
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-- wait for 100 ns;
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-- CW TONE
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-- vio_reserv1 <= x"00000000"; --RESERVED1
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-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
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-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
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-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
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-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
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-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
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-- vio_phase_off <= x"00000000"; --PHASE_OFF
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-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- cmd_idx <= "100";
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-- cmd_send <= '1';
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- wait until rising_edge(clk_in);
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-- cmd_send <= '0';
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-- wait for 100 ns;
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wait for 5 us;
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dac_holdoff <= '0';
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wait;
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end process;
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end generate sim_true;
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end architecture imp; |