2986 lines
165 KiB
Tcl
2986 lines
165 KiB
Tcl
#*****************************************************************************************
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# Vivado (TM) v2023.2 (64-bit)
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#
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# create_proj.tcl: Tcl script for re-creating project 'ad9081_fmca_ebz_zcu102'
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#
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# Generated by Vivado on Thu Apr 24 21:11:47 EDT 2025
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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#*****************************************************************************************
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# NOTE: In order to use this script for source control purposes, please make sure that the
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# following files are added to the source control system:-
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#
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# 1. This project restoration tcl script (create_proj.tcl) that was generated.
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#
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/system_top.v"
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# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/system_constr.xdc"
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# "/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102_orig/timing_constr.xdc"
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# "/home/nsantana/adi/hdl/library/common/ad_3w_spi.v"
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# "/home/nsantana/adi/hdl/library/common/ad_iobuf.v"
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# "/home/nsantana/adi/hdl/projects/common/zcu102/zcu102_system_constr.xdc"
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#
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#*****************************************************************************************
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# Check file required for this script exists
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proc checkRequiredFiles { origin_dir} {
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set status true
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set files [list \
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"[file normalize "$origin_dir/system_top.v"]"\
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"[file normalize "$origin_dir/system_constr.xdc"]"\
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"[file normalize "$origin_dir/timing_constr.xdc"]"\
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]
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foreach ifile $files {
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if { ![file isfile $ifile] } {
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puts " Could not find local file $ifile "
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set status false
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}
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}
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set files [list \
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"[file normalize "$origin_dir/../../../library/common/ad_3w_spi.v"]"\
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"[file normalize "$origin_dir/../../../library/common/ad_iobuf.v"]"\
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"[file normalize "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc"]"\
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]
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foreach ifile $files {
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if { ![file isfile $ifile] } {
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puts " Could not find remote file $ifile "
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set status false
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}
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}
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set paths [list \
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"[file normalize "$origin_dir/[file normalize "$origin_dir/../../../library"]"]"\
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]
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foreach ipath $paths {
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if { ![file isdirectory $ipath] } {
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puts " Could not access $ipath "
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set status false
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}
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}
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return $status
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}
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir "."
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::origin_dir_loc] } {
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set origin_dir $::origin_dir_loc
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}
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# Set the project name
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set _xil_proj_name_ "ad9081_fmca_ebz_zcu102"
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# Use project name variable, if specified in the tcl shell
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if { [info exists ::user_project_name] } {
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set _xil_proj_name_ $::user_project_name
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}
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variable script_file
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set script_file "create_proj.tcl"
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# Help information for this script
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proc print_help {} {
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variable script_file
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puts "\nDescription:"
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puts "Recreate a Vivado project from this script. The created project will be"
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puts "functionally equivalent to the original project for which this script was"
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puts "generated. The script contains commands for creating a project, filesets,"
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puts "runs, adding/importing sources and setting properties on various objects.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file -tclargs \[--origin_dir <path>\]"
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puts "$script_file -tclargs \[--project_name <name>\]"
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puts "$script_file -tclargs \[--help\]\n"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
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puts " origin_dir path value is \".\", otherwise, the value"
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puts " that was set with the \"-paths_relative_to\" switch"
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puts " when this script was generated.\n"
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puts "\[--project_name <name>\] Create project with the specified name. Default"
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puts " name is the name of the project from where this"
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puts " script was generated.\n"
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puts "\[--help\] Print help information for this script"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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if { $::argc > 0 } {
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for {set i 0} {$i < $::argc} {incr i} {
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set option [string trim [lindex $::argv $i]]
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switch -regexp -- $option {
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"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
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"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
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"--help" { print_help }
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default {
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if { [regexp {^-} $option] } {
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puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
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return 1
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}
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}
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}
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}
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}
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize "$origin_dir/"]"
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# Check for paths and files needed for project creation
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set validate_required 0
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if { $validate_required } {
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if { [checkRequiredFiles $origin_dir] } {
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puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
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} else {
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puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
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return
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}
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}
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# Create project
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create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu9eg-ffvb1156-2-e
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Reconstruct message rules
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {1} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {10} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {11} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {12} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {13} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {14} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {15} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {16} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {17} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {18} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {19} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {2} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {20} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {21} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {22} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {23} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {24} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {25} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {26} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {27} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {28} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {3} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {4} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {5} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {6} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {7} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2
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# Set project properties
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set obj [current_project]
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set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.4" -objects $obj
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set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
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set_property -name "enable_resource_estimation" -value "0" -objects $obj
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set_property -name "enable_vhdl_2008" -value "1" -objects $obj
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set_property -name "feature_set" -value "FeatureSet_Classic" -objects $obj
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set_property -name "ip_cache_permissions" -value "read write" -objects $obj
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set_property -name "ip_output_repo" -value "/home/nsantana/adi/hdl/ipcache" -objects $obj
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set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
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set_property -name "platform.board_id" -value "zcu102" -objects $obj
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set_property -name "revised_directory_structure" -value "1" -objects $obj
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set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
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set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
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set_property -name "simulator_language" -value "Mixed" -objects $obj
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set_property -name "sim_compile_state" -value "1" -objects $obj
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set_property -name "xpm_libraries" -value "XPM_FIFO XPM_MEMORY" -objects $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set IP repository paths
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set obj [get_filesets sources_1]
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if { $obj != {} } {
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set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../library"]" $obj
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# Rebuild user ip_repo's index before adding any source files
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update_ip_catalog -rebuild
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}
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "${origin_dir}/../../../library/common/ad_3w_spi.v"] \
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[file normalize "${origin_dir}/../../../library/common/ad_iobuf.v"] \
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]
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add_files -norecurse -fileset $obj $files
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# Import local files from the original project
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set files [list \
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[file normalize "${origin_dir}/system_top.v" ]\
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]
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set imported_files ""
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foreach f $files {
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lappend imported_files [import_files -fileset sources_1 $f]
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}
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# Set 'sources_1' fileset file properties for remote files
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# None
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# Set 'sources_1' fileset file properties for local files
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# None
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
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set_property -name "generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj
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set_property -name "top" -value "system_top" -objects $obj
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set_property -name "top_auto_set" -value "0" -objects $obj
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set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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# Set 'constrs_1' fileset object
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set obj [get_filesets constrs_1]
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$origin_dir/system_constr.xdc"]"
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set file_imported [import_files -fileset constrs_1 [list $file]]
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set file "zcu102_orig/system_constr.xdc"
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property -name "file_type" -value "XDC" -objects $file_obj
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$origin_dir/timing_constr.xdc"]"
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set file_imported [import_files -fileset constrs_1 [list $file]]
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set file "zcu102_orig/timing_constr.xdc"
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property -name "file_type" -value "XDC" -objects $file_obj
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc"]"
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set file_added [add_files -norecurse -fileset $obj [list $file]]
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set file "$origin_dir/../../common/zcu102/zcu102_system_constr.xdc"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property -name "file_type" -value "XDC" -objects $file_obj
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# Set 'constrs_1' fileset properties
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set obj [get_filesets constrs_1]
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# Create 'sim_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sim_1] ""]} {
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create_fileset -simset sim_1
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}
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# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
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# Empty (no sources present)
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# Set 'sim_1' fileset properties
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set obj [get_filesets sim_1]
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set_property -name "top" -value "system_top" -objects $obj
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set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
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# Set 'utils_1' fileset object
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set obj [get_filesets utils_1]
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# Empty (no sources present)
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# Set 'utils_1' fileset properties
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set obj [get_filesets utils_1]
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# Adding sources referenced in BDs, if not already added
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# Proc to create BD system
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proc cr_bd_system { parentCell } {
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# CHANGE DESIGN NAME HERE
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set design_name system
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common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:zynq_ultra_ps_e:3.5\
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xilinx.com:ip:proc_sys_reset:5.0\
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xilinx.com:ip:xlconcat:2.1\
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xilinx.com:ip:xlconstant:1.1\
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analog.com:user:axi_sysid:1.0\
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analog.com:user:sysid_rom:1.0\
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xilinx.com:ip:smartconnect:1.0\
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analog.com:user:util_adxcvr:1.0\
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analog.com:user:axi_adxcvr:1.0\
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analog.com:user:util_cpack2:1.0\
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analog.com:user:axi_dmac:1.0\
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analog.com:user:util_upack2:1.0\
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xilinx.com:ip:util_vector_logic:2.0\
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xilinx.com:ip:util_reduced_logic:2.0\
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analog.com:user:axi_jesd204_rx:1.0\
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analog.com:user:jesd204_rx:1.0\
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analog.com:user:ad_ip_jesd204_tpl_adc:1.0\
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xilinx.com:ip:xlslice:1.0\
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analog.com:user:data_offload:1.0\
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analog.com:user:util_do_ram:1.0\
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analog.com:user:axi_jesd204_tx:1.0\
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analog.com:user:jesd204_tx:1.0\
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analog.com:user:ad_ip_jesd204_tpl_dac:1.0\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
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return 3
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}
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# Hierarchical cell: mxfe_tx_data_offload
|
|
proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } {
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|
|
variable script_folder
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|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_CYCLIC_EN {true} \
|
|
CONFIG.DST_DATA_WIDTH {128} \
|
|
CONFIG.MEM_SIZE_LOG2 {20} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {128} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {1} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {128} \
|
|
CONFIG.LENGTH_WIDTH {20} \
|
|
CONFIG.SRC_DATA_WIDTH {128} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: tx_mxfe_tpl_core
|
|
proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I dac_dunf
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_0
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_1
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_2
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_3
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_3
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_4
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_4
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_4
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_5
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_5
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_5
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_6
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_6
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_6
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_7
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_7
|
|
create_bd_pin -dir I -from 15 -to 0 dac_data_7
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O dac_sync_manual_req_out
|
|
create_bd_pin -dir I dac_sync_manual_req_in
|
|
create_bd_pin -dir O dac_rst
|
|
|
|
# Create instance: dac_tpl_core, and set properties
|
|
set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.IQCORRECTION_DISABLE {0} \
|
|
CONFIG.NUM_CHANNELS {8} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.OCTETS_PER_BEAT {4} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $dac_tpl_core
|
|
|
|
|
|
# Create instance: data_concat0, and set properties
|
|
set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ]
|
|
set_property CONFIG.NUM_PORTS {8} $data_concat0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create instance: enable_slice_4, and set properties
|
|
set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {4} \
|
|
CONFIG.DIN_TO {4} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_4
|
|
|
|
|
|
# Create instance: valid_slice_4, and set properties
|
|
set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {4} \
|
|
CONFIG.DIN_TO {4} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_4
|
|
|
|
|
|
# Create instance: enable_slice_5, and set properties
|
|
set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {5} \
|
|
CONFIG.DIN_TO {5} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_5
|
|
|
|
|
|
# Create instance: valid_slice_5, and set properties
|
|
set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {5} \
|
|
CONFIG.DIN_TO {5} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_5
|
|
|
|
|
|
# Create instance: enable_slice_6, and set properties
|
|
set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {6} \
|
|
CONFIG.DIN_TO {6} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_6
|
|
|
|
|
|
# Create instance: valid_slice_6, and set properties
|
|
set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {6} \
|
|
CONFIG.DIN_TO {6} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_6
|
|
|
|
|
|
# Create instance: enable_slice_7, and set properties
|
|
set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {7} \
|
|
CONFIG.DIN_TO {7} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_7
|
|
|
|
|
|
# Create instance: valid_slice_7, and set properties
|
|
set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {7} \
|
|
CONFIG.DIN_TO {7} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_7
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins dac_tpl_core/link] [get_bd_intf_pins link]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0]
|
|
connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1]
|
|
connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2]
|
|
connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3]
|
|
connect_bd_net -net dac_data_4_1 [get_bd_pins dac_data_4] [get_bd_pins data_concat0/In4]
|
|
connect_bd_net -net dac_data_5_1 [get_bd_pins dac_data_5] [get_bd_pins data_concat0/In5]
|
|
connect_bd_net -net dac_data_6_1 [get_bd_pins dac_data_6] [get_bd_pins data_concat0/In6]
|
|
connect_bd_net -net dac_data_7_1 [get_bd_pins dac_data_7] [get_bd_pins data_concat0/In7]
|
|
connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf]
|
|
connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in]
|
|
connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_tpl_core/dac_rst] [get_bd_pins dac_rst]
|
|
connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] [get_bd_pins dac_sync_manual_req_out]
|
|
connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din]
|
|
connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din]
|
|
connect_bd_net -net data_concat0_dout [get_bd_pins data_concat0/dout] [get_bd_pins dac_tpl_core/dac_ddata]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins dac_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins dac_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins dac_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins dac_enable_3]
|
|
connect_bd_net -net enable_slice_4_Dout [get_bd_pins enable_slice_4/Dout] [get_bd_pins dac_enable_4]
|
|
connect_bd_net -net enable_slice_5_Dout [get_bd_pins enable_slice_5/Dout] [get_bd_pins dac_enable_5]
|
|
connect_bd_net -net enable_slice_6_Dout [get_bd_pins enable_slice_6/Dout] [get_bd_pins dac_enable_6]
|
|
connect_bd_net -net enable_slice_7_Dout [get_bd_pins enable_slice_7/Dout] [get_bd_pins dac_enable_7]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins dac_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins dac_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins dac_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins dac_valid_3]
|
|
connect_bd_net -net valid_slice_4_Dout [get_bd_pins valid_slice_4/Dout] [get_bd_pins dac_valid_4]
|
|
connect_bd_net -net valid_slice_5_Dout [get_bd_pins valid_slice_5/Dout] [get_bd_pins dac_valid_5]
|
|
connect_bd_net -net valid_slice_6_Dout [get_bd_pins valid_slice_6/Dout] [get_bd_pins dac_valid_6]
|
|
connect_bd_net -net valid_slice_7_Dout [get_bd_pins valid_slice_7/Dout] [get_bd_pins dac_valid_7]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_tx_jesd
|
|
proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir I -from 0 -to 0 sync
|
|
create_bd_pin -dir I sysref
|
|
|
|
# Create instance: tx_axi, and set properties
|
|
set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $tx_axi
|
|
|
|
|
|
# Create instance: tx, and set properties
|
|
set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {4} \
|
|
] $tx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi]
|
|
connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx_axi/tx_cfg] [get_bd_intf_pins tx/tx_cfg]
|
|
connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx_axi/tx_ctrl] [get_bd_intf_pins tx/tx_ctrl]
|
|
connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data]
|
|
connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event]
|
|
connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config]
|
|
connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx/tx_phy0] [get_bd_intf_pins tx_phy0]
|
|
connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx/tx_phy1] [get_bd_intf_pins tx_phy1]
|
|
connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx/tx_phy2] [get_bd_intf_pins tx_phy2]
|
|
connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx/tx_phy3] [get_bd_intf_pins tx_phy3]
|
|
connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx_axi/device_clk] [get_bd_pins tx/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx_axi/core_clk] [get_bd_pins tx/clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref]
|
|
connect_bd_net -net tx_axi_core_reset [get_bd_pins tx_axi/core_reset] [get_bd_pins tx/reset]
|
|
connect_bd_net -net tx_axi_device_reset [get_bd_pins tx_axi/device_reset] [get_bd_pins tx/device_reset]
|
|
connect_bd_net -net tx_axi_irq [get_bd_pins tx_axi/irq] [get_bd_pins irq]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: mxfe_rx_data_offload
|
|
proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {128} \
|
|
CONFIG.MEM_SIZE_LOG2 {20} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {128} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {0} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {128} \
|
|
CONFIG.LENGTH_WIDTH {20} \
|
|
CONFIG.SRC_DATA_WIDTH {128} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: rx_mxfe_tpl_core
|
|
proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -from 3 -to 0 link_sof
|
|
create_bd_pin -dir I link_valid
|
|
create_bd_pin -dir I -from 127 -to 0 link_data
|
|
create_bd_pin -dir I adc_dovf
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_0
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_1
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_2
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_3
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_3
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_4
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_4
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_4
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_5
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_5
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_5
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_6
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_6
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_6
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_7
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_7
|
|
create_bd_pin -dir O -from 15 -to 0 adc_data_7
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O adc_sync_manual_req_out
|
|
create_bd_pin -dir I adc_sync_manual_req_in
|
|
create_bd_pin -dir O adc_rst
|
|
|
|
# Create instance: adc_tpl_core, and set properties
|
|
set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.NUM_CHANNELS {8} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.OCTETS_PER_BEAT {4} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $adc_tpl_core
|
|
|
|
|
|
# Create instance: data_slice_0, and set properties
|
|
set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {15} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: data_slice_1, and set properties
|
|
set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {31} \
|
|
CONFIG.DIN_TO {16} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: data_slice_2, and set properties
|
|
set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {47} \
|
|
CONFIG.DIN_TO {32} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: data_slice_3, and set properties
|
|
set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {63} \
|
|
CONFIG.DIN_TO {48} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_3
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create instance: data_slice_4, and set properties
|
|
set data_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {79} \
|
|
CONFIG.DIN_TO {64} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_4
|
|
|
|
|
|
# Create instance: enable_slice_4, and set properties
|
|
set enable_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {4} \
|
|
CONFIG.DIN_TO {4} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_4
|
|
|
|
|
|
# Create instance: valid_slice_4, and set properties
|
|
set valid_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {4} \
|
|
CONFIG.DIN_TO {4} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_4
|
|
|
|
|
|
# Create instance: data_slice_5, and set properties
|
|
set data_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {95} \
|
|
CONFIG.DIN_TO {80} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_5
|
|
|
|
|
|
# Create instance: enable_slice_5, and set properties
|
|
set enable_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {5} \
|
|
CONFIG.DIN_TO {5} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_5
|
|
|
|
|
|
# Create instance: valid_slice_5, and set properties
|
|
set valid_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {5} \
|
|
CONFIG.DIN_TO {5} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_5
|
|
|
|
|
|
# Create instance: data_slice_6, and set properties
|
|
set data_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_6 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {111} \
|
|
CONFIG.DIN_TO {96} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_6
|
|
|
|
|
|
# Create instance: enable_slice_6, and set properties
|
|
set enable_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_6 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {6} \
|
|
CONFIG.DIN_TO {6} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_6
|
|
|
|
|
|
# Create instance: valid_slice_6, and set properties
|
|
set valid_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_6 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {6} \
|
|
CONFIG.DIN_TO {6} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_6
|
|
|
|
|
|
# Create instance: data_slice_7, and set properties
|
|
set data_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_7 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {127} \
|
|
CONFIG.DIN_TO {112} \
|
|
CONFIG.DIN_WIDTH {128} \
|
|
] $data_slice_7
|
|
|
|
|
|
# Create instance: enable_slice_7, and set properties
|
|
set enable_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_7 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {7} \
|
|
CONFIG.DIN_TO {7} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $enable_slice_7
|
|
|
|
|
|
# Create instance: valid_slice_7, and set properties
|
|
set valid_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_7 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {7} \
|
|
CONFIG.DIN_TO {7} \
|
|
CONFIG.DIN_WIDTH {8} \
|
|
] $valid_slice_7
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf]
|
|
connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in]
|
|
connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din] [get_bd_pins data_slice_4/Din] [get_bd_pins data_slice_5/Din] [get_bd_pins data_slice_6/Din] [get_bd_pins data_slice_7/Din]
|
|
connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_tpl_core/adc_rst] [get_bd_pins adc_rst]
|
|
connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] [get_bd_pins adc_sync_manual_req_out]
|
|
connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din] [get_bd_pins valid_slice_4/Din] [get_bd_pins valid_slice_5/Din] [get_bd_pins valid_slice_6/Din] [get_bd_pins valid_slice_7/Din]
|
|
connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din] [get_bd_pins enable_slice_4/Din] [get_bd_pins enable_slice_5/Din] [get_bd_pins enable_slice_6/Din] [get_bd_pins enable_slice_7/Din]
|
|
connect_bd_net -net data_slice_0_Dout [get_bd_pins data_slice_0/Dout] [get_bd_pins adc_data_0]
|
|
connect_bd_net -net data_slice_1_Dout [get_bd_pins data_slice_1/Dout] [get_bd_pins adc_data_1]
|
|
connect_bd_net -net data_slice_2_Dout [get_bd_pins data_slice_2/Dout] [get_bd_pins adc_data_2]
|
|
connect_bd_net -net data_slice_3_Dout [get_bd_pins data_slice_3/Dout] [get_bd_pins adc_data_3]
|
|
connect_bd_net -net data_slice_4_Dout [get_bd_pins data_slice_4/Dout] [get_bd_pins adc_data_4]
|
|
connect_bd_net -net data_slice_5_Dout [get_bd_pins data_slice_5/Dout] [get_bd_pins adc_data_5]
|
|
connect_bd_net -net data_slice_6_Dout [get_bd_pins data_slice_6/Dout] [get_bd_pins adc_data_6]
|
|
connect_bd_net -net data_slice_7_Dout [get_bd_pins data_slice_7/Dout] [get_bd_pins adc_data_7]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins adc_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins adc_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins adc_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins adc_enable_3]
|
|
connect_bd_net -net enable_slice_4_Dout [get_bd_pins enable_slice_4/Dout] [get_bd_pins adc_enable_4]
|
|
connect_bd_net -net enable_slice_5_Dout [get_bd_pins enable_slice_5/Dout] [get_bd_pins adc_enable_5]
|
|
connect_bd_net -net enable_slice_6_Dout [get_bd_pins enable_slice_6/Dout] [get_bd_pins adc_enable_6]
|
|
connect_bd_net -net enable_slice_7_Dout [get_bd_pins enable_slice_7/Dout] [get_bd_pins adc_enable_7]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk]
|
|
connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data]
|
|
connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof]
|
|
connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins adc_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins adc_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins adc_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins adc_valid_3]
|
|
connect_bd_net -net valid_slice_4_Dout [get_bd_pins valid_slice_4/Dout] [get_bd_pins adc_valid_4]
|
|
connect_bd_net -net valid_slice_5_Dout [get_bd_pins valid_slice_5/Dout] [get_bd_pins adc_valid_5]
|
|
connect_bd_net -net valid_slice_6_Dout [get_bd_pins valid_slice_6/Dout] [get_bd_pins adc_valid_6]
|
|
connect_bd_net -net valid_slice_7_Dout [get_bd_pins valid_slice_7/Dout] [get_bd_pins adc_valid_7]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_rx_jesd
|
|
proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir O -from 0 -to 0 sync
|
|
create_bd_pin -dir I sysref
|
|
create_bd_pin -dir O phy_en_char_align
|
|
create_bd_pin -dir O -from 3 -to 0 rx_eof
|
|
create_bd_pin -dir O -from 3 -to 0 rx_sof
|
|
create_bd_pin -dir O rx_data_tvalid
|
|
create_bd_pin -dir O -from 127 -to 0 rx_data_tdata
|
|
|
|
# Create instance: rx_axi, and set properties
|
|
set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $rx_axi
|
|
|
|
|
|
# Create instance: rx, and set properties
|
|
set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_INPUT_PIPELINE {1} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {4} \
|
|
] $rx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx_axi/rx_cfg] [get_bd_intf_pins rx/rx_cfg]
|
|
connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx/rx_phy0] [get_bd_intf_pins rx_phy0]
|
|
connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx/rx_phy1] [get_bd_intf_pins rx_phy1]
|
|
connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx/rx_phy2] [get_bd_intf_pins rx_phy2]
|
|
connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx/rx_phy3] [get_bd_intf_pins rx_phy3]
|
|
connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event]
|
|
connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config]
|
|
connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx_axi/device_clk] [get_bd_pins rx/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx_axi/core_clk] [get_bd_pins rx/clk]
|
|
connect_bd_net -net rx_axi_core_reset [get_bd_pins rx_axi/core_reset] [get_bd_pins rx/reset]
|
|
connect_bd_net -net rx_axi_device_reset [get_bd_pins rx_axi/device_reset] [get_bd_pins rx/device_reset]
|
|
connect_bd_net -net rx_axi_irq [get_bd_pins rx_axi/irq] [get_bd_pins irq]
|
|
connect_bd_net -net rx_phy_en_char_align [get_bd_pins rx/phy_en_char_align] [get_bd_pins phy_en_char_align]
|
|
connect_bd_net -net rx_rx_data [get_bd_pins rx/rx_data] [get_bd_pins rx_data_tdata]
|
|
connect_bd_net -net rx_rx_eof [get_bd_pins rx/rx_eof] [get_bd_pins rx_eof]
|
|
connect_bd_net -net rx_rx_sof [get_bd_pins rx/rx_sof] [get_bd_pins rx_sof]
|
|
connect_bd_net -net rx_rx_valid [get_bd_pins rx/rx_valid] [get_bd_pins rx_data_tvalid]
|
|
connect_bd_net -net rx_sync [get_bd_pins rx/sync] [get_bd_pins sync]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
|
|
# Create ports
|
|
set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ]
|
|
set spi0_sclk [ create_bd_port -dir O spi0_sclk ]
|
|
set spi0_mosi [ create_bd_port -dir O spi0_mosi ]
|
|
set spi0_miso [ create_bd_port -dir I spi0_miso ]
|
|
set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ]
|
|
set spi1_sclk [ create_bd_port -dir O spi1_sclk ]
|
|
set spi1_mosi [ create_bd_port -dir O spi1_mosi ]
|
|
set spi1_miso [ create_bd_port -dir I spi1_miso ]
|
|
set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ]
|
|
set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ]
|
|
set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ]
|
|
set rx_device_clk [ create_bd_port -dir I rx_device_clk ]
|
|
set tx_device_clk [ create_bd_port -dir I tx_device_clk ]
|
|
set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ]
|
|
set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ]
|
|
set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ]
|
|
set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ]
|
|
set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ]
|
|
set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ]
|
|
set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ]
|
|
set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ]
|
|
set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ]
|
|
set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ]
|
|
set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ]
|
|
set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ]
|
|
set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ]
|
|
set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ]
|
|
set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ]
|
|
set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ]
|
|
set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ]
|
|
set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ]
|
|
set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ]
|
|
set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ]
|
|
set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ]
|
|
set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ]
|
|
set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ]
|
|
set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ]
|
|
set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ]
|
|
set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ]
|
|
set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ]
|
|
set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ]
|
|
set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ]
|
|
set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ]
|
|
set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ]
|
|
set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ]
|
|
set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ]
|
|
set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ]
|
|
set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ]
|
|
set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ]
|
|
set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ]
|
|
set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ]
|
|
set ext_sync_in [ create_bd_port -dir I ext_sync_in ]
|
|
|
|
# Create instance: sys_ps8, and set properties
|
|
set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 sys_ps8 ]
|
|
set_property -dict [list \
|
|
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
|
|
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
|
|
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \
|
|
CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_13_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_22_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_23_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_26_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_38_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_43_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
|
|
SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\
|
|
GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
|
|
3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
|
|
CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
|
|
\
|
|
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
|
|
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
|
|
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
|
|
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
|
|
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
|
|
CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
|
|
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
|
|
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
|
|
CONFIG.PSU__DDRC__CL {15} \
|
|
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
|
|
CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
|
|
CONFIG.PSU__DDRC__CWL {14} \
|
|
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
|
|
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
|
|
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
|
|
CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
|
|
CONFIG.PSU__DDRC__ECC {Disabled} \
|
|
CONFIG.PSU__DDRC__FGRM {1X} \
|
|
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
|
|
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
|
|
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
|
|
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
|
|
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
|
|
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
|
|
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
|
|
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
|
|
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
|
|
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
|
|
CONFIG.PSU__DDRC__T_FAW {30.0} \
|
|
CONFIG.PSU__DDRC__T_RAS_MIN {33} \
|
|
CONFIG.PSU__DDRC__T_RC {47.06} \
|
|
CONFIG.PSU__DDRC__T_RCD {15} \
|
|
CONFIG.PSU__DDRC__T_RP {15} \
|
|
CONFIG.PSU__DDRC__VREF {1} \
|
|
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
|
|
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
|
|
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__DLL__ISUSED {1} \
|
|
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
|
|
CONFIG.PSU__DP__LANE_SEL {Single Lower} \
|
|
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
|
|
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
|
|
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
|
|
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
|
|
CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
|
|
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL2_ENABLE {1} \
|
|
CONFIG.PSU__GEM3_COHERENCY {0} \
|
|
CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__GEM__TSU__ENABLE {0} \
|
|
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
|
|
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
|
|
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \
|
|
CONFIG.PSU__GT__LINK_SPEED {HBR} \
|
|
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
|
|
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
|
|
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
|
|
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
|
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \
|
|
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
|
|
CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
|
|
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
|
|
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__EROM_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
|
|
CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
|
|
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
|
|
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
|
|
CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
|
|
CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \
|
|
CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \
|
|
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__PCIE__REVISION_ID {0x0} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK1_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK2_BUF {TRUE} \
|
|
CONFIG.PSU__PMU_COHERENCY {0} \
|
|
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
|
|
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
|
|
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPO0__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
|
|
CONFIG.PSU__PMU__GPO1__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
|
|
CONFIG.PSU__PMU__GPO2__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
|
|
CONFIG.PSU__PMU__GPO2__POLARITY {high} \
|
|
CONFIG.PSU__PMU__GPO3__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO3__IO {MIO 35} \
|
|
CONFIG.PSU__PMU__GPO3__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO4__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO4__IO {MIO 36} \
|
|
CONFIG.PSU__PMU__GPO4__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO5__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO5__IO {MIO 37} \
|
|
CONFIG.PSU__PMU__GPO5__POLARITY {low} \
|
|
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
|
|
CONFIG.PSU__PRESET_APPLIED {1} \
|
|
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
|
|
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
|
|
\
|
|
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \
|
|
CONFIG.PSU__QSPI_COHERENCY {0} \
|
|
CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
|
|
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
|
|
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
|
|
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
|
|
CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
|
|
CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SD1_COHERENCY {0} \
|
|
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \
|
|
CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \
|
|
CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \
|
|
CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
|
|
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \
|
|
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
|
|
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
|
|
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
|
|
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
|
|
CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \
|
|
CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \
|
|
CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
|
|
CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
|
|
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__UART0__BAUD_RATE {115200} \
|
|
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
|
|
CONFIG.PSU__UART1__BAUD_RATE {115200} \
|
|
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
|
|
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
|
|
CONFIG.PSU__USB0_COHERENCY {0} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
|
|
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
|
|
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
|
|
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
|
|
CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
|
|
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__USE__IRQ0 {1} \
|
|
CONFIG.PSU__USE__IRQ1 {1} \
|
|
CONFIG.PSU__USE__M_AXI_GP0 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP1 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP3 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP4 {1} \
|
|
] $sys_ps8
|
|
|
|
|
|
# Create instance: sys_rstgen, and set properties
|
|
set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen
|
|
|
|
|
|
# Create instance: sys_250m_rstgen, and set properties
|
|
set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen
|
|
|
|
|
|
# Create instance: sys_500m_rstgen, and set properties
|
|
set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen
|
|
|
|
|
|
# Create instance: spi0_csn_concat, and set properties
|
|
set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat
|
|
|
|
|
|
# Create instance: VCC_1, and set properties
|
|
set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {1} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $VCC_1
|
|
|
|
|
|
# Create instance: GND_1, and set properties
|
|
set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $GND_1
|
|
|
|
|
|
# Create instance: spi1_csn_concat, and set properties
|
|
set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat
|
|
|
|
|
|
# Create instance: axi_sysid_0, and set properties
|
|
set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ]
|
|
set_property CONFIG.ROM_ADDR_BITS {9} $axi_sysid_0
|
|
|
|
|
|
# Create instance: rom_sys_0, and set properties
|
|
set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.PATH_TO_FILE {/home/nsantana/adi/hdl/projects/ad9081_fmca_ebz/zcu102/mem_init_sys.txt} \
|
|
CONFIG.ROM_ADDR_BITS {9} \
|
|
] $rom_sys_0
|
|
|
|
|
|
# Create instance: axi_cpu_interconnect, and set properties
|
|
set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {11} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_cpu_interconnect
|
|
|
|
|
|
# Create instance: sys_concat_intc_0, and set properties
|
|
set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0
|
|
|
|
|
|
# Create instance: sys_concat_intc_1, and set properties
|
|
set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1
|
|
|
|
|
|
# Create instance: axi_hp0_interconnect, and set properties
|
|
set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp0_interconnect
|
|
|
|
|
|
# Create instance: util_mxfe_xcvr, and set properties
|
|
set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.A_TXDIFFCTRL {0x0C} \
|
|
CONFIG.CH_HSPMUX {0x6868} \
|
|
CONFIG.CPLL_CFG0 {0x01FA} \
|
|
CONFIG.CPLL_CFG1 {0x0023} \
|
|
CONFIG.CPLL_CFG2 {0x0002} \
|
|
CONFIG.CPLL_FBDIV {2} \
|
|
CONFIG.CPLL_FBDIV_4_5 {5} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.POR_CFG {0x0000} \
|
|
CONFIG.PPF0_CFG {0x0F00} \
|
|
CONFIG.PREIQ_FREQ_BST {1} \
|
|
CONFIG.QPLL_CFG0 {0x333c} \
|
|
CONFIG.QPLL_CFG4 {0x0045} \
|
|
CONFIG.QPLL_CP {0x0FF} \
|
|
CONFIG.QPLL_CP_G3 {0x00F} \
|
|
CONFIG.QPLL_FBDIV {"0000010100"} \
|
|
CONFIG.QPLL_LPF {0x2FF} \
|
|
CONFIG.QPLL_REFCLK_DIV {1} \
|
|
CONFIG.RXCDR_CFG0 {0x0003} \
|
|
CONFIG.RXCDR_CFG2_GEN2 {0x265} \
|
|
CONFIG.RXCDR_CFG2_GEN4 {0x0164} \
|
|
CONFIG.RXCDR_CFG3 {0x0012} \
|
|
CONFIG.RXCDR_CFG3_GEN2 {0x12} \
|
|
CONFIG.RXCDR_CFG3_GEN3 {0x0012} \
|
|
CONFIG.RXCDR_CFG3_GEN4 {0x0012} \
|
|
CONFIG.RXPI_CFG0 {0x0200} \
|
|
CONFIG.RXPI_CFG1 {0x00FD} \
|
|
CONFIG.RX_CLK25_DIV {31} \
|
|
CONFIG.RX_LANE_RATE {10} \
|
|
CONFIG.RX_NUM_OF_LANES {4} \
|
|
CONFIG.RX_OUT_DIV {1} \
|
|
CONFIG.RX_WIDEMODE_CDR {0x0} \
|
|
CONFIG.TXPI_CFG {0x0000} \
|
|
CONFIG.TX_CLK25_DIV {31} \
|
|
CONFIG.TX_LANE_RATE {10} \
|
|
CONFIG.TX_NUM_OF_LANES {4} \
|
|
CONFIG.TX_PI_BIASSET {3} \
|
|
] $util_mxfe_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_xcvr, and set properties
|
|
set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.LPM_OR_DFE_N {1} \
|
|
CONFIG.NUM_OF_LANES {4} \
|
|
CONFIG.QPLL_ENABLE {0} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {0} \
|
|
] $axi_mxfe_rx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_jesd
|
|
create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd
|
|
|
|
# Create instance: rx_mxfe_tpl_core
|
|
create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_cpack, and set properties
|
|
set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {8} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {1} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_cpack
|
|
|
|
|
|
# Create instance: mxfe_rx_data_offload
|
|
create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload
|
|
|
|
# Create instance: axi_mxfe_rx_dma, and set properties
|
|
set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {false} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {128} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {128} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {0} \
|
|
CONFIG.DMA_TYPE_SRC {1} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
CONFIG.SYNC_TRANSFER_START {false} \
|
|
] $axi_mxfe_rx_dma
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_xcvr, and set properties
|
|
set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_OF_LANES {4} \
|
|
CONFIG.QPLL_ENABLE {1} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {1} \
|
|
] $axi_mxfe_tx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_jesd
|
|
create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd
|
|
|
|
# Create instance: tx_mxfe_tpl_core
|
|
create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_upack, and set properties
|
|
set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {8} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {1} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_upack
|
|
|
|
|
|
# Create instance: mxfe_tx_data_offload
|
|
create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload
|
|
|
|
# Create instance: axi_mxfe_tx_dma, and set properties
|
|
set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {true} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {128} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {128} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {1} \
|
|
CONFIG.DMA_TYPE_SRC {0} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
] $axi_mxfe_tx_dma
|
|
|
|
|
|
# Create instance: rx_device_clk_rstgen, and set properties
|
|
set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ]
|
|
|
|
# Create instance: tx_device_clk_rstgen, and set properties
|
|
set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ]
|
|
|
|
# Create instance: axi_hp1_interconnect, and set properties
|
|
set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_CLKS {2} \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp1_interconnect
|
|
|
|
|
|
# Create instance: axi_hp2_interconnect, and set properties
|
|
set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp2_interconnect
|
|
|
|
|
|
# Create instance: manual_sync_or, and set properties
|
|
set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $manual_sync_or
|
|
|
|
|
|
# Create instance: cpack_rst_logic, and set properties
|
|
set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {3} \
|
|
] $cpack_rst_logic
|
|
|
|
|
|
# Create instance: rx_do_rstout_logic, and set properties
|
|
set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rx_do_rstout_logic
|
|
|
|
|
|
# Create instance: cpack_reset_sources, and set properties
|
|
set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ]
|
|
set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources
|
|
|
|
|
|
# Create instance: upack_rst_logic, and set properties
|
|
set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
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CONFIG.C_SIZE {2} \
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] $upack_rst_logic
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# Create instance: upack_reset_sources, and set properties
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set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ]
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set_property CONFIG.NUM_PORTS {2} $upack_reset_sources
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# Create interface connections
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi]
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connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD]
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connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD]
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connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD]
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connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2]
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connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3]
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connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi]
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connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins util_mxfe_xcvr/tx_0] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0]
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connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins util_mxfe_xcvr/tx_1] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1]
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connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins util_mxfe_xcvr/tx_2] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2]
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connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins util_mxfe_xcvr/tx_3] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3]
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connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0]
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connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1]
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connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2]
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connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3]
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connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0]
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connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins mxfe_rx_data_offload/m_axis] [get_bd_intf_pins axi_mxfe_rx_dma/s_axis]
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connect_bd_intf_net -intf_net mxfe_tx_data_offload_m_axis [get_bd_intf_pins util_mxfe_upack/s_axis] [get_bd_intf_pins mxfe_tx_data_offload/m_axis]
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connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins mxfe_tx_data_offload/s_axis] [get_bd_intf_pins axi_mxfe_tx_dma/m_axis]
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connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD]
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connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins tx_mxfe_tpl_core/link] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data]
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connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins util_mxfe_xcvr/rx_0] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0]
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connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins util_mxfe_xcvr/rx_1] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1]
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connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins util_mxfe_xcvr/rx_2] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2]
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connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins util_mxfe_xcvr/rx_3] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3]
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# Create port connections
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connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext]
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connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep]
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connect_bd_net -net adc_dovf_1 [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] [get_bd_pins rx_mxfe_tpl_core/adc_dovf]
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connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5]
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connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3]
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connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3]
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connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data]
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connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid]
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connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof]
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connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_pins axi_mxfe_rx_jesd/sync] [get_bd_ports rx_sync_0]
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connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3]
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connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4]
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connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2]
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connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0]
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connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr]
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connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1]
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connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset]
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connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in]
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connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i]
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connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req]
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connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req]
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connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in]
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connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1]
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connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3]
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connect_bd_net -net rom_sys_0_rom_data [get_bd_pins rom_sys_0/rom_data] [get_bd_pins axi_sysid_0/sys_rom_data]
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connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n]
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connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p]
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connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n]
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connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p]
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connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n]
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connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p]
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connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n]
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connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p]
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connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_cpack/clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk]
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connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn]
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connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins rx_device_clk_rstgen/peripheral_reset] [get_bd_pins cpack_reset_sources/In0]
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connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins rx_do_rstout_logic/Res] [get_bd_pins cpack_reset_sources/In2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_4 [get_bd_pins rx_mxfe_tpl_core/adc_data_4] [get_bd_pins util_mxfe_cpack/fifo_wr_data_4]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_5 [get_bd_pins rx_mxfe_tpl_core/adc_data_5] [get_bd_pins util_mxfe_cpack/fifo_wr_data_5]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_6 [get_bd_pins rx_mxfe_tpl_core/adc_data_6] [get_bd_pins util_mxfe_cpack/fifo_wr_data_6]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_7 [get_bd_pins rx_mxfe_tpl_core/adc_data_7] [get_bd_pins util_mxfe_cpack/fifo_wr_data_7]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_4 [get_bd_pins rx_mxfe_tpl_core/adc_enable_4] [get_bd_pins util_mxfe_cpack/enable_4]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_5 [get_bd_pins rx_mxfe_tpl_core/adc_enable_5] [get_bd_pins util_mxfe_cpack/enable_5]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_6 [get_bd_pins rx_mxfe_tpl_core/adc_enable_6] [get_bd_pins util_mxfe_cpack/enable_6]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_7 [get_bd_pins rx_mxfe_tpl_core/adc_enable_7] [get_bd_pins util_mxfe_cpack/enable_7]
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connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins rx_mxfe_tpl_core/adc_rst] [get_bd_pins cpack_reset_sources/In1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] [get_bd_pins manual_sync_or/Op1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en]
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connect_bd_net -net spi0_csn_concat_dout [get_bd_pins spi0_csn_concat/dout] [get_bd_ports spi0_csn]
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connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i]
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connect_bd_net -net spi1_csn_concat_dout [get_bd_pins spi1_csn_concat/dout] [get_bd_ports spi1_csn]
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connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i]
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connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync]
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connect_bd_net -net sys_250m_clk [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk]
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connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset]
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connect_bd_net -net sys_250m_resetn [get_bd_pins sys_250m_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_pins axi_hp2_interconnect/aresetn]
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connect_bd_net -net sys_500m_clk [get_bd_pins sys_ps8/pl_clk2] [get_bd_pins sys_500m_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_500m_reset [get_bd_pins sys_500m_rstgen/peripheral_reset]
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connect_bd_net -net sys_500m_resetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn]
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connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0]
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connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins rom_sys_0/clk] [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins util_mxfe_xcvr/up_clk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk]
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connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins util_mxfe_xcvr/up_rstn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn]
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connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_pins sys_ps8/emio_gpio_o] [get_bd_ports gpio_o]
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connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_pins sys_ps8/emio_gpio_t] [get_bd_ports gpio_t]
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connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_pins sys_ps8/emio_spi0_m_o] [get_bd_ports spi0_mosi]
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connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_pins sys_ps8/emio_spi0_sclk_o] [get_bd_ports spi0_sclk]
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connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] [get_bd_pins spi0_csn_concat/In1]
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connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] [get_bd_pins spi0_csn_concat/In2]
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connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins sys_ps8/emio_spi0_ss_o_n] [get_bd_pins spi0_csn_concat/In0]
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connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_pins sys_ps8/emio_spi1_m_o] [get_bd_ports spi1_mosi]
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connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_pins sys_ps8/emio_spi1_sclk_o] [get_bd_ports spi1_sclk]
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connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] [get_bd_pins spi1_csn_concat/In1]
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connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] [get_bd_pins spi1_csn_concat/In2]
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connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins sys_ps8/emio_spi1_ss_o_n] [get_bd_pins spi1_csn_concat/In0]
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connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in]
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connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref]
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connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref]
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connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins util_mxfe_upack/clk] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk]
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connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn]
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connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_4 [get_bd_pins tx_mxfe_tpl_core/dac_enable_4] [get_bd_pins util_mxfe_upack/enable_4]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_5 [get_bd_pins tx_mxfe_tpl_core/dac_enable_5] [get_bd_pins util_mxfe_upack/enable_5]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_6 [get_bd_pins tx_mxfe_tpl_core/dac_enable_6] [get_bd_pins util_mxfe_upack/enable_6]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_7 [get_bd_pins tx_mxfe_tpl_core/dac_enable_7] [get_bd_pins util_mxfe_upack/enable_7]
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connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1]
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connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] [get_bd_pins manual_sync_or/Op2]
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connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en]
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connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1]
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connect_bd_net -net upack_rst_logic_Res [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset]
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connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] [get_bd_pins mxfe_rx_data_offload/s_axis_tdata]
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connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins util_mxfe_upack/fifo_rd_data_0] [get_bd_pins tx_mxfe_tpl_core/dac_data_0]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins util_mxfe_upack/fifo_rd_data_1] [get_bd_pins tx_mxfe_tpl_core/dac_data_1]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins util_mxfe_upack/fifo_rd_data_2] [get_bd_pins tx_mxfe_tpl_core/dac_data_2]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins util_mxfe_upack/fifo_rd_data_3] [get_bd_pins tx_mxfe_tpl_core/dac_data_3]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_4 [get_bd_pins util_mxfe_upack/fifo_rd_data_4] [get_bd_pins tx_mxfe_tpl_core/dac_data_4]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_5 [get_bd_pins util_mxfe_upack/fifo_rd_data_5] [get_bd_pins tx_mxfe_tpl_core/dac_data_5]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_6 [get_bd_pins util_mxfe_upack/fifo_rd_data_6] [get_bd_pins tx_mxfe_tpl_core/dac_data_6]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_7 [get_bd_pins util_mxfe_upack/fifo_rd_data_7] [get_bd_pins tx_mxfe_tpl_core/dac_data_7]
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connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins axi_mxfe_rx_jesd/link_clk]
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connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_pins util_mxfe_xcvr/tx_0_n] [get_bd_ports tx_data_0_n]
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connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_pins util_mxfe_xcvr/tx_0_p] [get_bd_ports tx_data_0_p]
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connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_pins util_mxfe_xcvr/tx_1_n] [get_bd_ports tx_data_1_n]
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connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_pins util_mxfe_xcvr/tx_1_p] [get_bd_ports tx_data_1_p]
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connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_pins util_mxfe_xcvr/tx_2_n] [get_bd_ports tx_data_2_n]
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connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_pins util_mxfe_xcvr/tx_2_p] [get_bd_ports tx_data_2_p]
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connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_pins util_mxfe_xcvr/tx_3_n] [get_bd_ports tx_data_3_n]
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connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_pins util_mxfe_xcvr/tx_3_p] [get_bd_ports tx_data_3_p]
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connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins axi_mxfe_tx_jesd/link_clk]
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# Create address segments
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assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force
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assign_bd_address -offset 0x9C430000 -range 0x00001000 -with_name SEG_data_axi_mxfe_tx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84B90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_tx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84B60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_tx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force
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assign_bd_address -offset 0x85000000 -range 0x00010000 -with_name SEG_data_axi_sysid_0 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force
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assign_bd_address -offset 0x9C450000 -range 0x00010000 -with_name SEG_data_mxfe_rx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force
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assign_bd_address -offset 0x9C440000 -range 0x00010000 -with_name SEG_data_mxfe_tx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84A10000 -range 0x00002000 -with_name SEG_data_rx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force
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assign_bd_address -offset 0x84B10000 -range 0x00002000 -with_name SEG_data_tx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force
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assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force
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assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force
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assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force
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# Exclude Address Segments
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exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH]
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exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH]
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exclude_bd_addr_seg -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH]
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# Perform GUI Layout
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regenerate_bd_layout -layout_string {
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.17607",
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"Default View_TopLeft":"-165,464",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
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# -string -flagsOSRD
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preplace port port-id_spi0_sclk -pg 1 -lvl 15 -x 6170 -y 2770 -defaultsOSRD
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preplace port port-id_spi0_mosi -pg 1 -lvl 15 -x 6170 -y 2810 -defaultsOSRD
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preplace port port-id_spi0_miso -pg 1 -lvl 0 -x 0 -y 3200 -defaultsOSRD
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preplace port port-id_spi1_sclk -pg 1 -lvl 15 -x 6170 -y 2970 -defaultsOSRD
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preplace port port-id_spi1_mosi -pg 1 -lvl 15 -x 6170 -y 3170 -defaultsOSRD
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preplace port port-id_spi1_miso -pg 1 -lvl 0 -x 0 -y 3260 -defaultsOSRD
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preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x 0 -y 1490 -defaultsOSRD
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preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x 0 -y 1720 -defaultsOSRD
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preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x 0 -y 2450 -defaultsOSRD
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preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD
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preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x 0 -y 3180 -defaultsOSRD
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preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x 0 -y 1700 -defaultsOSRD
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preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x 0 -y 2470 -defaultsOSRD
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preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x 0 -y 2510 -defaultsOSRD
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preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x 0 -y 2490 -defaultsOSRD
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preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x 0 -y 3080 -defaultsOSRD
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preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x 0 -y 3060 -defaultsOSRD
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preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x 0 -y 3100 -defaultsOSRD
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preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x 0 -y 3120 -defaultsOSRD
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preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x 0 -y 3140 -defaultsOSRD
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preplace port port-id_tx_data_0_p -pg 1 -lvl 15 -x 6170 -y 2090 -defaultsOSRD
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preplace port port-id_tx_data_0_n -pg 1 -lvl 15 -x 6170 -y 2110 -defaultsOSRD
|
|
preplace port port-id_tx_data_1_p -pg 1 -lvl 15 -x 6170 -y 2130 -defaultsOSRD
|
|
preplace port port-id_tx_data_1_n -pg 1 -lvl 15 -x 6170 -y 2150 -defaultsOSRD
|
|
preplace port port-id_tx_data_2_p -pg 1 -lvl 15 -x 6170 -y 2170 -defaultsOSRD
|
|
preplace port port-id_tx_data_2_n -pg 1 -lvl 15 -x 6170 -y 2190 -defaultsOSRD
|
|
preplace port port-id_tx_data_3_p -pg 1 -lvl 15 -x 6170 -y 2230 -defaultsOSRD
|
|
preplace port port-id_tx_data_3_n -pg 1 -lvl 15 -x 6170 -y 2250 -defaultsOSRD
|
|
preplace port port-id_rx_data_4_n -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD
|
|
preplace port port-id_rx_data_4_p -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
|
preplace port port-id_rx_data_5_n -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
|
|
preplace port port-id_rx_data_5_p -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
|
preplace port port-id_rx_data_6_n -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
|
|
preplace port port-id_rx_data_6_p -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
|
|
preplace port port-id_rx_data_7_n -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
|
|
preplace port port-id_rx_data_7_p -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
|
|
preplace port port-id_tx_data_4_n -pg 1 -lvl 15 -x 6170 -y 20 -defaultsOSRD
|
|
preplace port port-id_tx_data_4_p -pg 1 -lvl 15 -x 6170 -y 40 -defaultsOSRD
|
|
preplace port port-id_tx_data_5_n -pg 1 -lvl 15 -x 6170 -y 60 -defaultsOSRD
|
|
preplace port port-id_tx_data_5_p -pg 1 -lvl 15 -x 6170 -y 80 -defaultsOSRD
|
|
preplace port port-id_tx_data_6_n -pg 1 -lvl 15 -x 6170 -y 100 -defaultsOSRD
|
|
preplace port port-id_tx_data_6_p -pg 1 -lvl 15 -x 6170 -y 120 -defaultsOSRD
|
|
preplace port port-id_tx_data_7_n -pg 1 -lvl 15 -x 6170 -y 140 -defaultsOSRD
|
|
preplace port port-id_tx_data_7_p -pg 1 -lvl 15 -x 6170 -y 160 -defaultsOSRD
|
|
preplace port port-id_ext_sync_in -pg 1 -lvl 0 -x 0 -y 1270 -defaultsOSRD
|
|
preplace portBus spi0_csn -pg 1 -lvl 15 -x 6170 -y 2890 -defaultsOSRD
|
|
preplace portBus spi1_csn -pg 1 -lvl 15 -x 6170 -y 3090 -defaultsOSRD
|
|
preplace portBus gpio_i -pg 1 -lvl 0 -x 0 -y 2910 -defaultsOSRD
|
|
preplace portBus gpio_o -pg 1 -lvl 15 -x 6170 -y 2690 -defaultsOSRD
|
|
preplace portBus gpio_t -pg 1 -lvl 15 -x 6170 -y 2710 -defaultsOSRD
|
|
preplace portBus rx_sync_0 -pg 1 -lvl 15 -x 6170 -y 1920 -defaultsOSRD
|
|
preplace portBus tx_sync_0 -pg 1 -lvl 0 -x 0 -y 3160 -defaultsOSRD
|
|
preplace inst sys_ps8 -pg 1 -lvl 9 -x 3350 -y 2910 -defaultsOSRD
|
|
preplace inst sys_rstgen -pg 1 -lvl 1 -x 200 -y 2120 -defaultsOSRD
|
|
preplace inst sys_250m_rstgen -pg 1 -lvl 5 -x 1560 -y 2320 -defaultsOSRD
|
|
preplace inst sys_500m_rstgen -pg 1 -lvl 10 -x 3900 -y 3230 -defaultsOSRD
|
|
preplace inst spi0_csn_concat -pg 1 -lvl 14 -x 5960 -y 2890 -defaultsOSRD
|
|
preplace inst VCC_1 -pg 1 -lvl 5 -x 1560 -y 2110 -defaultsOSRD
|
|
preplace inst GND_1 -pg 1 -lvl 5 -x 1560 -y 2010 -defaultsOSRD
|
|
preplace inst spi1_csn_concat -pg 1 -lvl 14 -x 5960 -y 3090 -defaultsOSRD
|
|
preplace inst axi_sysid_0 -pg 1 -lvl 11 -x 4500 -y 2170 -defaultsOSRD
|
|
preplace inst rom_sys_0 -pg 1 -lvl 10 -x 3900 -y 2340 -defaultsOSRD
|
|
preplace inst axi_cpu_interconnect -pg 1 -lvl 10 -x 3900 -y 1770 -defaultsOSRD
|
|
preplace inst sys_concat_intc_0 -pg 1 -lvl 8 -x 2720 -y 2620 -defaultsOSRD
|
|
preplace inst sys_concat_intc_1 -pg 1 -lvl 8 -x 2720 -y 2150 -defaultsOSRD
|
|
preplace inst axi_hp0_interconnect -pg 1 -lvl 8 -x 2720 -y 2830 -defaultsOSRD
|
|
preplace inst util_mxfe_xcvr -pg 1 -lvl 13 -x 5570 -y 2080 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_xcvr -pg 1 -lvl 7 -x 2320 -y 1530 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_jesd -pg 1 -lvl 14 -x 5960 -y 1960 -defaultsOSRD
|
|
preplace inst rx_mxfe_tpl_core -pg 1 -lvl 11 -x 4500 -y 330 -defaultsOSRD
|
|
preplace inst util_mxfe_cpack -pg 1 -lvl 5 -x 1560 -y 1010 -defaultsOSRD
|
|
preplace inst mxfe_rx_data_offload -pg 1 -lvl 6 -x 1970 -y 2130 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_dma -pg 1 -lvl 7 -x 2320 -y 2300 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_xcvr -pg 1 -lvl 12 -x 5030 -y 1720 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_jesd -pg 1 -lvl 12 -x 5030 -y 1970 -defaultsOSRD
|
|
preplace inst tx_mxfe_tpl_core -pg 1 -lvl 11 -x 4500 -y 1060 -defaultsOSRD
|
|
preplace inst util_mxfe_upack -pg 1 -lvl 12 -x 5030 -y 1260 -defaultsOSRD
|
|
preplace inst mxfe_tx_data_offload -pg 1 -lvl 11 -x 4500 -y 1890 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_dma -pg 1 -lvl 7 -x 2320 -y 2050 -defaultsOSRD
|
|
preplace inst rx_device_clk_rstgen -pg 1 -lvl 2 -x 550 -y 1600 -defaultsOSRD
|
|
preplace inst tx_device_clk_rstgen -pg 1 -lvl 9 -x 3350 -y 1850 -defaultsOSRD
|
|
preplace inst axi_hp1_interconnect -pg 1 -lvl 8 -x 2720 -y 3000 -defaultsOSRD
|
|
preplace inst axi_hp2_interconnect -pg 1 -lvl 8 -x 2720 -y 2360 -defaultsOSRD
|
|
preplace inst manual_sync_or -pg 1 -lvl 10 -x 3900 -y 860 -defaultsOSRD
|
|
preplace inst cpack_rst_logic -pg 1 -lvl 4 -x 1060 -y 850 -defaultsOSRD
|
|
preplace inst rx_do_rstout_logic -pg 1 -lvl 2 -x 550 -y 1430 -defaultsOSRD
|
|
preplace inst cpack_reset_sources -pg 1 -lvl 3 -x 830 -y 1410 -defaultsOSRD
|
|
preplace inst upack_rst_logic -pg 1 -lvl 11 -x 4500 -y 1370 -defaultsOSRD
|
|
preplace inst upack_reset_sources -pg 1 -lvl 10 -x 3900 -y 1410 -defaultsOSRD
|
|
preplace netloc GND_1_dout 1 5 6 1760 2320 2150J 2180 2530 2440 2850J 2420 3720 2410 4220
|
|
preplace netloc VCC_1_dout 1 5 5 1790 2450 NJ 2450 NJ 2450 2860J 2430 3670
|
|
preplace netloc adc_dovf_1 1 5 6 NJ 1040 NJ 1040 NJ 1040 NJ 1040 3660J 780 4090
|
|
preplace netloc axi_mxfe_rx_dma_irq 1 7 1 2540 2180n
|
|
preplace netloc axi_mxfe_rx_jesd_irq 1 7 8 2590 1970 NJ 1970 NJ 1970 4120J 2040 4730J 2100 5310J 1540 5800J 2100 6130
|
|
preplace netloc axi_mxfe_rx_jesd_phy_en_char_align 1 12 3 5430 2660 NJ 2660 6120
|
|
preplace netloc axi_mxfe_rx_jesd_rx_data_tdata 1 10 5 4260 1580 NJ 1580 5240J 1500 NJ 1500 6150
|
|
preplace netloc axi_mxfe_rx_jesd_rx_data_tvalid 1 10 5 4250 1590 NJ 1590 5250J 1510 NJ 1510 6140
|
|
preplace netloc axi_mxfe_rx_jesd_rx_sof 1 10 5 4240 1600 NJ 1600 5260J 1520 NJ 1520 6110
|
|
preplace netloc axi_mxfe_rx_jesd_sync 1 14 1 NJ 1920
|
|
preplace netloc axi_mxfe_rx_xcvr_up_pll_rst 1 7 6 2530J 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 5330
|
|
preplace netloc axi_mxfe_tx_dma_irq 1 7 1 2560 2060n
|
|
preplace netloc axi_mxfe_tx_jesd_irq 1 7 6 2580 2280 NJ 2280 3700J 2270 NJ 2270 NJ 2270 5180
|
|
preplace netloc axi_mxfe_tx_xcvr_up_pll_rst 1 12 1 5190 1780n
|
|
preplace netloc axi_sysid_0_rom_addr 1 9 3 3730 2420 NJ 2420 4690
|
|
preplace netloc cpack_reset_sources_dout 1 3 1 930 850n
|
|
preplace netloc cpack_rst_logic_Res 1 4 1 NJ 850
|
|
preplace netloc ext_sync_in_1 1 0 11 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 4110
|
|
preplace netloc gpio_i_1 1 0 10 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 NJ 2910 2940J 2480 3660
|
|
preplace netloc init_req_1 1 5 3 1840 2430 NJ 2430 2480
|
|
preplace netloc init_req_2 1 7 4 2490J 2010 NJ 2010 NJ 2010 4290
|
|
preplace netloc manual_sync_or_Res 1 10 1 4230 420n
|
|
preplace netloc mxfe_rx_data_offload_s_axis_tready 1 1 5 380 1500 NJ 1500 NJ 1500 NJ 1500 1810J
|
|
preplace netloc ref_clk_q0_1 1 0 13 NJ 2450 NJ 2450 NJ 2450 NJ 2450 NJ 2450 1760J 2460 NJ 2460 NJ 2460 2870J 2440 NJ 2440 NJ 2440 NJ 2440 5360
|
|
preplace netloc rom_sys_0_rom_data 1 10 1 4310 2190n
|
|
preplace netloc rx_data_0_n_1 1 0 13 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 NJ 2470 2890J 2450 NJ 2450 NJ 2450 NJ 2450 5340J
|
|
preplace netloc rx_data_0_p_1 1 0 13 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 2100J 1690 NJ 1690 2880J 1580 NJ 1580 4190J 1610 4750J 1840 5200J
|
|
preplace netloc rx_data_1_n_1 1 0 13 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 NJ 2490 2540J 2480 2900J 2460 NJ 2460 NJ 2460 NJ 2460 5240J
|
|
preplace netloc rx_data_1_p_1 1 0 13 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 NJ 2510 2580J 2490 2910J 2470 NJ 2470 NJ 2470 NJ 2470 5350J
|
|
preplace netloc rx_data_2_n_1 1 0 13 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 NJ 3060 2500J 3090 2950J 2490 NJ 2490 NJ 2490 NJ 2490 5390J
|
|
preplace netloc rx_data_2_p_1 1 0 13 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 NJ 3080 2480J 3100 2960J 2500 NJ 2500 NJ 2500 NJ 2500 5380J
|
|
preplace netloc rx_data_3_n_1 1 0 13 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 NJ 3120 2980J 2520 NJ 2520 NJ 2520 NJ 2520 5420J
|
|
preplace netloc rx_data_3_p_1 1 0 13 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 NJ 3100 2470J 3110 2970J 2510 NJ 2510 NJ 2510 NJ 2510 5410J
|
|
preplace netloc rx_device_clk_1 1 0 14 NJ 1490 370 1490 NJ 1490 NJ 1490 1190 1260 1800 1710 NJ 1710 NJ 1710 2930J 1600 NJ 1600 4200 2050 4720J 2140 5170J 2620 5770J
|
|
preplace netloc rx_device_clk_rstgen_peripheral_aresetn 1 2 4 NJ 1640 NJ 1640 NJ 1640 1780
|
|
preplace netloc rx_device_clk_rstgen_peripheral_reset 1 2 1 720 1390n
|
|
preplace netloc rx_do_rstout_logic_Res 1 2 1 NJ 1430
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_0 1 4 8 1220 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 4710
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_1 1 4 8 1250 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 4730
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_2 1 4 8 1210 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 4750
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_3 1 4 8 1240 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 4700
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_4 1 4 8 1200 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 4770
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_5 1 4 8 1230 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 690 4740
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_6 1 4 8 1260 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 NJ 700 4710
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_7 1 4 8 1340 750 NJ 750 NJ 750 NJ 750 NJ 750 NJ 750 NJ 750 4780
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_0 1 4 8 1270 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 4870
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_1 1 4 8 1290 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 4850
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_2 1 4 8 1310 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 4830
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_3 1 4 8 1280 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 NJ 710 4880
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_4 1 4 8 1300 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 4860
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_5 1 4 8 1320 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 NJ 730 4760
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_6 1 4 8 1330 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 4690
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_7 1 4 8 1350 760 NJ 760 NJ 760 NJ 760 NJ 760 NJ 760 NJ 760 4790
|
|
preplace netloc rx_mxfe_tpl_core_adc_rst 1 2 10 730 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 4210J 1460 4730
|
|
preplace netloc rx_mxfe_tpl_core_adc_sync_manual_req_out 1 9 3 3710 790 4130J 780 4720
|
|
preplace netloc rx_mxfe_tpl_core_adc_valid_0 1 4 8 1360 770 NJ 770 NJ 770 NJ 770 NJ 770 NJ 770 NJ 770 4890
|
|
preplace netloc spi0_csn_concat_dout 1 14 1 NJ 2890
|
|
preplace netloc spi0_miso_1 1 0 10 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 NJ 3200 2590J 3160 3030J 2560 3650
|
|
preplace netloc spi1_csn_concat_dout 1 14 1 NJ 3090
|
|
preplace netloc spi1_miso_1 1 0 10 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 NJ 3260 3660
|
|
preplace netloc sync_1 1 0 12 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 NJ 3160 2560J 3140 3010J 2540 NJ 2540 NJ 2540 4860J
|
|
preplace netloc sys_250m_clk 1 4 7 1310 2210 1780 2350 2160 2440 2520 3180 3050 3250 3730 3120 4280
|
|
preplace netloc sys_250m_reset 1 5 1 N 2320
|
|
preplace netloc sys_250m_resetn 1 5 6 1800 2360 2140 2170 2570 1980 NJ 1980 NJ 1980 4110J
|
|
preplace netloc sys_500m_clk 1 9 1 N 3190
|
|
preplace netloc sys_500m_reset 1 10 1 N 3230
|
|
preplace netloc sys_500m_resetn 1 10 1 N 3270
|
|
preplace netloc sys_concat_intc_0_dout 1 8 1 2910J 2620n
|
|
preplace netloc sys_concat_intc_1_dout 1 8 1 2920 2150n
|
|
preplace netloc sys_cpu_clk 1 0 14 30 2220 NJ 2220 NJ 2220 NJ 2220 NJ 2220 1820 2340 2130 2420 2490 3170 3040 2570 3710 1930 4170 2060 4850 2120 5400 2630 5750
|
|
preplace netloc sys_cpu_reset 1 1 1 N 2120
|
|
preplace netloc sys_cpu_resetn 1 1 13 380 2170 NJ 2170 NJ 2170 NJ 2170 1770 2330 2110 2530 2500 2750 2880 1950 3670 1940 4180 2070 4880 2110 5370 2640 5780
|
|
preplace netloc sys_ps8_emio_gpio_o 1 9 6 NJ 2690 NJ 2690 NJ 2690 NJ 2690 NJ 2690 NJ
|
|
preplace netloc sys_ps8_emio_gpio_t 1 9 6 NJ 2710 NJ 2710 NJ 2710 NJ 2710 NJ 2710 NJ
|
|
preplace netloc sys_ps8_emio_spi0_m_o 1 9 6 NJ 2810 NJ 2810 NJ 2810 NJ 2810 NJ 2810 NJ
|
|
preplace netloc sys_ps8_emio_spi0_sclk_o 1 9 6 NJ 2770 NJ 2770 NJ 2770 NJ 2770 NJ 2770 NJ
|
|
preplace netloc sys_ps8_emio_spi0_ss1_o_n 1 9 5 NJ 2890 NJ 2890 NJ 2890 NJ 2890 N
|
|
preplace netloc sys_ps8_emio_spi0_ss2_o_n 1 9 5 NJ 2910 NJ 2910 NJ 2910 NJ 2910 N
|
|
preplace netloc sys_ps8_emio_spi0_ss_o_n 1 9 5 NJ 2870 NJ 2870 NJ 2870 NJ 2870 N
|
|
preplace netloc sys_ps8_emio_spi1_m_o 1 9 6 3690J 3130 4090J 3170 NJ 3170 NJ 3170 NJ 3170 NJ
|
|
preplace netloc sys_ps8_emio_spi1_sclk_o 1 9 6 NJ 2970 NJ 2970 NJ 2970 NJ 2970 NJ 2970 NJ
|
|
preplace netloc sys_ps8_emio_spi1_ss1_o_n 1 9 5 NJ 3090 NJ 3090 NJ 3090 NJ 3090 N
|
|
preplace netloc sys_ps8_emio_spi1_ss2_o_n 1 9 5 NJ 3110 NJ 3110 NJ 3110 NJ 3110 N
|
|
preplace netloc sys_ps8_emio_spi1_ss_o_n 1 9 5 NJ 3070 NJ 3070 NJ 3070 NJ 3070 N
|
|
preplace netloc sys_ps8_pl_resetn0 1 0 10 20 2230 NJ 2230 NJ 2230 NJ 2230 1190 3270 NJ 3270 NJ 3270 NJ 3270 NJ 3270 3670
|
|
preplace netloc sysref_1 1 0 14 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 NJ 3180 2470J 3150 3020J 2550 NJ 2550 NJ 2550 NJ 2550 5180J 2680 5790J
|
|
preplace netloc sysref_2 1 0 12 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 NJ 3140 2500J 3130 2990J 2530 NJ 2530 NJ 2530 4870J
|
|
preplace netloc tx_device_clk_1 1 0 12 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 2940 1610 NJ 1610 4090 1310 4710
|
|
preplace netloc tx_device_clk_rstgen_peripheral_aresetn 1 9 2 3680J 1950 4270
|
|
preplace netloc tx_device_clk_rstgen_peripheral_reset 1 9 1 3660 1400n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_0 1 11 1 4890 900n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_1 1 11 1 4880 940n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_2 1 11 1 4860 980n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_3 1 11 1 4850 1020n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_4 1 11 1 4810 1060n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_5 1 11 1 4800 1100n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_6 1 11 1 4790 1140n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_7 1 11 1 4780 1180n
|
|
preplace netloc tx_mxfe_tpl_core_dac_rst 1 9 3 3710 1340 4190J 1470 4700
|
|
preplace netloc tx_mxfe_tpl_core_dac_sync_manual_req_out 1 9 3 3710 930 4140J 790 4720
|
|
preplace netloc tx_mxfe_tpl_core_dac_valid_0 1 11 1 4820 920n
|
|
preplace netloc upack_reset_sources_dout 1 10 1 4160 1370n
|
|
preplace netloc upack_rst_logic_Res 1 11 1 4770J 1190n
|
|
preplace netloc util_mxfe_cpack_packed_fifo_wr_data 1 5 1 1820 1020n
|
|
preplace netloc util_mxfe_cpack_packed_fifo_wr_en 1 5 1 1830 1000n
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_0 1 10 3 4270 800 NJ 800 5170
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_1 1 10 3 4300 810 NJ 810 5200
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_2 1 10 3 4310 820 NJ 820 5220
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_3 1 10 3 4290 1290 4740J 1080 5180
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_4 1 10 3 4280 1300 4750J 1090 5210
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_5 1 10 3 4310 1430 NJ 1430 5220
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_6 1 10 3 4300 1440 NJ 1440 5200
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_7 1 10 3 4270 1450 NJ 1450 5170
|
|
preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 12 2 5440 2650 5740
|
|
preplace netloc util_mxfe_xcvr_tx_0_n 1 13 2 5710J 2120 6150J
|
|
preplace netloc util_mxfe_xcvr_tx_0_p 1 13 2 5720J 2110 6140J
|
|
preplace netloc util_mxfe_xcvr_tx_1_n 1 13 2 5730J 2150 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_1_p 1 13 2 5760J 2130 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_2_n 1 13 2 5710J 2190 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_2_p 1 13 2 5720J 2170 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_3_n 1 13 2 NJ 2250 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_3_p 1 13 2 NJ 2230 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 11 3 4890 2130 5250 2670 5700
|
|
preplace netloc axi_cpu_interconnect_M00_AXI 1 10 1 4130 1670n
|
|
preplace netloc axi_cpu_interconnect_M01_AXI 1 6 5 2170 1700 NJ 1700 2920J 1590 NJ 1590 4080
|
|
preplace netloc axi_cpu_interconnect_M02_AXI 1 10 1 4100 240n
|
|
preplace netloc axi_cpu_interconnect_M03_AXI 1 10 4 NJ 1730 4740J 2090 5290J 1530 5810
|
|
preplace netloc axi_cpu_interconnect_M04_AXI 1 6 5 2170 2160 2510J 2020 NJ 2020 NJ 2020 4100
|
|
preplace netloc axi_cpu_interconnect_M05_AXI 1 5 6 1840 1930 NJ 1930 NJ 1930 2940J 1960 NJ 1960 4080
|
|
preplace netloc axi_cpu_interconnect_M06_AXI 1 10 2 4190J 1740 4790
|
|
preplace netloc axi_cpu_interconnect_M07_AXI 1 10 1 4150 920n
|
|
preplace netloc axi_cpu_interconnect_M08_AXI 1 10 2 4140J 2030 4840
|
|
preplace netloc axi_cpu_interconnect_M09_AXI 1 6 5 2170 1940 2560J 1990 NJ 1990 NJ 1990 4070
|
|
preplace netloc axi_cpu_interconnect_M10_AXI 1 10 1 4190 1800n
|
|
preplace netloc axi_hp0_interconnect_M00_AXI 1 8 1 N 2830
|
|
preplace netloc axi_hp1_interconnect_M00_AXI 1 8 1 3000 2850n
|
|
preplace netloc axi_hp2_interconnect_M00_AXI 1 8 1 2930 2360n
|
|
preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 7 1 2510 2280n
|
|
preplace netloc axi_mxfe_rx_xcvr_m_axi 1 7 1 2550 1430n
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 7 6 NJ 1470 NJ 1470 3690J 1490 NJ 1490 NJ 1490 5400
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 7 6 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 5220
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 7 6 2480J 1540 NJ 1540 NJ 1540 NJ 1540 NJ 1540 5200
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 7 6 2510J 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 5350
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 7 6 NJ 1450 2880J 1460 3710J 1480 NJ 1480 NJ 1480 5440
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 7 6 NJ 1490 NJ 1490 3670J 1500 NJ 1500 NJ 1500 5230
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 7 6 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 5210
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 7 6 2490J 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 5370
|
|
preplace netloc axi_mxfe_tx_dma_m_src_axi 1 7 1 2500 2020n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 12 1 5300 1680n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 12 1 5320 1760n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 12 1 5340 1840n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 12 1 5350 1920n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 12 1 5280 1660n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 12 1 5190 1700n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 12 1 5180 1720n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 12 1 5170 1740n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 12 1 5270 1600n
|
|
preplace netloc mxfe_rx_data_offload_m_axis 1 6 1 2120 2130n
|
|
preplace netloc mxfe_tx_data_offload_m_axis 1 11 1 4760 1150n
|
|
preplace netloc s_axis_1 1 7 4 2480J 2000 NJ 2000 NJ 2000 4250
|
|
preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 9 1 3690 1750n
|
|
preplace netloc tx_mxfe_tpl_core_link 1 11 1 4830 880n
|
|
preplace netloc util_mxfe_xcvr_rx_0 1 13 1 N 1890
|
|
preplace netloc util_mxfe_xcvr_rx_1 1 13 1 N 1910
|
|
preplace netloc util_mxfe_xcvr_rx_2 1 13 1 N 1930
|
|
preplace netloc util_mxfe_xcvr_rx_3 1 13 1 N 1950
|
|
levelinfo -pg 1 0 200 550 830 1060 1560 1970 2320 2720 3350 3900 4500 5030 5570 5960 6170
|
|
pagesize -pg 1 -db -bbox -sgen -150 0 6320 3320
|
|
"
|
|
}
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_system()
|
|
|
|
cr_bd_system ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ]
|
|
|
|
set idrFlowPropertiesConstraints ""
|
|
catch {
|
|
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
|
|
set_param runs.disableIDRFlowPropertyConstraints 1
|
|
}
|
|
|
|
# Create 'synth_1' run (if not found)
|
|
if {[string equal [get_runs -quiet synth_1] ""]} {
|
|
create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2023} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
|
} else {
|
|
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
|
set_property flow "Vivado Synthesis 2023" [get_runs synth_1]
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
|
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
|
|
|
# set the current synth run
|
|
current_run -synthesis [get_runs synth_1]
|
|
|
|
# Create 'impl_1' run (if not found)
|
|
if {[string equal [get_runs -quiet impl_1] ""]} {
|
|
create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2023} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
|
} else {
|
|
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
|
set_property flow "Vivado Implementation 2023" [get_runs impl_1]
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_io_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.verbose" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_power_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
|
|
|
# set the current impl run
|
|
current_run -implementation [get_runs impl_1]
|
|
catch {
|
|
if { $idrFlowPropertiesConstraints != {} } {
|
|
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
|
|
}
|
|
}
|
|
|
|
puts "INFO: Project created:${_xil_proj_name_}"
|
|
# Create 'drc_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {drc_1} -type drc
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
|
|
|
# Create 'methodology_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {methodology_1} -type methodology
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
|
|
|
# Create 'power_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {power_1} -type power
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
|
|
|
# Create 'timing_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {timing_1} -type timing
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
|
|
|
# Create 'utilization_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_1} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
|
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
|
set_property -name "run.step" -value "synth_design" -objects $obj
|
|
set_property -name "run.type" -value "synthesis" -objects $obj
|
|
|
|
# Create 'utilization_2' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_2} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
|
|
|
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
|
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
|
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
|
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
|
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
|
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|