moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,46 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9081_fmca_ebz_zcu102
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M_DEPS += timing_constr.xdc
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/data_offload_bd.tcl
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||||
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
|
||||
M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
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||||
M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
|
||||
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
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||||
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_3w_spi.v
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||||
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += axi_tdd
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LIB_DEPS += data_offload
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/axi_jesd204_tx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += jesd204/jesd204_tx
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LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx
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LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_adcfifo
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LIB_DEPS += util_dacfifo
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LIB_DEPS += util_do_ram
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LIB_DEPS += util_hbm
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk
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@@ -0,0 +1,27 @@
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# How to re-create Project
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Clone the hdl repository at the same level as this project
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https://github.com/analogdevicesinc/hdl
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1) open Vivado
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2) In the Tcl Console - cd into the project's folder ex. cd c:/erysys/dds_pulse_gen/zcu102
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3) In the Tcl Console type source ./script/create_proj.tcl
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4) Right-click on system_i:system and select "Create HDL Wrapper..."
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5) Build project
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To update the project file to save into git
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1) open Vivado
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2) remove system_wrapper.vhd from project - this files is auto-generated
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3) remove system_top.dcp from the project from under "Utility Sources" - this files is auto-generated
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3) In the Tcl Console type into the project's folder, ex. cd c:/erysys/dds_pulse_gen/zcu102
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4) in the tcl Console type write_project_tcl -force ./script/create_proj.tcl
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5) using a text editor open create_proj.tcl and replace line 120 with:
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from:
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set origin_dir "."
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to:
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set origin_dir "./zcu102_ad9081_dds_x4"
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You can now push all files into git
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@@ -0,0 +1,105 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
|
||||
`timescale 1ns/100ps
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//
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// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves.
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// The expected transfer format is defined in ADI_SPI technical specification
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// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
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//
|
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// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the
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// instruction defines the direction of the SDIO during data transfer. (READ
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// is 1 and WRITE is 0)
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//
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module ad_3w_spi #(
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parameter NUM_OF_SLAVES = 8
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) (
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input [NUM_OF_SLAVES-1:0] spi_csn,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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inout spi_sdio,
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output spi_dir
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);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_dir = ~spi_enable_s;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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||||
always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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||||
spi_count <= 6'd0;
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||||
spi_rd_wr_n <= 1'd0;
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||||
end else begin
|
||||
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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||||
if (spi_count == 6'd0) begin
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||||
spi_rd_wr_n <= spi_mosi;
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||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge spi_clk or posedge spi_csn_s) begin
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||||
if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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||||
if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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||||
end
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||||
end
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||||
end
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// io butter
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assign spi_miso = spi_sdio;
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assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
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endmodule
|
||||
@@ -0,0 +1,56 @@
|
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_iobuf #(
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||||
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||||
parameter DATA_WIDTH = 1
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||||
) (
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||||
input [(DATA_WIDTH-1):0] dio_t,
|
||||
input [(DATA_WIDTH-1):0] dio_i,
|
||||
output [(DATA_WIDTH-1):0] dio_o,
|
||||
inout [(DATA_WIDTH-1):0] dio_p
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||||
);
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||||
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||||
genvar n;
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||||
generate
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||||
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
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||||
assign dio_o[n] = dio_p[n];
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||||
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
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||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,93 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
#
|
||||
## mxfe
|
||||
#
|
||||
|
||||
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
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||||
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
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||||
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
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||||
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
|
||||
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
|
||||
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
|
||||
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67
|
||||
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67
|
||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
|
||||
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
|
||||
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
|
||||
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
|
||||
set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229
|
||||
set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229
|
||||
set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N
|
||||
set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P
|
||||
set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N
|
||||
set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P
|
||||
set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N
|
||||
set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P
|
||||
set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N
|
||||
set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P
|
||||
set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N
|
||||
set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P
|
||||
set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N
|
||||
set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P
|
||||
set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N
|
||||
set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P
|
||||
set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N
|
||||
set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P
|
||||
set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66
|
||||
set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
|
||||
set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67
|
||||
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66
|
||||
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66
|
||||
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
|
||||
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
|
||||
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66
|
||||
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66
|
||||
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66
|
||||
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66
|
||||
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66
|
||||
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66
|
||||
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66
|
||||
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66
|
||||
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66
|
||||
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66
|
||||
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
|
||||
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
|
||||
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66
|
||||
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p]
|
||||
create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p]
|
||||
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# constraints
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
|
||||
set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
|
||||
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
|
||||
set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4
|
||||
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6
|
||||
set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS33} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7
|
||||
|
||||
# Define SPI clock
|
||||
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
|
||||
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
|
||||
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports ext_trigger_in] ; ## L12N_AD8N_50_N
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
proc init { cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
set full_sbusif_list [list ]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
||||
set busif_param_list [list]
|
||||
set busif_name [get_property NAME $busif]
|
||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
||||
continue
|
||||
}
|
||||
foreach tparam $axi_standard_param_list {
|
||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
||||
}
|
||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc pre_propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
if { $val_on_cell != "" } {
|
||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
||||
if { $val_on_cell_intf_pin != "" } {
|
||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,246 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_pulse_intfc_v1_0 is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"00";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 6
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
m_axis_aclk : in std_logic;
|
||||
reset : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(127 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
|
||||
s00_axis_tdata : in std_logic_vector(127 downto 0);
|
||||
s00_axis_tvalid : in std_logic;
|
||||
s00_axis_tready : out std_logic;
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
|
||||
-- Ports of Axi Slave Bus Interface S00_AXI
|
||||
s00_axi_aclk : in std_logic;
|
||||
s00_axi_aresetn : in std_logic;
|
||||
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_awprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_awvalid : in std_logic;
|
||||
s00_axi_awready : out std_logic;
|
||||
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
s00_axi_wvalid : in std_logic;
|
||||
s00_axi_wready : out std_logic;
|
||||
s00_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_bvalid : out std_logic;
|
||||
s00_axi_bready : in std_logic;
|
||||
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_arprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_arvalid : in std_logic;
|
||||
s00_axi_arready : out std_logic;
|
||||
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_rresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_rvalid : out std_logic;
|
||||
s00_axi_rready : in std_logic
|
||||
);
|
||||
end dds_pulse_intfc_v1_0;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0 is
|
||||
|
||||
-- -- component declaration
|
||||
-- component dds_pulse_intfc_v1_0_S00_AXI is
|
||||
-- generic (
|
||||
-- FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
-- MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- C_S_AXI_ADDR_WIDTH : integer := 6
|
||||
-- );
|
||||
-- port (
|
||||
-- cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
-- cmd_send_out : out std_logic;
|
||||
--
|
||||
-- mode_out : out std_logic;
|
||||
-- scale_out : out std_logic_vector(15 downto 0);
|
||||
-- dac_holdoff_out : out std_logic;
|
||||
--
|
||||
-- reserv1_out : out std_logic_vector(31 downto 0);
|
||||
-- dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
-- dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
-- idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
-- dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
-- phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
-- phase_off_out : out std_logic_vector(31 downto 0);
|
||||
-- swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
--
|
||||
-- cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
-- pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
-- m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
-- dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
--
|
||||
--
|
||||
-- S_AXI_ACLK : in std_logic;
|
||||
-- S_AXI_ARESETN : in std_logic;
|
||||
-- S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- S_AXI_AWVALID : in std_logic;
|
||||
-- S_AXI_AWREADY : out std_logic;
|
||||
-- S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- S_AXI_WVALID : in std_logic;
|
||||
-- S_AXI_WREADY : out std_logic;
|
||||
-- S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- S_AXI_BVALID : out std_logic;
|
||||
-- S_AXI_BREADY : in std_logic;
|
||||
-- S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- S_AXI_ARVALID : in std_logic;
|
||||
-- S_AXI_ARREADY : out std_logic;
|
||||
-- S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- S_AXI_RVALID : out std_logic;
|
||||
-- S_AXI_RREADY : in std_logic
|
||||
-- );
|
||||
-- end component dds_pulse_intfc_v1_0_S00_AXI;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal cmd_send_cnt : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rden_cnt : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dac_data_src_sel : std_logic;
|
||||
signal m_axis_tdata_i : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid_i : std_logic;
|
||||
signal m_axis_tready_i : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
|
||||
MINOR_REV => MINOR_REV,
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
cmd_idx_out => cmd_idx,
|
||||
cmd_send_out => cmd_send,
|
||||
|
||||
mode_out => mode,
|
||||
scale_out => scale,
|
||||
dac_holdoff_out => dac_holdoff,
|
||||
|
||||
reserv1_out => reserv1,
|
||||
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_out => dds_phase_inc_step_size,
|
||||
idle_samples_out => idle_samples,
|
||||
dds_samples_out => dds_samples,
|
||||
phase_inc_out => phase_inc,
|
||||
phase_off_out => phase_off,
|
||||
swap_sf_out => swap_sf,
|
||||
dac_data_src_sel_out => dac_data_src_sel,
|
||||
|
||||
cmd_send_cnt_in => cmd_send_cnt,
|
||||
pipe_in_ch1_fifo_rden_cnt_in => pipe_in_ch1_fifo_rden_cnt,
|
||||
m_axis_tvalid_cnt_in => m_axis_tvalid_cnt,
|
||||
dds_pulse_data_cnt_in => dds_pulse_data_cnt,
|
||||
|
||||
|
||||
S_AXI_ACLK => s00_axi_aclk,
|
||||
S_AXI_ARESETN => s00_axi_aresetn,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
-- Add user logic here
|
||||
i_dds_pulse_wrapper : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
SIM_ENABLED => FALSE,
|
||||
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
|
||||
MINOR_REV => MINOR_REV
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s00_axi_aclk,
|
||||
s_axi_aresetn_in => s00_axi_aresetn,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
mode_in => mode,
|
||||
scale_in => scale,
|
||||
dac_holdoff_in => dac_holdoff,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk,
|
||||
m_axis_tdata_out => m_axis_tdata_i,
|
||||
m_axis_tvalid_out => m_axis_tvalid_i,
|
||||
m_axis_tready_in => m_axis_tready_i,
|
||||
|
||||
cmd_send_cnt_out => cmd_send_cnt,
|
||||
pipe_in_ch1_fifo_rden_cnt_out => pipe_in_ch1_fifo_rden_cnt,
|
||||
m_axis_tvalid_cnt_out => m_axis_tvalid_cnt,
|
||||
dds_pulse_data_cnt_out => dds_pulse_data_cnt,
|
||||
|
||||
reset_in => reset
|
||||
);
|
||||
|
||||
m_axis_tdata <= m_axis_tdata_i when dac_data_src_sel = '1' else s00_axis_tdata;
|
||||
m_axis_tvalid <= m_axis_tvalid_i when dac_data_src_sel = '1' else s00_axis_tvalid;
|
||||
|
||||
m_axis_tready_i <= m_axis_tready when dac_data_src_sel = '1' else '0';
|
||||
s00_axis_tready <= m_axis_tready when dac_data_src_sel = '0' else '0';
|
||||
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,601 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_pulse_intfc_v1_0_S00_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 6
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_send_out : out std_logic;
|
||||
|
||||
mode_out : out std_logic;
|
||||
scale_out : out std_logic_vector(15 downto 0);
|
||||
dac_holdoff_out : out std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
dac_data_src_sel_out : out std_logic;
|
||||
|
||||
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end dds_pulse_intfc_v1_0_S00_AXI;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0_S00_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 3;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 16
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"0000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"0111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"1111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"0000" =>
|
||||
reg_data_out <= dds_pulse_data_cnt_in; --slv_reg0;
|
||||
when b"0001" =>
|
||||
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
|
||||
when b"0010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"0011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"0100" =>
|
||||
reg_data_out <= slv_reg4;
|
||||
when b"0101" =>
|
||||
reg_data_out <= slv_reg5;
|
||||
when b"0110" =>
|
||||
reg_data_out <= slv_reg6;
|
||||
when b"0111" =>
|
||||
reg_data_out <= slv_reg7;
|
||||
when b"1000" =>
|
||||
reg_data_out <= slv_reg8;
|
||||
when b"1001" =>
|
||||
reg_data_out <= slv_reg9;
|
||||
when b"1010" =>
|
||||
reg_data_out <= slv_reg10;
|
||||
when b"1011" =>
|
||||
reg_data_out <= slv_reg11;
|
||||
when b"1100" =>
|
||||
reg_data_out <= slv_reg12;
|
||||
when b"1101" =>
|
||||
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in(15 downto 0) & cmd_send_cnt_in(15 downto 0); -- slv_reg13;
|
||||
when b"1110" =>
|
||||
reg_data_out <= m_axis_tvalid_cnt_in; --slv_reg14
|
||||
when b"1111" =>
|
||||
reg_data_out <= FPGA_REVISION_DATE; --slv_reg15;
|
||||
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if (slv_reg0(0) = '1') then
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cmd_send_out <= cmd_send_r(0);
|
||||
dac_holdoff_out <= slv_reg1(0);
|
||||
|
||||
cmd_idx_out <= slv_reg2(2 downto 0);
|
||||
|
||||
scale_out <= slv_reg3(15 downto 0);
|
||||
mode_out <= slv_reg4(0);
|
||||
dac_data_src_sel_out <= slv_reg4(31);
|
||||
|
||||
reserv1_out <= slv_reg5;
|
||||
dds_phase_inc_dwell_time_out <= slv_reg6;
|
||||
dds_phase_inc_step_size_out <= slv_reg7;
|
||||
idle_samples_out <= slv_reg8;
|
||||
dds_samples_out <= slv_reg9;
|
||||
phase_inc_out <= slv_reg10;
|
||||
phase_off_out <= slv_reg11;
|
||||
swap_sf_out <= slv_reg12;
|
||||
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
+228
@@ -0,0 +1,228 @@
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|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
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||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEMORY_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "511", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,219 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
vio_reserv1_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
vio_idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
vio_dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
vio_phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
vio_phase_off_in : in std_logic_vector(31 downto 0);
|
||||
vio_swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 4 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
|
||||
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
|
||||
--
|
||||
-- Phase Inc Start = 2^32 * (1/250) = 17179869
|
||||
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
|
||||
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
|
||||
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
|
||||
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
|
||||
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
|
||||
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
|
||||
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
|
||||
--
|
||||
|
||||
|
||||
signal dds_command_set : dds_command_list(0 to 4) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
|
||||
1 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
2 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
-- x"000FFFFF", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
|
||||
3 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
|
||||
x"000000FF", --IDLE_SAMPLES
|
||||
x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
),
|
||||
-- WFM 4
|
||||
-- ??????
|
||||
4 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"00000000", --DDS_SAMPLES (~5 us)
|
||||
x"00000000", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
)
|
||||
);
|
||||
|
||||
|
||||
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
dds_command_set(4)(0) <= vio_reserv1_in;
|
||||
dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in;
|
||||
dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in;
|
||||
dds_command_set(4)(3) <= vio_idle_samples_in;
|
||||
dds_command_set(4)(4) <= vio_dds_samples_in;
|
||||
dds_command_set(4)(5) <= vio_phase_inc_in;
|
||||
dds_command_set(4)(6) <= vio_phase_off_in;
|
||||
dds_command_set(4)(7) <= vio_swap_sf_in;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
-- if (rst_in = '1') then
|
||||
-- cmd_idx_r <= 0;
|
||||
-- cmd_send_r <= '0';
|
||||
-- fifo_wr_en_r <= '0';
|
||||
-- state_cnt_r <= 0;
|
||||
-- state_r <= IDLE;
|
||||
-- else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state_r <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = DONE else
|
||||
"11";
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_1 : entity work.ila_2
|
||||
port map (
|
||||
clk => clk_in,
|
||||
probe0 => test_state_r, -- 2
|
||||
probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
|
||||
probe2 => fifo_wr_data_r, -- 32
|
||||
probe3(0) => fifo_wr_en_r, -- 1
|
||||
probe4(0) => cmd_send_in, -- 1
|
||||
probe5(0) => cmd_send_r -- 1
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,366 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"cell_name": "i_dds_pulse_wrapper/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": "../../../../../../aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/dds_latency10",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "aclken" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,419 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
holdoff_r <= holdoff_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,415 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_latency10
|
||||
port(
|
||||
-- ce : in std_logic;
|
||||
-- clk : in std_logic;
|
||||
-- sclr : in std_logic;
|
||||
-- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- rdy : out std_logic;
|
||||
-- cosine : out std_logic_vector(15 downto 0);
|
||||
-- sine : out std_logic_vector(15 downto 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0);
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0);
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0);
|
||||
signal phase_offset_r : std_logic_vector(31 downto 0);
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
phase_offset_r <= fifo_data_r(223 downto 192);
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
phase_inc_r1 <= phase_inc_r;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data(31 downto 0)
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,606 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_wrapper is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE;
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
|
||||
);
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
mode_in : in std_logic;
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m_axis_tvalid_out : out std_logic;
|
||||
m_axis_tready_in : in std_logic;
|
||||
|
||||
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper;
|
||||
|
||||
architecture imp of dds_pulse_wrapper is
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal s_axi_areset : std_logic;
|
||||
|
||||
signal s_axis_tready : std_logic;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
signal m_axis_tdata : std_logic_vector(63 downto 0);
|
||||
signal m_axis_tvalid : std_logic;
|
||||
|
||||
signal pulse_data_word_r : std_logic_vector(63 downto 0) := (others => '0');
|
||||
signal pulse_data_word_dval_r : std_logic := '0';
|
||||
|
||||
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal vio_cmd_send : std_logic;
|
||||
|
||||
signal vio_mode : std_logic;
|
||||
signal vio_scale : std_logic_vector(15 downto 0);
|
||||
signal vio_dac_holdoff : std_logic;
|
||||
|
||||
signal vio_reserv1 : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_reserv1 : signal is "true";
|
||||
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
|
||||
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
|
||||
signal vio_idle_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_idle_samples : signal is "true";
|
||||
signal vio_dds_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_samples : signal is "true";
|
||||
signal vio_phase_inc : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_inc : signal is "true";
|
||||
signal vio_phase_off : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_off : signal is "true";
|
||||
signal vio_swap_sf : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_swap_sf : signal is "true";
|
||||
|
||||
signal vio_enable : std_logic;
|
||||
signal vio_cnt_rst : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m_axis_tvalid_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- file DataFile : text;
|
||||
|
||||
signal read_toggle_r : std_logic := '0';
|
||||
signal dds_m_axis_tready : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_send_cnt_out <= cmd_send_cnt_r;
|
||||
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
|
||||
m_axis_tvalid_cnt_out <= m_axis_tvalid_cnt_r;
|
||||
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
|
||||
|
||||
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
|
||||
reset_n <= not reset_in; -- synchronous with m_axis_aclk_in
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_vio_0 : entity work.vio_0
|
||||
port map (
|
||||
clk => s_axi_aclk_in,
|
||||
probe_in0 => fpga_revision_date_r, -- 32
|
||||
probe_in1 => minor_rev_r, -- 8
|
||||
probe_in2 => m_axis_aclk_freq_r, -- 32
|
||||
probe_in3 => m_axis_aclk_cnt_r , -- 32
|
||||
probe_in4 => s_axi_aclk_freq_r, -- 32
|
||||
probe_in5 => s_axi_aclk_cnt_r , -- 32
|
||||
probe_in6 => dds_pulse_data_overflow_cnt_r,
|
||||
|
||||
probe_out0(0) => vio_mode, -- 1
|
||||
probe_out1 => vio_scale, -- 16
|
||||
probe_out2 => vio_cmd_idx, -- 3
|
||||
probe_out3(0) => vio_cmd_send, -- 1
|
||||
probe_out4(0) => vio_dac_holdoff, -- 1
|
||||
|
||||
probe_out5 => vio_reserv1, -- 32
|
||||
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
|
||||
probe_out7 => vio_dds_phase_inc_step_size, -- 32
|
||||
probe_out8 => vio_idle_samples, -- 32
|
||||
probe_out9 => vio_dds_samples, -- 32
|
||||
probe_out10 => vio_phase_inc, -- 32
|
||||
probe_out11 => vio_phase_off, -- 32
|
||||
probe_out12 => vio_swap_sf, -- 32
|
||||
probe_out13 => vio_enable, -- 1
|
||||
probe_out14 => vio_cnt_rst -- 1
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
mode <= vio_mode when vio_enable = '1' else mode_in;
|
||||
scale <= vio_scale when vio_enable = '1' else scale_in;
|
||||
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
|
||||
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
|
||||
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
|
||||
|
||||
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
|
||||
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
|
||||
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
|
||||
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
|
||||
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
|
||||
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
|
||||
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
|
||||
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
|
||||
|
||||
|
||||
-- mode <= vio_mode;
|
||||
-- scale <= vio_scale;
|
||||
-- dac_holdoff <= vio_dac_holdoff;
|
||||
-- cmd_idx <= vio_cmd_idx;
|
||||
-- cmd_send <= vio_cmd_send;
|
||||
--
|
||||
-- reserv1 <= vio_reserv1;
|
||||
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
|
||||
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
|
||||
-- idle_samples <= vio_idle_samples;
|
||||
-- dds_samples <= vio_dds_samples;
|
||||
-- phase_inc <= vio_phase_inc;
|
||||
-- phase_off <= vio_phase_off;
|
||||
-- swap_sf <= vio_swap_sf;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
cmd_send_r <= cmd_send;
|
||||
if (cmd_send = '1' and cmd_send_r = '0') then
|
||||
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
generic map (
|
||||
SIM_ENABLED => SIM_ENABLED
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
vio_reserv1_in => reserv1,
|
||||
vio_dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
vio_dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
vio_idle_samples_in => idle_samples,
|
||||
vio_dds_samples_in => dds_samples,
|
||||
vio_phase_inc_in => phase_inc,
|
||||
vio_phase_off_in => phase_off,
|
||||
vio_swap_sf_in => swap_sf,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => s_axi_areset
|
||||
);
|
||||
|
||||
sim_false1 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_4 : entity work.ila_4
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
);
|
||||
end generate sim_false1;
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => reset_in,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
pulse_i <= dds_pulse_data(15 downto 0);
|
||||
pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
-- process(m_axis_aclk_in)
|
||||
-- variable LineOut : line;
|
||||
-- begin
|
||||
-- if (rising_edge(m_axis_aclk_in)) then
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- hwrite(LineOut, dds_pulse_data);
|
||||
-- writeline(DataFile, LineOut);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process(m_axis_aclk_in, vio_cnt_rst)
|
||||
begin
|
||||
if(vio_cnt_rst = '1') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
m_axis_tvalid_cnt_r <= (others => '0');
|
||||
dds_pulse_data_overflow_cnt_r <= (others => '0');
|
||||
elsif (rising_edge(m_axis_aclk_in)) then
|
||||
if (pulse_data_word_dval_r = '1' and s_axis_tready = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (pulse_data_word_dval_r = '1' and s_axis_tready = '0') then
|
||||
dds_pulse_data_overflow_cnt_r <= dds_pulse_data_overflow_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (pipe_in_ch1_fifo_rden = '1') then
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (m_axis_tvalid = '1' and m_axis_tready_in = '1') then
|
||||
m_axis_tvalid_cnt_r <= m_axis_tvalid_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sim_false2 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_3 : entity work.ila_3
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => dds_pulse_data(15 downto 0),
|
||||
probe1 => dds_pulse_data(31 downto 16),
|
||||
probe2(0) => dds_pulse_dval,
|
||||
probe3(0) => s_axis_tready
|
||||
);
|
||||
end generate sim_false2;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
pulse_data_word_dval_r <= '0';
|
||||
if (dds_pulse_dval = '1') then
|
||||
read_toggle_r <= not read_toggle_r;
|
||||
if (read_toggle_r = '0') then
|
||||
pulse_data_word_r(31 downto 0) <= dds_pulse_data;
|
||||
else
|
||||
pulse_data_word_r(63 downto 32) <= dds_pulse_data;
|
||||
pulse_data_word_dval_r <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- this FIFO is actually 32K by 64
|
||||
i_fifo : entity work.axis_data_fifo_512x128
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk_in,
|
||||
s_axis_aresetn => reset_n,
|
||||
|
||||
s_axis_tdata => pulse_data_word_r, ---dds_pulse_data,
|
||||
s_axis_tvalid => pulse_data_word_dval_r, --dds_pulse_dval,
|
||||
s_axis_tready => s_axis_tready,
|
||||
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tready => m_axis_tready_in
|
||||
);
|
||||
|
||||
m_axis_tdata_out <= m_axis_tdata & m_axis_tdata;--- & m_axis_tdata & m_axis_tdata;
|
||||
m_axis_tvalid_out <= m_axis_tvalid;
|
||||
|
||||
-- dds_m_axis_tready <= '1' when read_toggle_r = '0' and m_axis_tready_in = '1' else '0';
|
||||
--
|
||||
-- process(m_axis_aclk_in)
|
||||
-- begin
|
||||
-- if (rising_edge(m_axis_aclk_in)) then
|
||||
-- if (m_axis_tready_in = '1') then
|
||||
-- read_toggle_r <= not read_toggle_r;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
|
||||
sim_false3 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_2 : entity work.ila_0
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => m_axis_tdata(15 downto 0), -- 16
|
||||
probe1 => m_axis_tdata(31 downto 16), -- 16
|
||||
probe2 => m_axis_tdata(47 downto 32), -- 16
|
||||
probe3 => m_axis_tdata(63 downto 48), -- 16
|
||||
-- probe4 => m_axis_tdata(79 downto 64), -- 16
|
||||
-- probe5 => m_axis_tdata(95 downto 80), -- 16
|
||||
-- probe6 => m_axis_tdata(111 downto 96), -- 16
|
||||
-- probe7 => m_axis_tdata(127 downto 112), -- 16
|
||||
probe4(0) => m_axis_tvalid, -- 1
|
||||
probe5(0) => m_axis_tready_in -- 1
|
||||
);
|
||||
end generate sim_false3;
|
||||
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => reset_in
|
||||
);
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
|
||||
m_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
|
||||
s_axi_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
sim_true : if (SIM_ENABLED = TRUE) generate
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
|
||||
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
|
||||
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 1 ns;
|
||||
vio_mode <= '0';
|
||||
vio_scale <= x"8000";
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '0';
|
||||
vio_dac_holdoff <= '1';
|
||||
vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
|
||||
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
|
||||
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
|
||||
vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
vio_enable <= '1';
|
||||
vio_cnt_rst <= '0';
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "011";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "001";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 0
|
||||
-- -- FREQUENCY SWEEP (UP-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "000";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "001";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
--
|
||||
-- -- WFM 2
|
||||
-- -- CW TONE
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "010";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_dac_holdoff <= '0';
|
||||
|
||||
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "011";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
-- wait for 100 ns;
|
||||
-- CW TONE
|
||||
-- vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
|
||||
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
|
||||
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
|
||||
-- vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "100";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for 5 us;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end generate sim_true;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+169
@@ -0,0 +1,169 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mult_16signed_x_16unsigned_latency3",
|
||||
"cell_name": "i_dds_pulse_wrapper/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_MEMORY_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "992", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "991", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"interfaces": {
|
||||
"core_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity tick_gen is
|
||||
generic(
|
||||
CLOCK_SPEED_MHZ : integer := 100
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
tick_1us_out : out std_logic;
|
||||
tick_1ms_out : out std_logic;
|
||||
tick_500ms_out : out std_logic;
|
||||
tick_750ms_out : out std_logic;
|
||||
tick_1s_out : out std_logic;
|
||||
|
||||
prog_us_tick_rate_in : in std_logic_vector(15 downto 0);
|
||||
prog_us_tick_out : out std_logic;
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity tick_gen;
|
||||
|
||||
architecture imp of tick_gen is
|
||||
|
||||
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
|
||||
signal usec_cnt_r : integer range 0 to 999;
|
||||
signal msec_cnt_r : integer range 0 to 499;
|
||||
signal msec_cnt1_r : integer range 0 to 999;
|
||||
signal tick_1us_r : std_logic;
|
||||
signal tick_1ms_r : std_logic;
|
||||
signal tick_500ms_r : std_logic;
|
||||
signal tick_750ms_r : std_logic;
|
||||
signal tick_1s_r : std_logic;
|
||||
|
||||
signal prog_usec_cnt_r : std_logic_vector(15 downto 0);
|
||||
signal prog_us_tick_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
tick_1us_out <= tick_1us_r;
|
||||
tick_1ms_out <= tick_1ms_r;
|
||||
tick_500ms_out <= tick_500ms_r;
|
||||
tick_750ms_out <= tick_750ms_r;
|
||||
tick_1s_out <= tick_1s_r;
|
||||
prog_us_tick_out <= prog_us_tick_r;
|
||||
|
||||
process(clk_in, reset_in)
|
||||
begin
|
||||
if(reset_in = '1') then
|
||||
sysclk_cnt_r <= 0;
|
||||
usec_cnt_r <= 0;
|
||||
msec_cnt_r <= 0;
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_us_tick_r <= '0';
|
||||
|
||||
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
|
||||
sysclk_cnt_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
else
|
||||
sysclk_cnt_r <= sysclk_cnt_r + 1;
|
||||
tick_1us_r <= '0';
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(usec_cnt_r = 999) then -- 1000us
|
||||
usec_cnt_r <= 0;
|
||||
tick_1ms_r <= '1';
|
||||
else
|
||||
usec_cnt_r <= usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt_r = 499) then -- 500ms
|
||||
msec_cnt_r <= 0;
|
||||
tick_500ms_r <= '1';
|
||||
else
|
||||
msec_cnt_r <= msec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt1_r = 749) then -- 750ms
|
||||
tick_750ms_r <= '1';
|
||||
end if;
|
||||
if(msec_cnt1_r = 999) then -- 1s
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1s_r <= '1';
|
||||
else
|
||||
msec_cnt1_r <= msec_cnt1_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '1';
|
||||
else
|
||||
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,90 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
ipgui::add_param $IPINST -name "MINOR_REV"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to validate MINOR_REV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
proc init { cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
set full_sbusif_list [list ]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
||||
set busif_param_list [list]
|
||||
set busif_name [get_property NAME $busif]
|
||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
||||
continue
|
||||
}
|
||||
foreach tparam $axi_standard_param_list {
|
||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
||||
}
|
||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc pre_propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
if { $val_on_cell != "" } {
|
||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
||||
if { $val_on_cell_intf_pin != "" } {
|
||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,757 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pdw_generator_v1_0_S00_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_send_out : out std_logic;
|
||||
|
||||
mode_out : out std_logic;
|
||||
scale_out : out std_logic_vector(15 downto 0);
|
||||
dac_holdoff_out : out std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
latch_en_out : out std_logic;
|
||||
|
||||
loop_mode_en_out : out std_logic_vector( 7 downto 0);
|
||||
trigger_mode_out : out std_logic_vector( 1 downto 0);
|
||||
prog_us_tick_out : out std_logic_vector(31 downto 0);
|
||||
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_done_in : in std_logic;
|
||||
|
||||
fpga_reboot_out : out std_logic;
|
||||
|
||||
dac_data_src_sel_out : out std_logic;
|
||||
d_frmt_out : out std_logic_vector(1 downto 0);
|
||||
|
||||
slv_reg19_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg20_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg21_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg22_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
dds_reset_out : out std_logic;
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end pdw_generator_v1_0_S00_AXI;
|
||||
|
||||
architecture arch_imp of pdw_generator_v1_0_S00_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 4;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 24
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal dds_reset_r : std_logic_vector(0 to 15) := (others => '0');
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
slv_reg16 <= (others => '0');
|
||||
slv_reg17 <= (others => '0');
|
||||
slv_reg18 <= (others => '0');
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg4(16) <= '0'; -- self clear bit 16
|
||||
slv_reg3(31) <= '0'; -- self clear bit 31
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"00001" =>
|
||||
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
|
||||
when b"00010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"00011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"00100" =>
|
||||
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
|
||||
when b"00101" =>
|
||||
reg_data_out <= reserv1_in; -- slv_reg5;
|
||||
when b"00110" =>
|
||||
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
|
||||
when b"00111" =>
|
||||
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
|
||||
when b"01000" =>
|
||||
reg_data_out <= idle_samples_in; -- slv_reg8;
|
||||
when b"01001" =>
|
||||
reg_data_out <= dds_samples_in; -- slv_reg9;
|
||||
when b"01010" =>
|
||||
reg_data_out <= phase_inc_in; -- slv_reg10;
|
||||
when b"01011" =>
|
||||
reg_data_out <= phase_off_in; -- slv_reg11;
|
||||
when b"01100" =>
|
||||
reg_data_out <= swap_sf_in; -- slv_reg12;
|
||||
when b"01101" =>
|
||||
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
|
||||
when b"01110" =>
|
||||
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
|
||||
when b"01111" =>
|
||||
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
|
||||
when b"10000" =>
|
||||
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
|
||||
when b"10001" =>
|
||||
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
|
||||
when b"10010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"10011" =>
|
||||
reg_data_out <= slv_reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= slv_reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= slv_reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= slv_reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if (slv_reg0(0) = '1') then -- self clear bit 0
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
if (slv_reg3(31) = '1') then -- self clear bit 0
|
||||
dds_reset_r <= (others => '1');
|
||||
else
|
||||
dds_reset_r <= dds_reset_r(1 to 15) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
|
||||
-- <= slv_reg0(30 downto 1);
|
||||
fpga_reboot_out <= slv_reg0(31);
|
||||
|
||||
dac_holdoff_out <= slv_reg1(0);
|
||||
-- <= slv_reg1( 3 downto 1);
|
||||
cmd_idx_out <= slv_reg1( 6 downto 4);
|
||||
-- <= slv_reg1( 7);
|
||||
loop_mode_en_out <= slv_reg1(15 downto 8);
|
||||
d_frmt_out <= slv_reg1(17 downto 16);
|
||||
-- <= slv_reg1(31 downto 18);
|
||||
|
||||
prog_us_tick_out <= slv_reg2;
|
||||
|
||||
scale_out <= slv_reg3(15 downto 0);
|
||||
trigger_mode_out <= slv_reg3(17 downto 16);
|
||||
-- <= slv_reg3(30 downto 18);
|
||||
dds_reset_out <= dds_reset_r(0); -- self clear bit 0
|
||||
|
||||
mode_out <= slv_reg4(0);
|
||||
-- <= slv_reg4(15 downto 1);
|
||||
latch_en_out <= slv_reg4(16); -- self clear bit 0
|
||||
-- <= slv_reg4(30 downto 17);
|
||||
dac_data_src_sel_out <= slv_reg4(31);
|
||||
|
||||
reserv1_out <= slv_reg5;
|
||||
dds_phase_inc_dwell_time_out <= slv_reg6;
|
||||
dds_phase_inc_step_size_out <= slv_reg7;
|
||||
idle_samples_out <= slv_reg8;
|
||||
dds_samples_out <= slv_reg9;
|
||||
phase_inc_out <= slv_reg10;
|
||||
phase_off_out <= slv_reg11;
|
||||
swap_sf_out <= slv_reg12;
|
||||
|
||||
duration_ms_cnt_out <= slv_reg18;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,740 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pdw_generator_v1_0_S01_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_send_out : out std_logic;
|
||||
|
||||
mode_out : out std_logic;
|
||||
scale_out : out std_logic_vector(15 downto 0);
|
||||
dac_holdoff_out : out std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
latch_en_out : out std_logic;
|
||||
|
||||
loop_mode_en_out : out std_logic_vector( 7 downto 0);
|
||||
trigger_mode_out : out std_logic_vector( 1 downto 0);
|
||||
prog_us_tick_out : out std_logic_vector(31 downto 0);
|
||||
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_done_in : in std_logic;
|
||||
|
||||
slv_reg19_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg20_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg21_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg22_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end pdw_generator_v1_0_S01_AXI;
|
||||
|
||||
architecture arch_imp of pdw_generator_v1_0_S01_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 4;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 24
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
slv_reg16 <= (others => '0');
|
||||
slv_reg17 <= (others => '0');
|
||||
slv_reg18 <= (others => '0');
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg4(16) <= '0'; -- self clear bit 16
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"00001" =>
|
||||
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
|
||||
when b"00010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"00011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"00100" =>
|
||||
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
|
||||
when b"00101" =>
|
||||
reg_data_out <= reserv1_in; -- slv_reg5;
|
||||
when b"00110" =>
|
||||
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
|
||||
when b"00111" =>
|
||||
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
|
||||
when b"01000" =>
|
||||
reg_data_out <= idle_samples_in; -- slv_reg8;
|
||||
when b"01001" =>
|
||||
reg_data_out <= dds_samples_in; -- slv_reg9;
|
||||
when b"01010" =>
|
||||
reg_data_out <= phase_inc_in; -- slv_reg10;
|
||||
when b"01011" =>
|
||||
reg_data_out <= phase_off_in; -- slv_reg11;
|
||||
when b"01100" =>
|
||||
reg_data_out <= swap_sf_in; -- slv_reg12;
|
||||
when b"01101" =>
|
||||
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
|
||||
when b"01110" =>
|
||||
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
|
||||
when b"01111" =>
|
||||
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
|
||||
when b"10000" =>
|
||||
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
|
||||
when b"10001" =>
|
||||
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
|
||||
when b"10010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"10011" =>
|
||||
reg_data_out <= slv_reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= slv_reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= slv_reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= slv_reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if (slv_reg0(0) = '1') then -- self clear bit 0
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
|
||||
-- <= slv_reg0(30 downto 1);
|
||||
-- <= slv_reg0(31);
|
||||
|
||||
dac_holdoff_out <= slv_reg1(0);
|
||||
-- <= slv_reg1( 3 downto 1);
|
||||
cmd_idx_out <= slv_reg1( 6 downto 4);
|
||||
-- <= slv_reg1( 7);
|
||||
loop_mode_en_out <= slv_reg1(15 downto 8);
|
||||
-- <= slv_reg1(31 downto 16);
|
||||
|
||||
prog_us_tick_out <= slv_reg2;
|
||||
|
||||
scale_out <= slv_reg3(15 downto 0);
|
||||
trigger_mode_out <= slv_reg3(17 downto 16);
|
||||
-- <= slv_reg3(31 downto 18);
|
||||
|
||||
mode_out <= slv_reg4(0);
|
||||
-- <= slv_reg4(15 downto 1);
|
||||
latch_en_out <= slv_reg4(16); -- self clear bit 0
|
||||
-- <= slv_reg1(30 downto 17);
|
||||
-- <= slv_reg4(31);
|
||||
|
||||
reserv1_out <= slv_reg5;
|
||||
dds_phase_inc_dwell_time_out <= slv_reg6;
|
||||
dds_phase_inc_step_size_out <= slv_reg7;
|
||||
idle_samples_out <= slv_reg8;
|
||||
dds_samples_out <= slv_reg9;
|
||||
phase_inc_out <= slv_reg10;
|
||||
phase_off_out <= slv_reg11;
|
||||
swap_sf_out <= slv_reg12;
|
||||
|
||||
duration_ms_cnt_out <= slv_reg18;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,740 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pdw_generator_v1_0_S02_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_send_out : out std_logic;
|
||||
|
||||
mode_out : out std_logic;
|
||||
scale_out : out std_logic_vector(15 downto 0);
|
||||
dac_holdoff_out : out std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
latch_en_out : out std_logic;
|
||||
|
||||
loop_mode_en_out : out std_logic_vector( 7 downto 0);
|
||||
trigger_mode_out : out std_logic_vector( 1 downto 0);
|
||||
prog_us_tick_out : out std_logic_vector(31 downto 0);
|
||||
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_done_in : in std_logic;
|
||||
|
||||
slv_reg19_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg20_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg21_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg22_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end pdw_generator_v1_0_S02_AXI;
|
||||
|
||||
architecture arch_imp of pdw_generator_v1_0_S02_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 4;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 24
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
slv_reg16 <= (others => '0');
|
||||
slv_reg17 <= (others => '0');
|
||||
slv_reg18 <= (others => '0');
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg4(16) <= '0'; -- self clear bit 16
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"00001" =>
|
||||
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
|
||||
when b"00010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"00011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"00100" =>
|
||||
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
|
||||
when b"00101" =>
|
||||
reg_data_out <= reserv1_in; -- slv_reg5;
|
||||
when b"00110" =>
|
||||
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
|
||||
when b"00111" =>
|
||||
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
|
||||
when b"01000" =>
|
||||
reg_data_out <= idle_samples_in; -- slv_reg8;
|
||||
when b"01001" =>
|
||||
reg_data_out <= dds_samples_in; -- slv_reg9;
|
||||
when b"01010" =>
|
||||
reg_data_out <= phase_inc_in; -- slv_reg10;
|
||||
when b"01011" =>
|
||||
reg_data_out <= phase_off_in; -- slv_reg11;
|
||||
when b"01100" =>
|
||||
reg_data_out <= swap_sf_in; -- slv_reg12;
|
||||
when b"01101" =>
|
||||
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
|
||||
when b"01110" =>
|
||||
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
|
||||
when b"01111" =>
|
||||
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
|
||||
when b"10000" =>
|
||||
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
|
||||
when b"10001" =>
|
||||
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
|
||||
when b"10010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"10011" =>
|
||||
reg_data_out <= slv_reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= slv_reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= slv_reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= slv_reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if (slv_reg0(0) = '1') then -- self clear bit 0
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
|
||||
-- <= slv_reg0(30 downto 1);
|
||||
-- <= slv_reg0(31);
|
||||
|
||||
dac_holdoff_out <= slv_reg1(0);
|
||||
-- <= slv_reg1( 3 downto 1);
|
||||
cmd_idx_out <= slv_reg1( 6 downto 4);
|
||||
-- <= slv_reg1( 7);
|
||||
loop_mode_en_out <= slv_reg1(15 downto 8);
|
||||
-- <= slv_reg1(31 downto 16);
|
||||
|
||||
prog_us_tick_out <= slv_reg2;
|
||||
|
||||
scale_out <= slv_reg3(15 downto 0);
|
||||
trigger_mode_out <= slv_reg3(17 downto 16);
|
||||
-- <= slv_reg3(31 downto 18);
|
||||
|
||||
mode_out <= slv_reg4(0);
|
||||
-- <= slv_reg4(15 downto 1);
|
||||
latch_en_out <= slv_reg4(16); -- self clear bit 0
|
||||
-- <= slv_reg1(30 downto 17);
|
||||
-- <= slv_reg4(31);
|
||||
|
||||
reserv1_out <= slv_reg5;
|
||||
dds_phase_inc_dwell_time_out <= slv_reg6;
|
||||
dds_phase_inc_step_size_out <= slv_reg7;
|
||||
idle_samples_out <= slv_reg8;
|
||||
dds_samples_out <= slv_reg9;
|
||||
phase_inc_out <= slv_reg10;
|
||||
phase_off_out <= slv_reg11;
|
||||
swap_sf_out <= slv_reg12;
|
||||
|
||||
duration_ms_cnt_out <= slv_reg18;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,739 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pdw_generator_v1_0_S03_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
cmd_idx_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_send_out : out std_logic;
|
||||
|
||||
mode_out : out std_logic;
|
||||
scale_out : out std_logic_vector(15 downto 0);
|
||||
dac_holdoff_out : out std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
latch_en_out : out std_logic;
|
||||
|
||||
loop_mode_en_out : out std_logic_vector( 7 downto 0);
|
||||
trigger_mode_out : out std_logic_vector( 1 downto 0);
|
||||
prog_us_tick_out : out std_logic_vector(31 downto 0);
|
||||
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
|
||||
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dds_done_in : in std_logic;
|
||||
|
||||
slv_reg19_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg20_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg21_in : in std_logic_vector(31 downto 0);
|
||||
slv_reg22_in : in std_logic_vector(31 downto 0);
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end pdw_generator_v1_0_S03_AXI;
|
||||
|
||||
architecture arch_imp of pdw_generator_v1_0_S03_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 4;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 24
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
slv_reg16 <= (others => '0');
|
||||
slv_reg17 <= (others => '0');
|
||||
slv_reg18 <= (others => '0');
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg4(16) <= '0'; -- self clear bit 16
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"00001" =>
|
||||
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
|
||||
when b"00010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"00011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"00100" =>
|
||||
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
|
||||
when b"00101" =>
|
||||
reg_data_out <= reserv1_in; -- slv_reg5;
|
||||
when b"00110" =>
|
||||
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
|
||||
when b"00111" =>
|
||||
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
|
||||
when b"01000" =>
|
||||
reg_data_out <= idle_samples_in; -- slv_reg8;
|
||||
when b"01001" =>
|
||||
reg_data_out <= dds_samples_in; -- slv_reg9;
|
||||
when b"01010" =>
|
||||
reg_data_out <= phase_inc_in; -- slv_reg10;
|
||||
when b"01011" =>
|
||||
reg_data_out <= phase_off_in; -- slv_reg11;
|
||||
when b"01100" =>
|
||||
reg_data_out <= swap_sf_in; -- slv_reg12;
|
||||
when b"01101" =>
|
||||
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
|
||||
when b"01110" =>
|
||||
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
|
||||
when b"01111" =>
|
||||
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
|
||||
when b"10000" =>
|
||||
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
|
||||
when b"10001" =>
|
||||
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
|
||||
when b"10010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"10011" =>
|
||||
reg_data_out <= slv_reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= slv_reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= slv_reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= slv_reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if (slv_reg0(0) = '1') then -- self clear bit 0
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
|
||||
-- <= slv_reg0(30 downto 1);
|
||||
-- <= slv_reg0(31);
|
||||
|
||||
dac_holdoff_out <= slv_reg1(0);
|
||||
-- <= slv_reg1( 3 downto 1);
|
||||
cmd_idx_out <= slv_reg1( 6 downto 4);
|
||||
-- <= slv_reg1( 7);
|
||||
loop_mode_en_out <= slv_reg1(15 downto 8);
|
||||
-- <= slv_reg1(31 downto 16);
|
||||
|
||||
prog_us_tick_out <= slv_reg2;
|
||||
|
||||
scale_out <= slv_reg3(15 downto 0);
|
||||
trigger_mode_out <= slv_reg3(17 downto 16);
|
||||
-- <= slv_reg3(31 downto 18);
|
||||
|
||||
mode_out <= slv_reg4(0);
|
||||
-- <= slv_reg4(15 downto 1);
|
||||
latch_en_out <= slv_reg4(16); -- self clear bit 0
|
||||
-- <= slv_reg1(30 downto 17);
|
||||
-- <= slv_reg4(31);
|
||||
|
||||
reserv1_out <= slv_reg5;
|
||||
dds_phase_inc_dwell_time_out <= slv_reg6;
|
||||
dds_phase_inc_step_size_out <= slv_reg7;
|
||||
idle_samples_out <= slv_reg8;
|
||||
dds_samples_out <= slv_reg9;
|
||||
phase_inc_out <= slv_reg10;
|
||||
phase_off_out <= slv_reg11;
|
||||
swap_sf_out <= slv_reg12;
|
||||
|
||||
duration_ms_cnt_out <= slv_reg18;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "adder_16signed_16signed_latency2",
|
||||
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_pulse_adder1",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ],
|
||||
"Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Add_Mode": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
|
||||
"Out_Width": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Automatic", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Constant": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
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||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "511", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MSGON_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RST_SYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EN_SAFETY_CKT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ERROR_INJECTION_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_AXI_WR_CHANNEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"port_maps": {
|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,176 @@
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "master",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,176 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_512x128",
|
||||
"cell_name": "i_fifo_out",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/axis_data_fifo_512x128",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32768", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_512x128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "9" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/axis_data_fifo_512x128" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,286 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
busy_out : out std_logic;
|
||||
|
||||
latch_en_in : in std_logic;
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal latch_en_r : std_logic := '0';
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 7 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
|
||||
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
|
||||
--
|
||||
-- Phase Inc Start = 2^32 * (1/250) = 17179869
|
||||
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
|
||||
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
|
||||
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
|
||||
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
|
||||
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
|
||||
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
|
||||
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
|
||||
--
|
||||
|
||||
|
||||
signal dds_command_set : dds_command_list(0 to 7) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
|
||||
1 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"FFFEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
2 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
|
||||
3 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
|
||||
x"000000FF", --IDLE_SAMPLES
|
||||
x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 4
|
||||
-- ??????
|
||||
4 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 5
|
||||
-- ??????
|
||||
5 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 6
|
||||
-- ??????
|
||||
6 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
),
|
||||
-- WFM 7
|
||||
-- ??????
|
||||
7 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us)
|
||||
x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
|
||||
)
|
||||
|
||||
);
|
||||
|
||||
|
||||
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal busy_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
latch_en_r <= latch_en_in;
|
||||
if (latch_en_in = '1' and latch_en_r = '0') then
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(0) <= reserv1_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(1) <= dds_phase_inc_dwell_time_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(2) <= dds_phase_inc_step_size_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(3) <= idle_samples_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(4) <= dds_samples_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(5) <= phase_inc_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(6) <= phase_off_in;
|
||||
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(7) <= swap_sf_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reserv1_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(0);
|
||||
dds_phase_inc_dwell_time_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(1);
|
||||
dds_phase_inc_step_size_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(2);
|
||||
idle_samples_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(3);
|
||||
dds_samples_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(4);
|
||||
phase_inc_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(5);
|
||||
phase_off_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(6);
|
||||
swap_sf_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(7);
|
||||
busy_out <= busy_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
-- if (rst_in = '1') then
|
||||
-- cmd_idx_r <= 0;
|
||||
-- cmd_send_r <= '0';
|
||||
-- fifo_wr_en_r <= '0';
|
||||
-- state_cnt_r <= 0;
|
||||
-- state_r <= IDLE;
|
||||
-- else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
busy_r <= '1';
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
busy_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state_r <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = DONE else
|
||||
"11";
|
||||
|
||||
-- sim_false_ila_2 : if (SIM_ENABLED = FALSE) generate
|
||||
-- i_ila_2 : entity work.ila_2
|
||||
-- port map (
|
||||
-- clk => clk_in,
|
||||
-- probe0 => test_state_r, -- 2
|
||||
-- probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
|
||||
-- probe2 => fifo_wr_data_r, -- 32
|
||||
-- probe3(0) => fifo_wr_en_r, -- 1
|
||||
-- probe4(0) => cmd_send_in, -- 1
|
||||
-- probe5(0) => cmd_send_r -- 1
|
||||
-- );
|
||||
-- end generate sim_false_ila_2;
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,366 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/dds_latency10",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "aclken" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,432 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic;
|
||||
done_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
signal done_r : std_logic_vector(0 to 7) := (others => '0');
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse1_fifo_empty_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
done_out <= done_r(0);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
-- holdoff_r <= holdoff_in;
|
||||
pulse1_fifo_empty_r <= pulse1_fifo_empty;
|
||||
done_r <= done_r(1 to 7) &'0';
|
||||
if (holdoff_in = '0' and pulse1_fifo_empty = '0') then
|
||||
holdoff_r <= '0';
|
||||
elsif(pulse1_fifo_empty_r = '0' and pulse1_fifo_empty = '1') then -- rising_edge of pulse1_fifo_empty
|
||||
holdoff_r <= '1';
|
||||
done_r <= (others => '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,415 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_latency10
|
||||
port(
|
||||
-- ce : in std_logic;
|
||||
-- clk : in std_logic;
|
||||
-- sclr : in std_logic;
|
||||
-- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- rdy : out std_logic;
|
||||
-- cosine : out std_logic_vector(15 downto 0);
|
||||
-- sine : out std_logic_vector(15 downto 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0);
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0);
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0);
|
||||
signal phase_offset_r : std_logic_vector(31 downto 0);
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
phase_offset_r <= fifo_data_r(223 downto 192);
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
phase_inc_r1 <= phase_inc_r;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data(31 downto 0)
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,520 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_wrapper_x4 is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE;
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
|
||||
);
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
mode_in : in std_logic;
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
dds_pulse_data_out : out std_logic_vector(31 downto 0);
|
||||
dds_pulse_dval_out : out std_logic;
|
||||
|
||||
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper_x4;
|
||||
|
||||
architecture imp of dds_pulse_wrapper_x4 is
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal s_axi_areset : std_logic;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal vio_cmd_send : std_logic;
|
||||
|
||||
signal vio_mode : std_logic;
|
||||
signal vio_scale : std_logic_vector(15 downto 0);
|
||||
signal vio_dac_holdoff : std_logic;
|
||||
|
||||
signal vio_reserv1 : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_reserv1 : signal is "true";
|
||||
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
|
||||
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
|
||||
signal vio_idle_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_idle_samples : signal is "true";
|
||||
signal vio_dds_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_samples : signal is "true";
|
||||
signal vio_phase_inc : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_inc : signal is "true";
|
||||
signal vio_phase_off : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_off : signal is "true";
|
||||
signal vio_swap_sf : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_swap_sf : signal is "true";
|
||||
|
||||
signal vio_enable : std_logic;
|
||||
signal vio_cnt_rst : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- file DataFile : text;
|
||||
|
||||
signal dds_m_axis_tready : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cmd_send_cnt_out <= cmd_send_cnt_r;
|
||||
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
|
||||
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
|
||||
|
||||
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sim_false : if (SIM_ENABLED = FALSE) generate
|
||||
i_vio_0 : entity work.vio_0
|
||||
port map (
|
||||
clk => s_axi_aclk_in,
|
||||
probe_in0 => fpga_revision_date_r, -- 32
|
||||
probe_in1 => minor_rev_r, -- 8
|
||||
probe_in2 => m_axis_aclk_freq_r, -- 32
|
||||
probe_in3 => m_axis_aclk_cnt_r , -- 32
|
||||
probe_in4 => s_axi_aclk_freq_r, -- 32
|
||||
probe_in5 => s_axi_aclk_cnt_r , -- 32
|
||||
probe_in6 => dds_pulse_data_overflow_cnt_r,
|
||||
|
||||
probe_out0(0) => vio_mode, -- 1
|
||||
probe_out1 => vio_scale, -- 16
|
||||
probe_out2 => vio_cmd_idx, -- 3
|
||||
probe_out3(0) => vio_cmd_send, -- 1
|
||||
probe_out4(0) => vio_dac_holdoff, -- 1
|
||||
|
||||
probe_out5 => vio_reserv1, -- 32
|
||||
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
|
||||
probe_out7 => vio_dds_phase_inc_step_size, -- 32
|
||||
probe_out8 => vio_idle_samples, -- 32
|
||||
probe_out9 => vio_dds_samples, -- 32
|
||||
probe_out10 => vio_phase_inc, -- 32
|
||||
probe_out11 => vio_phase_off, -- 32
|
||||
probe_out12 => vio_swap_sf, -- 32
|
||||
probe_out13 => vio_enable, -- 1
|
||||
probe_out14 => vio_cnt_rst -- 1
|
||||
);
|
||||
end generate sim_false;
|
||||
|
||||
mode <= vio_mode when vio_enable = '1' else mode_in;
|
||||
scale <= vio_scale when vio_enable = '1' else scale_in;
|
||||
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
|
||||
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
|
||||
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
|
||||
|
||||
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
|
||||
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
|
||||
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
|
||||
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
|
||||
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
|
||||
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
|
||||
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
|
||||
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
|
||||
|
||||
|
||||
-- mode <= vio_mode;
|
||||
-- scale <= vio_scale;
|
||||
-- dac_holdoff <= vio_dac_holdoff;
|
||||
-- cmd_idx <= vio_cmd_idx;
|
||||
-- cmd_send <= vio_cmd_send;
|
||||
--
|
||||
-- reserv1 <= vio_reserv1;
|
||||
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
|
||||
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
|
||||
-- idle_samples <= vio_idle_samples;
|
||||
-- dds_samples <= vio_dds_samples;
|
||||
-- phase_inc <= vio_phase_inc;
|
||||
-- phase_off <= vio_phase_off;
|
||||
-- swap_sf <= vio_swap_sf;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
cmd_send_r <= cmd_send;
|
||||
if (cmd_send = '1' and cmd_send_r = '0') then
|
||||
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
generic map (
|
||||
SIM_ENABLED => SIM_ENABLED
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
vio_reserv1_in => reserv1,
|
||||
vio_dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
vio_dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
vio_idle_samples_in => idle_samples,
|
||||
vio_dds_samples_in => dds_samples,
|
||||
vio_phase_inc_in => phase_inc,
|
||||
vio_phase_off_in => phase_off,
|
||||
vio_swap_sf_in => swap_sf,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => s_axi_areset
|
||||
);
|
||||
|
||||
sim_false1 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_4 : entity work.ila_4
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
);
|
||||
end generate sim_false1;
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => reset_in,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
pulse_i <= dds_pulse_data(15 downto 0);
|
||||
pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
-- process(m_axis_aclk_in)
|
||||
-- variable LineOut : line;
|
||||
-- begin
|
||||
-- if (rising_edge(m_axis_aclk_in)) then
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- hwrite(LineOut, dds_pulse_data);
|
||||
-- writeline(DataFile, LineOut);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process(m_axis_aclk_in, vio_cnt_rst)
|
||||
begin
|
||||
if(vio_cnt_rst = '1') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
elsif (rising_edge(m_axis_aclk_in)) then
|
||||
if (dds_pulse_dval = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
|
||||
if (pipe_in_ch1_fifo_rden = '1') then
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sim_false2 : if (SIM_ENABLED = FALSE) generate
|
||||
i_ila_3 : entity work.ila_3
|
||||
port map (
|
||||
clk => m_axis_aclk_in,
|
||||
probe0 => dds_pulse_data(15 downto 0),
|
||||
probe1 => dds_pulse_data(31 downto 16),
|
||||
probe2(0) => dds_pulse_dval,
|
||||
probe3(0) => '0'
|
||||
);
|
||||
end generate sim_false2;
|
||||
|
||||
dds_pulse_data_out <= dds_pulse_data;
|
||||
dds_pulse_dval_out <= dds_pulse_dval;
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => reset_in
|
||||
);
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
|
||||
m_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
|
||||
s_axi_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
sim_true : if (SIM_ENABLED = TRUE) generate
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
|
||||
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
|
||||
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 1 ns;
|
||||
vio_mode <= '0';
|
||||
vio_scale <= x"8000";
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '0';
|
||||
vio_dac_holdoff <= '1';
|
||||
vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
|
||||
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
|
||||
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
|
||||
vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
vio_enable <= '1';
|
||||
vio_cnt_rst <= '0';
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "011";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "001";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 0
|
||||
-- -- FREQUENCY SWEEP (UP-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "000";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "001";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
--
|
||||
--
|
||||
-- -- WFM 2
|
||||
-- -- CW TONE
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_idx <= "010";
|
||||
-- vio_cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_dac_holdoff <= '0';
|
||||
|
||||
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "011";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
-- wait for 100 ns;
|
||||
-- CW TONE
|
||||
-- vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
|
||||
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
|
||||
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
|
||||
-- vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "100";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for 5 us;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
end generate sim_true;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,159 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_wrapper is
|
||||
generic (
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"00";
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 6
|
||||
);
|
||||
port (
|
||||
m_axis_aclk_in : in std_logic;
|
||||
reset_in : in std_logic;
|
||||
dds_pulse_data_out : out std_logic_vector(31 downto 0);
|
||||
dds_pulse_dval_out : out std_logic;
|
||||
|
||||
S_AXI_ACLK : in std_logic;
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
S_AXI_WDATA : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
S_AXI_WVALID : in std_logic;
|
||||
S_AXI_WREADY : out std_logic;
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
S_AXI_BVALID : out std_logic;
|
||||
S_AXI_BREADY : in std_logic;
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
S_AXI_RDATA : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
S_AXI_RVALID : out std_logic;
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end dds_wrapper;
|
||||
|
||||
architecture arch_imp of dds_wrapper is
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal cmd_send_cnt : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rden_cnt : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
|
||||
MINOR_REV => MINOR_REV,
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
cmd_idx_out => cmd_idx,
|
||||
cmd_send_out => cmd_send,
|
||||
|
||||
mode_out => mode,
|
||||
scale_out => scale,
|
||||
dac_holdoff_out => dac_holdoff,
|
||||
|
||||
reserv1_out => reserv1,
|
||||
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_out => dds_phase_inc_step_size,
|
||||
idle_samples_out => idle_samples,
|
||||
dds_samples_out => dds_samples,
|
||||
phase_inc_out => phase_inc,
|
||||
phase_off_out => phase_off,
|
||||
swap_sf_out => swap_sf,
|
||||
|
||||
cmd_send_cnt_in => cmd_send_cnt,
|
||||
pipe_in_ch1_fifo_rden_cnt_in => pipe_in_ch1_fifo_rden_cnt,
|
||||
m_axis_tvalid_cnt_in => x"0000_0000",
|
||||
dds_pulse_data_cnt_in => dds_pulse_data_cnt,
|
||||
|
||||
|
||||
S_AXI_ACLK => S_AXI_ACLK,
|
||||
S_AXI_ARESETN => S_AXI_ARESETN,
|
||||
S_AXI_AWADDR => S_AXI_AWADDR,
|
||||
S_AXI_AWPROT => S_AXI_AWPROT,
|
||||
S_AXI_AWVALID => S_AXI_AWVALID,
|
||||
S_AXI_AWREADY => S_AXI_AWREADY,
|
||||
S_AXI_WDATA => S_AXI_WDATA,
|
||||
S_AXI_WSTRB => S_AXI_WSTRB,
|
||||
S_AXI_WVALID => S_AXI_WVALID,
|
||||
S_AXI_WREADY => S_AXI_WREADY,
|
||||
S_AXI_BRESP => S_AXI_BRESP,
|
||||
S_AXI_BVALID => S_AXI_BVALID,
|
||||
S_AXI_BREADY => S_AXI_BREADY,
|
||||
S_AXI_ARADDR => S_AXI_ARADDR,
|
||||
S_AXI_ARPROT => S_AXI_ARPROT,
|
||||
S_AXI_ARVALID => S_AXI_ARVALID,
|
||||
S_AXI_ARREADY => S_AXI_ARREADY,
|
||||
S_AXI_RDATA => S_AXI_RDATA,
|
||||
S_AXI_RRESP => S_AXI_RRESP,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY => S_AXI_RREADY
|
||||
);
|
||||
|
||||
-- Add user logic here
|
||||
i_dds_pulse_wrapper_x4 : entity work.dds_pulse_wrapper_x4
|
||||
generic map (
|
||||
SIM_ENABLED => FALSE,
|
||||
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
|
||||
MINOR_REV => MINOR_REV
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => S_AXI_ACLK,
|
||||
s_axi_aresetn_in => S_AXI_ARESETN,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
mode_in => mode,
|
||||
scale_in => scale,
|
||||
dac_holdoff_in => dac_holdoff,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
dds_pulse_data_out => dds_pulse_data_out,
|
||||
dds_pulse_dval_out => dds_pulse_dval_out,
|
||||
|
||||
cmd_send_cnt_out => cmd_send_cnt,
|
||||
pipe_in_ch1_fifo_rden_cnt_out => pipe_in_ch1_fifo_rden_cnt,
|
||||
dds_pulse_data_cnt_out => dds_pulse_data_cnt,
|
||||
|
||||
reset_in => reset_in
|
||||
);
|
||||
|
||||
|
||||
end architecture arch_imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+169
@@ -0,0 +1,169 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mult_16signed_x_16unsigned_latency3",
|
||||
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OutputWidthHigh": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutputWidthLow": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PipeStages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ClockEnable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SyncClear": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_HIGH": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_LOW": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"SCLR": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "SCLR" } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,813 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity pdw_wrapper is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE;
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
|
||||
);
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
loop_mode_en_in : in std_logic_vector( 7 downto 0);
|
||||
|
||||
mode_in : in std_logic;
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
latch_en_in : in std_logic;
|
||||
|
||||
reserv1_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
|
||||
idle_samples_out : out std_logic_vector(31 downto 0);
|
||||
dds_samples_out : out std_logic_vector(31 downto 0);
|
||||
phase_inc_out : out std_logic_vector(31 downto 0);
|
||||
phase_off_out : out std_logic_vector(31 downto 0);
|
||||
swap_sf_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
dds_pulse_data_out : out std_logic_vector(63 downto 0);
|
||||
dds_pulse_dval_out : out std_logic;
|
||||
|
||||
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
|
||||
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
|
||||
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
|
||||
dds_done_out : out std_logic;
|
||||
|
||||
trigger_mode_in : in std_logic_vector( 1 downto 0);
|
||||
ext_trigger_in : in std_logic;
|
||||
prog_us_tick_in : in std_logic_vector(31 downto 0);
|
||||
duration_ms_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity pdw_wrapper;
|
||||
|
||||
architecture imp of pdw_wrapper is
|
||||
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal s_axi_areset : std_logic;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
signal dac_holdoff_n_r : std_logic := '1';
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
|
||||
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal vio_cmd_send : std_logic;
|
||||
|
||||
signal vio_mode : std_logic;
|
||||
signal vio_scale : std_logic_vector(15 downto 0);
|
||||
signal vio_dac_holdoff : std_logic;
|
||||
|
||||
signal vio_reserv1 : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_reserv1 : signal is "true";
|
||||
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
|
||||
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
|
||||
signal vio_idle_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_idle_samples : signal is "true";
|
||||
signal vio_dds_samples : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_dds_samples : signal is "true";
|
||||
signal vio_phase_inc : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_inc : signal is "true";
|
||||
signal vio_phase_off : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_phase_off : signal is "true";
|
||||
signal vio_swap_sf : std_logic_vector(31 downto 0);
|
||||
attribute keep of vio_swap_sf : signal is "true";
|
||||
|
||||
signal vio_enable : std_logic := '0';
|
||||
signal vio_cnt_rst : std_logic;
|
||||
|
||||
signal latch_en : std_logic;
|
||||
signal vio_latch_en : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- file DataFile : text;
|
||||
|
||||
signal dds_m_axis_tready : std_logic;
|
||||
|
||||
signal dac_holdoff_trig : std_logic;
|
||||
signal dds_done : std_logic;
|
||||
signal dds_done_r : std_logic_vector(0 to 3) := (others => '0');
|
||||
attribute keep of dds_done_r : signal is "true";
|
||||
|
||||
signal loop_mode_en : std_logic_vector( 7 downto 0);
|
||||
signal loop_mode_en_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
signal vio_loop_mode_en : std_logic_vector( 7 downto 0);
|
||||
signal loop_mode_cmd_idx_r : std_logic_vector( 2 downto 0) := (others => '0');
|
||||
signal loop_mode_cmd_send_r : std_logic := '0';
|
||||
type fsm_state is (IDLE, SEND, WAIT1);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
signal cmd_idx_mux : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send_mux : std_logic;
|
||||
signal cmd_gen_busy : std_logic;
|
||||
|
||||
signal trigger_mode : std_logic_vector( 1 downto 0);
|
||||
signal vio_trigger_mode : std_logic_vector( 1 downto 0);
|
||||
signal bit_idx_r : std_logic_vector( 2 downto 0) := (others => '0');
|
||||
|
||||
signal prog_tick : std_logic;
|
||||
signal prog_tick_trig_n : std_logic;
|
||||
|
||||
signal prog_us_tick : std_logic_vector(31 downto 0);
|
||||
signal vio_prog_us_tick : std_logic_vector(31 downto 0);
|
||||
|
||||
signal ext_trigger_n_r : std_logic := '1';
|
||||
|
||||
signal test_state : std_logic_vector(1 downto 0);
|
||||
|
||||
type fsm_state1 is (IDLE, DURATION_CNT);
|
||||
signal state1_r : fsm_state1 := IDLE;
|
||||
signal duration_ms_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal duration_en_r : std_logic := '0';
|
||||
signal duration_done_r : std_logic := '0';
|
||||
|
||||
signal dds_done_done_r : std_logic := '0';
|
||||
signal ext_trigger_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
signal pulse_data_word_r : std_logic_vector(63 downto 0) := (others => '0');
|
||||
signal pulse_data_word_dval_r : std_logic := '0';
|
||||
signal read_toggle_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
cmd_send_cnt_out <= cmd_send_cnt_r;
|
||||
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
|
||||
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
|
||||
dds_done_out <= duration_done_r when trigger_mode = "11" else dds_done_done_r;
|
||||
|
||||
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- sim_false_vio_0 : if (SIM_ENABLED = FALSE) generate
|
||||
-- i_vio_0 : entity work.vio_0
|
||||
-- port map (
|
||||
-- clk => s_axi_aclk_in,
|
||||
-- probe_in0 => fpga_revision_date_r, -- 32
|
||||
-- probe_in1 => minor_rev_r, -- 8
|
||||
-- probe_in2 => m_axis_aclk_freq_r, -- 32
|
||||
-- probe_in3 => m_axis_aclk_cnt_r , -- 32
|
||||
-- probe_in4 => s_axi_aclk_freq_r, -- 32
|
||||
-- probe_in5 => s_axi_aclk_cnt_r , -- 32
|
||||
-- probe_in6 => , --32
|
||||
--
|
||||
-- probe_out0(0) => vio_mode, -- 1
|
||||
-- probe_out1 => vio_scale, -- 16
|
||||
-- probe_out2 => vio_cmd_idx, -- 3
|
||||
-- probe_out3(0) => vio_cmd_send, -- 1
|
||||
-- probe_out4(0) => vio_dac_holdoff, -- 1
|
||||
--
|
||||
-- probe_out5 => vio_reserv1, -- 32
|
||||
-- probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
|
||||
-- probe_out7 => vio_dds_phase_inc_step_size, -- 32
|
||||
-- probe_out8 => vio_idle_samples, -- 32
|
||||
-- probe_out9 => vio_dds_samples, -- 32
|
||||
-- probe_out10 => vio_phase_inc, -- 32
|
||||
-- probe_out11 => vio_phase_off, -- 32
|
||||
-- probe_out12 => vio_swap_sf, -- 32
|
||||
-- probe_out13 => vio_enable, -- 1
|
||||
-- probe_out14 => vio_cnt_rst, -- 1
|
||||
-- probe_out15 => vio_latch_en, -- 1
|
||||
-- probe_out16 => vio_loop_mode_en, -- 8
|
||||
-- probe_out17 => vio_trigger_mode, -- 2
|
||||
-- probe_out18 => vio_prog_us_tick -- 32
|
||||
-- );
|
||||
-- end generate sim_false_vio_0;
|
||||
|
||||
mode <= vio_mode when vio_enable = '1' else mode_in;
|
||||
scale <= vio_scale when vio_enable = '1' else scale_in;
|
||||
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
|
||||
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
|
||||
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
|
||||
loop_mode_en <= vio_loop_mode_en when vio_enable = '1' else loop_mode_en_in;
|
||||
trigger_mode <= vio_trigger_mode when vio_enable = '1' else trigger_mode_in;
|
||||
|
||||
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
|
||||
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
|
||||
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
|
||||
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
|
||||
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
|
||||
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
|
||||
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
|
||||
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
|
||||
latch_en <= vio_latch_en when vio_enable = '1' else latch_en_in;
|
||||
prog_us_tick <= vio_prog_us_tick when vio_enable = '1' else prog_us_tick_in;
|
||||
|
||||
cmd_idx_mux <= loop_mode_cmd_idx_r when loop_mode_en /= x"00" and dac_holdoff = '0' else cmd_idx;
|
||||
cmd_send_mux <= loop_mode_cmd_send_r when loop_mode_en /= x"00" and dac_holdoff = '0' else cmd_send;
|
||||
dac_holdoff_trig <= dac_holdoff when trigger_mode = "00" else
|
||||
ext_trigger_n_r when trigger_mode = "01" and dac_holdoff = '0' else
|
||||
prog_tick_trig_n when (trigger_mode = "10" or trigger_mode = "11") and dac_holdoff = '0' else '1';
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (dds_done = '1') then
|
||||
dds_done_done_r <= '1';
|
||||
elsif (cmd_send_mux = '1') then
|
||||
dds_done_done_r <= '0';
|
||||
end if;
|
||||
|
||||
ext_trigger_r <= ext_trigger_r(1 to 2) & ext_trigger_in;
|
||||
if (ext_trigger_r(0) = '0' and ext_trigger_r(1) = '1') then -- detect rising_edge of trigger
|
||||
ext_trigger_n_r <= '0';
|
||||
else
|
||||
ext_trigger_n_r <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
loop_mode_cmd_send_r <= '0';
|
||||
dds_done_r <= dds_done_r(1 to 3) & dds_done;
|
||||
case (state_r) is
|
||||
when IDLE => --0
|
||||
if (dds_done_r(0) = '1' and loop_mode_en /= x"00" and dac_holdoff = '0' and trigger_mode /= "00" ) then
|
||||
loop_mode_en_r <= loop_mode_en;
|
||||
bit_idx_r <= (others => '0');
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND => --1
|
||||
if (cmd_gen_busy = '0') then
|
||||
bit_idx_r <= bit_idx_r + 1;
|
||||
if (loop_mode_en_r(conv_integer(unsigned(bit_idx_r))) = '1') then
|
||||
loop_mode_cmd_idx_r <= bit_idx_r;
|
||||
loop_mode_cmd_send_r <= '1';
|
||||
state_cnt_r <= 3;
|
||||
else
|
||||
state_cnt_r <= 0;
|
||||
end if;
|
||||
if (bit_idx_r = 7) then
|
||||
state_r <= IDLE;
|
||||
else
|
||||
state_r <= WAIT1;
|
||||
end if;
|
||||
else
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when WAIT1 => --2
|
||||
if (state_cnt_r = 0) then
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r - 1;
|
||||
state_r <= WAIT1;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = WAIT1 else
|
||||
"11";
|
||||
|
||||
-- sim_false_ila_1 : if (SIM_ENABLED = FALSE) generate
|
||||
-- i_ila_1 : entity work.ila_1
|
||||
-- port map (
|
||||
-- clk => s_axi_aclk_in,
|
||||
-- probe0 => test_state, -- 2
|
||||
-- probe1(0) => dac_holdoff_trig, -- 1
|
||||
-- probe2 => trigger_mode, -- 2
|
||||
-- probe3(0) => dds_done_r(0), -- 1
|
||||
-- probe4 => cmd_idx_mux, -- 3
|
||||
-- probe5(0) => cmd_send_mux, -- 1
|
||||
-- probe6(0) => cmd_gen_busy -- 1
|
||||
-- );
|
||||
-- end generate sim_false_ila_1;
|
||||
|
||||
|
||||
|
||||
|
||||
-- mode <= vio_mode;
|
||||
-- scale <= vio_scale;
|
||||
-- dac_holdoff <= vio_dac_holdoff;
|
||||
-- cmd_idx <= vio_cmd_idx;
|
||||
-- cmd_send <= vio_cmd_send;
|
||||
--
|
||||
-- reserv1 <= vio_reserv1;
|
||||
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
|
||||
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
|
||||
-- idle_samples <= vio_idle_samples;
|
||||
-- dds_samples <= vio_dds_samples;
|
||||
-- phase_inc <= vio_phase_inc;
|
||||
-- phase_off <= vio_phase_off;
|
||||
-- swap_sf <= vio_swap_sf;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
cmd_send_r <= cmd_send_mux;
|
||||
if (reset_in = '1') then
|
||||
cmd_send_cnt_r <= (others => '0');
|
||||
else
|
||||
if (cmd_send_mux = '1' and cmd_send_r = '0') then
|
||||
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
generic map (
|
||||
SIM_ENABLED => SIM_ENABLED
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
cmd_idx_in => cmd_idx_mux, --cmd_idx,
|
||||
cmd_send_in => cmd_send_mux, --cmd_send,
|
||||
busy_out => cmd_gen_busy,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
latch_en_in => latch_en,
|
||||
|
||||
reserv1_out => reserv1_out,
|
||||
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time_out,
|
||||
dds_phase_inc_step_size_out => dds_phase_inc_step_size_out,
|
||||
idle_samples_out => idle_samples_out,
|
||||
dds_samples_out => dds_samples_out,
|
||||
phase_inc_out => phase_inc_out,
|
||||
phase_off_out => phase_off_out,
|
||||
swap_sf_out => swap_sf_out,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => s_axi_areset
|
||||
);
|
||||
|
||||
-- sim_false_ila_4 : if (SIM_ENABLED = FALSE) generate
|
||||
-- i_ila_4 : entity work.ila_4
|
||||
-- port map (
|
||||
-- clk => m_axis_aclk_in,
|
||||
-- probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
-- probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
-- probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
-- probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
-- );
|
||||
-- end generate sim_false_ila_4;
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => reset_in,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff_trig, --dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval,
|
||||
done_out => dds_done
|
||||
);
|
||||
|
||||
pulse_i <= dds_pulse_data(15 downto 0);
|
||||
pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
-- process(m_axis_aclk_in)
|
||||
-- variable LineOut : line;
|
||||
-- begin
|
||||
-- if (rising_edge(m_axis_aclk_in)) then
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- hwrite(LineOut, dds_pulse_data);
|
||||
-- writeline(DataFile, LineOut);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process(m_axis_aclk_in, vio_cnt_rst)
|
||||
begin
|
||||
if(vio_cnt_rst = '1') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
elsif (rising_edge(m_axis_aclk_in)) then
|
||||
if (reset_in = '1') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
else
|
||||
if (dds_pulse_dval = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (pipe_in_ch1_fifo_rden = '1') then
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- sim_false_ila_3 : if (SIM_ENABLED = FALSE) generate
|
||||
-- i_ila_3 : entity work.ila_3
|
||||
-- port map (
|
||||
-- clk => m_axis_aclk_in,
|
||||
-- probe0 => dds_pulse_data(15 downto 0),
|
||||
-- probe1 => dds_pulse_data(31 downto 16),
|
||||
-- probe2(0) => dds_pulse_dval,
|
||||
-- probe3(0) => s_axis_tready
|
||||
-- );
|
||||
-- end generate sim_false_ila_3;
|
||||
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
pulse_data_word_dval_r <= '0';
|
||||
if (dds_pulse_dval = '1') then
|
||||
read_toggle_r <= not read_toggle_r;
|
||||
if (read_toggle_r = '0') then
|
||||
pulse_data_word_r(31 downto 0) <= dds_pulse_data;
|
||||
else
|
||||
pulse_data_word_r(63 downto 32) <= dds_pulse_data;
|
||||
pulse_data_word_dval_r <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_pulse_data_out <= pulse_data_word_r;
|
||||
dds_pulse_dval_out <= pulse_data_word_dval_r;
|
||||
|
||||
-- dds_pulse_data_out <= dds_pulse_data;
|
||||
-- dds_pulse_dval_out <= dds_pulse_dval;
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => prog_us_tick,
|
||||
prog_us_tick_out => prog_tick,
|
||||
|
||||
reset_in => reset_in
|
||||
);
|
||||
|
||||
prog_tick_trig_n <= not prog_tick when trigger_mode = "11" and duration_en_r = '1' else
|
||||
not prog_tick when trigger_mode = "10" else '1';
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
dac_holdoff_n_r <= dac_holdoff;
|
||||
|
||||
case (state1_r) is
|
||||
when IDLE => --0
|
||||
if (trigger_mode = "11" and dac_holdoff_n_r = '1' and dac_holdoff = '0') then
|
||||
duration_ms_cnt_r <= (others => '0');
|
||||
duration_en_r <= '1';
|
||||
duration_done_r <= '0';
|
||||
state1_r <= DURATION_CNT;
|
||||
else
|
||||
state1_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when DURATION_CNT => --1
|
||||
if (tick_1ms = '1') then
|
||||
if((duration_ms_cnt_r = duration_ms_cnt_in) or dac_holdoff = '1') then
|
||||
duration_ms_cnt_r <= (others => '0');
|
||||
duration_en_r <= '0';
|
||||
duration_done_r <= '1';
|
||||
state1_r <= IDLE;
|
||||
else
|
||||
duration_ms_cnt_r <= duration_ms_cnt_r + 1;
|
||||
state1_r <= DURATION_CNT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
|
||||
m_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
|
||||
s_axi_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sim_true : if (SIM_ENABLED = TRUE) generate
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
|
||||
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
|
||||
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 1 ns;
|
||||
vio_mode <= '0';
|
||||
vio_scale <= x"8000";
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '0';
|
||||
vio_loop_mode_en <= x"00";
|
||||
vio_trigger_mode <= "00"; -- manual trigger
|
||||
vio_prog_us_tick <= conv_std_logic_vector(100, 32);
|
||||
vio_dac_holdoff <= '1';
|
||||
vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
|
||||
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
|
||||
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
|
||||
vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
vio_enable <= '1';
|
||||
vio_cnt_rst <= '0';
|
||||
wait for ok_clk_in_period*10;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
wait for 200 ns;
|
||||
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "000";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 1
|
||||
-- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "001";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 2
|
||||
-- CW TONE
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "010";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
-- WFM 3
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "011";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 4
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "100";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 5
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "101";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 6
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "110";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
|
||||
-- WFM 7
|
||||
-- FREQUENCY SWEEP (UP-SWEEP)
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_idx <= "111";
|
||||
vio_cmd_send <= '1';
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_cmd_send <= '0';
|
||||
wait for 100 ns;
|
||||
|
||||
vio_loop_mode_en <= x"FF";
|
||||
|
||||
-- wait for ok_clk_in_period*10;
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_dac_holdoff <= '0';
|
||||
-- wait for ok_clk_in_period*10;
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_dac_holdoff <= '1';
|
||||
--
|
||||
-- wait for 15 us;
|
||||
-- wait for ok_clk_in_period*10;
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_dac_holdoff <= '0';
|
||||
-- wait for ok_clk_in_period*10;
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- vio_dac_holdoff <= '1';
|
||||
|
||||
-- vio_trigger_mode <= "01"; -- external trigger
|
||||
vio_trigger_mode <= "10"; -- periodic trigger
|
||||
|
||||
wait for 200 ns;
|
||||
wait until rising_edge(s_axi_aclk_in);
|
||||
vio_dac_holdoff <= '0';
|
||||
|
||||
-- wait for 125 us;
|
||||
-- vio_dac_holdoff <= '1';
|
||||
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "011";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
-- wait for 100 ns;
|
||||
-- CW TONE
|
||||
-- vio_reserv1 <= x"00000000"; --RESERVED1
|
||||
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
|
||||
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
|
||||
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
|
||||
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
|
||||
-- vio_phase_off <= x"00000000"; --PHASE_OFF
|
||||
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_idx <= "100";
|
||||
-- cmd_send <= '1';
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- wait until rising_edge(s_axi_aclk_in);
|
||||
-- cmd_send <= '0';
|
||||
-- wait for 100 ns;
|
||||
|
||||
wait for 5 us;
|
||||
|
||||
wait; -- wait here forever
|
||||
end process;
|
||||
end generate sim_true;
|
||||
|
||||
end architecture imp;
|
||||
+468
@@ -0,0 +1,468 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "sfifo_32b_1024_pf992_latency1",
|
||||
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_pulse1_fifo",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Builtin_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "992", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "991", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEMORY_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "992", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "991", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"srst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"din": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"overflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"underflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"prog_full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"core_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity tick_gen is
|
||||
generic(
|
||||
CLOCK_SPEED_MHZ : integer := 100
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
tick_1us_out : out std_logic;
|
||||
tick_1ms_out : out std_logic;
|
||||
tick_500ms_out : out std_logic;
|
||||
tick_750ms_out : out std_logic;
|
||||
tick_1s_out : out std_logic;
|
||||
|
||||
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
|
||||
prog_us_tick_out : out std_logic;
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity tick_gen;
|
||||
|
||||
architecture imp of tick_gen is
|
||||
|
||||
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
|
||||
signal usec_cnt_r : integer range 0 to 999;
|
||||
signal msec_cnt_r : integer range 0 to 499;
|
||||
signal msec_cnt1_r : integer range 0 to 999;
|
||||
signal tick_1us_r : std_logic;
|
||||
signal tick_1ms_r : std_logic;
|
||||
signal tick_500ms_r : std_logic;
|
||||
signal tick_750ms_r : std_logic;
|
||||
signal tick_1s_r : std_logic;
|
||||
|
||||
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
|
||||
signal prog_us_tick_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
tick_1us_out <= tick_1us_r;
|
||||
tick_1ms_out <= tick_1ms_r;
|
||||
tick_500ms_out <= tick_500ms_r;
|
||||
tick_750ms_out <= tick_750ms_r;
|
||||
tick_1s_out <= tick_1s_r;
|
||||
prog_us_tick_out <= prog_us_tick_r;
|
||||
|
||||
process(clk_in, reset_in)
|
||||
begin
|
||||
if(reset_in = '1') then
|
||||
sysclk_cnt_r <= 0;
|
||||
usec_cnt_r <= 0;
|
||||
msec_cnt_r <= 0;
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_us_tick_r <= '0';
|
||||
|
||||
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
|
||||
sysclk_cnt_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
else
|
||||
sysclk_cnt_r <= sysclk_cnt_r + 1;
|
||||
tick_1us_r <= '0';
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(usec_cnt_r = 999) then -- 1000us
|
||||
usec_cnt_r <= 0;
|
||||
tick_1ms_r <= '1';
|
||||
else
|
||||
usec_cnt_r <= usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt_r = 499) then -- 500ms
|
||||
msec_cnt_r <= 0;
|
||||
tick_500ms_r <= '1';
|
||||
else
|
||||
msec_cnt_r <= msec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt1_r = 749) then -- 750ms
|
||||
tick_750ms_r <= '1';
|
||||
end if;
|
||||
if(msec_cnt1_r = 999) then -- 1s
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1s_r <= '1';
|
||||
else
|
||||
msec_cnt1_r <= msec_cnt1_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '1';
|
||||
else
|
||||
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S01_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S01_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S01_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S01_AXI_HIGHADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S03_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S03_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S03_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S03_AXI_HIGHADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S02_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S02_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S02_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S02_AXI_HIGHADDR" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "MINOR_REV"
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to validate MINOR_REV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S01_AXI_DATA_WIDTH { PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S01_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S01_AXI_DATA_WIDTH { PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S01_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S01_AXI_ADDR_WIDTH { PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S01_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S01_AXI_ADDR_WIDTH { PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S01_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S01_AXI_BASEADDR { PARAM_VALUE.C_S01_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S01_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S01_AXI_BASEADDR { PARAM_VALUE.C_S01_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S01_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S01_AXI_HIGHADDR { PARAM_VALUE.C_S01_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S01_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S01_AXI_HIGHADDR { PARAM_VALUE.C_S01_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S01_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S03_AXI_DATA_WIDTH { PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S03_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S03_AXI_DATA_WIDTH { PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S03_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S03_AXI_ADDR_WIDTH { PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S03_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S03_AXI_ADDR_WIDTH { PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S03_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S03_AXI_BASEADDR { PARAM_VALUE.C_S03_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S03_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S03_AXI_BASEADDR { PARAM_VALUE.C_S03_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S03_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S03_AXI_HIGHADDR { PARAM_VALUE.C_S03_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S03_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S03_AXI_HIGHADDR { PARAM_VALUE.C_S03_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S03_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S02_AXI_DATA_WIDTH { PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S02_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S02_AXI_DATA_WIDTH { PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S02_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S02_AXI_ADDR_WIDTH { PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S02_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S02_AXI_ADDR_WIDTH { PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S02_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S02_AXI_BASEADDR { PARAM_VALUE.C_S02_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S02_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S02_AXI_BASEADDR { PARAM_VALUE.C_S02_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S02_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S02_AXI_HIGHADDR { PARAM_VALUE.C_S02_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S02_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S02_AXI_HIGHADDR { PARAM_VALUE.C_S02_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S02_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S01_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S01_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S03_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S03_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S02_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S02_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,512 @@
|
||||
00000002
|
||||
00000010
|
||||
000001d0
|
||||
000001d8
|
||||
000001e0
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
63000000
|
||||
7473616d
|
||||
00007265
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
34346339
|
||||
36316136
|
||||
36393064
|
||||
62623463
|
||||
65336535
|
||||
39333263
|
||||
62396264
|
||||
36393136
|
||||
62353866
|
||||
33376661
|
||||
00000000
|
||||
00000066
|
||||
6a646176
|
||||
34393631
|
||||
33383130
|
||||
00003236
|
||||
00000000
|
||||
31000000
|
||||
00000000
|
||||
00000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000
|
||||
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|
||||
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|
||||
00000000
|
||||
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|
||||
00000000
|
||||
00000000
|
||||
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|
||||
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|
||||
00000000
|
||||
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|
||||
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|
||||
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|
||||
00000000
|
||||
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|
||||
00000000
|
||||
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|
||||
00000000
|
||||
00000000
|
||||
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|
||||
00000000
|
||||
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|
||||
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|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000
|
||||
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|
||||
00000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000
|
||||
00000000
|
||||
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|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
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|
||||
00000000
|
||||
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|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
30396461
|
||||
665f3138
|
||||
5f61636d
|
||||
007a6265
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
3175637a
|
||||
00003230
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,455 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_misc.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
library work;
|
||||
|
||||
entity axi_lite_traffic_gen is
|
||||
generic (
|
||||
C_M_AXI_ADDR_WIDTH : integer := 32;
|
||||
C_M_AXI_DATA_WIDTH : integer := 32
|
||||
);
|
||||
port (
|
||||
m_axi_aclk : in std_logic;
|
||||
m_axi_aresetn : in std_logic;
|
||||
|
||||
-- Master Interface Write Address
|
||||
m_axi_awaddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
m_axi_awprot : out std_logic_vector (2 downto 0);
|
||||
m_axi_awvalid : out std_logic;
|
||||
m_axi_awready : in std_logic;
|
||||
|
||||
-- master interface write data
|
||||
m_axi_wdata : out std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
m_axi_wstrb : out std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0);
|
||||
m_axi_wvalid : out std_logic;
|
||||
m_axi_wready : in std_logic;
|
||||
|
||||
-- master interface write response
|
||||
m_axi_bresp : in std_logic_vector (1 downto 0);
|
||||
m_axi_bvalid : in std_logic;
|
||||
m_axi_bready : out std_logic;
|
||||
|
||||
-- master interface read address
|
||||
m_axi_araddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
m_axi_arprot : out std_logic_vector (2 downto 0);
|
||||
m_axi_arvalid : out std_logic;
|
||||
m_axi_arready : in std_logic;
|
||||
|
||||
-- master interface read data
|
||||
m_axi_rdata : in std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
m_axi_rresp : in std_logic_vector (1 downto 0);
|
||||
m_axi_rvalid : in std_logic;
|
||||
m_axi_rready : out std_logic;
|
||||
|
||||
num_burst_cnt_out : out std_logic_vector(7 downto 0);
|
||||
xfer_en_out : out std_logic;
|
||||
xfer_done_in : in std_logic;
|
||||
dma_xfer_done_in : in std_logic;
|
||||
|
||||
buffer_rdy_intr_in : in std_logic
|
||||
|
||||
);
|
||||
end entity axi_lite_traffic_gen;
|
||||
|
||||
architecture impl of axi_lite_traffic_gen is
|
||||
|
||||
procedure writeReg (
|
||||
addr : in std_logic_vector(31 downto 0);
|
||||
wr_data : in std_logic_vector(31 downto 0);
|
||||
|
||||
signal m_axi_aclk : in std_logic;
|
||||
signal awaddr : out std_logic_vector(31 downto 0);
|
||||
signal wdata : out std_logic_vector(31 downto 0);
|
||||
signal wstrb : out std_logic_vector( 3 downto 0);
|
||||
signal awvalid : out std_logic;
|
||||
signal wvalid : out std_logic;
|
||||
signal bready : out std_logic;
|
||||
signal awready : in std_logic;
|
||||
signal wready : in std_logic;
|
||||
signal bvalid : in std_logic;
|
||||
signal done : out std_logic
|
||||
) is
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
done <= '0';
|
||||
awaddr <= addr;
|
||||
wdata <= wr_data;
|
||||
wstrb <= x"F";
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
awvalid <= '1';
|
||||
wvalid <= '1';
|
||||
bready <= '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until wready = '1' and awready = '1';
|
||||
awvalid <= '0';
|
||||
wvalid <= '0';
|
||||
wait until bvalid = '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
done <= '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
done <= '0';
|
||||
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
end procedure writeReg;
|
||||
|
||||
|
||||
procedure readReg (
|
||||
addr : in std_logic_vector(31 downto 0);
|
||||
|
||||
signal m_axi_aclk : in std_logic;
|
||||
signal araddr : out std_logic_vector(31 downto 0);
|
||||
|
||||
signal rready : out std_logic;
|
||||
signal arvalid : out std_logic;
|
||||
|
||||
signal arready : in std_logic;
|
||||
signal rvalid : in std_logic;
|
||||
signal rdata : in std_logic_vector(31 downto 0);
|
||||
signal rd_data : out std_logic_vector(31 downto 0);
|
||||
signal done : out std_logic
|
||||
) is
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
done <= '0';
|
||||
araddr <= addr;
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
rready <= '1';
|
||||
arvalid <= '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until arready = '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
arvalid <= '0';
|
||||
-- wait until rising_edge(m_axi_aclk);
|
||||
wait until rvalid = '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
rready <= '0';
|
||||
rd_data <= rdata;
|
||||
|
||||
done <= '1';
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
done <= '0';
|
||||
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
wait until rising_edge(m_axi_aclk);
|
||||
end procedure readReg;
|
||||
|
||||
|
||||
signal m_axi_awaddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal m_axi_awvalid_i : std_logic := '0';
|
||||
signal m_axi_wdata_i : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal m_axi_wstrb_i : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
|
||||
signal m_axi_wvalid_i : std_logic := '0';
|
||||
signal m_axi_bready_i : std_logic := '0';
|
||||
|
||||
signal m_axi_araddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal m_axi_arvalid_i : std_logic := '0';
|
||||
signal m_axi_rready_i : std_logic := '0';
|
||||
|
||||
signal read_complete : std_logic := '0';
|
||||
signal read_complete_r : std_logic := '0';
|
||||
signal rd_data : std_logic_vector(31 downto 0);
|
||||
signal write_complete : std_logic := '0';
|
||||
signal write_complete_r : std_logic := '0';
|
||||
|
||||
signal num_burst_cnt : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal xfer_en : std_logic := '0';
|
||||
|
||||
signal buffer_rdy_intr_r : std_logic;
|
||||
|
||||
signal m_axi_awaddr_ii : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
|
||||
signal m_axi_awvalid_ii : std_logic := '0';
|
||||
signal m_axi_wdata_ii : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
|
||||
signal m_axi_wstrb_ii : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
|
||||
signal m_axi_wvalid_ii : std_logic := '0';
|
||||
signal m_axi_bready_ii : std_logic := '0';
|
||||
|
||||
signal s2mm_cmd_en : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axi_awaddr <= m_axi_awaddr_i when s2mm_cmd_en = '0' else m_axi_awaddr_ii;
|
||||
m_axi_awvalid <= m_axi_awvalid_i when s2mm_cmd_en = '0' else m_axi_awvalid_ii;
|
||||
m_axi_wdata <= m_axi_wdata_i when s2mm_cmd_en = '0' else m_axi_wdata_ii;
|
||||
m_axi_wstrb <= m_axi_wstrb_i when s2mm_cmd_en = '0' else m_axi_wstrb_ii;
|
||||
m_axi_wvalid <= m_axi_wvalid_i when s2mm_cmd_en = '0' else m_axi_wvalid_ii;
|
||||
m_axi_bready <= m_axi_bready_i when s2mm_cmd_en = '0' else m_axi_bready_ii;
|
||||
|
||||
m_axi_araddr <= m_axi_araddr_i;
|
||||
m_axi_arvalid <= m_axi_arvalid_i;
|
||||
m_axi_rready <= m_axi_rready_i;
|
||||
|
||||
m_axi_awprot <= "000";
|
||||
m_axi_arprot <= "000";
|
||||
|
||||
num_burst_cnt_out <= num_burst_cnt;
|
||||
xfer_en_out <= xfer_en;
|
||||
|
||||
process
|
||||
variable my_line : line;
|
||||
begin
|
||||
|
||||
wait for 10 us;
|
||||
|
||||
|
||||
----------------------
|
||||
|
||||
|
||||
write(my_line, string'("reading REG_VERSION at 0x00")); -- read REG_VERSION
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
write(my_line, string'("reading REG_CONFIG at 0x0C")); -- read REG_CONFIG
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
write(my_line, string'("reading REG_PPS_IRQ_MASK at 0x10")); -- read REG_PPS_IRQ_MASK
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_0010", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
write(my_line, string'("reading REG_FPGA_INFO at 0x1C")); -- read REG_FPGA_INFO
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
wait for 5 us;
|
||||
|
||||
write(my_line, string'("reading REG_STATUS1 at 0x54")); -- read REG_STATUS1
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_0054", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
write(my_line, string'("reading REG_STATUS2 at 0x58")); -- read REG_STATUS2
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_0058", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
write(my_line, string'("reading REG_STATUS3 at 0x5C")); -- read REG_STATUS3
|
||||
writeline(output, my_line);
|
||||
readReg(x"0000_005C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
|
||||
wait for 10 us;
|
||||
|
||||
write(my_line, string'("writing REG_RSTN at 0x040")); -- write REG_RSTN
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0040", x"0000_0003", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
|
||||
|
||||
wait for 5 us;
|
||||
|
||||
|
||||
write(my_line, string'("writing REG_TPL_DESCRIPTOR_1 at 0x240")); -- write REG_TPL_DESCRIPTOR_1
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0240", x"0401_0408", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
write(my_line, string'("writing REG_TPL_DESCRIPTOR_2 at 0x244")); -- write REG_TPL_DESCRIPTOR_2
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0244", x"0000_1010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
----sending user data
|
||||
|
||||
wait for 1 us;
|
||||
|
||||
write(my_line, string'("writing REG_USR_CNTRL_3 at 0x420")); -- write REG_USR_CNTRL_3
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0420", x"0200_8010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
|
||||
|
||||
wait for 1 us;
|
||||
|
||||
write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write CHAN 0 - REG_CHAN_CNTRL_7 -- input data (DMA)
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0418", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x458")); -- write CHAN 1 - write REG_CHAN_CNTRL_7 -- input data (DMA)
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0458", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x498")); -- write CHAN 2 - write REG_CHAN_CNTRL_7 -- input data (DMA)
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_0498", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x4D8")); -- write CHAN 3 - write REG_CHAN_CNTRL_7 -- input data (DMA)
|
||||
writeline(output, my_line);
|
||||
writeReg(x"0000_04D8", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
|
||||
-- wait for 1 us;
|
||||
--
|
||||
-- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 - inverted pn15
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0418", x"0000_0005", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
-- write(my_line, string'("writing REG_CHAN_CNTRL_5 at 0x410")); -- write REG_CHAN_CNTRL_5
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0410", x"DEAD_BEEF", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- wait for 1 us;
|
||||
--
|
||||
-- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 -- pattern (SED)
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0418", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
|
||||
|
||||
|
||||
-- write(my_line, string'("reading TDFV at 0x0C")); -- read Transmit Data FIFO Vacancy
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0003_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RDFO at 0x1C")); -- Receive Data FIFO Occupancy
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0003_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RLR at 0x24")); -- Receive Length Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0003_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
--
|
||||
--
|
||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("writing (TDFR) at 0x8")); --Transmit Data FIFO Reset
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0008", x"0000_00A5", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
--
|
||||
--
|
||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("-----------------------------------"));
|
||||
-- writeline(output, my_line);
|
||||
-- write(my_line, string'("writing TDFD at 0x10")); -- Transmit Data FIFO 32-bit Wide Data Write Port
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0010", x"dead_beef", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing TLR at 0x14")); --MM2S Source Address. Lower 32 bits of address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0014", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("reading ISR at 0x00")); -- read Interrupt Status Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0003_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- wait for 500 ns;
|
||||
-- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RLR at 0x20")); -- read Receive Data FIFO 32-bit Wide Data Read Port
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0020", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
|
||||
-- write(my_line, string'("writing MM2S_SA_MSB at 0x1C")); -- MM2S Source Address. Upper 32 bits of address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_001C", x"0000_0000", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- -- dma transfer starts here (1)
|
||||
-- write(my_line, string'("writing MM2S_LENGTH at 0x28")); -- MM2S Transfer Length (Bytes)
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0028", conv_std_logic_vector(16, 32), m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
-- -- 2048+8 ==> 8 is packet length
|
||||
--
|
||||
-- wait until dma_xfer_done_in = '1';
|
||||
-- wait for 50 us;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wait; -- wait here forever
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
-- process
|
||||
-- variable my_line : line;
|
||||
-- begin
|
||||
---- if(rising_edge(m_axi_aclk)) then
|
||||
---- buffer_rdy_intr_r <= buffer_rdy_intr_in;
|
||||
---- if(buffer_rdy_intr_in = '1' and buffer_rdy_intr_r = '0') then
|
||||
--
|
||||
--
|
||||
-- -- dma the data **********From Stream to Memory ****************
|
||||
-- wait until buffer_rdy_intr_in = '1';
|
||||
-- s2mm_cmd_en <= '1';
|
||||
-- wait for 100 ns;
|
||||
-- write(my_line, string'("-----------------------------------"));
|
||||
-- writeline(output, my_line);
|
||||
--
|
||||
-- -- 0x34 S2MM DMA Status register
|
||||
--
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DMACR at 0x30")); -- S2MM DMA Control register
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0030", x"0000_7001", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DA at 0x48")); -- S2MM Destination Address. Lower 32 bit address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0048", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DA_MSB at 0x4C")); -- S2MM Destination Address. Upper 32 bit address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_004C", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- -- dma transfer starts here
|
||||
-- write(my_line, string'("writing S2MM_LENGTH at 0x58")); -- S2MM Buffer Length (Bytes)
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0058", x"0000_0800", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- wait for 100 ns;
|
||||
-- -- dma transfer starts here
|
||||
-- write(my_line, string'("writing S2MM_LENGTH at 0x58"));
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0058", x"0000_1000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
--
|
||||
-- wait for 100 ns;
|
||||
-- s2mm_cmd_en <= '0';
|
||||
--
|
||||
-- wait; -- wait here forever
|
||||
-- end process;
|
||||
|
||||
|
||||
|
||||
process(m_axi_aclk)
|
||||
variable my_line : line;
|
||||
begin
|
||||
read_complete_r <= read_complete;
|
||||
write_complete_r <= write_complete;
|
||||
|
||||
if(read_complete = '1' and read_complete_r = '0') then
|
||||
write(my_line, string'("Read Complete: "));
|
||||
hwrite(my_line, rd_data);
|
||||
writeline(output, my_line);
|
||||
end if;
|
||||
|
||||
if(write_complete = '1' and write_complete_r = '0') then
|
||||
write(my_line, string'("Write Complete: "));
|
||||
writeline(output, my_line);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture impl;
|
||||
@@ -0,0 +1,557 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:53:22 03/24/2017
|
||||
-- Design Name:
|
||||
-- Module Name:
|
||||
-- Project Name: xem7350
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: dac_interface
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
entity tb_fifos is
|
||||
end tb_fifos;
|
||||
|
||||
architecture behavior of tb_fifos is
|
||||
|
||||
constant C_M_AXI_DATA_WIDTH : integer := 32;
|
||||
constant C_M_AXI_ADDR_WIDTH : integer := 32;
|
||||
|
||||
-- Clock period definitions
|
||||
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
|
||||
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
|
||||
|
||||
|
||||
signal m_axis_aclk : std_logic := '0';
|
||||
signal reset_n : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal reset : std_logic;
|
||||
|
||||
signal s00_axi_aclk : std_logic := '0';
|
||||
|
||||
|
||||
|
||||
signal dds_pulse_data_0 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_0 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_0 : std_logic;
|
||||
|
||||
signal dds_pulse_data_1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_1 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_1 : std_logic;
|
||||
|
||||
signal dds_pulse_data_2 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_2 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_2 : std_logic;
|
||||
|
||||
signal dds_pulse_data_3 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_3 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_3 : std_logic;
|
||||
|
||||
signal dds_pulse_data_word : std_logic_vector(127 downto 0);
|
||||
signal dds_pulse_data_word_dval : std_logic;
|
||||
signal dds_pulse_data_word_tready : std_logic;
|
||||
signal dds_pulse_data_word_tready_valid : std_logic;
|
||||
|
||||
signal m_axis_tdata_i : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid_i : std_logic;
|
||||
signal m_axis_tready_i : std_logic;
|
||||
|
||||
signal s_axis_tready_0 : std_logic;
|
||||
signal s_axis_tready_1 : std_logic;
|
||||
signal s_axis_tready_2 : std_logic;
|
||||
signal s_axis_tready_3 : std_logic;
|
||||
|
||||
signal fifo_en : std_logic := '1';
|
||||
|
||||
signal fifo_rd_data_0 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_1 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_2 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_3 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_4 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_5 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_6 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_7 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_8 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_9 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_10 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_11 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_12 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_13 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_14 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_15 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_16 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_17 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_18 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_19 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_20 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_21 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_22 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_23 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_24 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_25 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_26 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_27 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_28 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_29 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_30 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_31 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_32 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_33 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_34 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_35 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_36 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_37 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_38 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_39 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_40 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_41 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_42 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_43 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_44 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_45 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_46 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_47 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_48 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_49 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_50 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_51 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_52 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_53 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_54 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_55 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_56 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_57 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_58 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_59 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_60 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_61 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_62 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_63 : std_logic_vector(15 downto 0);
|
||||
|
||||
signal fifo_rd_valid : std_logic;
|
||||
signal fifo_rd_underflow : std_logic;
|
||||
|
||||
signal cmd_send_0 : std_logic := '0';
|
||||
signal dac_holdoff_0 : std_logic := '1';
|
||||
|
||||
signal fifo_rd_en : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_aclk <= not m_axis_aclk after M_AXI_ACLK_PERIOD/2;
|
||||
s00_axi_aclk <= not s00_axi_aclk after S_AXI_ACLK_PERIOD/2;
|
||||
|
||||
process(m_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk)) then
|
||||
reset_n <= reset_n(1 to 2) & '1';
|
||||
|
||||
if (reset_n = "111") then
|
||||
fifo_rd_en <= not fifo_rd_en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reset <= not reset_n(0);
|
||||
|
||||
-- i_pdw_wrapper_0 : entity work.pdw_wrapper
|
||||
-- generic map (
|
||||
-- SIM_ENABLED => FALSE,
|
||||
-- FPGA_REVISION_DATE => x"0528_2024",
|
||||
-- MINOR_REV => x"01"
|
||||
-- )
|
||||
-- port map (
|
||||
-- s_axi_aclk_in => s00_axi_aclk,
|
||||
-- s_axi_aresetn_in => reset_n(0),
|
||||
-- cmd_idx_in => "010",
|
||||
-- cmd_send_in => cmd_send_0,
|
||||
-- loop_mode_en_in => x"00",
|
||||
--
|
||||
-- mode_in => '0',
|
||||
-- scale_in => x"8000",
|
||||
-- dac_holdoff_in => dac_holdoff_0,
|
||||
--
|
||||
-- reserv1_in => x"00000000",
|
||||
-- dds_phase_inc_dwell_time_in => x"00000000",
|
||||
-- dds_phase_inc_step_size_in => x"00000000",
|
||||
-- idle_samples_in => x"00000000",
|
||||
-- dds_samples_in => x"000004E2",
|
||||
-- phase_inc_in => x"0624DD2F",
|
||||
-- phase_off_in => x"00000000",
|
||||
-- swap_sf_in => x"00008000",
|
||||
-- latch_en_in => '0',
|
||||
--
|
||||
-- reserv1_out => open,
|
||||
-- dds_phase_inc_dwell_time_out => open,
|
||||
-- dds_phase_inc_step_size_out => open,
|
||||
-- idle_samples_out => open,
|
||||
-- dds_samples_out => open,
|
||||
-- phase_inc_out => open,
|
||||
-- phase_off_out => open,
|
||||
-- swap_sf_out => open,
|
||||
--
|
||||
-- m_axis_aclk_in => m_axis_aclk,
|
||||
-- dds_pulse_data_out => dds_pulse_data_0,
|
||||
-- dds_pulse_dval_out => dds_pulse_dval_0,
|
||||
--
|
||||
-- cmd_send_cnt_out => open,
|
||||
-- pipe_in_ch1_fifo_rden_cnt_out => open,
|
||||
-- dds_pulse_data_cnt_out => open,
|
||||
-- dds_done_out => open,
|
||||
--
|
||||
-- trigger_mode_in => "00", -- 00 = internal, 01 = external, 10 = internal
|
||||
-- ext_trigger_in => '0',
|
||||
-- prog_us_tick_in => x"0000_0100",
|
||||
-- duration_ms_cnt_in => x"0000_0064",
|
||||
--
|
||||
-- reset_in => reset
|
||||
-- );
|
||||
|
||||
i_fifo_0 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_0,
|
||||
s_axis_tvalid => dds_pulse_dval_0,
|
||||
s_axis_tready => s_axis_tready_0,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_0,
|
||||
m_axis_tvalid => m_axis_tvalid_0,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
|
||||
i_fifo_1 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_1,
|
||||
s_axis_tvalid => dds_pulse_dval_1,
|
||||
s_axis_tready => s_axis_tready_1,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_1,
|
||||
m_axis_tvalid => m_axis_tvalid_1,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
i_fifo_2 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_2,
|
||||
s_axis_tvalid => dds_pulse_dval_2,
|
||||
s_axis_tready => s_axis_tready_2,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_2,
|
||||
m_axis_tvalid => m_axis_tvalid_2,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
|
||||
i_fifo_3 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_3,
|
||||
s_axis_tvalid => dds_pulse_dval_3,
|
||||
s_axis_tready => s_axis_tready_3,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_3,
|
||||
m_axis_tvalid => m_axis_tvalid_3,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
dds_pulse_data_word <= m_axis_tdata_3 & m_axis_tdata_2 & m_axis_tdata_1 & m_axis_tdata_0;
|
||||
dds_pulse_data_word_dval <= m_axis_tvalid_3 and m_axis_tvalid_2 and m_axis_tvalid_1 and m_axis_tvalid_0;
|
||||
|
||||
dds_pulse_data_word_tready_valid <= '1' when dds_pulse_data_word_dval = '1' and dds_pulse_data_word_tready = '1' else '0';
|
||||
|
||||
-- this FIFO is actually 32K by 128
|
||||
i_fifo_out : entity work.axis_data_fifo_512x128
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_word,
|
||||
s_axis_tvalid => dds_pulse_data_word_dval,
|
||||
s_axis_tready => dds_pulse_data_word_tready,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_i,
|
||||
m_axis_tvalid => m_axis_tvalid_i,
|
||||
m_axis_tready => m_axis_tready_i
|
||||
);
|
||||
|
||||
|
||||
|
||||
i_util_upack2 : entity work.util_upack2
|
||||
generic map (
|
||||
NUM_OF_CHANNELS => 8,
|
||||
SAMPLES_PER_CHANNEL => 1,
|
||||
SAMPLE_DATA_WIDTH => 16
|
||||
)
|
||||
port map (
|
||||
clk => m_axis_aclk, --input
|
||||
reset => reset, -- input
|
||||
enable_0 => fifo_en, -- input
|
||||
enable_1 => fifo_en, -- input
|
||||
enable_2 => fifo_en, -- input
|
||||
enable_3 => fifo_en, -- input
|
||||
enable_4 => fifo_en, -- input
|
||||
enable_5 => fifo_en, -- input
|
||||
enable_6 => fifo_en, -- input
|
||||
enable_7 => fifo_en, -- input
|
||||
enable_8 => '0', -- input
|
||||
enable_9 => '0', -- input
|
||||
enable_10 => '0', -- input
|
||||
enable_11 => '0', -- input
|
||||
enable_12 => '0', -- input
|
||||
enable_13 => '0', -- input
|
||||
enable_14 => '0', -- input
|
||||
enable_15 => '0', -- input
|
||||
enable_16 => '0', -- input
|
||||
enable_17 => '0', -- input
|
||||
enable_18 => '0', -- input
|
||||
enable_19 => '0', -- input
|
||||
enable_20 => '0', -- input
|
||||
enable_21 => '0', -- input
|
||||
enable_22 => '0', -- input
|
||||
enable_23 => '0', -- input
|
||||
enable_24 => '0', -- input
|
||||
enable_25 => '0', -- input
|
||||
enable_26 => '0', -- input
|
||||
enable_27 => '0', -- input
|
||||
enable_28 => '0', -- input
|
||||
enable_29 => '0', -- input
|
||||
enable_30 => '0', -- input
|
||||
enable_31 => '0', -- input
|
||||
enable_32 => '0', -- input
|
||||
enable_33 => '0', -- input
|
||||
enable_34 => '0', -- input
|
||||
enable_35 => '0', -- input
|
||||
enable_36 => '0', -- input
|
||||
enable_37 => '0', -- input
|
||||
enable_38 => '0', -- input
|
||||
enable_39 => '0', -- input
|
||||
enable_40 => '0', -- input
|
||||
enable_41 => '0', -- input
|
||||
enable_42 => '0', -- input
|
||||
enable_43 => '0', -- input
|
||||
enable_44 => '0', -- input
|
||||
enable_45 => '0', -- input
|
||||
enable_46 => '0', -- input
|
||||
enable_47 => '0', -- input
|
||||
enable_48 => '0', -- input
|
||||
enable_49 => '0', -- input
|
||||
enable_50 => '0', -- input
|
||||
enable_51 => '0', -- input
|
||||
enable_52 => '0', -- input
|
||||
enable_53 => '0', -- input
|
||||
enable_54 => '0', -- input
|
||||
enable_55 => '0', -- input
|
||||
enable_56 => '0', -- input
|
||||
enable_57 => '0', -- input
|
||||
enable_58 => '0', -- input
|
||||
enable_59 => '0', -- input
|
||||
enable_60 => '0', -- input
|
||||
enable_61 => '0', -- input
|
||||
enable_62 => '0', -- input
|
||||
enable_63 => '0', -- input
|
||||
|
||||
fifo_rd_en => fifo_rd_en,-- input
|
||||
fifo_rd_valid => fifo_rd_valid , -- output
|
||||
fifo_rd_underflow => fifo_rd_underflow, -- output
|
||||
|
||||
fifo_rd_data_0 => fifo_rd_data_0, --
|
||||
fifo_rd_data_1 => fifo_rd_data_1, --
|
||||
fifo_rd_data_2 => fifo_rd_data_2, --
|
||||
fifo_rd_data_3 => fifo_rd_data_3, --
|
||||
fifo_rd_data_4 => fifo_rd_data_4, --
|
||||
fifo_rd_data_5 => fifo_rd_data_5, --
|
||||
fifo_rd_data_6 => fifo_rd_data_6, --
|
||||
fifo_rd_data_7 => fifo_rd_data_7, --
|
||||
fifo_rd_data_8 => fifo_rd_data_8 , --
|
||||
fifo_rd_data_9 => fifo_rd_data_9 , --
|
||||
fifo_rd_data_10 => fifo_rd_data_10, --
|
||||
fifo_rd_data_11 => fifo_rd_data_11, --
|
||||
fifo_rd_data_12 => fifo_rd_data_12, --
|
||||
fifo_rd_data_13 => fifo_rd_data_13, --
|
||||
fifo_rd_data_14 => fifo_rd_data_14, --
|
||||
fifo_rd_data_15 => fifo_rd_data_15, --
|
||||
fifo_rd_data_16 => fifo_rd_data_16, --
|
||||
fifo_rd_data_17 => fifo_rd_data_17, --
|
||||
fifo_rd_data_18 => fifo_rd_data_18, --
|
||||
fifo_rd_data_19 => fifo_rd_data_19, --
|
||||
fifo_rd_data_20 => fifo_rd_data_20, --
|
||||
fifo_rd_data_21 => fifo_rd_data_21, --
|
||||
fifo_rd_data_22 => fifo_rd_data_22, --
|
||||
fifo_rd_data_23 => fifo_rd_data_23, --
|
||||
fifo_rd_data_24 => fifo_rd_data_24, --
|
||||
fifo_rd_data_25 => fifo_rd_data_25, --
|
||||
fifo_rd_data_26 => fifo_rd_data_26, --
|
||||
fifo_rd_data_27 => fifo_rd_data_27, --
|
||||
fifo_rd_data_28 => fifo_rd_data_28, --
|
||||
fifo_rd_data_29 => fifo_rd_data_29, --
|
||||
fifo_rd_data_30 => fifo_rd_data_30, --
|
||||
fifo_rd_data_31 => fifo_rd_data_31, --
|
||||
fifo_rd_data_32 => fifo_rd_data_32, --
|
||||
fifo_rd_data_33 => fifo_rd_data_33, --
|
||||
fifo_rd_data_34 => fifo_rd_data_34, --
|
||||
fifo_rd_data_35 => fifo_rd_data_35, --
|
||||
fifo_rd_data_36 => fifo_rd_data_36, --
|
||||
fifo_rd_data_37 => fifo_rd_data_37, --
|
||||
fifo_rd_data_38 => fifo_rd_data_38, --
|
||||
fifo_rd_data_39 => fifo_rd_data_39, --
|
||||
fifo_rd_data_40 => fifo_rd_data_40, --
|
||||
fifo_rd_data_41 => fifo_rd_data_41, --
|
||||
fifo_rd_data_42 => fifo_rd_data_42, --
|
||||
fifo_rd_data_43 => fifo_rd_data_43, --
|
||||
fifo_rd_data_44 => fifo_rd_data_44, --
|
||||
fifo_rd_data_45 => fifo_rd_data_45, --
|
||||
fifo_rd_data_46 => fifo_rd_data_46, --
|
||||
fifo_rd_data_47 => fifo_rd_data_47, --
|
||||
fifo_rd_data_48 => fifo_rd_data_48, --
|
||||
fifo_rd_data_49 => fifo_rd_data_49, --
|
||||
fifo_rd_data_50 => fifo_rd_data_50, --
|
||||
fifo_rd_data_51 => fifo_rd_data_51, --
|
||||
fifo_rd_data_52 => fifo_rd_data_52, --
|
||||
fifo_rd_data_53 => fifo_rd_data_53, --
|
||||
fifo_rd_data_54 => fifo_rd_data_54, --
|
||||
fifo_rd_data_55 => fifo_rd_data_55, --
|
||||
fifo_rd_data_56 => fifo_rd_data_56, --
|
||||
fifo_rd_data_57 => fifo_rd_data_57, --
|
||||
fifo_rd_data_58 => fifo_rd_data_58, --
|
||||
fifo_rd_data_59 => fifo_rd_data_59, --
|
||||
fifo_rd_data_60 => fifo_rd_data_60, --
|
||||
fifo_rd_data_61 => fifo_rd_data_61, --
|
||||
fifo_rd_data_62 => fifo_rd_data_62, --
|
||||
fifo_rd_data_63 => fifo_rd_data_63, --
|
||||
|
||||
s_axis_valid => m_axis_tvalid_i,-- input ,
|
||||
s_axis_ready => m_axis_tready_i,-- output ,
|
||||
s_axis_data => m_axis_tdata_i -- output
|
||||
);
|
||||
|
||||
|
||||
|
||||
process
|
||||
begin
|
||||
wait for 200 ns;
|
||||
|
||||
-- cmd_send_0 <= '1';
|
||||
-- wait for 500 ns;
|
||||
-- dac_holdoff_0 <= '0';
|
||||
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"1111_2222";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"3333_4444";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"5555_6666";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"7777_8888";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= (others => '0');
|
||||
dds_pulse_dval_0 <= '0';
|
||||
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"9999_aaaa";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"bbbb_cccc";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"dddd_eeee";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"ffff_1234";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= (others => '0');
|
||||
dds_pulse_dval_1 <= '0';
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"1122_3344";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"5566_7788";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"99aa_bbcc";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"ddee_ff00";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= (others => '0');
|
||||
dds_pulse_dval_2 <= '0';
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"0123_4567";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"89ab_cdef";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"fedc_ba98";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"7654_3210";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= (others => '0');
|
||||
dds_pulse_dval_3 <= '0';
|
||||
|
||||
wait for 500 ns;
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
-- m_axis_tready_i <= '1';
|
||||
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
end architecture behavior;
|
||||
@@ -0,0 +1,317 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:53:22 03/24/2017
|
||||
-- Design Name:
|
||||
-- Module Name:
|
||||
-- Project Name: xem7350
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: dac_interface
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
entity test_bench is
|
||||
end test_bench;
|
||||
|
||||
architecture behavior of test_bench is
|
||||
|
||||
constant C_M_AXI_DATA_WIDTH : integer := 32;
|
||||
constant C_M_AXI_ADDR_WIDTH : integer := 32;
|
||||
|
||||
-- Clock period definitions
|
||||
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
|
||||
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
|
||||
|
||||
signal s_axi_aclk : std_logic := '0';
|
||||
signal m_axi_aclk : std_logic := '0';
|
||||
|
||||
signal s_axi_aresetn : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal reset : std_logic_vector(0 to 2) := (others => '1');
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0) := (others => '0');
|
||||
signal cmd_send : std_logic := '0';
|
||||
|
||||
signal mode : std_logic := '0';
|
||||
signal scale : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal dac_holdoff : std_logic := '0';
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal idle_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal phase_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal phase_off : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal swap_sf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal mb_m_axi_awaddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_awprot : std_logic_vector (2 downto 0);
|
||||
signal mb_m_axi_awvalid : std_logic;
|
||||
signal mb_m_axi_awready : std_logic;
|
||||
|
||||
-- master interface write data
|
||||
signal mb_m_axi_wdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_wstrb : std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0);
|
||||
signal mb_m_axi_wvalid : std_logic;
|
||||
signal mb_m_axi_wready : std_logic;
|
||||
|
||||
-- master interface write response
|
||||
signal mb_m_axi_bresp : std_logic_vector (1 downto 0);
|
||||
signal mb_m_axi_bvalid : std_logic;
|
||||
signal mb_m_axi_bready : std_logic;
|
||||
|
||||
-- master interface read address
|
||||
signal mb_m_axi_araddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_arprot : std_logic_vector (2 downto 0);
|
||||
signal mb_m_axi_arvalid : std_logic;
|
||||
signal mb_m_axi_arready : std_logic;
|
||||
|
||||
signal mb_m_axi_rdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_rresp : std_logic_vector (1 downto 0);
|
||||
signal mb_m_axi_rvalid : std_logic;
|
||||
signal mb_m_axi_rready : std_logic;
|
||||
|
||||
signal m_axis_tdata : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid : std_logic;
|
||||
signal m_axis_tready : std_logic;
|
||||
|
||||
signal fifo_rd_valid : std_logic;
|
||||
signal fifo_rd_underflow : std_logic;
|
||||
signal fifo_rd_data_0 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_1 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_2 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_3 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_4 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_5 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_6 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_7 : std_logic_vector(15 downto 0);
|
||||
|
||||
signal fifo_rd_enable : std_logic := '0';
|
||||
signal fifo_rd_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
s_axi_aclk <= not s_axi_aclk after S_AXI_ACLK_PERIOD/2;
|
||||
m_axi_aclk <= not m_axi_aclk after M_AXI_ACLK_PERIOD/2;
|
||||
|
||||
process(s_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk)) then
|
||||
s_axi_aresetn <= s_axi_aresetn(1 to 2) & '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axi_aclk)) then
|
||||
reset <= reset(1 to 2) & '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_pulse_wrapper : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
SIM_ENABLED => TRUE,
|
||||
FPGA_REVISION_DATE => x"0911_2023",
|
||||
MINOR_REV => x"01"
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk,
|
||||
s_axi_aresetn_in => s_axi_aresetn(0),
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
mode_in => mode,
|
||||
scale_in => scale,
|
||||
dac_holdoff_in => dac_holdoff,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
m_axis_aclk_in => m_axi_aclk,
|
||||
|
||||
m_axis_tdata_out => m_axis_tdata,
|
||||
m_axis_tvalid_out => m_axis_tvalid,
|
||||
m_axis_tready_in => m_axis_tready,
|
||||
|
||||
cmd_send_cnt_out => open,
|
||||
pipe_in_ch1_fifo_rden_cnt_out => open,
|
||||
m_axis_tvalid_cnt_out => open,
|
||||
dds_pulse_data_cnt_out => open,
|
||||
|
||||
reset_in => reset(0)
|
||||
);
|
||||
|
||||
i_util_upack2_0 : entity work.util_upack2_0
|
||||
port map (
|
||||
clk => m_axi_aclk,
|
||||
reset => reset(0),
|
||||
enable_0 => fifo_rd_enable,
|
||||
enable_1 => fifo_rd_enable,
|
||||
enable_2 => fifo_rd_enable,
|
||||
enable_3 => fifo_rd_enable,
|
||||
enable_4 => fifo_rd_enable,
|
||||
enable_5 => fifo_rd_enable,
|
||||
enable_6 => fifo_rd_enable,
|
||||
enable_7 => fifo_rd_enable,
|
||||
fifo_rd_en => fifo_rd_r,
|
||||
fifo_rd_valid => fifo_rd_valid,
|
||||
fifo_rd_underflow => fifo_rd_underflow,
|
||||
fifo_rd_data_0 => fifo_rd_data_0,
|
||||
fifo_rd_data_1 => fifo_rd_data_1,
|
||||
fifo_rd_data_2 => fifo_rd_data_2,
|
||||
fifo_rd_data_3 => fifo_rd_data_3,
|
||||
fifo_rd_data_4 => fifo_rd_data_4,
|
||||
fifo_rd_data_5 => fifo_rd_data_5,
|
||||
fifo_rd_data_6 => fifo_rd_data_6,
|
||||
fifo_rd_data_7 => fifo_rd_data_7,
|
||||
s_axis_data => m_axis_tdata,
|
||||
s_axis_valid => m_axis_tvalid,
|
||||
s_axis_ready => m_axis_tready
|
||||
);
|
||||
|
||||
process(m_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axi_aclk)) then
|
||||
if (fifo_rd_enable = '1') then
|
||||
fifo_rd_r <= not fifo_rd_r;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait for 1.5 us;
|
||||
|
||||
fifo_rd_enable <= '1';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- i_dds_pulse_intfc_v1_0 : entity work.dds_pulse_intfc_v1_0
|
||||
-- generic map (
|
||||
-- FPGA_REVISION_DATE => x"0911_2023",
|
||||
-- MINOR_REV => x"00",
|
||||
--
|
||||
-- -- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
-- C_S00_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
|
||||
-- C_S00_AXI_ADDR_WIDTH => 6
|
||||
-- )
|
||||
-- port map (
|
||||
-- -- Users to add ports here
|
||||
-- m_axis_aclk => m_axi_aclk,
|
||||
-- reset => reset(0),
|
||||
-- m_axis_tdata => open,
|
||||
-- m_axis_tvalid => open,
|
||||
-- m_axis_tready => '1',
|
||||
-- -- User ports ends
|
||||
-- -- Do not modify the ports beyond this line
|
||||
--
|
||||
--
|
||||
-- -- Ports of Axi Slave Bus Interface S00_AXI
|
||||
-- s00_axi_aclk => s_axi_aclk,
|
||||
-- s00_axi_aresetn => s_axi_aresetn(0),
|
||||
--
|
||||
-- s00_axi_awaddr => mb_m_axi_awaddr(5 DOWNTO 0),-- : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- s00_axi_awprot => mb_m_axi_awprot, --: in std_logic_vector(2 downto 0);
|
||||
-- s00_axi_awvalid => mb_m_axi_awvalid, --: in std_logic;
|
||||
-- s00_axi_awready => mb_m_axi_awready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_wdata => mb_m_axi_wdata, --: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- s00_axi_wstrb => mb_m_axi_wstrb, --: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- s00_axi_wvalid => mb_m_axi_wvalid, --: in std_logic;
|
||||
-- s00_axi_wready => mb_m_axi_wready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_bresp => mb_m_axi_bresp, --: out std_logic_vector(1 downto 0);
|
||||
-- s00_axi_bvalid => mb_m_axi_bvalid, --: out std_logic;
|
||||
-- s00_axi_bready => mb_m_axi_bready, --: in std_logic;
|
||||
--
|
||||
-- s00_axi_araddr => mb_m_axi_araddr(5 DOWNTO 0), --: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- s00_axi_arprot => mb_m_axi_arprot, --: in std_logic_vector(2 downto 0);
|
||||
-- s00_axi_arvalid => mb_m_axi_arvalid, --: in std_logic;
|
||||
-- s00_axi_arready => mb_m_axi_arready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_rdata => mb_m_axi_rdata, --: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- s00_axi_rresp => mb_m_axi_rresp, --: out std_logic_vector(1 downto 0);
|
||||
-- s00_axi_rvalid => mb_m_axi_rvalid, --: out std_logic;
|
||||
-- s00_axi_rready => mb_m_axi_rready -- : in std_logic
|
||||
-- );
|
||||
|
||||
i_axi_lite_traffic_gen_mb : entity work.axi_lite_traffic_gen
|
||||
generic map (
|
||||
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
|
||||
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH
|
||||
)
|
||||
port map (
|
||||
m_axi_aclk => s_axi_aclk,
|
||||
m_axi_aresetn => s_axi_aresetn(0),
|
||||
|
||||
-- Master Interface Write Address
|
||||
m_axi_awaddr => mb_m_axi_awaddr, -- : out
|
||||
m_axi_awprot => mb_m_axi_awprot, -- : out
|
||||
m_axi_awvalid => mb_m_axi_awvalid, -- : out
|
||||
m_axi_awready => mb_m_axi_awready, -- : in
|
||||
--
|
||||
-- master interface write data --
|
||||
m_axi_wdata => mb_m_axi_wdata, -- : out
|
||||
m_axi_wstrb => mb_m_axi_wstrb, -- : out
|
||||
m_axi_wvalid => mb_m_axi_wvalid, -- : out
|
||||
m_axi_wready => mb_m_axi_wready, -- : in
|
||||
--
|
||||
-- master interface write response --
|
||||
m_axi_bresp => mb_m_axi_bresp, -- : in
|
||||
m_axi_bvalid => mb_m_axi_bvalid, -- : in
|
||||
m_axi_bready => mb_m_axi_bready, -- : out
|
||||
--
|
||||
-- master interface read address --
|
||||
m_axi_araddr => mb_m_axi_araddr, -- : out
|
||||
m_axi_arprot => mb_m_axi_arprot, -- : out
|
||||
m_axi_arvalid => mb_m_axi_arvalid, -- : out
|
||||
m_axi_arready => mb_m_axi_arready, -- : in
|
||||
--
|
||||
-- master interface read data --
|
||||
m_axi_rdata => mb_m_axi_rdata, -- : in
|
||||
m_axi_rresp => mb_m_axi_rresp, -- : in
|
||||
m_axi_rvalid => mb_m_axi_rvalid, -- : in
|
||||
m_axi_rready => mb_m_axi_rready, -- : out
|
||||
|
||||
num_burst_cnt_out => open,
|
||||
xfer_en_out => open,
|
||||
xfer_done_in => '0',
|
||||
dma_xfer_done_in => '0',
|
||||
|
||||
buffer_rdy_intr_in => '0'
|
||||
|
||||
);
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,610 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>dds_pulse_wrapper</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_out</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata_out</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid_out</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>dds_pulse_wrapper</spirit:modelName>
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||||
<spirit:fileSetRef>
|
||||
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|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
|
||||
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|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:localName>
|
||||
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|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>d4e6fb9a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>dds_pulse_wrapper</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:localName>
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||||
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|
||||
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|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
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<spirit:fileSetRef>
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<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:localName>
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|
||||
<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
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|
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||||
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|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
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<spirit:fileSetRef>
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|
||||
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|
||||
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|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:fileSets>
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<spirit:description>dds_pulse_wrapper_v1_0</spirit:description>
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<spirit:parameter>
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<spirit:name>SIM_ENABLED</spirit:name>
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<spirit:displayName>Sim Enabled</spirit:displayName>
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||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SIM_ENABLED">FALSE</spirit:value>
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</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dds_pulse_wrapper_v1_0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FPGA_REVISION_DATE</spirit:name>
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<spirit:displayName>Fpga Revision Date</spirit:displayName>
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<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_REVISION_DATE" spirit:bitStringLength="32">0x10242023</spirit:value>
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</spirit:parameter>
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<spirit:vendorExtensions>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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<xilinx:displayName>dds_pulse_wrapper_v1_0</xilinx:displayName>
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<xilinx:tag xilinx:name="nopcore"/>
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<xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
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</spirit:component>
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||||
@@ -0,0 +1,85 @@
|
||||
library ieee;
|
||||
Library UNISIM;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity iprog_icap is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
go : in std_logic
|
||||
);
|
||||
end iprog_icap;
|
||||
|
||||
architecture iprog of iprog_icap is
|
||||
|
||||
attribute mark_debug : string;
|
||||
attribute keep : string;
|
||||
constant CCOUNT : integer := 8;
|
||||
|
||||
signal cnt_bitst : integer range 0 to CCOUNT := 0;
|
||||
attribute keep of cnt_bitst : signal is "true";
|
||||
signal reboot : std_logic := '0';
|
||||
attribute keep of reboot : signal is "true";
|
||||
signal reprog : std_logic := '0';
|
||||
attribute keep of reprog : signal is "true";
|
||||
signal icap_cs : std_logic := '1';
|
||||
signal icap_rw : std_logic := '1';
|
||||
signal d : std_logic_vector(31 downto 0) :=X"FBFFFFAC";
|
||||
signal bit_swapped : std_logic_vector(31 downto 0) :=X"FFFFFFFF";
|
||||
|
||||
begin
|
||||
|
||||
ICAPE3_inst: ICAPE3
|
||||
port map (
|
||||
AVAIL => open,
|
||||
O => open,
|
||||
PRDONE => open,
|
||||
PRERROR => open,
|
||||
CLK => clk, -- Icap Clock Input
|
||||
CSIB => icap_cs, -- Active-Low ICAP Enable
|
||||
I => bit_swapped, -- Configuration data input bus
|
||||
RDWRB => icap_rw -- Read/Write Select input 1= Write
|
||||
);
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if (rising_edge(clk)) then
|
||||
if (go = '1') then
|
||||
reboot <= '1';
|
||||
end if;
|
||||
|
||||
if (reboot = '0') then
|
||||
icap_cs <= '1';
|
||||
icap_rw <= '1';
|
||||
cnt_bitst <= 0;
|
||||
else
|
||||
if(cnt_bitst /= CCOUNT) then
|
||||
cnt_bitst <= cnt_bitst + 1;
|
||||
end if;
|
||||
case cnt_bitst is
|
||||
when 0 => icap_cs <= '0'; icap_rw <= '0';
|
||||
-- using registers for now
|
||||
when 1 => d <= x"FFFFFFFF"; -- Dummy Word
|
||||
when 2 => d <= x"AA995566"; -- Sync Word
|
||||
when 3 => d <= x"20000000"; -- Type 1 NO OP
|
||||
when 4 => d <= x"30020001"; -- Type 1 Write 1 Word to WBSTAR
|
||||
when 5 => d <= x"00000000"; -- Warm Boot Start Address
|
||||
when 6 => d <= x"20000000"; -- Type 1 NO OP
|
||||
when 7 => d <= x"30008001"; -- Type 1 Write 1 Words to CMD
|
||||
when 8 => d <= x"0000000F"; -- IPROG Command
|
||||
-- Bye, bye
|
||||
when others => icap_cs <= '1'; icap_rw <= '1';
|
||||
end case;
|
||||
end if; -- if go
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Bit swap the ICAP bytes
|
||||
bit_swapped(31 downto 24) <= d(24)&d(25)&d(26)&d(27)&d(28)&d(29)&d(30)&d(31);
|
||||
bit_swapped(23 downto 16) <= d(16)&d(17)&d(18)&d(19)&d(20)&d(21)&d(22)&d(23);
|
||||
bit_swapped(15 downto 8) <= d(8)&d(9)&d(10)&d(11)&d(12)&d(13)&d(14)&d(15);
|
||||
bit_swapped(7 downto 0) <= d(0)&d(1)&d(2)&d(3)&d(4)&d(5)&d(6)&d(7);
|
||||
|
||||
end iprog;
|
||||
@@ -0,0 +1,228 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "adder_16signed_16signed_latency2",
|
||||
"cell_name": "i_dds_pulse_2x_top/i_pulse_adder1",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../zcu102/zcu102_test2/ad9081_fmca_ebz_zcu102/ad9081_fmca_ebz_zcu102.tmp/dds_pulse_wrapper_v1_0_project/dds_pulse_wrapper_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ],
|
||||
"Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Add_Mode": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
|
||||
"Out_Width": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Automatic", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Constant": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"B_Value": [ { "value": "0000000000000000", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_In": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_Out": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Borrow_Sense": [ { "value": "Active_Low", "resolve_type": "user", "usage": "all" } ],
|
||||
"SCLR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SSET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Bypass_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_Ctrl_Priority": [ { "value": "Reset_Overrides_Set", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_CE_Priority": [ { "value": "Sync_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass_CE_Priority": [ { "value": "CE_Overrides_Bypass", "resolve_type": "user", "usage": "all" } ],
|
||||
"AINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADD_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_CONSTANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "0000000000000000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYPASS_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCLR_OVERRIDES_SSET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BORROW_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
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}
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{
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
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||||
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||||
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+169
@@ -0,0 +1,169 @@
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|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../zcu102/zcu102_test2/ad9081_fmca_ebz_zcu102/ad9081_fmca_ebz_zcu102.tmp/dds_pulse_wrapper_v1_0_project/dds_pulse_wrapper_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Common_Clock_Builtin_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "992", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "991", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
"C_WR_DEPTH_AXIS": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_WRCH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RACH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_RDCH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH_AXIS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNTS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_PROG_FLAGS_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_WRCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RACH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_RDCH": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL_AXIS": [ { "value": "1023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS": [ { "value": "1022", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_WRCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RACH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_RDCH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu9eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvb1156" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../zcu102/zcu102_test2/ad9081_fmca_ebz_zcu102/ad9081_fmca_ebz_zcu102.tmp/dds_pulse_wrapper_v1_0_project/dds_pulse_wrapper_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"srst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"din": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"overflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"underflow": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"prog_full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"core_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,380 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top #(
|
||||
parameter TX_JESD_L = 8,
|
||||
parameter TX_NUM_LINKS = 1,
|
||||
parameter RX_JESD_L = 8,
|
||||
parameter RX_NUM_LINKS = 1,
|
||||
parameter SHARED_DEVCLK = 0,
|
||||
parameter JESD_MODE = "8B10B"
|
||||
) (
|
||||
input [12:0] gpio_bd_i,
|
||||
output [ 7:0] gpio_bd_o,
|
||||
|
||||
// FMC HPC IOs
|
||||
input [1:0] agc0,
|
||||
input [1:0] agc1,
|
||||
input [1:0] agc2,
|
||||
input [1:0] agc3,
|
||||
input clkin6_n,
|
||||
input clkin6_p,
|
||||
input clkin10_n,
|
||||
input clkin10_p,
|
||||
input fpga_refclk_in_n,
|
||||
input fpga_refclk_in_p,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
||||
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
||||
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
||||
input fpga_syncin_0_n,
|
||||
input fpga_syncin_0_p,
|
||||
inout fpga_syncin_1_n,
|
||||
inout fpga_syncin_1_p,
|
||||
output fpga_syncout_0_n,
|
||||
output fpga_syncout_0_p,
|
||||
inout fpga_syncout_1_n,
|
||||
inout fpga_syncout_1_p,
|
||||
inout [10:0] gpio,
|
||||
inout hmc_gpio1,
|
||||
output hmc_sync,
|
||||
input [1:0] irqb,
|
||||
output rstb,
|
||||
output [1:0] rxen,
|
||||
output spi0_csb,
|
||||
input spi0_miso,
|
||||
output spi0_mosi,
|
||||
output spi0_sclk,
|
||||
output spi1_csb,
|
||||
output spi1_sclk,
|
||||
inout spi1_sdio,
|
||||
input sysref2_n,
|
||||
input sysref2_p,
|
||||
input ext_trigger_in,
|
||||
output [1:0] txen
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [94:0] gpio_i;
|
||||
wire [94:0] gpio_o;
|
||||
wire [94:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
|
||||
wire ref_clk;
|
||||
wire sysref;
|
||||
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
||||
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
||||
|
||||
wire [7:0] rx_data_p_loc;
|
||||
wire [7:0] rx_data_n_loc;
|
||||
wire [7:0] tx_data_p_loc;
|
||||
wire [7:0] tx_data_n_loc;
|
||||
|
||||
wire clkin6;
|
||||
wire clkin10;
|
||||
wire tx_device_clk;
|
||||
wire rx_device_clk_internal;
|
||||
wire rx_device_clk;
|
||||
|
||||
wire dac_rst;
|
||||
wire tx_device_clk_div4;
|
||||
|
||||
wire [127:0] s_axis_tx_data_0_tdata;
|
||||
wire s_axis_tx_data_0_tready;
|
||||
wire s_axis_tx_data_0_tvalid;
|
||||
|
||||
assign iic_rstn = 1'b1;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fpga_refclk_in_p),
|
||||
.IB (fpga_refclk_in_n),
|
||||
.O (ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_sysref (
|
||||
.I (sysref2_p),
|
||||
.IB (sysref2_n),
|
||||
.O (sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_device_clk (
|
||||
.I (clkin6_p),
|
||||
.IB (clkin6_n),
|
||||
.O (clkin6));
|
||||
|
||||
IBUFDS i_ibufds_rx_device_clk (
|
||||
.I (clkin10_p),
|
||||
.IB (clkin10_n),
|
||||
.O (clkin10));
|
||||
|
||||
IBUFDS i_ibufds_syncin_0 (
|
||||
.I (fpga_syncin_0_p),
|
||||
.IB (fpga_syncin_0_n),
|
||||
.O (tx_syncin[0]));
|
||||
|
||||
OBUFDS i_obufds_syncout_0 (
|
||||
.I (rx_syncout[0]),
|
||||
.O (fpga_syncout_0_p),
|
||||
.OB (fpga_syncout_0_n));
|
||||
|
||||
BUFG i_tx_device_clk (
|
||||
.I (clkin6),
|
||||
.O (tx_device_clk));
|
||||
|
||||
|
||||
BUFGCE_DIV #(
|
||||
.BUFGCE_DIVIDE(4), // 1-8
|
||||
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
|
||||
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
|
||||
.IS_I_INVERTED(1'b0) // Optional inversion for I
|
||||
)
|
||||
BUFGCE_DIV_inst (
|
||||
.O(tx_device_clk_div4), // 1-bit output: Buffer
|
||||
.CE(1'b1), // 1-bit input: Buffer enable
|
||||
.CLR(1'b0), // 1-bit input: Asynchronous clear
|
||||
.I(clkin6) // 1-bit input: Buffer
|
||||
);
|
||||
// E
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG i_rx_device_clk (
|
||||
.I (clkin10),
|
||||
.O (rx_device_clk_internal));
|
||||
|
||||
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
|
||||
|
||||
// spi
|
||||
|
||||
assign spi0_csb = spi0_csn[0];
|
||||
assign spi1_csb = spi1_csn[0];
|
||||
|
||||
ad_3w_spi #(
|
||||
.NUM_OF_SLAVES(1)
|
||||
) i_spi (
|
||||
.spi_csn (spi1_csn[0]),
|
||||
.spi_clk (spi1_sclk),
|
||||
.spi_mosi (spi1_mosi),
|
||||
.spi_miso (spi1_miso),
|
||||
.spi_sdio (spi1_sdio),
|
||||
.spi_dir ());
|
||||
|
||||
// gpios
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(12)
|
||||
) i_iobuf (
|
||||
.dio_t (gpio_t[43:32]),
|
||||
.dio_i (gpio_o[43:32]),
|
||||
.dio_o (gpio_i[43:32]),
|
||||
.dio_p ({hmc_gpio1, // 43
|
||||
gpio[10:0]})); // 42-32
|
||||
|
||||
assign gpio_i[44] = agc0[0];
|
||||
assign gpio_i[45] = agc0[1];
|
||||
assign gpio_i[46] = agc1[0];
|
||||
assign gpio_i[47] = agc1[1];
|
||||
assign gpio_i[48] = agc2[0];
|
||||
assign gpio_i[49] = agc2[1];
|
||||
assign gpio_i[50] = agc3[0];
|
||||
assign gpio_i[51] = agc3[1];
|
||||
assign gpio_i[52] = irqb[0];
|
||||
assign gpio_i[53] = irqb[1];
|
||||
|
||||
assign hmc_sync = gpio_o[54];
|
||||
assign rstb = gpio_o[55];
|
||||
assign rxen[0] = gpio_o[56];
|
||||
assign rxen[1] = gpio_o[57];
|
||||
assign txen[0] = gpio_o[58];
|
||||
assign txen[1] = gpio_o[59];
|
||||
|
||||
generate
|
||||
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign tx_syncin[1] = fpga_syncin_1_p;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncin_iobuf (
|
||||
.dio_t (gpio_t[61:60]),
|
||||
.dio_i (gpio_o[61:60]),
|
||||
.dio_o (gpio_i[61:60]),
|
||||
.dio_p ({fpga_syncin_1_n, // 61
|
||||
fpga_syncin_1_p})); // 60
|
||||
end
|
||||
|
||||
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
|
||||
assign fpga_syncout_1_p = rx_syncout[1];
|
||||
assign fpga_syncout_1_n = 0;
|
||||
end else begin
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_syncout_iobuf (
|
||||
.dio_t (gpio_t[63:62]),
|
||||
.dio_i (gpio_o[63:62]),
|
||||
.dio_o (gpio_i[63:62]),
|
||||
.dio_p ({fpga_syncout_1_n, // 63
|
||||
fpga_syncout_1_p})); // 62
|
||||
end
|
||||
endgenerate
|
||||
/* Board GPIOS. Buttons, LEDs, etc... */
|
||||
assign gpio_i[20: 8] = gpio_bd_i;
|
||||
assign gpio_bd_o = gpio_o[7:0];
|
||||
|
||||
// Unused GPIOs
|
||||
assign gpio_i[59:54] = gpio_o[59:54];
|
||||
assign gpio_i[94:64] = gpio_o[94:64];
|
||||
assign gpio_i[31:21] = gpio_o[31:21];
|
||||
assign gpio_i[7:0] = gpio_o[7:0];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.spi0_csn (spi0_csn),
|
||||
.spi0_miso (spi0_miso),
|
||||
.spi0_mosi (spi0_mosi),
|
||||
.spi0_sclk (spi0_sclk),
|
||||
.spi1_csn (spi1_csn),
|
||||
.spi1_miso (spi1_miso),
|
||||
.spi1_mosi (spi1_mosi),
|
||||
.spi1_sclk (spi1_sclk),
|
||||
// FMC HPC
|
||||
.rx_data_0_n (rx_data_n_loc[0]),
|
||||
.rx_data_0_p (rx_data_p_loc[0]),
|
||||
.rx_data_1_n (rx_data_n_loc[1]),
|
||||
.rx_data_1_p (rx_data_p_loc[1]),
|
||||
.rx_data_2_n (rx_data_n_loc[2]),
|
||||
.rx_data_2_p (rx_data_p_loc[2]),
|
||||
.rx_data_3_n (rx_data_n_loc[3]),
|
||||
.rx_data_3_p (rx_data_p_loc[3]),
|
||||
.rx_data_4_n (rx_data_n_loc[4]),
|
||||
.rx_data_4_p (rx_data_p_loc[4]),
|
||||
.rx_data_5_n (rx_data_n_loc[5]),
|
||||
.rx_data_5_p (rx_data_p_loc[5]),
|
||||
.rx_data_6_n (rx_data_n_loc[6]),
|
||||
.rx_data_6_p (rx_data_p_loc[6]),
|
||||
.rx_data_7_n (rx_data_n_loc[7]),
|
||||
.rx_data_7_p (rx_data_p_loc[7]),
|
||||
.tx_data_0_n (tx_data_n_loc[0]),
|
||||
.tx_data_0_p (tx_data_p_loc[0]),
|
||||
.tx_data_1_n (tx_data_n_loc[1]),
|
||||
.tx_data_1_p (tx_data_p_loc[1]),
|
||||
.tx_data_2_n (tx_data_n_loc[2]),
|
||||
.tx_data_2_p (tx_data_p_loc[2]),
|
||||
.tx_data_3_n (tx_data_n_loc[3]),
|
||||
.tx_data_3_p (tx_data_p_loc[3]),
|
||||
.tx_data_4_n (tx_data_n_loc[4]),
|
||||
.tx_data_4_p (tx_data_p_loc[4]),
|
||||
.tx_data_5_n (tx_data_n_loc[5]),
|
||||
.tx_data_5_p (tx_data_p_loc[5]),
|
||||
.tx_data_6_n (tx_data_n_loc[6]),
|
||||
.tx_data_6_p (tx_data_p_loc[6]),
|
||||
.tx_data_7_n (tx_data_n_loc[7]),
|
||||
.tx_data_7_p (tx_data_p_loc[7]),
|
||||
.ref_clk_q0 (ref_clk),
|
||||
.ref_clk_q1 (ref_clk),
|
||||
.rx_device_clk (rx_device_clk),
|
||||
.tx_device_clk (tx_device_clk),
|
||||
.ext_trigger_in(ext_trigger_in),
|
||||
// .dac_rst_out (dac_rst),
|
||||
.fpga_reboot_out_0(fpga_reboot),
|
||||
.clk100_out(clk100),
|
||||
// .s_axis_tx_data_0_tdata (s_axis_tx_data_0_tdata),
|
||||
// .s_axis_tx_data_0_tvalid (s_axis_tx_data_0_tvalid),
|
||||
// .s_axis_tx_data_0_tready (s_axis_tx_data_0_tready),
|
||||
|
||||
.clk_in_1 (tx_device_clk_div4),
|
||||
.rx_sync_0 (rx_syncout),
|
||||
.tx_sync_0 (tx_syncin),
|
||||
.rx_sysref_0 (sysref),
|
||||
.tx_sysref_0 (sysref));
|
||||
|
||||
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
||||
|
||||
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||
/*
|
||||
dds_pulse_wrapper i_dds_pulse_wrapper (
|
||||
.clk_in (tx_device_clk_div4),
|
||||
|
||||
.m_axis_aclk_in (tx_device_clk),
|
||||
|
||||
.m_axis_tdata_out (s_axis_tx_data_0_tdata),
|
||||
.m_axis_tvalid_out (s_axis_tx_data_0_tvalid),
|
||||
.m_axis_tready_in (s_axis_tx_data_0_tready),
|
||||
|
||||
.rst_in (dac_rst)
|
||||
);
|
||||
|
||||
*/
|
||||
BUFGCE_DIV #(
|
||||
.BUFGCE_DIVIDE(2), // 1-8
|
||||
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
.IS_CE_INVERTED(1'b0), // Optional inversion for CE
|
||||
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
|
||||
.IS_I_INVERTED(1'b0) // Optional inversion for I
|
||||
)
|
||||
_BUFGCE_DIV_clk100 (
|
||||
.O(clk50), // 1-bit output: Buffer
|
||||
.CE(1'b1), // 1-bit input: Buffer enable
|
||||
.CLR(1'b0), // 1-bit input: Asynchronous clear
|
||||
.I(clk100) // 1-bit input: Buffer
|
||||
);
|
||||
|
||||
|
||||
iprog_icap i_iprog_icap (
|
||||
.clk (clk50),
|
||||
.go (fpga_reboot)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity tick_gen is
|
||||
generic(
|
||||
CLOCK_SPEED_MHZ : integer := 100
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
tick_1us_out : out std_logic;
|
||||
tick_1ms_out : out std_logic;
|
||||
tick_500ms_out : out std_logic;
|
||||
tick_750ms_out : out std_logic;
|
||||
tick_1s_out : out std_logic;
|
||||
|
||||
prog_us_tick_rate_in : in std_logic_vector(15 downto 0);
|
||||
prog_us_tick_out : out std_logic;
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity tick_gen;
|
||||
|
||||
architecture imp of tick_gen is
|
||||
|
||||
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
|
||||
signal usec_cnt_r : integer range 0 to 999;
|
||||
signal msec_cnt_r : integer range 0 to 499;
|
||||
signal msec_cnt1_r : integer range 0 to 999;
|
||||
signal tick_1us_r : std_logic;
|
||||
signal tick_1ms_r : std_logic;
|
||||
signal tick_500ms_r : std_logic;
|
||||
signal tick_750ms_r : std_logic;
|
||||
signal tick_1s_r : std_logic;
|
||||
|
||||
signal prog_usec_cnt_r : std_logic_vector(15 downto 0);
|
||||
signal prog_us_tick_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
tick_1us_out <= tick_1us_r;
|
||||
tick_1ms_out <= tick_1ms_r;
|
||||
tick_500ms_out <= tick_500ms_r;
|
||||
tick_750ms_out <= tick_750ms_r;
|
||||
tick_1s_out <= tick_1s_r;
|
||||
prog_us_tick_out <= prog_us_tick_r;
|
||||
|
||||
process(clk_in, reset_in)
|
||||
begin
|
||||
if(reset_in = '1') then
|
||||
sysclk_cnt_r <= 0;
|
||||
usec_cnt_r <= 0;
|
||||
msec_cnt_r <= 0;
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_us_tick_r <= '0';
|
||||
|
||||
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
|
||||
sysclk_cnt_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
else
|
||||
sysclk_cnt_r <= sysclk_cnt_r + 1;
|
||||
tick_1us_r <= '0';
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(usec_cnt_r = 999) then -- 1000us
|
||||
usec_cnt_r <= 0;
|
||||
tick_1ms_r <= '1';
|
||||
else
|
||||
usec_cnt_r <= usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt_r = 499) then -- 500ms
|
||||
msec_cnt_r <= 0;
|
||||
tick_500ms_r <= '1';
|
||||
else
|
||||
msec_cnt_r <= msec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt1_r = 749) then -- 750ms
|
||||
tick_750ms_r <= '1';
|
||||
end if;
|
||||
if(msec_cnt1_r = 999) then -- 1s
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1s_r <= '1';
|
||||
else
|
||||
msec_cnt1_r <= msec_cnt1_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '1';
|
||||
else
|
||||
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "SIM_ENABLED" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to update SIM_ENABLED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SIM_ENABLED { PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to validate SIM_ENABLED
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.SIM_ENABLED { MODELPARAM_VALUE.SIM_ENABLED PARAM_VALUE.SIM_ENABLED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SIM_ENABLED}] ${MODELPARAM_VALUE.SIM_ENABLED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user