318 lines
15 KiB
VHDL
318 lines
15 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:53:22 03/24/2017
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-- Design Name:
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-- Module Name:
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-- Project Name: xem7350
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: dac_interface
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.STD_LOGIC_arith.ALL;
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USE IEEE.STD_LOGIC_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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entity test_bench is
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end test_bench;
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architecture behavior of test_bench is
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constant C_M_AXI_DATA_WIDTH : integer := 32;
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constant C_M_AXI_ADDR_WIDTH : integer := 32;
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-- Clock period definitions
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constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
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constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
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signal s_axi_aclk : std_logic := '0';
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signal m_axi_aclk : std_logic := '0';
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signal s_axi_aresetn : std_logic_vector(0 to 2) := (others => '0');
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signal reset : std_logic_vector(0 to 2) := (others => '1');
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signal cmd_idx : std_logic_vector( 2 downto 0) := (others => '0');
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signal cmd_send : std_logic := '0';
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signal mode : std_logic := '0';
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signal scale : std_logic_vector(15 downto 0) := (others => '0');
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signal dac_holdoff : std_logic := '0';
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signal reserv1 : std_logic_vector(31 downto 0) := (others => '0');
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signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
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signal dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
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signal idle_samples : std_logic_vector(31 downto 0) := (others => '0');
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signal dds_samples : std_logic_vector(31 downto 0) := (others => '0');
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signal phase_inc : std_logic_vector(31 downto 0) := (others => '0');
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signal phase_off : std_logic_vector(31 downto 0) := (others => '0');
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signal swap_sf : std_logic_vector(31 downto 0) := (others => '0');
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signal mb_m_axi_awaddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
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signal mb_m_axi_awprot : std_logic_vector (2 downto 0);
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signal mb_m_axi_awvalid : std_logic;
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signal mb_m_axi_awready : std_logic;
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-- master interface write data
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signal mb_m_axi_wdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
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signal mb_m_axi_wstrb : std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0);
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signal mb_m_axi_wvalid : std_logic;
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signal mb_m_axi_wready : std_logic;
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-- master interface write response
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signal mb_m_axi_bresp : std_logic_vector (1 downto 0);
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signal mb_m_axi_bvalid : std_logic;
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signal mb_m_axi_bready : std_logic;
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-- master interface read address
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signal mb_m_axi_araddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
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signal mb_m_axi_arprot : std_logic_vector (2 downto 0);
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signal mb_m_axi_arvalid : std_logic;
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signal mb_m_axi_arready : std_logic;
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signal mb_m_axi_rdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
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signal mb_m_axi_rresp : std_logic_vector (1 downto 0);
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signal mb_m_axi_rvalid : std_logic;
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signal mb_m_axi_rready : std_logic;
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signal m_axis_tdata : std_logic_vector(127 downto 0);
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signal m_axis_tvalid : std_logic;
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signal m_axis_tready : std_logic;
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signal fifo_rd_valid : std_logic;
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signal fifo_rd_underflow : std_logic;
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signal fifo_rd_data_0 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_1 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_2 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_3 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_4 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_5 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_6 : std_logic_vector(15 downto 0);
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signal fifo_rd_data_7 : std_logic_vector(15 downto 0);
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signal fifo_rd_enable : std_logic := '0';
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signal fifo_rd_r : std_logic := '0';
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begin
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s_axi_aclk <= not s_axi_aclk after S_AXI_ACLK_PERIOD/2;
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m_axi_aclk <= not m_axi_aclk after M_AXI_ACLK_PERIOD/2;
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process(s_axi_aclk)
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begin
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if (rising_edge(s_axi_aclk)) then
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s_axi_aresetn <= s_axi_aresetn(1 to 2) & '1';
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end if;
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end process;
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process(m_axi_aclk)
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begin
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if (rising_edge(m_axi_aclk)) then
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reset <= reset(1 to 2) & '0';
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end if;
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end process;
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i_dds_pulse_wrapper : entity work.dds_pulse_wrapper
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generic map (
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SIM_ENABLED => TRUE,
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FPGA_REVISION_DATE => x"0911_2023",
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MINOR_REV => x"01"
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)
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port map (
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s_axi_aclk_in => s_axi_aclk,
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s_axi_aresetn_in => s_axi_aresetn(0),
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cmd_idx_in => cmd_idx,
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cmd_send_in => cmd_send,
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mode_in => mode,
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scale_in => scale,
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dac_holdoff_in => dac_holdoff,
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reserv1_in => reserv1,
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dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
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dds_phase_inc_step_size_in => dds_phase_inc_step_size,
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idle_samples_in => idle_samples,
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dds_samples_in => dds_samples,
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phase_inc_in => phase_inc,
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phase_off_in => phase_off,
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swap_sf_in => swap_sf,
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m_axis_aclk_in => m_axi_aclk,
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m_axis_tdata_out => m_axis_tdata,
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m_axis_tvalid_out => m_axis_tvalid,
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m_axis_tready_in => m_axis_tready,
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cmd_send_cnt_out => open,
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pipe_in_ch1_fifo_rden_cnt_out => open,
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m_axis_tvalid_cnt_out => open,
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dds_pulse_data_cnt_out => open,
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reset_in => reset(0)
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);
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i_util_upack2_0 : entity work.util_upack2_0
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port map (
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clk => m_axi_aclk,
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reset => reset(0),
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enable_0 => fifo_rd_enable,
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enable_1 => fifo_rd_enable,
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enable_2 => fifo_rd_enable,
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enable_3 => fifo_rd_enable,
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enable_4 => fifo_rd_enable,
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enable_5 => fifo_rd_enable,
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enable_6 => fifo_rd_enable,
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enable_7 => fifo_rd_enable,
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fifo_rd_en => fifo_rd_r,
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fifo_rd_valid => fifo_rd_valid,
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fifo_rd_underflow => fifo_rd_underflow,
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fifo_rd_data_0 => fifo_rd_data_0,
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fifo_rd_data_1 => fifo_rd_data_1,
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fifo_rd_data_2 => fifo_rd_data_2,
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fifo_rd_data_3 => fifo_rd_data_3,
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fifo_rd_data_4 => fifo_rd_data_4,
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fifo_rd_data_5 => fifo_rd_data_5,
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fifo_rd_data_6 => fifo_rd_data_6,
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fifo_rd_data_7 => fifo_rd_data_7,
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s_axis_data => m_axis_tdata,
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s_axis_valid => m_axis_tvalid,
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s_axis_ready => m_axis_tready
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);
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process(m_axi_aclk)
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begin
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if (rising_edge(m_axi_aclk)) then
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if (fifo_rd_enable = '1') then
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fifo_rd_r <= not fifo_rd_r;
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end if;
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end if;
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end process;
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process
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begin
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wait for 1.5 us;
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fifo_rd_enable <= '1';
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wait;
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end process;
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-- i_dds_pulse_intfc_v1_0 : entity work.dds_pulse_intfc_v1_0
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-- generic map (
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-- FPGA_REVISION_DATE => x"0911_2023",
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-- MINOR_REV => x"00",
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--
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-- -- Parameters of Axi Slave Bus Interface S00_AXI
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-- C_S00_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
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-- C_S00_AXI_ADDR_WIDTH => 6
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-- )
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-- port map (
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-- -- Users to add ports here
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-- m_axis_aclk => m_axi_aclk,
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-- reset => reset(0),
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-- m_axis_tdata => open,
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-- m_axis_tvalid => open,
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-- m_axis_tready => '1',
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-- -- User ports ends
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-- -- Do not modify the ports beyond this line
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--
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--
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-- -- Ports of Axi Slave Bus Interface S00_AXI
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-- s00_axi_aclk => s_axi_aclk,
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-- s00_axi_aresetn => s_axi_aresetn(0),
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--
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-- s00_axi_awaddr => mb_m_axi_awaddr(5 DOWNTO 0),-- : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
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-- s00_axi_awprot => mb_m_axi_awprot, --: in std_logic_vector(2 downto 0);
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-- s00_axi_awvalid => mb_m_axi_awvalid, --: in std_logic;
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-- s00_axi_awready => mb_m_axi_awready, --: out std_logic;
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--
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-- s00_axi_wdata => mb_m_axi_wdata, --: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
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-- s00_axi_wstrb => mb_m_axi_wstrb, --: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
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-- s00_axi_wvalid => mb_m_axi_wvalid, --: in std_logic;
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-- s00_axi_wready => mb_m_axi_wready, --: out std_logic;
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--
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-- s00_axi_bresp => mb_m_axi_bresp, --: out std_logic_vector(1 downto 0);
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-- s00_axi_bvalid => mb_m_axi_bvalid, --: out std_logic;
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-- s00_axi_bready => mb_m_axi_bready, --: in std_logic;
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--
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-- s00_axi_araddr => mb_m_axi_araddr(5 DOWNTO 0), --: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
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-- s00_axi_arprot => mb_m_axi_arprot, --: in std_logic_vector(2 downto 0);
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-- s00_axi_arvalid => mb_m_axi_arvalid, --: in std_logic;
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-- s00_axi_arready => mb_m_axi_arready, --: out std_logic;
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--
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-- s00_axi_rdata => mb_m_axi_rdata, --: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
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-- s00_axi_rresp => mb_m_axi_rresp, --: out std_logic_vector(1 downto 0);
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-- s00_axi_rvalid => mb_m_axi_rvalid, --: out std_logic;
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-- s00_axi_rready => mb_m_axi_rready -- : in std_logic
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-- );
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i_axi_lite_traffic_gen_mb : entity work.axi_lite_traffic_gen
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generic map (
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C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
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C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH
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)
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port map (
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m_axi_aclk => s_axi_aclk,
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m_axi_aresetn => s_axi_aresetn(0),
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-- Master Interface Write Address
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m_axi_awaddr => mb_m_axi_awaddr, -- : out
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m_axi_awprot => mb_m_axi_awprot, -- : out
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m_axi_awvalid => mb_m_axi_awvalid, -- : out
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m_axi_awready => mb_m_axi_awready, -- : in
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--
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-- master interface write data --
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m_axi_wdata => mb_m_axi_wdata, -- : out
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m_axi_wstrb => mb_m_axi_wstrb, -- : out
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m_axi_wvalid => mb_m_axi_wvalid, -- : out
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m_axi_wready => mb_m_axi_wready, -- : in
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--
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-- master interface write response --
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m_axi_bresp => mb_m_axi_bresp, -- : in
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m_axi_bvalid => mb_m_axi_bvalid, -- : in
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m_axi_bready => mb_m_axi_bready, -- : out
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--
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-- master interface read address --
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m_axi_araddr => mb_m_axi_araddr, -- : out
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m_axi_arprot => mb_m_axi_arprot, -- : out
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m_axi_arvalid => mb_m_axi_arvalid, -- : out
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m_axi_arready => mb_m_axi_arready, -- : in
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--
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-- master interface read data --
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m_axi_rdata => mb_m_axi_rdata, -- : in
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m_axi_rresp => mb_m_axi_rresp, -- : in
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m_axi_rvalid => mb_m_axi_rvalid, -- : in
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m_axi_rready => mb_m_axi_rready, -- : out
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num_burst_cnt_out => open,
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xfer_en_out => open,
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xfer_done_in => '0',
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dma_xfer_done_in => '0',
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buffer_rdy_intr_in => '0'
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);
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end;
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