-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:53:22 03/24/2017 -- Design Name: -- Module Name: -- Project Name: xem7350 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: dac_interface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; entity test_bench is end test_bench; architecture behavior of test_bench is constant C_M_AXI_DATA_WIDTH : integer := 32; constant C_M_AXI_ADDR_WIDTH : integer := 32; -- Clock period definitions constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz signal s_axi_aclk : std_logic := '0'; signal m_axi_aclk : std_logic := '0'; signal s_axi_aresetn : std_logic_vector(0 to 2) := (others => '0'); signal reset : std_logic_vector(0 to 2) := (others => '1'); signal cmd_idx : std_logic_vector( 2 downto 0) := (others => '0'); signal cmd_send : std_logic := '0'; signal mode : std_logic := '0'; signal scale : std_logic_vector(15 downto 0) := (others => '0'); signal dac_holdoff : std_logic := '0'; signal reserv1 : std_logic_vector(31 downto 0) := (others => '0'); signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0'); signal dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0'); signal idle_samples : std_logic_vector(31 downto 0) := (others => '0'); signal dds_samples : std_logic_vector(31 downto 0) := (others => '0'); signal phase_inc : std_logic_vector(31 downto 0) := (others => '0'); signal phase_off : std_logic_vector(31 downto 0) := (others => '0'); signal swap_sf : std_logic_vector(31 downto 0) := (others => '0'); signal mb_m_axi_awaddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0); signal mb_m_axi_awprot : std_logic_vector (2 downto 0); signal mb_m_axi_awvalid : std_logic; signal mb_m_axi_awready : std_logic; -- master interface write data signal mb_m_axi_wdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0); signal mb_m_axi_wstrb : std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0); signal mb_m_axi_wvalid : std_logic; signal mb_m_axi_wready : std_logic; -- master interface write response signal mb_m_axi_bresp : std_logic_vector (1 downto 0); signal mb_m_axi_bvalid : std_logic; signal mb_m_axi_bready : std_logic; -- master interface read address signal mb_m_axi_araddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0); signal mb_m_axi_arprot : std_logic_vector (2 downto 0); signal mb_m_axi_arvalid : std_logic; signal mb_m_axi_arready : std_logic; signal mb_m_axi_rdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0); signal mb_m_axi_rresp : std_logic_vector (1 downto 0); signal mb_m_axi_rvalid : std_logic; signal mb_m_axi_rready : std_logic; signal m_axis_tdata : std_logic_vector(127 downto 0); signal m_axis_tvalid : std_logic; signal m_axis_tready : std_logic; signal fifo_rd_valid : std_logic; signal fifo_rd_underflow : std_logic; signal fifo_rd_data_0 : std_logic_vector(15 downto 0); signal fifo_rd_data_1 : std_logic_vector(15 downto 0); signal fifo_rd_data_2 : std_logic_vector(15 downto 0); signal fifo_rd_data_3 : std_logic_vector(15 downto 0); signal fifo_rd_data_4 : std_logic_vector(15 downto 0); signal fifo_rd_data_5 : std_logic_vector(15 downto 0); signal fifo_rd_data_6 : std_logic_vector(15 downto 0); signal fifo_rd_data_7 : std_logic_vector(15 downto 0); signal fifo_rd_enable : std_logic := '0'; signal fifo_rd_r : std_logic := '0'; begin s_axi_aclk <= not s_axi_aclk after S_AXI_ACLK_PERIOD/2; m_axi_aclk <= not m_axi_aclk after M_AXI_ACLK_PERIOD/2; process(s_axi_aclk) begin if (rising_edge(s_axi_aclk)) then s_axi_aresetn <= s_axi_aresetn(1 to 2) & '1'; end if; end process; process(m_axi_aclk) begin if (rising_edge(m_axi_aclk)) then reset <= reset(1 to 2) & '0'; end if; end process; i_dds_pulse_wrapper : entity work.dds_pulse_wrapper generic map ( SIM_ENABLED => TRUE, FPGA_REVISION_DATE => x"0911_2023", MINOR_REV => x"01" ) port map ( s_axi_aclk_in => s_axi_aclk, s_axi_aresetn_in => s_axi_aresetn(0), cmd_idx_in => cmd_idx, cmd_send_in => cmd_send, mode_in => mode, scale_in => scale, dac_holdoff_in => dac_holdoff, reserv1_in => reserv1, dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time, dds_phase_inc_step_size_in => dds_phase_inc_step_size, idle_samples_in => idle_samples, dds_samples_in => dds_samples, phase_inc_in => phase_inc, phase_off_in => phase_off, swap_sf_in => swap_sf, m_axis_aclk_in => m_axi_aclk, m_axis_tdata_out => m_axis_tdata, m_axis_tvalid_out => m_axis_tvalid, m_axis_tready_in => m_axis_tready, cmd_send_cnt_out => open, pipe_in_ch1_fifo_rden_cnt_out => open, m_axis_tvalid_cnt_out => open, dds_pulse_data_cnt_out => open, reset_in => reset(0) ); i_util_upack2_0 : entity work.util_upack2_0 port map ( clk => m_axi_aclk, reset => reset(0), enable_0 => fifo_rd_enable, enable_1 => fifo_rd_enable, enable_2 => fifo_rd_enable, enable_3 => fifo_rd_enable, enable_4 => fifo_rd_enable, enable_5 => fifo_rd_enable, enable_6 => fifo_rd_enable, enable_7 => fifo_rd_enable, fifo_rd_en => fifo_rd_r, fifo_rd_valid => fifo_rd_valid, fifo_rd_underflow => fifo_rd_underflow, fifo_rd_data_0 => fifo_rd_data_0, fifo_rd_data_1 => fifo_rd_data_1, fifo_rd_data_2 => fifo_rd_data_2, fifo_rd_data_3 => fifo_rd_data_3, fifo_rd_data_4 => fifo_rd_data_4, fifo_rd_data_5 => fifo_rd_data_5, fifo_rd_data_6 => fifo_rd_data_6, fifo_rd_data_7 => fifo_rd_data_7, s_axis_data => m_axis_tdata, s_axis_valid => m_axis_tvalid, s_axis_ready => m_axis_tready ); process(m_axi_aclk) begin if (rising_edge(m_axi_aclk)) then if (fifo_rd_enable = '1') then fifo_rd_r <= not fifo_rd_r; end if; end if; end process; process begin wait for 1.5 us; fifo_rd_enable <= '1'; wait; end process; -- i_dds_pulse_intfc_v1_0 : entity work.dds_pulse_intfc_v1_0 -- generic map ( -- FPGA_REVISION_DATE => x"0911_2023", -- MINOR_REV => x"00", -- -- -- Parameters of Axi Slave Bus Interface S00_AXI -- C_S00_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- C_S00_AXI_ADDR_WIDTH => 6 -- ) -- port map ( -- -- Users to add ports here -- m_axis_aclk => m_axi_aclk, -- reset => reset(0), -- m_axis_tdata => open, -- m_axis_tvalid => open, -- m_axis_tready => '1', -- -- User ports ends -- -- Do not modify the ports beyond this line -- -- -- -- Ports of Axi Slave Bus Interface S00_AXI -- s00_axi_aclk => s_axi_aclk, -- s00_axi_aresetn => s_axi_aresetn(0), -- -- s00_axi_awaddr => mb_m_axi_awaddr(5 DOWNTO 0),-- : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); -- s00_axi_awprot => mb_m_axi_awprot, --: in std_logic_vector(2 downto 0); -- s00_axi_awvalid => mb_m_axi_awvalid, --: in std_logic; -- s00_axi_awready => mb_m_axi_awready, --: out std_logic; -- -- s00_axi_wdata => mb_m_axi_wdata, --: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); -- s00_axi_wstrb => mb_m_axi_wstrb, --: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); -- s00_axi_wvalid => mb_m_axi_wvalid, --: in std_logic; -- s00_axi_wready => mb_m_axi_wready, --: out std_logic; -- -- s00_axi_bresp => mb_m_axi_bresp, --: out std_logic_vector(1 downto 0); -- s00_axi_bvalid => mb_m_axi_bvalid, --: out std_logic; -- s00_axi_bready => mb_m_axi_bready, --: in std_logic; -- -- s00_axi_araddr => mb_m_axi_araddr(5 DOWNTO 0), --: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); -- s00_axi_arprot => mb_m_axi_arprot, --: in std_logic_vector(2 downto 0); -- s00_axi_arvalid => mb_m_axi_arvalid, --: in std_logic; -- s00_axi_arready => mb_m_axi_arready, --: out std_logic; -- -- s00_axi_rdata => mb_m_axi_rdata, --: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); -- s00_axi_rresp => mb_m_axi_rresp, --: out std_logic_vector(1 downto 0); -- s00_axi_rvalid => mb_m_axi_rvalid, --: out std_logic; -- s00_axi_rready => mb_m_axi_rready -- : in std_logic -- ); i_axi_lite_traffic_gen_mb : entity work.axi_lite_traffic_gen generic map ( C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH ) port map ( m_axi_aclk => s_axi_aclk, m_axi_aresetn => s_axi_aresetn(0), -- Master Interface Write Address m_axi_awaddr => mb_m_axi_awaddr, -- : out m_axi_awprot => mb_m_axi_awprot, -- : out m_axi_awvalid => mb_m_axi_awvalid, -- : out m_axi_awready => mb_m_axi_awready, -- : in -- -- master interface write data -- m_axi_wdata => mb_m_axi_wdata, -- : out m_axi_wstrb => mb_m_axi_wstrb, -- : out m_axi_wvalid => mb_m_axi_wvalid, -- : out m_axi_wready => mb_m_axi_wready, -- : in -- -- master interface write response -- m_axi_bresp => mb_m_axi_bresp, -- : in m_axi_bvalid => mb_m_axi_bvalid, -- : in m_axi_bready => mb_m_axi_bready, -- : out -- -- master interface read address -- m_axi_araddr => mb_m_axi_araddr, -- : out m_axi_arprot => mb_m_axi_arprot, -- : out m_axi_arvalid => mb_m_axi_arvalid, -- : out m_axi_arready => mb_m_axi_arready, -- : in -- -- master interface read data -- m_axi_rdata => mb_m_axi_rdata, -- : in m_axi_rresp => mb_m_axi_rresp, -- : in m_axi_rvalid => mb_m_axi_rvalid, -- : in m_axi_rready => mb_m_axi_rready, -- : out num_burst_cnt_out => open, xfer_en_out => open, xfer_done_in => '0', dma_xfer_done_in => '0', buffer_rdy_intr_in => '0' ); end;