121 lines
3.6 KiB
VHDL
121 lines
3.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity tick_gen is
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generic(
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CLOCK_SPEED_MHZ : integer := 100
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);
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port(
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clk_in : in std_logic;
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tick_1us_out : out std_logic;
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tick_1ms_out : out std_logic;
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tick_500ms_out : out std_logic;
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tick_750ms_out : out std_logic;
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tick_1s_out : out std_logic;
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prog_us_tick_rate_in : in std_logic_vector(15 downto 0);
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prog_us_tick_out : out std_logic;
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reset_in : in std_logic
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);
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end entity tick_gen;
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architecture imp of tick_gen is
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signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
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signal usec_cnt_r : integer range 0 to 999;
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signal msec_cnt_r : integer range 0 to 499;
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signal msec_cnt1_r : integer range 0 to 999;
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signal tick_1us_r : std_logic;
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signal tick_1ms_r : std_logic;
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signal tick_500ms_r : std_logic;
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signal tick_750ms_r : std_logic;
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signal tick_1s_r : std_logic;
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signal prog_usec_cnt_r : std_logic_vector(15 downto 0);
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signal prog_us_tick_r : std_logic;
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begin
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tick_1us_out <= tick_1us_r;
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tick_1ms_out <= tick_1ms_r;
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tick_500ms_out <= tick_500ms_r;
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tick_750ms_out <= tick_750ms_r;
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tick_1s_out <= tick_1s_r;
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prog_us_tick_out <= prog_us_tick_r;
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process(clk_in, reset_in)
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begin
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if(reset_in = '1') then
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sysclk_cnt_r <= 0;
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usec_cnt_r <= 0;
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msec_cnt_r <= 0;
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msec_cnt1_r <= 0;
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tick_1us_r <= '1';
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tick_1ms_r <= '0';
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tick_500ms_r <= '0';
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tick_750ms_r <= '0';
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tick_1s_r <= '0';
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prog_usec_cnt_r <= (others => '0');
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prog_us_tick_r <= '0';
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elsif rising_edge(clk_in) then
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tick_1ms_r <= '0';
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tick_500ms_r <= '0';
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tick_750ms_r <= '0';
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tick_1s_r <= '0';
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prog_us_tick_r <= '0';
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if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
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sysclk_cnt_r <= 0;
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tick_1us_r <= '1';
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else
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sysclk_cnt_r <= sysclk_cnt_r + 1;
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tick_1us_r <= '0';
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end if;
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if(tick_1us_r = '1') then
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if(usec_cnt_r = 999) then -- 1000us
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usec_cnt_r <= 0;
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tick_1ms_r <= '1';
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else
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usec_cnt_r <= usec_cnt_r + 1;
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end if;
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end if;
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if(tick_1ms_r = '1') then
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if(msec_cnt_r = 499) then -- 500ms
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msec_cnt_r <= 0;
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tick_500ms_r <= '1';
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else
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msec_cnt_r <= msec_cnt_r + 1;
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end if;
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end if;
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if(tick_1ms_r = '1') then
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if(msec_cnt1_r = 749) then -- 750ms
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tick_750ms_r <= '1';
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end if;
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if(msec_cnt1_r = 999) then -- 1s
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msec_cnt1_r <= 0;
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tick_1s_r <= '1';
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else
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msec_cnt1_r <= msec_cnt1_r + 1;
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end if;
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end if;
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if(tick_1us_r = '1') then
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if(prog_usec_cnt_r = prog_us_tick_rate_in) then
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prog_usec_cnt_r <= (others => '0');
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prog_us_tick_r <= '1';
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else
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prog_usec_cnt_r <= prog_usec_cnt_r + 1;
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end if;
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end if;
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end if;
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end process;
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end architecture imp; |