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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-05-29 13:36:02 -07:00
commit 55cdbdb59c
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dds_pulse_wrapper is
generic (
SIM_ENABLED : boolean := FALSE;
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0916_2023"
);
port(
clk_in : in std_logic;
m_axis_aclk_in : in std_logic;
m_axis_tdata_out : out std_logic_vector(127 downto 0);
m_axis_tvalid_out : out std_logic;
m_axis_tready_in : in std_logic;
rst_in : in std_logic
);
end entity dds_pulse_wrapper;
architecture imp of dds_pulse_wrapper is
constant ok_clk_in_period : time := 10 ns;
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal reset_n : std_logic;
signal s_axis_keep_r : std_logic_vector(3 downto 0) := "0001";
signal s_axis_tready : std_logic;
signal dds_pulse_data_r : std_logic_vector(127 downto 0) := (others => '0');
signal dds_pulse_dval_r : std_logic := '0';
signal dds_pulse_data_cnt_r : std_logic_vector(15 downto 0) := (others => '0');
signal dds_pulse_data_cnt_r1 : std_logic_vector(15 downto 0) := (others => '0');
signal cmd_idx : std_logic_vector( 2 downto 0) := "000";
signal cmd_send : std_logic := '0';
signal mode : std_logic := '0';
signal scale : std_logic_vector(15 downto 0) := x"0000";
signal dac_holdoff : std_logic := '1';
signal dds_pulse_dval : std_logic;
signal dds_pulse_data : std_logic_vector(31 downto 0);
signal pulse_i : std_logic_vector(15 downto 0);
signal pulse_q : std_logic_vector(15 downto 0);
signal pipe_in_ch1_fifo_rden : std_logic;
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rd_dval : std_logic;
signal pipe_in_ch1_fifo_empty : std_logic;
signal pipe_in_ch2_fifo_rden : std_logic;
signal m_axis_tdata : std_logic_vector(127 downto 0);
signal m_axis_tvalid : std_logic;
signal pulse_data_word : std_logic_vector(127 downto 0);
signal vio_reserv1 : std_logic_vector(31 downto 0) := (others => '0');
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
signal vio_idle_samples : std_logic_vector(31 downto 0) := (others => '0');
signal vio_dds_samples : std_logic_vector(31 downto 0) := (others => '0');
signal vio_phase_inc : std_logic_vector(31 downto 0) := (others => '0');
signal vio_phase_off : std_logic_vector(31 downto 0) := (others => '0');
signal vio_swap_sf : std_logic_vector(31 downto 0) := (others => '0');
begin
reset_n <= not rst_in;
-- process(clk_in)
-- begin
-- if (rising_edge(clk_in)) then
-- fpga_revision_date_r <= FPGA_REVISION_DATE;
-- end if;
-- end process;
sim_false : if (SIM_ENABLED = FALSE) generate
i_vio_0 : entity work.vio_0
port map (
clk => clk_in,
-- probe_in0 => fpga_revison_r, -- 32
probe_out0(0) => mode, -- 1
probe_out1 => scale, -- 16
probe_out2 => cmd_idx, -- 3
probe_out3(0) => cmd_send, -- 1
probe_out4(0) => dac_holdoff, -- 1
probe_out5 => vio_reserv1, -- 32
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
probe_out7 => vio_dds_phase_inc_step_size, -- 32
probe_out8 => vio_idle_samples, -- 32
probe_out9 => vio_dds_samples, -- 32
probe_out10 => vio_phase_inc, -- 32
probe_out11 => vio_phase_off, -- 32
probe_out12 => vio_swap_sf -- 32
);
end generate sim_false;
i_dds_cmd_gen : entity work.dds_cmd_gen
generic map (
SIM_ENABLED => SIM_ENABLED
)
port map (
clk_in => clk_in,
cmd_idx_in => cmd_idx,
cmd_send_in => cmd_send,
vio_reserv1_in => vio_reserv1,
vio_dds_phase_inc_dwell_time_in => vio_dds_phase_inc_dwell_time,
vio_dds_phase_inc_step_size_in => vio_dds_phase_inc_step_size,
vio_idle_samples_in => vio_idle_samples,
vio_dds_samples_in => vio_dds_samples,
vio_phase_inc_in => vio_phase_inc,
vio_phase_off_in => vio_phase_off,
vio_swap_sf_in => vio_swap_sf,
fifo_rd_clk_in => m_axis_aclk_in,
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
rst_in => rst_in
);
sim_false1 : if (SIM_ENABLED = FALSE) generate
i_ila_4 : entity work.ila_4
port map (
clk => m_axis_aclk_in,
probe0 => pipe_in_ch1_fifo_rd_data, --32
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
probe2(0) => pipe_in_ch1_fifo_rden, --1
probe3(0) => pipe_in_ch1_fifo_empty --1
);
end generate sim_false1;
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
port map(
clk_in => m_axis_aclk_in,
rst_in => rst_in,
mode_in => mode, -- 0=single, 1=dual
scale_in => scale,
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
fifo1_empty_in => pipe_in_ch1_fifo_empty,
fifo1_rden_out => pipe_in_ch1_fifo_rden,
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
fifo2_rden_out => pipe_in_ch2_fifo_rden,
holdoff_in => dac_holdoff,
overflow_out => open,
underflow_out => open,
i_max_abs_out => open,
q_max_abs_out => open,
data_out => dds_pulse_data,
dval_out => dds_pulse_dval
);
pulse_i <= dds_pulse_data(15 downto 0);
pulse_q <= dds_pulse_data(31 downto 16);
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
dds_pulse_dval_r <= dds_pulse_dval;
if (dds_pulse_dval_r = '1' and dds_pulse_dval = '0') then
dds_pulse_data_cnt_r <= (others => '0');
dds_pulse_data_cnt_r1 <= dds_pulse_data_cnt_r;
elsif (dds_pulse_dval = '1') then
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
end if;
-- if (dds_pulse_dval = '1') then
-- s_axis_keep_r <= s_axis_keep_r(2 downto 0) & s_axis_keep_r(3);
--
-- if (s_axis_keep_r = "0001") then
-- dds_pulse_data_r(31 downto 0) <= dds_pulse_data;
-- elsif (s_axis_keep_r = "0010") then
-- dds_pulse_data_r(63 downto 32) <= dds_pulse_data;
-- elsif (s_axis_keep_r = "0100") then
-- dds_pulse_data_r(95 downto 64) <= dds_pulse_data;
-- elsif (s_axis_keep_r = "1000") then
-- dds_pulse_data_r(127 downto 96) <= dds_pulse_data;
-- dds_pulse_dval_r <= '1';
-- end if;
-- end if;
end if;
end process;
pulse_data_word <= dds_pulse_data & dds_pulse_data & dds_pulse_data & dds_pulse_data;
sim_false2 : if (SIM_ENABLED = FALSE) generate
i_ila_3 : entity work.ila_3
port map (
clk => m_axis_aclk_in,
probe0 => dds_pulse_data(15 downto 0),
probe1 => dds_pulse_data(31 downto 16),
probe2(0) => dds_pulse_dval,
probe3(0) => s_axis_tready
);
end generate sim_false2;
i_fifo : entity work.axis_data_fifo_512x128
port map (
s_axis_aclk => m_axis_aclk_in,
s_axis_aresetn => reset_n,
s_axis_tdata => pulse_data_word,
s_axis_tvalid => dds_pulse_dval,
s_axis_tready => s_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready_in
);
m_axis_tdata_out <= m_axis_tdata;
m_axis_tvalid_out <= m_axis_tvalid;
sim_false3 : if (SIM_ENABLED = FALSE) generate
i_ila_2 : entity work.ila_0
port map (
clk => m_axis_aclk_in,
probe0 => m_axis_tdata(15 downto 0),
probe1 => m_axis_tdata(31 downto 16),
probe2 => m_axis_tdata(47 downto 32),
probe3 => m_axis_tdata(63 downto 48),
probe4 => m_axis_tdata(79 downto 64),
probe5 => m_axis_tdata(95 downto 80),
probe6 => m_axis_tdata(111 downto 96),
probe7 => m_axis_tdata(127 downto 112),
probe8(0) => m_axis_tvalid,
probe9(0) => m_axis_tready_in
);
end generate sim_false3;
sim_true : if (SIM_ENABLED = TRUE) generate
-- Stimulus process
stim_proc: process
begin
wait for 200 ns;
wait for 200 ns;
wait for 200 ns;
wait until rising_edge(clk_in);
wait for 1 ns;
mode <= '0';
scale <= x"8000";
wait for ok_clk_in_period*10;
wait until rising_edge(clk_in);
-- dac_holdoff <= '0';
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(clk_in);
cmd_idx <= "000";
cmd_send <= '1';
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
cmd_send <= '0';
wait for 100 ns;
-- WFM 1
-- FREQUENCY SWEEP (DOWN-SWEEP)
wait until rising_edge(clk_in);
cmd_idx <= "000";
cmd_send <= '1';
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
cmd_send <= '0';
wait for 100 ns;
-- WFM 2
-- CW TONE
wait until rising_edge(clk_in);
cmd_idx <= "000";
cmd_send <= '1';
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
wait until rising_edge(clk_in);
cmd_send <= '0';
wait for 100 ns;
-- -- WFM 3
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(clk_in);
-- cmd_idx <= "011";
-- cmd_send <= '1';
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
-- wait for 100 ns;
-- CW TONE
-- vio_reserv1 <= x"00000000"; --RESERVED1
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
-- vio_phase_off <= x"00000000"; --PHASE_OFF
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- cmd_idx <= "100";
-- cmd_send <= '1';
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- wait until rising_edge(clk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
wait for 5 us;
dac_holdoff <= '0';
wait;
end process;
end generate sim_true;
end architecture imp;