playback functions work now
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-62
@@ -3,7 +3,7 @@
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#
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# create_proj.tcl: Tcl script for re-creating project 'ad9082_fmca_ebz_alinx_z19'
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#
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# Generated by Vivado on Mon May 18 20:58:52 EDT 2026
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# Generated by Vivado on Tue Jun 16 00:27:30 EDT 2026
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -27,34 +27,36 @@
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#
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# 3. The following remote source files that were added to the original project:-
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||||
#
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_packer.vhd"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_unpacker.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_mux_256b/axis_mux_256b.xci"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/ad_3w_spi.v"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/ad_iobuf.v"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/raw_eth_wrapper_cmac_4.v"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/global_types.vhd"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/i2c.vhd"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/i2c_st.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/tick_gen.vhd"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/Si5332/src/si5332_wrapper.vhd"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/system_raw_eth_top.v"
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||||
# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/ila_5/ila_5.xci"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/constraints/system_constr.xdc"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/constraints/qsfp_constr.xdc"
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# "/home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/constraints/timing_constr.xdc"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_mux_256b/axis_mux_256b.xci"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/ila_5/ila_5.xci"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/ad_3w_spi.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/ad_iobuf.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/raw_eth_wrapper_cmac_4.v"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/axis_mux_chan_sel.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/global_types.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/i2c.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/i2c_st.vhd"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/tick_gen.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5332_wrapper.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/system_raw_eth_top.v"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/system_constr.xdc"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/qsfp_constr.xdc"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/timing_constr.xdc"
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||||
# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/sim/test_bench.vhd"
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#
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||||
#*****************************************************************************************
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||||
@@ -68,11 +70,13 @@ proc checkRequiredFiles { origin_dir} {
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"[file normalize "$origin_dir/source/eth_frame_unpacker.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"]"\
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||||
"[file normalize "$origin_dir/ip_repo/axis_mux_256b/axis_mux_256b.xci"]"\
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||||
"[file normalize "$origin_dir/ip_repo/ila_5/ila_5.xci"]"\
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"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\
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||||
"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\
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||||
"[file normalize "$origin_dir/source/ad_3w_spi.v"]"\
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"[file normalize "$origin_dir/source/ad_iobuf.v"]"\
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||||
"[file normalize "$origin_dir/source/raw_eth_wrapper_cmac_4.v"]"\
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||||
"[file normalize "$origin_dir/source/axis_mux_chan_sel.vhd"]"\
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||||
"[file normalize "$origin_dir/ip_repo/Si5332/src/global_types.vhd"]"\
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||||
"[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"]"\
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||||
"[file normalize "$origin_dir/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"]"\
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||||
@@ -85,11 +89,11 @@ proc checkRequiredFiles { origin_dir} {
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"[file normalize "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"]"\
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||||
"[file normalize "$origin_dir/source/system_raw_eth_top.v"]"\
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||||
"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"]"\
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||||
"[file normalize "$origin_dir/ip_repo/ila_5/ila_5.xci"]"\
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||||
"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"]"\
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||||
"[file normalize "$origin_dir/constraints/system_constr.xdc"]"\
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||||
"[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"\
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"[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\
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||||
"[file normalize "$origin_dir/sim/test_bench.vhd"]"\
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||||
]
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||||
foreach ifile $files {
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if { ![file isfile $ifile] } {
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@@ -176,7 +180,7 @@ if { $::argc > 0 } {
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||||
}
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||||
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||||
# Set the directory path for the original project from where this script was exported
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||||
set orig_proj_dir "[file normalize "$origin_dir/ad9082_z19_TEST"]"
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set orig_proj_dir "[file normalize "$origin_dir/ad9082_fmca_ebz_alinx_z19"]"
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||||
# Check for paths and files needed for project creation
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||||
set validate_required 0
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||||
@@ -203,8 +207,6 @@ set_msg_config -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}} -new_severity {WAR
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set_msg_config -id {BD 41-1343} -new_severity {WARNING} -ruleid {2} -source 2
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set_msg_config -id {BD 41-1306} -new_severity {WARNING} -ruleid {3} -source 2
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set_msg_config -id {BD 41-1276} -severity {CRITICAL WARNING} -new_severity {ERROR} -ruleid {4} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2
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set_msg_config -id {IP_Flow 19-3656} -new_severity {INFO} -ruleid {5} -source 2
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||||
set_msg_config -id {IP_Flow 19-4623} -new_severity {INFO} -ruleid {6} -source 2
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||||
set_msg_config -id {IP_Flow 19-459} -new_severity {INFO} -ruleid {7} -source 2
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||||
@@ -227,12 +229,14 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
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set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
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set_property -name "simulator_language" -value "Mixed" -objects $obj
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set_property -name "sim_compile_state" -value "1" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "50" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "50" -objects $obj
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set_property -name "webtalk.questa_export_sim" -value "50" -objects $obj
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||||
set_property -name "webtalk.riviera_export_sim" -value "50" -objects $obj
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set_property -name "webtalk.vcs_export_sim" -value "50" -objects $obj
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set_property -name "webtalk.xsim_export_sim" -value "50" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "51" -objects $obj
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||||
set_property -name "webtalk.questa_export_sim" -value "51" -objects $obj
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||||
set_property -name "webtalk.riviera_export_sim" -value "51" -objects $obj
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||||
set_property -name "webtalk.vcs_export_sim" -value "51" -objects $obj
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||||
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
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||||
set_property -name "webtalk.xsim_export_sim" -value "51" -objects $obj
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||||
set_property -name "webtalk.xsim_launch_sim" -value "4" -objects $obj
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set_property -name "xpm_libraries" -value "XPM_CDC XPM_COMP_DECL XPM_FIFO XPM_MEMORY" -objects $obj
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||||
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||||
# Create 'sources_1' fileset (if not found)
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||||
@@ -258,11 +262,13 @@ set files [list \
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||||
[file normalize "${origin_dir}/source/eth_frame_unpacker.vhd"] \
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||||
[file normalize "${origin_dir}/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"] \
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||||
[file normalize "${origin_dir}/ip_repo/axis_mux_256b/axis_mux_256b.xci"] \
|
||||
[file normalize "${origin_dir}/ip_repo/ila_5/ila_5.xci"] \
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||||
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \
|
||||
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \
|
||||
[file normalize "${origin_dir}/source/ad_3w_spi.v"] \
|
||||
[file normalize "${origin_dir}/source/ad_iobuf.v"] \
|
||||
[file normalize "${origin_dir}/source/raw_eth_wrapper_cmac_4.v"] \
|
||||
[file normalize "${origin_dir}/source/axis_mux_chan_sel.vhd"] \
|
||||
[file normalize "${origin_dir}/ip_repo/Si5332/src/global_types.vhd"] \
|
||||
[file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_gen_cfg.vhd"] \
|
||||
[file normalize "${origin_dir}/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"] \
|
||||
@@ -275,7 +281,6 @@ set files [list \
|
||||
[file normalize "${origin_dir}/ip_repo/Si5332/src/si5332_wrapper.vhd"] \
|
||||
[file normalize "${origin_dir}/source/system_raw_eth_top.v"] \
|
||||
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"] \
|
||||
[file normalize "${origin_dir}/ip_repo/ila_5/ila_5.xci"] \
|
||||
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"] \
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
@@ -319,6 +324,15 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/ip_repo/ila_5/ila_5.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
@@ -337,6 +351,11 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/source/axis_mux_chan_sel.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/ip_repo/Si5332/src/global_types.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
@@ -396,15 +415,6 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/ip_repo/ila_5/ila_5.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
@@ -469,12 +479,26 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
|
||||
|
||||
# Set 'sim_1' fileset object
|
||||
set obj [get_filesets sim_1]
|
||||
# Empty (no sources present)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/sim/test_bench.vhd"] \
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
# Set 'sim_1' fileset file properties for remote files
|
||||
set file "$origin_dir/sim/test_bench.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sim_1' fileset file properties for local files
|
||||
# None
|
||||
|
||||
# Set 'sim_1' fileset properties
|
||||
set obj [get_filesets sim_1]
|
||||
set_property -name "top" -value "system_raw_eth_top" -objects $obj
|
||||
set_property -name "top" -value "test_bench" -objects $obj
|
||||
set_property -name "top_auto_set" -value "0" -objects $obj
|
||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
||||
|
||||
# Set 'utils_1' fileset object
|
||||
set obj [get_filesets utils_1]
|
||||
@@ -486,16 +510,16 @@ set obj [get_filesets utils_1]
|
||||
|
||||
# Adding sources referenced in BDs, if not already added
|
||||
if { [get_files [list eth_flowctrl_rx.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
||||
}
|
||||
if { [get_files [list eth_frame_packer.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
||||
}
|
||||
if { [get_files [list eth_flowctrl_tx.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
||||
}
|
||||
if { [get_files [list eth_frame_unpacker.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
||||
}
|
||||
|
||||
|
||||
@@ -1196,7 +1220,7 @@ proc create_hier_cell_srl2 { parentCell nameHier } {
|
||||
# Create instance: cmac_rx_fifo_i, and set properties
|
||||
set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.FIFO_DEPTH {1024} \
|
||||
CONFIG.FIFO_DEPTH {8192} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
@@ -1503,6 +1527,147 @@ proc create_hier_cell_hier_0 { parentCell nameHier } {
|
||||
assign_bd_address -offset 0x82000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x82010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force
|
||||
|
||||
# Perform GUI Layout
|
||||
regenerate_bd_layout -layout_string {
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"2611,887",
|
||||
"ExpandedHierarchyInLayout":"/hier_0|/hier_0/srl2|/hier_0/srl2/Ethernet",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port cmac_gt_0 -pg 1 -lvl 2 -x 5180 -y 150 -defaultsOSRD
|
||||
preplace port m_axis -pg 1 -lvl 2 -x 5180 -y 170 -defaultsOSRD
|
||||
preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
||||
preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
|
||||
preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
||||
preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
|
||||
preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
|
||||
preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
|
||||
preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
|
||||
preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD
|
||||
preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
|
||||
preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
||||
preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
|
||||
preplace inst hier_0 -pg 1 -lvl 1 -x 360 -y 162 -defaultsOSRD
|
||||
preplace inst hier_0|srl2 -pg 1 -lvl 1 -x 600 -y 194 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|axis_reg_0_i -pg 1 -lvl 1 -x 670 -y 144 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|axis_ss_conv_0_i -pg 1 -lvl 2 -x 950 -y 164 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|cmac_rx_fifo_i -pg 1 -lvl 6 -x 4480 -y 564 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|axis_ss_conv_1_i -pg 1 -lvl 5 -x 4100 -y 544 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|axis_reg_1_i -pg 1 -lvl 7 -x 4780 -y 574 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|cmac_tx_fifo_i -pg 1 -lvl 3 -x 1250 -y 194 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet -pg 1 -lvl 4 -x 1740 -y 326 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|eth_flowctrl_rx_i -pg 1 -lvl 1 -x 1910 -y 1366 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|cmac_usplus_i -pg 1 -lvl 2 -x 2550 -y 1096 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|eth_frame_packer_i -pg 1 -lvl 1 -x 1910 -y 336 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|eth_flowctrl_tx_i -pg 1 -lvl 1 -x 1910 -y 606 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|eth_frame_unpacker_i -pg 1 -lvl 3 -x 3070 -y 1366 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|system_ila_i -pg 1 -lvl 4 -x 3550 -y 1186 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|ETH_regs -pg 1 -lvl 2 -x 2550 -y 656 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|rst_inv_i -pg 1 -lvl 1 -x 1910 -y 1056 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|counter_i -pg 1 -lvl 1 -x 1910 -y 1176 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|smartcon_i -pg 1 -lvl 1 -x 1910 -y 806 -defaultsOSRD
|
||||
preplace inst hier_0|srl2|Ethernet|proc_sys_reset_0 -pg 1 -lvl 3 -x 3070 -y 1166 -defaultsOSRD
|
||||
preplace netloc aresetn_0_1 1 0 1 20J 260n
|
||||
preplace netloc axil_clk_0_1 1 0 1 70J 160n
|
||||
preplace netloc axil_resetn_0_1 1 0 1 60J 180n
|
||||
preplace netloc axis_clk_0_1 1 0 1 90J 120n
|
||||
preplace netloc axis_resetn_0_1 1 0 1 80J 140n
|
||||
preplace netloc clk_100_0_1 1 0 1 50J 200n
|
||||
preplace netloc clk_100_reset_0_1 1 0 1 40J 220n
|
||||
preplace netloc m_axis_aclk_1 1 0 1 30J 240n
|
||||
preplace netloc cmac_refclk_0_1 1 0 1 100J 100n
|
||||
preplace netloc hier_0_cmac_gt_0 1 1 1 5150J 150n
|
||||
preplace netloc hier_0_m_axis_0 1 1 1 5160J 170n
|
||||
preplace netloc s_axil_0_1 1 0 1 120J 60n
|
||||
preplace netloc s_axis_0_1 1 0 1 110J 80n
|
||||
preplace netloc hier_0|aresetn_0_1 1 0 1 280 292n
|
||||
preplace netloc hier_0|axil_clk_1 1 0 1 330 192n
|
||||
preplace netloc hier_0|axil_resetn_1 1 0 1 320 212n
|
||||
preplace netloc hier_0|axis_clk_1 1 0 1 350 152n
|
||||
preplace netloc hier_0|axis_resetn_1 1 0 1 340 172n
|
||||
preplace netloc hier_0|clk_100_1 1 0 1 310 232n
|
||||
preplace netloc hier_0|clk_100_reset_1 1 0 1 300 252n
|
||||
preplace netloc hier_0|m_axis_aclk_1 1 0 1 290 272n
|
||||
preplace netloc hier_0|Conn1 1 1 1 5010 182n
|
||||
preplace netloc hier_0|Conn2 1 1 1 5020 202n
|
||||
preplace netloc hier_0|Conn3 1 0 1 380 92n
|
||||
preplace netloc hier_0|Conn4 1 0 1 370 112n
|
||||
preplace netloc hier_0|Conn5 1 0 1 360 132n
|
||||
preplace netloc hier_0|srl2|Ethernet_axis_aclk 1 2 4 1130 474 1370J 1598 3900 644 4310J
|
||||
preplace netloc hier_0|srl2|Ethernet_axis_aresetn 1 4 2 3890 634 4290J
|
||||
preplace netloc hier_0|srl2|Net 1 0 7 NJ 454 NJ 454 NJ 454 1400J 1578 3860J 454 4300 474 4660
|
||||
preplace netloc hier_0|srl2|aresetn_0_1 1 0 7 NJ 474 NJ 474 1110J 464 1380J 1588 3880J 464 NJ 464 4670
|
||||
preplace netloc hier_0|srl2|clk_100_1 1 0 4 NJ 404 NJ 404 NJ 404 1410
|
||||
preplace netloc hier_0|srl2|clk_100_reset_1 1 0 4 530J 484 NJ 484 NJ 484 1390
|
||||
preplace netloc hier_0|srl2|cmac_rx_fifo_i_axis_wr_data_count 1 3 4 1440 1778 3920J 654 NJ 654 4650
|
||||
preplace netloc hier_0|srl2|cmac_rx_overflow 1 3 3 1460 1748 3910J 624 4280
|
||||
preplace netloc hier_0|srl2|s_axi_sreset_1 1 0 4 NJ 384 NJ 384 NJ 384 1420
|
||||
preplace netloc hier_0|srl2|s_axilite_dsp_clk 1 0 4 NJ 364 NJ 364 NJ 364 1430
|
||||
preplace netloc hier_0|srl2|s_axis_dsp_clk 1 0 3 540 314 780 254 1120J
|
||||
preplace netloc hier_0|srl2|s_axis_dsp_resetn 1 0 3 560 324 790 244 1110J
|
||||
preplace netloc hier_0|srl2|Ethernet_M_AXIS 1 4 1 3870 524n
|
||||
preplace netloc hier_0|srl2|Ethernet_cmac_gt 1 4 4 3850 294 NJ 294 NJ 294 NJ
|
||||
preplace netloc hier_0|srl2|axis_data_fifo_0_M_AXIS 1 6 1 N 554
|
||||
preplace netloc hier_0|srl2|axis_reg_1_i_M_AXIS 1 7 1 N 574
|
||||
preplace netloc hier_0|srl2|axis_register_slice_1_M_AXIS 1 1 1 N 144
|
||||
preplace netloc hier_0|srl2|axis_ss_conv_0_i_M_AXIS 1 2 1 N 164
|
||||
preplace netloc hier_0|srl2|axis_subset_converter_0_M_AXIS1 1 5 1 N 534
|
||||
preplace netloc hier_0|srl2|cmac_refclk_1 1 0 4 NJ 304 NJ 304 NJ 304 1450
|
||||
preplace netloc hier_0|srl2|cmac_tx_fifo_i_M_AXIS 1 3 1 1460 194n
|
||||
preplace netloc hier_0|srl2|s_axil_1 1 0 4 550J 284 NJ 284 NJ 284 1440
|
||||
preplace netloc hier_0|srl2|s_axis_1 1 0 1 530 124n
|
||||
preplace netloc hier_0|srl2|Ethernet|ETH_regs_prog_full_off 1 0 4 1710 716 2290J 806 2850 986 3350J
|
||||
preplace netloc hier_0|srl2|Ethernet|ETH_regs_prog_full_on 1 0 4 1700 486 NJ 486 2870 996 3340J
|
||||
preplace netloc hier_0|srl2|Ethernet|axil_clk 1 0 2 1640 896 2310
|
||||
preplace netloc hier_0|srl2|Ethernet|axil_resetn 1 0 2 1660 996 2160
|
||||
preplace netloc hier_0|srl2|Ethernet|clk_100 1 0 2 NJ 986 2170
|
||||
preplace netloc hier_0|srl2|Ethernet|clk_100_reset 1 0 2 NJ 966 2220
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_reset 1 2 1 2820 1146n
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_resetn 1 0 5 1670 1276 2120J 1396 2890 1526 3280 1516 NJ
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_rx_fifo_i_axis_wr_data_count 1 0 4 1630 1476 NJ 1476 NJ 1476 3360
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_gt_powergoodout 1 2 2 2800 1016 3280J
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_gt_txusrclk2 1 0 5 1680 906 2270 1436 2830 1026 3400 856 3690J
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx_pause 1 0 4 1710 1456 2120J 1406 2770 1536 3400J
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx_pause_quanta8 1 0 4 1700 1466 2130J 1416 2780 1516 3270J
|
||||
preplace netloc hier_0|srl2|Ethernet|counter_i_Q 1 1 1 2230 756n
|
||||
preplace netloc hier_0|srl2|Ethernet|ctl_tx_pause_req 1 1 3 2180 1446 NJ 1446 3330J
|
||||
preplace netloc hier_0|srl2|Ethernet|ctl_tx_resend_pause 1 1 3 2190 1456 NJ 1456 3260J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_rx_0_pause 1 1 3 2110 1506 NJ 1506 3390J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_rx_0_rx_pause_cnt 1 1 3 2250 1486 NJ 1486 3380J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_tx_i_tx_pause_cnt 1 1 3 2140 1546 NJ 1546 3410J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_frame_packer_i_tx_cnt 1 1 3 2210 1466 NJ 1466 3370J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_frame_unpacker_i_rx_frame_cnt 1 1 3 2320 1496 NJ 1496 3250
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_regs_EtherType 1 0 4 1690 476 NJ 476 2880 1006 3390J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_regs_dest_addr 1 0 4 1710 456 NJ 456 2890 1036 3380J
|
||||
preplace netloc hier_0|srl2|Ethernet|eth_regs_source_addr 1 0 4 1700 466 NJ 466 2860 1056 3250J
|
||||
preplace netloc hier_0|srl2|Ethernet|packer_underrun_cnt 1 1 3 2260 1366 2810J 1046 3360J
|
||||
preplace netloc hier_0|srl2|Ethernet|probe2_1 1 0 4 1620 1266 2130J 1386 2870J 1276 3300
|
||||
preplace netloc hier_0|srl2|Ethernet|proc_sys_reset_0_peripheral_reset 1 0 4 1710 1256 2150J 1376 2850J 1266 3250
|
||||
preplace netloc hier_0|srl2|Ethernet|prog_full_manual 1 0 4 1710 496 NJ 496 2840 1066 3310J
|
||||
preplace netloc hier_0|srl2|Ethernet|rst_inv_i_Res 1 1 1 2200 1056n
|
||||
preplace netloc hier_0|srl2|Ethernet|unpacker_rx_frame_err_cnt 1 1 3 2330 1426 2880J 1286 3320
|
||||
preplace netloc hier_0|srl2|Ethernet|Conn1 1 0 1 N 786
|
||||
preplace netloc hier_0|srl2|Ethernet|S_AXI_1 1 1 1 2150 556n
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_axis_rx 1 2 2 2790 956 3380
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_refclk 1 0 2 NJ 726 2280
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_tx_fifo_M_AXIS 1 0 4 1650 886 2220J 816 NJ 816 3410
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_0_gt_serial_port 1 2 3 2800 826 NJ 826 NJ
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx 1 2 2 2770J 976 N
|
||||
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_tx 1 2 2 NJ 966 3390
|
||||
preplace netloc hier_0|srl2|Ethernet|packer_m_axis 1 1 3 2300 826 2790J 836 3380
|
||||
preplace netloc hier_0|srl2|Ethernet|smartcon_i_M00_AXI 1 1 1 2240 796n
|
||||
preplace netloc hier_0|srl2|Ethernet|unpacker_m_axis 1 3 2 3290 846 NJ
|
||||
levelinfo -pg 1 0 360 5180
|
||||
levelinfo -hier hier_0 * 600 *
|
||||
levelinfo -hier hier_0|srl2 * 670 950 1250 1740 4100 4480 4780 *
|
||||
levelinfo -hier hier_0|srl2|Ethernet * 1910 2550 3070 3550 *
|
||||
pagesize -pg 1 -db -bbox -sgen -170 0 5310 1850
|
||||
pagesize -hier hier_0 -db -bbox -sgen 250 32 5050 1822
|
||||
pagesize -hier hier_0|srl2 -db -bbox -sgen 500 64 4920 1794
|
||||
pagesize -hier hier_0|srl2|Ethernet -db -bbox -sgen 1590 216 3720 1556
|
||||
"
|
||||
}
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
@@ -1518,16 +1683,16 @@ set_property REGISTERED_WITH_MANAGER "1" [get_files raw_eth_cmac_4.bd ]
|
||||
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files raw_eth_cmac_4.bd ]
|
||||
|
||||
if { [get_files [list eth_flowctrl_rx.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
||||
}
|
||||
if { [get_files [list eth_frame_packer.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
||||
}
|
||||
if { [get_files [list eth_flowctrl_tx.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
||||
}
|
||||
if { [get_files [list eth_frame_unpacker.vhd]] == "" } {
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_alinx_z19/ALINX_Z19/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
||||
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
||||
}
|
||||
|
||||
|
||||
@@ -2228,7 +2393,7 @@ proc create_hier_cell_srl2 { parentCell nameHier } {
|
||||
# Create instance: cmac_rx_fifo_i, and set properties
|
||||
set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.FIFO_DEPTH {1024} \
|
||||
CONFIG.FIFO_DEPTH {8192} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TSTRB {0} \
|
||||
@@ -2535,6 +2700,45 @@ proc create_hier_cell_hier_0 { parentCell nameHier } {
|
||||
assign_bd_address -offset 0x81000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x81010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force
|
||||
|
||||
# Perform GUI Layout
|
||||
regenerate_bd_layout -layout_string {
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"1175,1945",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port cmac_gt_0 -pg 1 -lvl 2 -x 520 -y 150 -defaultsOSRD
|
||||
preplace port m_axis -pg 1 -lvl 2 -x 520 -y 170 -defaultsOSRD
|
||||
preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
||||
preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
|
||||
preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
||||
preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
|
||||
preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
|
||||
preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
|
||||
preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
|
||||
preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD
|
||||
preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
|
||||
preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
||||
preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
|
||||
preplace inst hier_0 -pg 1 -lvl 1 -x 360 -y 160 -defaultsOSRD
|
||||
preplace netloc aresetn_0_1 1 0 1 NJ 260
|
||||
preplace netloc axil_clk_0_1 1 0 1 NJ 160
|
||||
preplace netloc axil_resetn_0_1 1 0 1 NJ 180
|
||||
preplace netloc axis_clk_0_1 1 0 1 NJ 120
|
||||
preplace netloc axis_resetn_0_1 1 0 1 NJ 140
|
||||
preplace netloc clk_100_0_1 1 0 1 NJ 200
|
||||
preplace netloc clk_100_reset_0_1 1 0 1 NJ 220
|
||||
preplace netloc m_axis_aclk_1 1 0 1 NJ 240
|
||||
preplace netloc cmac_refclk_0_1 1 0 1 NJ 100
|
||||
preplace netloc hier_0_cmac_gt_0 1 1 1 NJ 150
|
||||
preplace netloc hier_0_m_axis_0 1 1 1 NJ 170
|
||||
preplace netloc s_axil_0_1 1 0 1 NJ 60
|
||||
preplace netloc s_axis_0_1 1 0 1 NJ 80
|
||||
levelinfo -pg 1 0 360 520
|
||||
pagesize -pg 1 -db -bbox -sgen -170 0 6880 3140
|
||||
"
|
||||
}
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
@@ -5151,7 +5355,7 @@ set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ]
|
||||
|
||||
#call make_wrapper to create wrapper files
|
||||
if { [get_property IS_LOCKED [ get_files -norecurse [list raw_eth.bd]] ] == 1 } {
|
||||
import_files -fileset sources_1 [file normalize "${origin_dir}/ad9082_z19_TEST/ad9082_fmca_ebz_alinx_z19.gen/sources_1/bd/raw_eth/hdl/raw_eth_wrapper.v" ]
|
||||
import_files -fileset sources_1 [file normalize "${origin_dir}/ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/bd/raw_eth/hdl/raw_eth_wrapper.v" ]
|
||||
} else {
|
||||
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse [list raw_eth.bd]] -top]
|
||||
add_files -norecurse -fileset sources_1 $wrapper_path
|
||||
|
||||
@@ -0,0 +1,55 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_mux_chan_sel is
|
||||
port (
|
||||
aselect_in : in std_logic_vector( 1 downto 0);
|
||||
|
||||
cmac_0_tdata_in : in std_logic_vector(127 downto 0);
|
||||
cmac_0_tvalid_in : in std_logic;
|
||||
cmac_0_tready_out : out std_logic;
|
||||
|
||||
cmac_4_tdata_in : in std_logic_vector(127 downto 0);
|
||||
cmac_4_tvalid_in : in std_logic;
|
||||
cmac_4_tready_out : out std_logic;
|
||||
|
||||
m_axis_tdata_out : out std_logic_vector(255 downto 0);
|
||||
m_axis_tvalid_out : out std_logic;
|
||||
m_axis_tready_in : in std_logic
|
||||
);
|
||||
end entity axis_mux_chan_sel;
|
||||
|
||||
architecture imp of axis_mux_chan_sel is
|
||||
|
||||
begin
|
||||
|
||||
-- adc_chan1_s3 adc_chan0_s3 adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
|
||||
m_axis_tdata_out <= cmac_4_tdata_in(127 downto 96) & cmac_0_tdata_in(127 downto 96) & cmac_4_tdata_in(95 downto 64) & cmac_0_tdata_in(95 downto 64) & cmac_4_tdata_in(63 downto 32) & cmac_0_tdata_in(63 downto 32) & cmac_4_tdata_in(31 downto 0) & cmac_0_tdata_in(31 downto 0) when aselect_in = "00" else
|
||||
x"FFFF_0000" & cmac_0_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_0_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_0_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_0_tdata_in(31 downto 0) when aselect_in = "01" else
|
||||
cmac_4_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_4_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_4_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_4_tdata_in(31 downto 0) & x"FFFF_0000";
|
||||
|
||||
|
||||
m_axis_tvalid_out <= cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
|
||||
cmac_0_tvalid_in when aselect_in = "01" else
|
||||
cmac_4_tvalid_in when aselect_in = "10" else
|
||||
'0';
|
||||
|
||||
cmac_0_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
|
||||
m_axis_tready_in and cmac_0_tvalid_in when aselect_in = "01" else '0';
|
||||
|
||||
cmac_4_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
|
||||
m_axis_tready_in and cmac_4_tvalid_in when aselect_in = "10" else '0';
|
||||
|
||||
end imp;
|
||||
|
||||
+28
-12
@@ -36,8 +36,8 @@
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_raw_eth_top #(
|
||||
parameter FPGA_REVISION_DATE = 32'h05212026,
|
||||
parameter MINOR_REV = 8'h02,
|
||||
parameter FPGA_REVISION_DATE = 32'h06122026,
|
||||
parameter MINOR_REV = 8'h01,
|
||||
parameter TX_JESD_L = 8,
|
||||
parameter TX_NUM_LINKS = 1,
|
||||
parameter RX_JESD_L = 8,
|
||||
@@ -246,7 +246,8 @@ module system_raw_eth_top #(
|
||||
|
||||
wire [127:0] cmac_0_rx_tdata_128b;
|
||||
wire cmac_0_rx_tvalid_128b;
|
||||
|
||||
wire cmac_0_rx_tready_128b;
|
||||
|
||||
////
|
||||
wire [511:0] cmac_4_tx_tdata_512b;
|
||||
wire cmac_4_tx_tvalid_512b;
|
||||
@@ -264,12 +265,12 @@ module system_raw_eth_top #(
|
||||
|
||||
wire [127:0] cmac_4_rx_tdata_128b;
|
||||
wire cmac_4_rx_tvalid_128b;
|
||||
wire cmac_4_rx_tready_128b;
|
||||
|
||||
////
|
||||
wire [255:0] cmac_rx_tdata_256b;
|
||||
wire cmac_rx_tvalid_256b;
|
||||
wire cmac_rx_tready_256b;
|
||||
wire cmac_rx_tready_256b_i;
|
||||
reg [31:0] cmac_rx_tvalid_256b_cnt_r = 32'h0;
|
||||
|
||||
////
|
||||
@@ -398,6 +399,7 @@ module system_raw_eth_top #(
|
||||
wire [127:0] adc_tdata_128b_chan0;
|
||||
wire [127:0] adc_tdata_128b_chan1;
|
||||
|
||||
wire [1:0] cmac_2_dac_chan_sel;
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
@@ -856,7 +858,8 @@ module system_raw_eth_top #(
|
||||
assign chan1to4_mode_sel = slv_reg10[12];
|
||||
//assign = slv_reg10[14:13];
|
||||
//assign = slv_reg10[15];
|
||||
//assign = slv_reg10[30:16];
|
||||
assign cmac_2_dac_chan_sel = slv_reg10[17:16];
|
||||
//assign = slv_reg10[30:18];
|
||||
assign playback_path_data_enable_n = slv_reg10[31];
|
||||
|
||||
//ila_5 i_ila_rx (
|
||||
@@ -878,7 +881,7 @@ module system_raw_eth_top #(
|
||||
// .probe14 (cmac_rx_tdata_256b[239:224]), // 16
|
||||
// .probe15 (cmac_rx_tdata_256b[255:240]), // 16
|
||||
// .probe16 (cmac_rx_tvalid_256b), // 1
|
||||
// .probe17 (cmac_rx_tready_256b_i) // 1
|
||||
// .probe17 (cmac_rx_tready_256b) // 1
|
||||
// );
|
||||
|
||||
///////////////////////////////////////////////////////////////
|
||||
@@ -987,7 +990,7 @@ module system_raw_eth_top #(
|
||||
|
||||
.m_axis_tdata (cmac_0_rx_tdata_128b), // out
|
||||
.m_axis_tvalid (cmac_0_rx_tvalid_128b), // out
|
||||
.m_axis_tready (cmac_rx_tready_256b_i) // in
|
||||
.m_axis_tready (cmac_0_rx_tready_128b) // in
|
||||
);
|
||||
|
||||
|
||||
@@ -1099,7 +1102,7 @@ module system_raw_eth_top #(
|
||||
|
||||
.m_axis_tdata (cmac_4_rx_tdata_128b), // out
|
||||
.m_axis_tvalid (cmac_4_rx_tvalid_128b), // out
|
||||
.m_axis_tready (cmac_rx_tready_256b_i) // in
|
||||
.m_axis_tready (cmac_4_rx_tready_128b) // in
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
@@ -1107,11 +1110,24 @@ module system_raw_eth_top #(
|
||||
|
||||
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b, cmac_0_rx_tdata_128b};
|
||||
// adc_chan1_s3 adc_chan0_s3 //adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
|
||||
assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b[127:96], cmac_0_rx_tdata_128b[127:96], cmac_4_rx_tdata_128b[95:64], cmac_0_rx_tdata_128b[95:64], cmac_4_rx_tdata_128b[63:32], cmac_0_rx_tdata_128b[63:32], cmac_4_rx_tdata_128b[31:0], cmac_0_rx_tdata_128b[31:0]};
|
||||
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b[127:96], cmac_0_rx_tdata_128b[127:96], cmac_4_rx_tdata_128b[95:64], cmac_0_rx_tdata_128b[95:64], cmac_4_rx_tdata_128b[63:32], cmac_0_rx_tdata_128b[63:32], cmac_4_rx_tdata_128b[31:0], cmac_0_rx_tdata_128b[31:0]};
|
||||
|
||||
assign cmac_rx_tvalid_256b = cmac_4_rx_tvalid_128b & cmac_0_rx_tvalid_128b;
|
||||
assign cmac_rx_tready_256b_i = cmac_rx_tvalid_256b & cmac_rx_tready_256b;
|
||||
axis_mux_chan_sel i_axis_mux_chan_sel (
|
||||
.aselect_in (cmac_2_dac_chan_sel),
|
||||
|
||||
.cmac_0_tdata_in (cmac_0_rx_tdata_128b), // in
|
||||
.cmac_0_tvalid_in (cmac_0_rx_tvalid_128b), // in
|
||||
.cmac_0_tready_out (cmac_0_rx_tready_128b), // out
|
||||
|
||||
.cmac_4_tdata_in (cmac_4_rx_tdata_128b), // in
|
||||
.cmac_4_tvalid_in (cmac_4_rx_tvalid_128b), // in
|
||||
.cmac_4_tready_out (cmac_4_rx_tready_128b), // out
|
||||
|
||||
.m_axis_tdata_out (cmac_rx_tdata_256b), // out
|
||||
.m_axis_tvalid_out (cmac_rx_tvalid_256b), // out
|
||||
.m_axis_tready_in (cmac_rx_tready_256b) // in
|
||||
);
|
||||
|
||||
ila_5 i_ila_rx (
|
||||
.clk (tx_device_clk_1),
|
||||
.probe0 (cmac_rx_tdata_256b[15:0]), // 16
|
||||
@@ -1186,7 +1202,7 @@ module system_raw_eth_top #(
|
||||
begin
|
||||
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
|
||||
cmac_rx_tvalid_256b_cnt_r <= 32'h0;
|
||||
else if (cmac_rx_tvalid_256b == 1'b1 && cmac_rx_tready_256b_i == 1'b1)
|
||||
else if (cmac_rx_tvalid_256b == 1'b1 && (cmac_0_rx_tready_128b || cmac_4_rx_tready_128b) == 1'b1)
|
||||
cmac_rx_tvalid_256b_cnt_r <= cmac_rx_tvalid_256b_cnt_r + 1;
|
||||
end
|
||||
|
||||
|
||||
Reference in New Issue
Block a user