31266 lines
2.1 MiB
Plaintext
31266 lines
2.1 MiB
Plaintext
{
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"ltx_root": {
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"version": 4,
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"minor": 0,
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"ltx_data": [
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{
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"name": "EDA_PROBESET",
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"active": true,
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"debug_cores": [
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "322265766"
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},
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{
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"type": "ILA_V3",
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"name": "i_ila_rx",
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"spec": "labtools_ila_v6",
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"ipName": "ila",
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"core_location": {
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"user_chain": 1,
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"slave_index": 0,
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"bscan_switch_index": 0
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},
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"uuid": "2E0826F7203854339CADCFF49DE2EF06",
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"pins": [
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{
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"name": "probe0",
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"id": 0,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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"nets": [
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{
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"name": "cmac_rx_tdata_256b_1",
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"isBus": true,
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"subnets": [
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{
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"name": "cmac_rx_tdata_256b_1[15]"
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{
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"name": "cmac_rx_tdata_256b_1[14]"
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{
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"name": "cmac_rx_tdata_256b_1[13]"
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{
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"name": "cmac_rx_tdata_256b_1[12]"
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{
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"name": "cmac_rx_tdata_256b_1[11]"
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{
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"name": "cmac_rx_tdata_256b_1[10]"
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{
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"name": "cmac_rx_tdata_256b_1[9]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[8]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[7]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[6]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[5]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[4]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[3]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[2]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[1]"
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},
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{
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"name": "cmac_rx_tdata_256b_1[0]"
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}
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]
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}
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]
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},
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{
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"name": "probe1",
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"id": 1,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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"leftIndex": 0,
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"portIndex": 1,
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"nets": [
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{
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"name": "cmac_rx_tdata_256b_2",
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"isBus": true,
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"subnets": [
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{
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"name": "cmac_rx_tdata_256b_2[31]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[30]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[29]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[28]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[27]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[26]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[25]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[24]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[23]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[22]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[21]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[20]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[19]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[18]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[17]"
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},
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{
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"name": "cmac_rx_tdata_256b_2[16]"
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}
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]
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}
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]
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},
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{
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"name": "probe2",
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"id": 2,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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"leftIndex": 0,
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"portIndex": 2,
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"nets": [
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{
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"name": "cmac_rx_tdata_256b_3",
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"isBus": true,
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"subnets": [
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{
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"name": "cmac_rx_tdata_256b_3[47]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[46]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[45]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[44]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[43]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[42]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[41]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[40]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[39]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[38]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[37]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[36]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[35]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[34]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[33]"
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},
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{
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"name": "cmac_rx_tdata_256b_3[32]"
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}
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]
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}
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]
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},
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{
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"name": "probe3",
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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"nets": [
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{
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"name": "cmac_rx_tdata_256b_4",
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"isBus": true,
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{
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"name": "cmac_rx_tdata_256b_4[63]"
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{
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"name": "cmac_rx_tdata_256b_4[62]"
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{
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"name": "cmac_rx_tdata_256b_4[61]"
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{
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"name": "cmac_rx_tdata_256b_4[60]"
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{
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"name": "cmac_rx_tdata_256b_4[59]"
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{
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"name": "cmac_rx_tdata_256b_4[58]"
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{
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"name": "cmac_rx_tdata_256b_4[57]"
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},
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{
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"name": "cmac_rx_tdata_256b_4[56]"
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},
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{
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"name": "cmac_rx_tdata_256b_4[55]"
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{
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"name": "cmac_rx_tdata_256b_4[54]"
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},
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{
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"name": "cmac_rx_tdata_256b_4[53]"
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{
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"name": "cmac_rx_tdata_256b_4[52]"
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{
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"name": "cmac_rx_tdata_256b_4[51]"
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{
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"name": "cmac_rx_tdata_256b_4[50]"
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},
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{
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"name": "cmac_rx_tdata_256b_4[49]"
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},
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{
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"name": "cmac_rx_tdata_256b_4[48]"
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}
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]
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}
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]
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},
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{
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"name": "probe4",
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"id": 4,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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{
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"name": "cmac_rx_tdata_256b_5",
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"isBus": true,
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{
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"name": "cmac_rx_tdata_256b_5[79]"
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},
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{
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"name": "cmac_rx_tdata_256b_5[78]"
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{
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"name": "cmac_rx_tdata_256b_5[77]"
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{
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"name": "cmac_rx_tdata_256b_5[76]"
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{
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"name": "cmac_rx_tdata_256b_5[75]"
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{
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"name": "cmac_rx_tdata_256b_5[74]"
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{
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"name": "cmac_rx_tdata_256b_5[73]"
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{
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"name": "cmac_rx_tdata_256b_5[72]"
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{
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"name": "cmac_rx_tdata_256b_5[71]"
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{
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"name": "cmac_rx_tdata_256b_5[70]"
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{
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"name": "cmac_rx_tdata_256b_5[69]"
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{
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"name": "cmac_rx_tdata_256b_5[68]"
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{
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"name": "cmac_rx_tdata_256b_5[67]"
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{
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"name": "cmac_rx_tdata_256b_5[66]"
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{
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"name": "cmac_rx_tdata_256b_5[65]"
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{
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"name": "cmac_rx_tdata_256b_5[64]"
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}
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]
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{
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"direction": "IN",
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{
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"isBus": true,
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{
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"name": "cmac_rx_tdata_256b_6[95]"
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{
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"name": "cmac_rx_tdata_256b_6[94]"
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{
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"name": "cmac_rx_tdata_256b_6[93]"
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{
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"name": "cmac_rx_tdata_256b_6[92]"
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{
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"name": "cmac_rx_tdata_256b_6[91]"
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{
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"name": "cmac_rx_tdata_256b_6[90]"
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{
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"name": "cmac_rx_tdata_256b_6[89]"
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{
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"name": "cmac_rx_tdata_256b_6[88]"
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{
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"name": "cmac_rx_tdata_256b_6[87]"
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{
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"name": "cmac_rx_tdata_256b_6[86]"
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{
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"name": "cmac_rx_tdata_256b_6[85]"
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{
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"name": "cmac_rx_tdata_256b_6[84]"
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{
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"name": "cmac_rx_tdata_256b_6[83]"
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{
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"name": "cmac_rx_tdata_256b_6[82]"
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{
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"name": "cmac_rx_tdata_256b_6[81]"
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{
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"name": "cmac_rx_tdata_256b_6[80]"
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}
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]
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}
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]
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},
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{
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"name": "probe6",
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"id": 6,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": true,
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{
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"name": "cmac_rx_tdata_256b_7",
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"isBus": true,
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{
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"name": "cmac_rx_tdata_256b_7[111]"
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},
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{
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"name": "cmac_rx_tdata_256b_7[110]"
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{
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"name": "cmac_rx_tdata_256b_7[109]"
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{
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"name": "cmac_rx_tdata_256b_7[108]"
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{
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|
"name": "cmac_rx_tdata_256b_7[107]"
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{
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"name": "cmac_rx_tdata_256b_7[106]"
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{
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"name": "cmac_rx_tdata_256b_7[105]"
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{
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|
"name": "cmac_rx_tdata_256b_7[104]"
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{
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|
"name": "cmac_rx_tdata_256b_7[103]"
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{
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|
"name": "cmac_rx_tdata_256b_7[102]"
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},
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{
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|
"name": "cmac_rx_tdata_256b_7[101]"
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{
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|
"name": "cmac_rx_tdata_256b_7[100]"
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},
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{
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|
"name": "cmac_rx_tdata_256b_7[99]"
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|
},
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{
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|
"name": "cmac_rx_tdata_256b_7[98]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_7[97]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_7[96]"
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|
}
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]
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|
}
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|
]
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|
},
|
|
{
|
|
"name": "probe7",
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|
"id": 7,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
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|
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|
"portIndex": 7,
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|
"nets": [
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{
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|
"name": "cmac_rx_tdata_256b_8",
|
|
"isBus": true,
|
|
"subnets": [
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|
{
|
|
"name": "cmac_rx_tdata_256b_8[127]"
|
|
},
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|
{
|
|
"name": "cmac_rx_tdata_256b_8[126]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[125]"
|
|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[124]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[123]"
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},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[122]"
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},
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{
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|
"name": "cmac_rx_tdata_256b_8[121]"
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},
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{
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|
"name": "cmac_rx_tdata_256b_8[120]"
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},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[119]"
|
|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[118]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[117]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_8[116]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_8[115]"
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|
},
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|
{
|
|
"name": "cmac_rx_tdata_256b_8[114]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[113]"
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|
},
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|
{
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|
"name": "cmac_rx_tdata_256b_8[112]"
|
|
}
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|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe8",
|
|
"id": 8,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
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|
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"rightIndex": 15,
|
|
"portIndex": 8,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[143]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[142]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[141]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[140]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[139]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[138]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[137]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[136]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[135]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[134]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[133]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[132]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[131]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[130]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[129]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_9[128]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe9",
|
|
"id": 9,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 9,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[159]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[158]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[157]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[156]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[155]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[154]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[153]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[152]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[151]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[150]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[149]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[148]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[147]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[146]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[145]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_10[144]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe10",
|
|
"id": 10,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 10,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[175]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[174]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[173]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[172]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[171]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[170]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[169]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[168]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[167]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[166]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[165]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[164]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[163]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[162]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[161]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_11[160]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe11",
|
|
"id": 11,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 11,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[191]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[190]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[189]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[188]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[187]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[186]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[185]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[184]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[183]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[182]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[181]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[180]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[179]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[178]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[177]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_12[176]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe12",
|
|
"id": 12,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 12,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[207]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[206]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[205]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[204]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[203]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[202]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[201]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[200]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[199]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[198]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[197]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[196]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[195]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[194]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[193]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_13[192]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe13",
|
|
"id": 13,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 13,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[223]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[222]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[221]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[220]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[219]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[218]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[217]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[216]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[215]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[214]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[213]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[212]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[211]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[210]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[209]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_14[208]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe14",
|
|
"id": 14,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 14,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[239]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[238]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[237]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[236]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[235]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[234]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[233]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[232]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[231]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[230]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[229]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[228]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[227]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[226]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[225]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b_15[224]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe15",
|
|
"id": 15,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 15,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "cmac_rx_tdata_256b[255]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[254]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[253]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[252]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[251]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[250]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[249]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[248]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[247]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[246]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[245]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[244]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[243]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[242]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[241]"
|
|
},
|
|
{
|
|
"name": "cmac_rx_tdata_256b[240]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe16",
|
|
"id": 16,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 16,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tvalid_256b",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe17",
|
|
"id": 17,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 17,
|
|
"nets": [
|
|
{
|
|
"name": "cmac_rx_tready_256b",
|
|
"isBus": false
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"type": "ILA_V3",
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/ila_lib",
|
|
"spec": "labtools_ila_v6",
|
|
"ipName": "ila",
|
|
"core_location": {
|
|
"user_chain": 1,
|
|
"slave_index": 1,
|
|
"bscan_switch_index": 0
|
|
},
|
|
"uuid": "E47C7E4DB3875B4897F135A60B03E947",
|
|
"pins": [
|
|
{
|
|
"name": "probe0",
|
|
"id": 18,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 3,
|
|
"portIndex": 0,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe1",
|
|
"id": 19,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 1,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe2",
|
|
"id": 20,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 2,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe2_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe3",
|
|
"id": 21,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 3,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe4",
|
|
"id": 22,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 47,
|
|
"portIndex": 4,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe5",
|
|
"id": 23,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 47,
|
|
"portIndex": 5,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe6",
|
|
"id": 24,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 6,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe7",
|
|
"id": 25,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 7,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe7_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe8",
|
|
"id": 26,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 8,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe8_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe9",
|
|
"id": 27,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 9,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe10",
|
|
"id": 28,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 10,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe11",
|
|
"id": 29,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 11,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe12",
|
|
"id": 30,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 12,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe13",
|
|
"id": 31,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 13,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe14",
|
|
"id": 32,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 14,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe15",
|
|
"id": 33,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 15,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe15_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe16",
|
|
"id": 34,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 16,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe16_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe17",
|
|
"id": 35,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 17,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe18",
|
|
"id": 36,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 18,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe19",
|
|
"id": 37,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 19,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe20",
|
|
"id": 38,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 20,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[491]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[490]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[489]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[487]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[486]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[485]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[484]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[483]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[482]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[481]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[480]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[479]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[478]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[477]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[476]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[475]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[474]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[473]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[472]"
|
|
},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[471]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[470]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[469]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[468]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[467]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[466]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[465]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[464]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[463]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[462]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[461]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[460]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[459]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[458]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[457]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[456]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[455]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[454]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[453]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[452]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[451]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[450]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[449]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[448]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[447]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[446]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[445]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[444]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[443]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[442]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[441]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[440]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[439]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[438]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[436]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[435]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[434]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[433]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[431]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[430]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[429]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[406]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[403]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[402]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[401]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[399]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[398]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[397]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[396]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[395]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[394]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[393]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[392]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[391]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[390]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[389]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[388]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[387]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[386]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[385]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[384]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[383]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[382]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[381]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[380]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[379]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[378]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[377]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[376]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[375]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[374]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[373]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[372]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[371]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[368]"
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{
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[273]"
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{
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[271]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[270]"
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{
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{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[67]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[66]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[65]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[64]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[63]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[62]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[61]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[60]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[59]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[58]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[57]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[56]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[55]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[54]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[53]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[52]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[51]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[50]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[49]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[48]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe21",
|
|
"id": 39,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 21,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe22",
|
|
"id": 40,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 22,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tready",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe23",
|
|
"id": 41,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 23,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe24",
|
|
"id": 42,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 24,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[491]"
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{
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[401]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[400]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[399]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[398]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[397]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[396]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[394]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[393]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[392]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[391]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[390]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[87]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[86]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[85]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[84]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[83]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[82]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[81]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[79]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[78]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[77]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[76]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[75]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[74]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[73]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[72]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[71]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[69]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[68]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[67]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[66]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[65]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[64]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[59]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[58]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[57]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[56]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[55]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[54]"
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{
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{
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{
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{
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{
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{
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{
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{
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|
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]
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|
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|
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{
|
|
"name": "probe25",
|
|
"id": 43,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
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"portIndex": 25,
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"isBus": true,
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{
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[56]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[55]"
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{
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|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[54]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[53]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[52]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[51]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[50]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[49]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[48]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe26",
|
|
"id": 44,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 26,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe27",
|
|
"id": 45,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 27,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe28",
|
|
"id": 46,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 28,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tready",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe29",
|
|
"id": 47,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 29,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe30",
|
|
"id": 48,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 30,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_bad_fcs_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe31",
|
|
"id": 49,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 31,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_broadcast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe32",
|
|
"id": 50,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 32,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_frame_error_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe33",
|
|
"id": 51,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 33,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe34",
|
|
"id": 52,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 34,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_multicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe35",
|
|
"id": 53,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 35,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_64_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe36",
|
|
"id": 54,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 36,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_65_127_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe37",
|
|
"id": 55,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 37,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_128_255_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe38",
|
|
"id": 56,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 38,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_256_511_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe39",
|
|
"id": 57,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 39,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_512_1023_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe40",
|
|
"id": 58,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 40,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1024_1518_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe41",
|
|
"id": 59,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 41,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1519_1522_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe42",
|
|
"id": 60,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 42,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1523_1548_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe43",
|
|
"id": 61,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 43,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1549_2047_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe44",
|
|
"id": 62,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 44,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_2048_4095_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe45",
|
|
"id": 63,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 45,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_4096_8191_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe46",
|
|
"id": 64,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 46,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_8192_9215_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe47",
|
|
"id": 65,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 47,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_large_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe48",
|
|
"id": 66,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 48,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_small_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe49",
|
|
"id": 67,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 49,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe50",
|
|
"id": 68,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 50,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe51",
|
|
"id": 69,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 5,
|
|
"portIndex": 51,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe52",
|
|
"id": 70,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 13,
|
|
"portIndex": 52,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe53",
|
|
"id": 71,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 53,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe54",
|
|
"id": 72,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 54,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe55",
|
|
"id": 73,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 55,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_unicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe56",
|
|
"id": 74,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 56,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_user_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe57",
|
|
"id": 75,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 57,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_vlan_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe58",
|
|
"id": 76,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 58,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_aligned_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe59",
|
|
"id": 77,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 59,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_aligned_err_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe60",
|
|
"id": 78,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 60,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe61",
|
|
"id": 79,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 61,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe62",
|
|
"id": 80,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 62,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_preamble_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe63",
|
|
"id": 81,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 63,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_sfd_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe64",
|
|
"id": 82,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 64,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_0_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe65",
|
|
"id": 83,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 65,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_1_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe66",
|
|
"id": 84,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 66,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_2_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe67",
|
|
"id": 85,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 67,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_3_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe68",
|
|
"id": 86,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 68,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_4_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe69",
|
|
"id": 87,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 69,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_5_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe70",
|
|
"id": 88,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 70,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_6_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe71",
|
|
"id": 89,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 71,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_7_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe72",
|
|
"id": 90,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 72,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_8_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe73",
|
|
"id": 91,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 73,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_9_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe74",
|
|
"id": 92,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 74,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_10_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe75",
|
|
"id": 93,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 75,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_11_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe76",
|
|
"id": 94,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 76,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_12_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe77",
|
|
"id": 95,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 77,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_13_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe78",
|
|
"id": 96,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 78,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_14_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe79",
|
|
"id": 97,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 79,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_15_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe80",
|
|
"id": 98,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 80,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_16_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe81",
|
|
"id": 99,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 81,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_17_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe82",
|
|
"id": 100,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 82,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_18_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe83",
|
|
"id": 101,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 83,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_19_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe84",
|
|
"id": 102,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 84,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe85",
|
|
"id": 103,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 85,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_broadcast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe86",
|
|
"id": 104,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 86,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe87",
|
|
"id": 105,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 87,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe88",
|
|
"id": 106,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 88,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe89",
|
|
"id": 107,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 89,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe90",
|
|
"id": 108,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 90,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe91",
|
|
"id": 109,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 91,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe92",
|
|
"id": 110,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 92,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe93",
|
|
"id": 111,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 93,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe94",
|
|
"id": 112,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 94,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe95",
|
|
"id": 113,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 95,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe96",
|
|
"id": 114,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 96,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe97",
|
|
"id": 115,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 97,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe98",
|
|
"id": 116,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 98,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe99",
|
|
"id": 117,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 99,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe100",
|
|
"id": 118,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 100,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe101",
|
|
"id": 119,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 101,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe102",
|
|
"id": 120,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 102,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe103",
|
|
"id": 121,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 103,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe104",
|
|
"id": 122,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 104,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe105",
|
|
"id": 123,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 105,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe106",
|
|
"id": 124,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 106,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe107",
|
|
"id": 125,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 107,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_0_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe108",
|
|
"id": 126,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 108,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_1_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe109",
|
|
"id": 127,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 109,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_2_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe110",
|
|
"id": 128,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 110,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_3_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe111",
|
|
"id": 129,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 111,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_4_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe112",
|
|
"id": 130,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 112,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_5_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe113",
|
|
"id": 131,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 113,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_6_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe114",
|
|
"id": 132,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 114,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_7_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe115",
|
|
"id": 133,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 115,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_8_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe116",
|
|
"id": 134,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 116,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_9_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe117",
|
|
"id": 135,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 117,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_10_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe118",
|
|
"id": 136,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 118,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_11_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe119",
|
|
"id": 137,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 119,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_12_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe120",
|
|
"id": 138,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 120,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_13_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe121",
|
|
"id": 139,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 121,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_14_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe122",
|
|
"id": 140,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 122,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_15_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe123",
|
|
"id": 141,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 123,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_16_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe124",
|
|
"id": 142,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 124,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_17_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe125",
|
|
"id": 143,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 125,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_18_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe126",
|
|
"id": 144,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 126,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_19_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe127",
|
|
"id": 145,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 127,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_got_signal_os_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe128",
|
|
"id": 146,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 128,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_hi_ber_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe129",
|
|
"id": 147,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 129,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_inrangeerr_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe130",
|
|
"id": 148,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 130,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_internal_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe131",
|
|
"id": 149,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 131,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_jabber_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe132",
|
|
"id": 150,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 132,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe133",
|
|
"id": 151,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 133,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe134",
|
|
"id": 152,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 134,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe135",
|
|
"id": 153,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 135,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe136",
|
|
"id": 154,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 136,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_misaligned_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe137",
|
|
"id": 155,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 137,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_multicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe138",
|
|
"id": 156,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 138,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_oversize_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe139",
|
|
"id": 157,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 139,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_64_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe140",
|
|
"id": 158,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 140,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_65_127_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe141",
|
|
"id": 159,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 141,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_128_255_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe142",
|
|
"id": 160,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 142,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_256_511_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe143",
|
|
"id": 161,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 143,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_512_1023_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe144",
|
|
"id": 162,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 144,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1024_1518_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe145",
|
|
"id": 163,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 145,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1519_1522_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe146",
|
|
"id": 164,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 146,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1523_1548_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe147",
|
|
"id": 165,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 147,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1549_2047_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe148",
|
|
"id": 166,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 148,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_2048_4095_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe149",
|
|
"id": 167,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 149,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_4096_8191_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe150",
|
|
"id": 168,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 150,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_8192_9215_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe151",
|
|
"id": 169,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 151,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_bad_fcs_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe152",
|
|
"id": 170,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 152,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_large_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe153",
|
|
"id": 171,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 153,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe154",
|
|
"id": 172,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 154,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe155",
|
|
"id": 173,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 155,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe156",
|
|
"id": 174,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 156,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe157",
|
|
"id": 175,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 157,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe158",
|
|
"id": 176,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 158,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe159",
|
|
"id": 177,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 159,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe160",
|
|
"id": 178,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 160,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe161",
|
|
"id": 179,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 161,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe162",
|
|
"id": 180,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 162,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe163",
|
|
"id": 181,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 163,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe164",
|
|
"id": 182,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 164,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe165",
|
|
"id": 183,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 165,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe166",
|
|
"id": 184,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 166,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe167",
|
|
"id": 185,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 167,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe168",
|
|
"id": 186,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 168,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe169",
|
|
"id": 187,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 169,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe170",
|
|
"id": 188,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 170,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe171",
|
|
"id": 189,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 171,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe172",
|
|
"id": 190,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 172,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe173",
|
|
"id": 191,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 173,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe174",
|
|
"id": 192,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 174,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe175",
|
|
"id": 193,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 175,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe176",
|
|
"id": 194,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 176,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe177",
|
|
"id": 195,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 177,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe178",
|
|
"id": 196,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 178,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe179",
|
|
"id": 197,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 179,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe180",
|
|
"id": 198,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 180,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe181",
|
|
"id": 199,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 181,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe182",
|
|
"id": 200,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 182,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe183",
|
|
"id": 201,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 183,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe184",
|
|
"id": 202,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 184,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe185",
|
|
"id": 203,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 185,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe186",
|
|
"id": 204,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 186,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe187",
|
|
"id": 205,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 187,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_received_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe188",
|
|
"id": 206,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 188,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_remote_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe189",
|
|
"id": 207,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 189,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_status_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe190",
|
|
"id": 208,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 190,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe191",
|
|
"id": 209,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 191,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe192",
|
|
"id": 210,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 192,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe193",
|
|
"id": 211,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 193,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe194",
|
|
"id": 212,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 194,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_toolong_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe195",
|
|
"id": 213,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 6,
|
|
"portIndex": 195,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe196",
|
|
"id": 214,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 13,
|
|
"portIndex": 196,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe197",
|
|
"id": 215,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 197,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe198",
|
|
"id": 216,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 198,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe199",
|
|
"id": 217,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 199,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_truncated_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe200",
|
|
"id": 218,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 200,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe201",
|
|
"id": 219,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 201,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_unicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe202",
|
|
"id": 220,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 202,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_user_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe203",
|
|
"id": 221,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 203,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_vlan_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe204",
|
|
"id": 222,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 204,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[491]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[490]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[489]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[487]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[486]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[485]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[484]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[483]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[482]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[481]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[480]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[479]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[478]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[477]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[476]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[475]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[474]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[473]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[472]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[471]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[470]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[469]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[468]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[467]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[466]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[465]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[464]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[463]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[462]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[461]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[460]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[459]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[458]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[457]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[456]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[455]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[454]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[453]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[452]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[451]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[450]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[449]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[448]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[447]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[446]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[445]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[355]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[351]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[350]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[349]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[348]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[347]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[246]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[44]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[43]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[42]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[41]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[40]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[39]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[38]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[37]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[36]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[35]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[34]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[33]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[32]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[31]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[30]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[29]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[28]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[27]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[26]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[25]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[24]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[23]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[22]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[21]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[20]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[19]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[18]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[17]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[16]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[15]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[14]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[13]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[12]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[11]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[10]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[9]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[8]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[7]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[6]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[5]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[4]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[3]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[2]"
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},
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{
|
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[1]"
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},
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{
|
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[0]"
|
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}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe205",
|
|
"id": 223,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
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|
"rightIndex": 63,
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"portIndex": 205,
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"nets": [
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep",
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"isBus": true,
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"subnets": [
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[63]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[62]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[61]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[60]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[59]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[58]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[57]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[56]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[55]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[54]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[53]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[52]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[51]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[50]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[49]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[48]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[47]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[46]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[45]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[44]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[43]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[42]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[41]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[40]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[39]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[38]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[37]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[36]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[35]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[34]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[33]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[32]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[31]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[30]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[29]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[28]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[27]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[26]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[25]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[24]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[23]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[22]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[21]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[20]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[19]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[18]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[17]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[16]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[15]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[14]"
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},
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[13]"
|
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},
|
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[12]"
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},
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{
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|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe206",
|
|
"id": 224,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 206,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe207",
|
|
"id": 225,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 207,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe208",
|
|
"id": 226,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 208,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe209",
|
|
"id": 227,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 209,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[491]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[490]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[489]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[487]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[486]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[485]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[484]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[483]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[482]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[481]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[480]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[479]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[478]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[477]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[476]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[475]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[474]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[473]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[472]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[471]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[470]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[469]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[468]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[467]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[466]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[465]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[464]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[463]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[462]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[461]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[460]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[459]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[458]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[457]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[456]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[455]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[454]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[453]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[452]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[451]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[450]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[449]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[448]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[447]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[446]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[445]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[444]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[443]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[442]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[441]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[440]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[439]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[438]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[437]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[436]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[435]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[434]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[433]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[432]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[431]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[430]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[429]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[428]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[427]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[426]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[425]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[424]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[421]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[419]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[418]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[417]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[416]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[414]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[413]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[412]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[411]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[406]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[366]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[365]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[364]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[361]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[357]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[356]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[355]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[354]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[353]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[351]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[350]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[349]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[346]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[342]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[341]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[339]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[338]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[337]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[336]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[335]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[334]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[254]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[237]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[236]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[235]"
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{
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[234]"
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"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[233]"
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|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe210",
|
|
"id": 228,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 210,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe211",
|
|
"id": 229,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 211,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe212",
|
|
"id": 230,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 212,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_0/raw_eth_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"bus_interfaces": [
|
|
{
|
|
"name": "SLOT_0_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "cmac_tx_fifo_M_AXIS",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 38,
|
|
"name": "probe20",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 41,
|
|
"name": "probe23",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TREADY",
|
|
"physical_pin": {
|
|
"id": 40,
|
|
"name": "probe22",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 39,
|
|
"name": "probe21",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_1_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "packer_m_axis",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 42,
|
|
"name": "probe24",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TKEEP",
|
|
"physical_pin": {
|
|
"id": 43,
|
|
"name": "probe25",
|
|
"leftBit": 0,
|
|
"width": 64
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 47,
|
|
"name": "probe29",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TREADY",
|
|
"physical_pin": {
|
|
"id": 46,
|
|
"name": "probe28",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 44,
|
|
"name": "probe26",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 45,
|
|
"name": "probe27",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_2_STATISTICS_PORTS",
|
|
"vlnv": "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0",
|
|
"connectedBus": "cmac_usplus_i_stat_tx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "stat_tx_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 48,
|
|
"name": "probe30",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_broadcast",
|
|
"physical_pin": {
|
|
"id": 49,
|
|
"name": "probe31",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_frame_error",
|
|
"physical_pin": {
|
|
"id": 50,
|
|
"name": "probe32",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_local_fault",
|
|
"physical_pin": {
|
|
"id": 51,
|
|
"name": "probe33",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_multicast",
|
|
"physical_pin": {
|
|
"id": 52,
|
|
"name": "probe34",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1024_1518_bytes",
|
|
"physical_pin": {
|
|
"id": 58,
|
|
"name": "probe40",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_128_255_bytes",
|
|
"physical_pin": {
|
|
"id": 55,
|
|
"name": "probe37",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1519_1522_bytes",
|
|
"physical_pin": {
|
|
"id": 59,
|
|
"name": "probe41",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1523_1548_bytes",
|
|
"physical_pin": {
|
|
"id": 60,
|
|
"name": "probe42",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1549_2047_bytes",
|
|
"physical_pin": {
|
|
"id": 61,
|
|
"name": "probe43",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_2048_4095_bytes",
|
|
"physical_pin": {
|
|
"id": 62,
|
|
"name": "probe44",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_256_511_bytes",
|
|
"physical_pin": {
|
|
"id": 56,
|
|
"name": "probe38",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_4096_8191_bytes",
|
|
"physical_pin": {
|
|
"id": 63,
|
|
"name": "probe45",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_512_1023_bytes",
|
|
"physical_pin": {
|
|
"id": 57,
|
|
"name": "probe39",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_64_bytes",
|
|
"physical_pin": {
|
|
"id": 53,
|
|
"name": "probe35",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_65_127_bytes",
|
|
"physical_pin": {
|
|
"id": 54,
|
|
"name": "probe36",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_8192_9215_bytes",
|
|
"physical_pin": {
|
|
"id": 64,
|
|
"name": "probe46",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_large",
|
|
"physical_pin": {
|
|
"id": 65,
|
|
"name": "probe47",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_small",
|
|
"physical_pin": {
|
|
"id": 66,
|
|
"name": "probe48",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_pause",
|
|
"physical_pin": {
|
|
"id": 67,
|
|
"name": "probe49",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_pause_valid",
|
|
"physical_pin": {
|
|
"id": 68,
|
|
"name": "probe50",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_bytes",
|
|
"physical_pin": {
|
|
"id": 69,
|
|
"name": "probe51",
|
|
"leftBit": 0,
|
|
"width": 6
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_good_bytes",
|
|
"physical_pin": {
|
|
"id": 70,
|
|
"name": "probe52",
|
|
"leftBit": 0,
|
|
"width": 14
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_good_packets",
|
|
"physical_pin": {
|
|
"id": 71,
|
|
"name": "probe53",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_packets",
|
|
"physical_pin": {
|
|
"id": 72,
|
|
"name": "probe54",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_unicast",
|
|
"physical_pin": {
|
|
"id": 73,
|
|
"name": "probe55",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_user_pause",
|
|
"physical_pin": {
|
|
"id": 74,
|
|
"name": "probe56",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_vlan",
|
|
"physical_pin": {
|
|
"id": 75,
|
|
"name": "probe57",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_3_STATISTICS_PORTS",
|
|
"vlnv": "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0",
|
|
"connectedBus": "cmac_usplus_i_stat_rx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "stat_rx_aligned",
|
|
"physical_pin": {
|
|
"id": 76,
|
|
"name": "probe58",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_aligned_err",
|
|
"physical_pin": {
|
|
"id": 77,
|
|
"name": "probe59",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_code",
|
|
"physical_pin": {
|
|
"id": 78,
|
|
"name": "probe60",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 79,
|
|
"name": "probe61",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_preamble",
|
|
"physical_pin": {
|
|
"id": 80,
|
|
"name": "probe62",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_sfd",
|
|
"physical_pin": {
|
|
"id": 81,
|
|
"name": "probe63",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_0",
|
|
"physical_pin": {
|
|
"id": 82,
|
|
"name": "probe64",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_1",
|
|
"physical_pin": {
|
|
"id": 83,
|
|
"name": "probe65",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_10",
|
|
"physical_pin": {
|
|
"id": 92,
|
|
"name": "probe74",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_11",
|
|
"physical_pin": {
|
|
"id": 93,
|
|
"name": "probe75",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_12",
|
|
"physical_pin": {
|
|
"id": 94,
|
|
"name": "probe76",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_13",
|
|
"physical_pin": {
|
|
"id": 95,
|
|
"name": "probe77",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_14",
|
|
"physical_pin": {
|
|
"id": 96,
|
|
"name": "probe78",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_15",
|
|
"physical_pin": {
|
|
"id": 97,
|
|
"name": "probe79",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_16",
|
|
"physical_pin": {
|
|
"id": 98,
|
|
"name": "probe80",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_17",
|
|
"physical_pin": {
|
|
"id": 99,
|
|
"name": "probe81",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_18",
|
|
"physical_pin": {
|
|
"id": 100,
|
|
"name": "probe82",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_19",
|
|
"physical_pin": {
|
|
"id": 101,
|
|
"name": "probe83",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_2",
|
|
"physical_pin": {
|
|
"id": 84,
|
|
"name": "probe66",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_3",
|
|
"physical_pin": {
|
|
"id": 85,
|
|
"name": "probe67",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_4",
|
|
"physical_pin": {
|
|
"id": 86,
|
|
"name": "probe68",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_5",
|
|
"physical_pin": {
|
|
"id": 87,
|
|
"name": "probe69",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_6",
|
|
"physical_pin": {
|
|
"id": 88,
|
|
"name": "probe70",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_7",
|
|
"physical_pin": {
|
|
"id": 89,
|
|
"name": "probe71",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_8",
|
|
"physical_pin": {
|
|
"id": 90,
|
|
"name": "probe72",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_9",
|
|
"physical_pin": {
|
|
"id": 91,
|
|
"name": "probe73",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_block_lock",
|
|
"physical_pin": {
|
|
"id": 102,
|
|
"name": "probe84",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_broadcast",
|
|
"physical_pin": {
|
|
"id": 103,
|
|
"name": "probe85",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_fragment",
|
|
"physical_pin": {
|
|
"id": 104,
|
|
"name": "probe86",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_0",
|
|
"physical_pin": {
|
|
"id": 105,
|
|
"name": "probe87",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_10",
|
|
"physical_pin": {
|
|
"id": 115,
|
|
"name": "probe97",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_11",
|
|
"physical_pin": {
|
|
"id": 116,
|
|
"name": "probe98",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_12",
|
|
"physical_pin": {
|
|
"id": 117,
|
|
"name": "probe99",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_13",
|
|
"physical_pin": {
|
|
"id": 118,
|
|
"name": "probe100",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_14",
|
|
"physical_pin": {
|
|
"id": 119,
|
|
"name": "probe101",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_15",
|
|
"physical_pin": {
|
|
"id": 120,
|
|
"name": "probe102",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_16",
|
|
"physical_pin": {
|
|
"id": 121,
|
|
"name": "probe103",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_17",
|
|
"physical_pin": {
|
|
"id": 122,
|
|
"name": "probe104",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_18",
|
|
"physical_pin": {
|
|
"id": 123,
|
|
"name": "probe105",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_19",
|
|
"physical_pin": {
|
|
"id": 124,
|
|
"name": "probe106",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_1",
|
|
"physical_pin": {
|
|
"id": 106,
|
|
"name": "probe88",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_2",
|
|
"physical_pin": {
|
|
"id": 107,
|
|
"name": "probe89",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_3",
|
|
"physical_pin": {
|
|
"id": 108,
|
|
"name": "probe90",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_4",
|
|
"physical_pin": {
|
|
"id": 109,
|
|
"name": "probe91",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_5",
|
|
"physical_pin": {
|
|
"id": 110,
|
|
"name": "probe92",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_6",
|
|
"physical_pin": {
|
|
"id": 111,
|
|
"name": "probe93",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_7",
|
|
"physical_pin": {
|
|
"id": 112,
|
|
"name": "probe94",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_8",
|
|
"physical_pin": {
|
|
"id": 113,
|
|
"name": "probe95",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_9",
|
|
"physical_pin": {
|
|
"id": 114,
|
|
"name": "probe96",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_0",
|
|
"physical_pin": {
|
|
"id": 125,
|
|
"name": "probe107",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_1",
|
|
"physical_pin": {
|
|
"id": 126,
|
|
"name": "probe108",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_10",
|
|
"physical_pin": {
|
|
"id": 135,
|
|
"name": "probe117",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_11",
|
|
"physical_pin": {
|
|
"id": 136,
|
|
"name": "probe118",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_12",
|
|
"physical_pin": {
|
|
"id": 137,
|
|
"name": "probe119",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_13",
|
|
"physical_pin": {
|
|
"id": 138,
|
|
"name": "probe120",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_14",
|
|
"physical_pin": {
|
|
"id": 139,
|
|
"name": "probe121",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_15",
|
|
"physical_pin": {
|
|
"id": 140,
|
|
"name": "probe122",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_16",
|
|
"physical_pin": {
|
|
"id": 141,
|
|
"name": "probe123",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_17",
|
|
"physical_pin": {
|
|
"id": 142,
|
|
"name": "probe124",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_18",
|
|
"physical_pin": {
|
|
"id": 143,
|
|
"name": "probe125",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_19",
|
|
"physical_pin": {
|
|
"id": 144,
|
|
"name": "probe126",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_2",
|
|
"physical_pin": {
|
|
"id": 127,
|
|
"name": "probe109",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_3",
|
|
"physical_pin": {
|
|
"id": 128,
|
|
"name": "probe110",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_4",
|
|
"physical_pin": {
|
|
"id": 129,
|
|
"name": "probe111",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_5",
|
|
"physical_pin": {
|
|
"id": 130,
|
|
"name": "probe112",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_6",
|
|
"physical_pin": {
|
|
"id": 131,
|
|
"name": "probe113",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_7",
|
|
"physical_pin": {
|
|
"id": 132,
|
|
"name": "probe114",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_8",
|
|
"physical_pin": {
|
|
"id": 133,
|
|
"name": "probe115",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_9",
|
|
"physical_pin": {
|
|
"id": 134,
|
|
"name": "probe116",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_got_signal_os",
|
|
"physical_pin": {
|
|
"id": 145,
|
|
"name": "probe127",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_hi_ber",
|
|
"physical_pin": {
|
|
"id": 146,
|
|
"name": "probe128",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_inrangeerr",
|
|
"physical_pin": {
|
|
"id": 147,
|
|
"name": "probe129",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_internal_local_fault",
|
|
"physical_pin": {
|
|
"id": 148,
|
|
"name": "probe130",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_jabber",
|
|
"physical_pin": {
|
|
"id": 149,
|
|
"name": "probe131",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_local_fault",
|
|
"physical_pin": {
|
|
"id": 150,
|
|
"name": "probe132",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_err",
|
|
"physical_pin": {
|
|
"id": 151,
|
|
"name": "probe133",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_len_err",
|
|
"physical_pin": {
|
|
"id": 152,
|
|
"name": "probe134",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_repeat_err",
|
|
"physical_pin": {
|
|
"id": 153,
|
|
"name": "probe135",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_misaligned",
|
|
"physical_pin": {
|
|
"id": 154,
|
|
"name": "probe136",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_multicast",
|
|
"physical_pin": {
|
|
"id": 155,
|
|
"name": "probe137",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_oversize",
|
|
"physical_pin": {
|
|
"id": 156,
|
|
"name": "probe138",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1024_1518_bytes",
|
|
"physical_pin": {
|
|
"id": 162,
|
|
"name": "probe144",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_128_255_bytes",
|
|
"physical_pin": {
|
|
"id": 159,
|
|
"name": "probe141",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1519_1522_bytes",
|
|
"physical_pin": {
|
|
"id": 163,
|
|
"name": "probe145",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1523_1548_bytes",
|
|
"physical_pin": {
|
|
"id": 164,
|
|
"name": "probe146",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1549_2047_bytes",
|
|
"physical_pin": {
|
|
"id": 165,
|
|
"name": "probe147",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_2048_4095_bytes",
|
|
"physical_pin": {
|
|
"id": 166,
|
|
"name": "probe148",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_256_511_bytes",
|
|
"physical_pin": {
|
|
"id": 160,
|
|
"name": "probe142",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_4096_8191_bytes",
|
|
"physical_pin": {
|
|
"id": 167,
|
|
"name": "probe149",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_512_1023_bytes",
|
|
"physical_pin": {
|
|
"id": 161,
|
|
"name": "probe143",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_64_bytes",
|
|
"physical_pin": {
|
|
"id": 157,
|
|
"name": "probe139",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_65_127_bytes",
|
|
"physical_pin": {
|
|
"id": 158,
|
|
"name": "probe140",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_8192_9215_bytes",
|
|
"physical_pin": {
|
|
"id": 168,
|
|
"name": "probe150",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 169,
|
|
"name": "probe151",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_large",
|
|
"physical_pin": {
|
|
"id": 170,
|
|
"name": "probe152",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_small",
|
|
"physical_pin": {
|
|
"id": 171,
|
|
"name": "probe153",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause",
|
|
"physical_pin": {
|
|
"id": 172,
|
|
"name": "probe154",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta0",
|
|
"physical_pin": {
|
|
"id": 173,
|
|
"name": "probe155",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta1",
|
|
"physical_pin": {
|
|
"id": 174,
|
|
"name": "probe156",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta2",
|
|
"physical_pin": {
|
|
"id": 175,
|
|
"name": "probe157",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta3",
|
|
"physical_pin": {
|
|
"id": 176,
|
|
"name": "probe158",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta4",
|
|
"physical_pin": {
|
|
"id": 177,
|
|
"name": "probe159",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta5",
|
|
"physical_pin": {
|
|
"id": 178,
|
|
"name": "probe160",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta6",
|
|
"physical_pin": {
|
|
"id": 179,
|
|
"name": "probe161",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta7",
|
|
"physical_pin": {
|
|
"id": 180,
|
|
"name": "probe162",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta8",
|
|
"physical_pin": {
|
|
"id": 181,
|
|
"name": "probe163",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_req",
|
|
"physical_pin": {
|
|
"id": 182,
|
|
"name": "probe164",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_valid",
|
|
"physical_pin": {
|
|
"id": 183,
|
|
"name": "probe165",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_demuxed",
|
|
"physical_pin": {
|
|
"id": 184,
|
|
"name": "probe166",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_0",
|
|
"physical_pin": {
|
|
"id": 185,
|
|
"name": "probe167",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_10",
|
|
"physical_pin": {
|
|
"id": 195,
|
|
"name": "probe177",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_11",
|
|
"physical_pin": {
|
|
"id": 196,
|
|
"name": "probe178",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_12",
|
|
"physical_pin": {
|
|
"id": 197,
|
|
"name": "probe179",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_13",
|
|
"physical_pin": {
|
|
"id": 198,
|
|
"name": "probe180",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_14",
|
|
"physical_pin": {
|
|
"id": 199,
|
|
"name": "probe181",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_15",
|
|
"physical_pin": {
|
|
"id": 200,
|
|
"name": "probe182",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_16",
|
|
"physical_pin": {
|
|
"id": 201,
|
|
"name": "probe183",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_17",
|
|
"physical_pin": {
|
|
"id": 202,
|
|
"name": "probe184",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_18",
|
|
"physical_pin": {
|
|
"id": 203,
|
|
"name": "probe185",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_19",
|
|
"physical_pin": {
|
|
"id": 204,
|
|
"name": "probe186",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_1",
|
|
"physical_pin": {
|
|
"id": 186,
|
|
"name": "probe168",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_2",
|
|
"physical_pin": {
|
|
"id": 187,
|
|
"name": "probe169",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_3",
|
|
"physical_pin": {
|
|
"id": 188,
|
|
"name": "probe170",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_4",
|
|
"physical_pin": {
|
|
"id": 189,
|
|
"name": "probe171",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_5",
|
|
"physical_pin": {
|
|
"id": 190,
|
|
"name": "probe172",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_6",
|
|
"physical_pin": {
|
|
"id": 191,
|
|
"name": "probe173",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_7",
|
|
"physical_pin": {
|
|
"id": 192,
|
|
"name": "probe174",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_8",
|
|
"physical_pin": {
|
|
"id": 193,
|
|
"name": "probe175",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_9",
|
|
"physical_pin": {
|
|
"id": 194,
|
|
"name": "probe176",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_received_local_fault",
|
|
"physical_pin": {
|
|
"id": 205,
|
|
"name": "probe187",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_remote_fault",
|
|
"physical_pin": {
|
|
"id": 206,
|
|
"name": "probe188",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_status",
|
|
"physical_pin": {
|
|
"id": 207,
|
|
"name": "probe189",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_stomped_fcs",
|
|
"physical_pin": {
|
|
"id": 208,
|
|
"name": "probe190",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_synced",
|
|
"physical_pin": {
|
|
"id": 209,
|
|
"name": "probe191",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_synced_err",
|
|
"physical_pin": {
|
|
"id": 210,
|
|
"name": "probe192",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_test_pattern_mismatch",
|
|
"physical_pin": {
|
|
"id": 211,
|
|
"name": "probe193",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_toolong",
|
|
"physical_pin": {
|
|
"id": 212,
|
|
"name": "probe194",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_bytes",
|
|
"physical_pin": {
|
|
"id": 213,
|
|
"name": "probe195",
|
|
"leftBit": 0,
|
|
"width": 7
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_good_bytes",
|
|
"physical_pin": {
|
|
"id": 214,
|
|
"name": "probe196",
|
|
"leftBit": 0,
|
|
"width": 14
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_good_packets",
|
|
"physical_pin": {
|
|
"id": 215,
|
|
"name": "probe197",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_packets",
|
|
"physical_pin": {
|
|
"id": 216,
|
|
"name": "probe198",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_truncated",
|
|
"physical_pin": {
|
|
"id": 217,
|
|
"name": "probe199",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_undersize",
|
|
"physical_pin": {
|
|
"id": 218,
|
|
"name": "probe200",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_unicast",
|
|
"physical_pin": {
|
|
"id": 219,
|
|
"name": "probe201",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_user_pause",
|
|
"physical_pin": {
|
|
"id": 220,
|
|
"name": "probe202",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_vlan",
|
|
"physical_pin": {
|
|
"id": 221,
|
|
"name": "probe203",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_4_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "cmac_axis_rx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 222,
|
|
"name": "probe204",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TKEEP",
|
|
"physical_pin": {
|
|
"id": 223,
|
|
"name": "probe205",
|
|
"leftBit": 0,
|
|
"width": 64
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 226,
|
|
"name": "probe208",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 224,
|
|
"name": "probe206",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 225,
|
|
"name": "probe207",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_5_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "unpacker_m_axis",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 227,
|
|
"name": "probe209",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 230,
|
|
"name": "probe212",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 228,
|
|
"name": "probe210",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 229,
|
|
"name": "probe211",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"native_ports": [
|
|
{
|
|
"name": "probe0",
|
|
"connectedBus": "cmac_usplus_i_gt_powergoodout",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe0",
|
|
"physical_pin": {
|
|
"id": 18,
|
|
"name": "probe0",
|
|
"leftBit": 0,
|
|
"width": 4
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe10",
|
|
"connectedBus": "rx_fifo_wr_data_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe10",
|
|
"physical_pin": {
|
|
"id": 28,
|
|
"name": "probe10",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe11",
|
|
"connectedBus": "ETH_regs_prog_full_on",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe11",
|
|
"physical_pin": {
|
|
"id": 29,
|
|
"name": "probe11",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe12",
|
|
"connectedBus": "ETH_regs_prog_full_off",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe12",
|
|
"physical_pin": {
|
|
"id": 30,
|
|
"name": "probe12",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe13",
|
|
"connectedBus": "eth_frame_packer_i_tx_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe13",
|
|
"physical_pin": {
|
|
"id": 31,
|
|
"name": "probe13",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe14",
|
|
"connectedBus": "eth_flowctrl_rx_0_rx_pause_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe14",
|
|
"physical_pin": {
|
|
"id": 32,
|
|
"name": "probe14",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe15",
|
|
"connectedBus": "eth_flowctrl_rx_0_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe15",
|
|
"physical_pin": {
|
|
"id": 33,
|
|
"name": "probe15",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe16",
|
|
"connectedBus": "cmac_usplus_i_stat_rx_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe16",
|
|
"physical_pin": {
|
|
"id": 34,
|
|
"name": "probe16",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe17",
|
|
"connectedBus": "cmac_usplus_i_stat_rx_pause_quanta8",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe17",
|
|
"physical_pin": {
|
|
"id": 35,
|
|
"name": "probe17",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe18",
|
|
"connectedBus": "eth_frame_unpacker_i_rx_frame_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe18",
|
|
"physical_pin": {
|
|
"id": 36,
|
|
"name": "probe18",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe19",
|
|
"connectedBus": "eth_flowctrl_tx_i_tx_pause_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe19",
|
|
"physical_pin": {
|
|
"id": 37,
|
|
"name": "probe19",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe1",
|
|
"connectedBus": "packer_underrun_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe1",
|
|
"physical_pin": {
|
|
"id": 19,
|
|
"name": "probe1",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe2",
|
|
"connectedBus": "rx_fifo_overflow",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe2",
|
|
"physical_pin": {
|
|
"id": 20,
|
|
"name": "probe2",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe3",
|
|
"connectedBus": "unpacker_rx_frame_err_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe3",
|
|
"physical_pin": {
|
|
"id": 21,
|
|
"name": "probe3",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe4",
|
|
"connectedBus": "eth_regs_dest_addr",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe4",
|
|
"physical_pin": {
|
|
"id": 22,
|
|
"name": "probe4",
|
|
"leftBit": 0,
|
|
"width": 48
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe5",
|
|
"connectedBus": "eth_regs_source_addr",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe5",
|
|
"physical_pin": {
|
|
"id": 23,
|
|
"name": "probe5",
|
|
"leftBit": 0,
|
|
"width": 48
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe6",
|
|
"connectedBus": "eth_regs_EtherType",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe6",
|
|
"physical_pin": {
|
|
"id": 24,
|
|
"name": "probe6",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe7",
|
|
"connectedBus": "prog_full_manual",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe7",
|
|
"physical_pin": {
|
|
"id": 25,
|
|
"name": "probe7",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe8",
|
|
"connectedBus": "ctl_tx_resend_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe8",
|
|
"physical_pin": {
|
|
"id": 26,
|
|
"name": "probe8",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe9",
|
|
"connectedBus": "ctl_tx_pause_req",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe9",
|
|
"physical_pin": {
|
|
"id": 27,
|
|
"name": "probe9",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"type": "ILA_V3",
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/ila_lib",
|
|
"spec": "labtools_ila_v6",
|
|
"ipName": "ila",
|
|
"core_location": {
|
|
"user_chain": 1,
|
|
"slave_index": 2,
|
|
"bscan_switch_index": 0
|
|
},
|
|
"uuid": "CB2DFF98B59250A799E4E9C077D09366",
|
|
"pins": [
|
|
{
|
|
"name": "probe0",
|
|
"id": 231,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 3,
|
|
"portIndex": 0,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe1",
|
|
"id": 232,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 1,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe2",
|
|
"id": 233,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 2,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe2_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe3",
|
|
"id": 234,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 3,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe4",
|
|
"id": 235,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 47,
|
|
"portIndex": 4,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe5",
|
|
"id": 236,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 47,
|
|
"portIndex": 5,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe6",
|
|
"id": 237,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 6,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe7",
|
|
"id": 238,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 7,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe7_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe8",
|
|
"id": 239,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 8,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe8_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe9",
|
|
"id": 240,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 9,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe10",
|
|
"id": 241,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 10,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe11",
|
|
"id": 242,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 11,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe12",
|
|
"id": 243,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 12,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe13",
|
|
"id": 244,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 13,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe14",
|
|
"id": 245,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 14,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe15",
|
|
"id": 246,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 15,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe15_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe16",
|
|
"id": 247,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 16,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe16_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe17",
|
|
"id": 248,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 17,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe18",
|
|
"id": 249,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 18,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe19",
|
|
"id": 250,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 31,
|
|
"portIndex": 19,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/probe19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe20",
|
|
"id": 251,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 20,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[491]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[490]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[489]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[487]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[486]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[485]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[484]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[483]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[482]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[480]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[479]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[478]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[477]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[475]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[474]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[473]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[472]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[471]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[470]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[469]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[468]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[467]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[466]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[465]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[464]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[463]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[460]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[429]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[427]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[425]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[422]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[421]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[416]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[415]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[414]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[413]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[412]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[411]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[410]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[409]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[408]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[407]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[406]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[405]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[404]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[403]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[402]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[401]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[400]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[399]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[398]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[397]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[396]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[395]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[394]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[393]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[300]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[299]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[298]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe21",
|
|
"id": 252,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 21,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe22",
|
|
"id": 253,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 22,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tready",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe23",
|
|
"id": 254,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 23,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_0_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe24",
|
|
"id": 255,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 24,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[505]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[504]"
|
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},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[503]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[502]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[501]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[500]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[499]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[498]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[497]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[496]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[495]"
|
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},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[494]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[493]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[492]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[491]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[490]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[489]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[487]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[486]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[485]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[484]"
|
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},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[483]"
|
|
},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[482]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[481]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[480]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[479]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[478]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[477]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[476]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[475]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[474]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[473]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[472]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[471]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[470]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[469]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[468]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[467]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[466]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[465]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[464]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[463]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[462]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[461]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[460]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[459]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[458]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[457]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[456]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[455]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[454]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[453]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[452]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[451]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[450]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[449]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[448]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[447]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[446]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[445]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[444]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[443]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[442]"
|
|
},
|
|
{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[441]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[356]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[355]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[354]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[353]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[351]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[350]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[349]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[348]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[347]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[252]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[61]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[60]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[59]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[58]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[57]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[56]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[55]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[54]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[53]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[52]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[51]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[50]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[49]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[48]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[47]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[46]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[45]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[44]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[43]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[42]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[41]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[40]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[39]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[38]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[37]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[36]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[35]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[34]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[33]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[32]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[31]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[30]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[29]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[28]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[27]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[26]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[25]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[24]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[23]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[22]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[21]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[20]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[19]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[18]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[17]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[16]"
|
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[15]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[14]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[13]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[12]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[11]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[10]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[9]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[8]"
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[7]"
|
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[6]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[5]"
|
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[4]"
|
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[3]"
|
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[2]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[1]"
|
|
},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe25",
|
|
"id": 256,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 63,
|
|
"portIndex": 25,
|
|
"nets": [
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|
{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep",
|
|
"isBus": true,
|
|
"subnets": [
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[63]"
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[62]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[61]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[60]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[59]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[58]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[57]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[56]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[55]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[54]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[53]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[52]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[51]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[50]"
|
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},
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[49]"
|
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[48]"
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{
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|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[47]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[46]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[45]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[44]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[43]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[42]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[41]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[40]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[39]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[38]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[37]"
|
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[36]"
|
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[35]"
|
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},
|
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[34]"
|
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},
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{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tkeep[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe26",
|
|
"id": 257,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 26,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe27",
|
|
"id": 258,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 27,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe28",
|
|
"id": 259,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 28,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tready",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe29",
|
|
"id": 260,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 29,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_1_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe30",
|
|
"id": 261,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 30,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_bad_fcs_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe31",
|
|
"id": 262,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 31,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_broadcast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe32",
|
|
"id": 263,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 32,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_frame_error_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe33",
|
|
"id": 264,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 33,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe34",
|
|
"id": 265,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 34,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_multicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe35",
|
|
"id": 266,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 35,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_64_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe36",
|
|
"id": 267,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 36,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_65_127_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe37",
|
|
"id": 268,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 37,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_128_255_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe38",
|
|
"id": 269,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 38,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_256_511_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe39",
|
|
"id": 270,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 39,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_512_1023_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe40",
|
|
"id": 271,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 40,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1024_1518_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe41",
|
|
"id": 272,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 41,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1519_1522_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe42",
|
|
"id": 273,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 42,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1523_1548_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe43",
|
|
"id": 274,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 43,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_1549_2047_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe44",
|
|
"id": 275,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 44,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_2048_4095_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe45",
|
|
"id": 276,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 45,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_4096_8191_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe46",
|
|
"id": 277,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 46,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_8192_9215_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe47",
|
|
"id": 278,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 47,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_large_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe48",
|
|
"id": 279,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 48,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_packet_small_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe49",
|
|
"id": 280,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 49,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe50",
|
|
"id": 281,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 50,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_pause_valid_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe51",
|
|
"id": 282,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 5,
|
|
"portIndex": 51,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe52",
|
|
"id": 283,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 13,
|
|
"portIndex": 52,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe53",
|
|
"id": 284,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 53,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_good_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe54",
|
|
"id": 285,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 54,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_total_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe55",
|
|
"id": 286,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 55,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_unicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe56",
|
|
"id": 287,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 56,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_user_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe57",
|
|
"id": 288,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 57,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_2_STATISTICS_PORTS_stat_tx_vlan_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe58",
|
|
"id": 289,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 58,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_aligned_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe59",
|
|
"id": 290,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 59,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_aligned_err_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe60",
|
|
"id": 291,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 60,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_code_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe61",
|
|
"id": 292,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 61,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_fcs_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe62",
|
|
"id": 293,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 62,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bad_preamble_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe63",
|
|
"id": 294,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 63,
|
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{
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|
|
"isBus": false
|
|
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|
|
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|
|
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|
{
|
|
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|
|
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|
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|
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|
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|
|
"isBus": false
|
|
}
|
|
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|
|
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|
|
{
|
|
"name": "probe65",
|
|
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|
|
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|
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|
|
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|
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|
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|
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{
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe66",
|
|
"id": 297,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
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|
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|
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|
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{
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe67",
|
|
"id": 298,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe68",
|
|
"id": 299,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe69",
|
|
"id": 300,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe70",
|
|
"id": 301,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
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|
|
"portIndex": 70,
|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe71",
|
|
"id": 302,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
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|
|
"portIndex": 71,
|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe72",
|
|
"id": 303,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_8_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe73",
|
|
"id": 304,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
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|
|
"portIndex": 73,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_9_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe74",
|
|
"id": 305,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
"portIndex": 74,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_10_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe75",
|
|
"id": 306,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
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|
|
"portIndex": 75,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_11_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe76",
|
|
"id": 307,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
"portIndex": 76,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_12_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe77",
|
|
"id": 308,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
"portIndex": 77,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_13_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe78",
|
|
"id": 309,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_14_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe79",
|
|
"id": 310,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe80",
|
|
"id": 311,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_16_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe81",
|
|
"id": 312,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe82",
|
|
"id": 313,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe83",
|
|
"id": 314,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_bip_err_19_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe84",
|
|
"id": 315,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 84,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_block_lock_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe85",
|
|
"id": 316,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 85,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_broadcast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe86",
|
|
"id": 317,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 86,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_fragment_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe87",
|
|
"id": 318,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 87,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe88",
|
|
"id": 319,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 88,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe89",
|
|
"id": 320,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 89,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe90",
|
|
"id": 321,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 90,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe91",
|
|
"id": 322,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 91,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe92",
|
|
"id": 323,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 92,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe93",
|
|
"id": 324,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 93,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe94",
|
|
"id": 325,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 94,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe95",
|
|
"id": 326,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 95,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe96",
|
|
"id": 327,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 96,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe97",
|
|
"id": 328,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 97,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe98",
|
|
"id": 329,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 98,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe99",
|
|
"id": 330,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 99,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe100",
|
|
"id": 331,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 100,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe101",
|
|
"id": 332,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 101,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe102",
|
|
"id": 333,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 102,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_15_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe103",
|
|
"id": 334,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 103,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_16_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe104",
|
|
"id": 335,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 104,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe105",
|
|
"id": 336,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 1,
|
|
"portIndex": 105,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1",
|
|
"isBus": true,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe106",
|
|
"id": 337,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
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|
|
"portIndex": 106,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1",
|
|
"isBus": true,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe107",
|
|
"id": 338,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe108",
|
|
"id": 339,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
"portIndex": 108,
|
|
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|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_framing_err_valid_1_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe109",
|
|
"id": 340,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe110",
|
|
"id": 341,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
"portIndex": 110,
|
|
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|
{
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe111",
|
|
"id": 342,
|
|
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|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
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|
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|
{
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
{
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
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|
|
}
|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
|
}
|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
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|
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|
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|
|
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|
|
}
|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
|
}
|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
|
}
|
|
]
|
|
},
|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
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|
|
}
|
|
]
|
|
},
|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe121",
|
|
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|
|
"type": "DATA_TRIGGER",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe123",
|
|
"id": 354,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe124",
|
|
"id": 355,
|
|
"type": "DATA_TRIGGER",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe125",
|
|
"id": 356,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe126",
|
|
"id": 357,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
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|
|
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|
|
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|
|
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|
|
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|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe127",
|
|
"id": 358,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
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|
|
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|
|
"portIndex": 127,
|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe128",
|
|
"id": 359,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe129",
|
|
"id": 360,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 129,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_inrangeerr_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe130",
|
|
"id": 361,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 130,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_internal_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe131",
|
|
"id": 362,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 131,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_jabber_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe132",
|
|
"id": 363,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 132,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe133",
|
|
"id": 364,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 133,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe134",
|
|
"id": 365,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 134,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_len_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe135",
|
|
"id": 366,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 135,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_mf_repeat_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe136",
|
|
"id": 367,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 136,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_misaligned_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe137",
|
|
"id": 368,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 137,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_multicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe138",
|
|
"id": 369,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 138,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_oversize_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe139",
|
|
"id": 370,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 139,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_64_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe140",
|
|
"id": 371,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 140,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_65_127_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe141",
|
|
"id": 372,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 141,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_128_255_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe142",
|
|
"id": 373,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 142,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_256_511_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe143",
|
|
"id": 374,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 143,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_512_1023_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe144",
|
|
"id": 375,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 144,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1024_1518_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe145",
|
|
"id": 376,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 145,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1519_1522_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe146",
|
|
"id": 377,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 146,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1523_1548_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe147",
|
|
"id": 378,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 147,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_1549_2047_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe148",
|
|
"id": 379,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 148,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_2048_4095_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe149",
|
|
"id": 380,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 149,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_4096_8191_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe150",
|
|
"id": 381,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 150,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_8192_9215_bytes_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe151",
|
|
"id": 382,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 151,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_bad_fcs_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe152",
|
|
"id": 383,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 152,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_large_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe153",
|
|
"id": 384,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 153,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_packet_small_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe154",
|
|
"id": 385,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 154,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe155",
|
|
"id": 386,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 155,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe156",
|
|
"id": 387,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 156,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe157",
|
|
"id": 388,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 157,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe158",
|
|
"id": 389,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 158,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe159",
|
|
"id": 390,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 159,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe160",
|
|
"id": 391,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 160,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe161",
|
|
"id": 392,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 161,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe162",
|
|
"id": 393,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 162,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe163",
|
|
"id": 394,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 15,
|
|
"portIndex": 163,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_quanta8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe164",
|
|
"id": 395,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 164,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_req_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe165",
|
|
"id": 396,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 8,
|
|
"portIndex": 165,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pause_valid_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe166",
|
|
"id": 397,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 166,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_demuxed_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe167",
|
|
"id": 398,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 167,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_0_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe168",
|
|
"id": 399,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 168,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_1_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe169",
|
|
"id": 400,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 169,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_2_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe170",
|
|
"id": 401,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 170,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_3_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe171",
|
|
"id": 402,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 171,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_4_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe172",
|
|
"id": 403,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 172,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_5_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe173",
|
|
"id": 404,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 173,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_6_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe174",
|
|
"id": 405,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 174,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_7_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe175",
|
|
"id": 406,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 175,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_8_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe176",
|
|
"id": 407,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 176,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_9_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe177",
|
|
"id": 408,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 177,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_10_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe178",
|
|
"id": 409,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 178,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_11_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe179",
|
|
"id": 410,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 179,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_12_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe180",
|
|
"id": 411,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 180,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_13_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe181",
|
|
"id": 412,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 181,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_14_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe182",
|
|
"id": 413,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 182,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_15_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe183",
|
|
"id": 414,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 183,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_16_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe184",
|
|
"id": 415,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 184,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_17_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe185",
|
|
"id": 416,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 185,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_18_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe186",
|
|
"id": 417,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 4,
|
|
"portIndex": 186,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_pcsl_number_19_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe187",
|
|
"id": 418,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 187,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_received_local_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe188",
|
|
"id": 419,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 188,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_remote_fault_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe189",
|
|
"id": 420,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 189,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_status_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe190",
|
|
"id": 421,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 190,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_stomped_fcs_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe191",
|
|
"id": 422,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 191,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe192",
|
|
"id": 423,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 19,
|
|
"portIndex": 192,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_synced_err_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe193",
|
|
"id": 424,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 193,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_test_pattern_mismatch_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe194",
|
|
"id": 425,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 194,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_toolong_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe195",
|
|
"id": 426,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 6,
|
|
"portIndex": 195,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe196",
|
|
"id": 427,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 13,
|
|
"portIndex": 196,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_bytes_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe197",
|
|
"id": 428,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 197,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_good_packets_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe198",
|
|
"id": 429,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 198,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_total_packets_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe199",
|
|
"id": 430,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 199,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_truncated_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe200",
|
|
"id": 431,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 2,
|
|
"portIndex": 200,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_undersize_1[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe201",
|
|
"id": 432,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 201,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_unicast_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe202",
|
|
"id": 433,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 202,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_user_pause_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe203",
|
|
"id": 434,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 203,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/SLOT_3_STATISTICS_PORTS_stat_rx_vlan_1",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe204",
|
|
"id": 435,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 204,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[497]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[496]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[495]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[494]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[493]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[492]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[491]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[490]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[489]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[488]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[487]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[486]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[485]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[484]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[483]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[482]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[481]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[480]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[479]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[478]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[477]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[476]"
|
|
},
|
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[475]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[474]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[473]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[472]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[471]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[470]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[469]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[468]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[467]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[466]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[465]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[464]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[463]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[462]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[461]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[460]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[459]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[458]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[457]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[456]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[455]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[454]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[453]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[452]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[451]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[450]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[449]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[448]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[447]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[446]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[445]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[444]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[443]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[442]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[441]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[440]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[439]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[438]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[437]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[436]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[435]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[434]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[433]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[432]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[431]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[430]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[429]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[428]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[427]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[426]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[425]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[424]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[423]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[422]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[421]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[420]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[419]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[418]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[417]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[416]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[415]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[414]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[413]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[412]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[411]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[410]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[409]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[408]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[407]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[406]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[405]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[404]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[403]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[402]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[401]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[400]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[399]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[398]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[397]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[396]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[395]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[394]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[393]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[392]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[391]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[390]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[389]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[388]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[387]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[386]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[385]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[384]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[383]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[382]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[381]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[380]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[379]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[378]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[377]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[376]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[375]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[374]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[373]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[372]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[371]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[370]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[369]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[368]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[367]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[366]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[365]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[364]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[363]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[362]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[361]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[360]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[359]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[358]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[357]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[356]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[355]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[354]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[353]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[352]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[351]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[350]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[349]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[348]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[347]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[346]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[345]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[344]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[343]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[342]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[341]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[340]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[338]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[337]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[336]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[335]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[334]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[333]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[332]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[331]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[330]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[323]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[321]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[320]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[318]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[317]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[316]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[315]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[314]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[313]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[312]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[311]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[310]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[309]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[308]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[307]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[306]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[305]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[304]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[303]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[302]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[301]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[300]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[299]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[298]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[297]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[296]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[295]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[294]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[293]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[292]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[291]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[290]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[289]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[288]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[287]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[286]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[285]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[284]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[283]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[282]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[281]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[280]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[279]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[278]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[277]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[276]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[275]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[274]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[273]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[272]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[271]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[270]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[269]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[268]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[267]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[266]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[265]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[264]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[263]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[262]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[261]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[260]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[259]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[258]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[257]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[255]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[254]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[253]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[252]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[248]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[246]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[245]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[243]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[240]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[239]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[238]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[237]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[236]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[234]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[233]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[232]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[231]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[230]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[226]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[225]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[224]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[223]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[222]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[221]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[220]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[219]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[218]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[217]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[216]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[215]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[214]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[213]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[212]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[211]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[210]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[209]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[208]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[207]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[206]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[205]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[204]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[203]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[202]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[201]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[200]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[199]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[198]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[197]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[196]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[195]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[194]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[193]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[192]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[191]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[190]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[111]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[107]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[106]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[105]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[104]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[103]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[102]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[101]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[100]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[99]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[98]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[97]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[96]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[95]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[94]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[93]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[86]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[85]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[84]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[83]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[82]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[81]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[80]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[79]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[78]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[77]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[76]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[74]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[73]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[71]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[69]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[49]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[37]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[33]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[32]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[31]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[29]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[28]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[27]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[26]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[25]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[24]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[23]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[22]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[21]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[20]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[19]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[18]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[17]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[16]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[15]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[14]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[13]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[12]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[11]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[10]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[9]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[8]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[7]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[6]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[5]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[4]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[3]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[2]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[1]"
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|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe205",
|
|
"id": 436,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 63,
|
|
"portIndex": 205,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[63]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[62]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[61]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[60]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[59]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[58]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[57]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[56]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[55]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[54]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[53]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[52]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[51]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[50]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[49]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[48]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[47]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[46]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[45]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[44]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[43]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[42]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[41]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[40]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[39]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[38]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[37]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[36]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[35]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[34]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[33]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[32]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[31]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[30]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[29]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[28]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[27]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[26]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[25]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[24]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[23]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[22]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tkeep[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe206",
|
|
"id": 437,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 206,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe207",
|
|
"id": 438,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 207,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe208",
|
|
"id": 439,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 208,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_4_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe209",
|
|
"id": 440,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": true,
|
|
"leftIndex": 0,
|
|
"rightIndex": 511,
|
|
"portIndex": 209,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata",
|
|
"isBus": true,
|
|
"subnets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[511]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[510]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[509]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[508]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[507]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[506]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[505]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[504]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[503]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[502]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[501]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[500]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[499]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[498]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[497]"
|
|
},
|
|
{
|
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[496]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[495]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[494]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[493]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[492]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[491]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[490]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[489]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[488]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[487]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[486]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[485]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[484]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[483]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[482]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[481]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[480]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[479]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[478]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[477]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[476]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[475]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[474]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[473]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[472]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[471]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[470]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[469]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[468]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[467]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[466]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[465]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[464]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[463]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[462]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[461]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[460]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[459]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[458]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[457]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[456]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[455]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[454]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[453]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[452]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[451]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[450]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[449]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[448]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[447]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[446]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[445]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[444]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[443]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[442]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[441]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[440]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[439]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[438]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[437]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[436]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[435]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[434]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[433]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[432]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[431]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[430]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[429]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[428]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[427]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[426]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[425]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[424]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[423]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[422]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[421]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[420]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[419]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[418]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[417]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[416]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[415]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[414]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[413]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[412]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[411]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[410]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[409]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[408]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[407]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[406]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[405]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[404]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[403]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[402]"
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},
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[401]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[400]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[399]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[398]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[397]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[396]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[395]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[394]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[393]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[392]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[391]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[390]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[389]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[388]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[387]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[386]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[385]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[384]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[383]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[382]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[381]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[380]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[379]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[378]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[377]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[376]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[375]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[374]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[373]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[372]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[371]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[370]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[369]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[368]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[367]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[366]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[365]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[364]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[363]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[362]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[361]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[360]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[359]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[358]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[357]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[356]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[355]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[354]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[353]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[352]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[351]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[350]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[349]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[348]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[347]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[346]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[345]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[344]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[343]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[342]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[341]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[340]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[339]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[338]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[337]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[336]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[335]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[334]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[333]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[332]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[331]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[330]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[329]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[328]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[327]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[326]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[325]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[324]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[323]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[322]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[321]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[320]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[319]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[318]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[317]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[316]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[315]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[314]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[313]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[312]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[311]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[310]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[309]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[308]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[307]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[306]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[305]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[303]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[302]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[301]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[300]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[299]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[297]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[294]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[293]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[292]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[291]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[289]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[288]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[285]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[284]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[243]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[240]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[238]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[237]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[236]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[235]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[234]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[233]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[232]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[231]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[230]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[229]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[228]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[227]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[226]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[225]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[224]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[223]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[222]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[221]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[220]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[219]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[218]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[217]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[216]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[215]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[214]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[213]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[212]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[211]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[210]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[208]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[207]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[206]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[202]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[135]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[126]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[125]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[124]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[123]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[122]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[121]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[120]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[119]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[118]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[117]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[116]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[115]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[114]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[113]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[112]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[111]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[110]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[109]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[108]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[107]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[106]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[105]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[104]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[103]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[102]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[101]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[100]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[99]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[98]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[97]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[95]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[94]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[93]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[92]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[91]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[87]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[86]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[85]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[74]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[54]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[53]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[52]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[51]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[50]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[49]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[48]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[47]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[46]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[45]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[44]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[43]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[42]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[41]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[40]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[39]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[38]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[37]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[36]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[35]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[34]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[33]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[32]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[31]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[30]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[29]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[28]"
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[27]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[26]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[25]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[24]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[23]"
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{
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"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[22]"
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|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[21]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[20]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[19]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[18]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[17]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[16]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[15]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[14]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[13]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[12]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[11]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[10]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[9]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[8]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[7]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[6]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[5]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[4]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[3]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[2]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[1]"
|
|
},
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tdata[0]"
|
|
}
|
|
]
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe210",
|
|
"id": 441,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 210,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tuser",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe211",
|
|
"id": 442,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 211,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tvalid",
|
|
"isBus": false
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe212",
|
|
"id": 443,
|
|
"type": "DATA_TRIGGER",
|
|
"direction": "IN",
|
|
"isVector": false,
|
|
"leftIndex": 0,
|
|
"rightIndex": 0,
|
|
"portIndex": 212,
|
|
"nets": [
|
|
{
|
|
"name": "i_raw_eth_cmac_4/raw_eth_cmac_4_i/hier_0/srl2/Ethernet/system_ila_i/inst/net_slot_5_axis_tlast",
|
|
"isBus": false
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"bus_interfaces": [
|
|
{
|
|
"name": "SLOT_0_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "cmac_tx_fifo_M_AXIS",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 251,
|
|
"name": "probe20",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 254,
|
|
"name": "probe23",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TREADY",
|
|
"physical_pin": {
|
|
"id": 253,
|
|
"name": "probe22",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 252,
|
|
"name": "probe21",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_1_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "packer_m_axis",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 255,
|
|
"name": "probe24",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TKEEP",
|
|
"physical_pin": {
|
|
"id": 256,
|
|
"name": "probe25",
|
|
"leftBit": 0,
|
|
"width": 64
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 260,
|
|
"name": "probe29",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TREADY",
|
|
"physical_pin": {
|
|
"id": 259,
|
|
"name": "probe28",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 257,
|
|
"name": "probe26",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 258,
|
|
"name": "probe27",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_2_STATISTICS_PORTS",
|
|
"vlnv": "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0",
|
|
"connectedBus": "cmac_usplus_i_stat_tx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "stat_tx_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 261,
|
|
"name": "probe30",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_broadcast",
|
|
"physical_pin": {
|
|
"id": 262,
|
|
"name": "probe31",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_frame_error",
|
|
"physical_pin": {
|
|
"id": 263,
|
|
"name": "probe32",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_local_fault",
|
|
"physical_pin": {
|
|
"id": 264,
|
|
"name": "probe33",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_multicast",
|
|
"physical_pin": {
|
|
"id": 265,
|
|
"name": "probe34",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1024_1518_bytes",
|
|
"physical_pin": {
|
|
"id": 271,
|
|
"name": "probe40",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_128_255_bytes",
|
|
"physical_pin": {
|
|
"id": 268,
|
|
"name": "probe37",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1519_1522_bytes",
|
|
"physical_pin": {
|
|
"id": 272,
|
|
"name": "probe41",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1523_1548_bytes",
|
|
"physical_pin": {
|
|
"id": 273,
|
|
"name": "probe42",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_1549_2047_bytes",
|
|
"physical_pin": {
|
|
"id": 274,
|
|
"name": "probe43",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_2048_4095_bytes",
|
|
"physical_pin": {
|
|
"id": 275,
|
|
"name": "probe44",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_256_511_bytes",
|
|
"physical_pin": {
|
|
"id": 269,
|
|
"name": "probe38",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_4096_8191_bytes",
|
|
"physical_pin": {
|
|
"id": 276,
|
|
"name": "probe45",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_512_1023_bytes",
|
|
"physical_pin": {
|
|
"id": 270,
|
|
"name": "probe39",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_64_bytes",
|
|
"physical_pin": {
|
|
"id": 266,
|
|
"name": "probe35",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_65_127_bytes",
|
|
"physical_pin": {
|
|
"id": 267,
|
|
"name": "probe36",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_8192_9215_bytes",
|
|
"physical_pin": {
|
|
"id": 277,
|
|
"name": "probe46",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_large",
|
|
"physical_pin": {
|
|
"id": 278,
|
|
"name": "probe47",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_packet_small",
|
|
"physical_pin": {
|
|
"id": 279,
|
|
"name": "probe48",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_pause",
|
|
"physical_pin": {
|
|
"id": 280,
|
|
"name": "probe49",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_pause_valid",
|
|
"physical_pin": {
|
|
"id": 281,
|
|
"name": "probe50",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_bytes",
|
|
"physical_pin": {
|
|
"id": 282,
|
|
"name": "probe51",
|
|
"leftBit": 0,
|
|
"width": 6
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_good_bytes",
|
|
"physical_pin": {
|
|
"id": 283,
|
|
"name": "probe52",
|
|
"leftBit": 0,
|
|
"width": 14
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_good_packets",
|
|
"physical_pin": {
|
|
"id": 284,
|
|
"name": "probe53",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_total_packets",
|
|
"physical_pin": {
|
|
"id": 285,
|
|
"name": "probe54",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_unicast",
|
|
"physical_pin": {
|
|
"id": 286,
|
|
"name": "probe55",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_user_pause",
|
|
"physical_pin": {
|
|
"id": 287,
|
|
"name": "probe56",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_tx_vlan",
|
|
"physical_pin": {
|
|
"id": 288,
|
|
"name": "probe57",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_3_STATISTICS_PORTS",
|
|
"vlnv": "xilinx.com:display_cmac_usplus:statistics_ports_int:2.0",
|
|
"connectedBus": "cmac_usplus_i_stat_rx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "stat_rx_aligned",
|
|
"physical_pin": {
|
|
"id": 289,
|
|
"name": "probe58",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_aligned_err",
|
|
"physical_pin": {
|
|
"id": 290,
|
|
"name": "probe59",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_code",
|
|
"physical_pin": {
|
|
"id": 291,
|
|
"name": "probe60",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 292,
|
|
"name": "probe61",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_preamble",
|
|
"physical_pin": {
|
|
"id": 293,
|
|
"name": "probe62",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bad_sfd",
|
|
"physical_pin": {
|
|
"id": 294,
|
|
"name": "probe63",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_0",
|
|
"physical_pin": {
|
|
"id": 295,
|
|
"name": "probe64",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_1",
|
|
"physical_pin": {
|
|
"id": 296,
|
|
"name": "probe65",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_10",
|
|
"physical_pin": {
|
|
"id": 305,
|
|
"name": "probe74",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_11",
|
|
"physical_pin": {
|
|
"id": 306,
|
|
"name": "probe75",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_12",
|
|
"physical_pin": {
|
|
"id": 307,
|
|
"name": "probe76",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_13",
|
|
"physical_pin": {
|
|
"id": 308,
|
|
"name": "probe77",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_14",
|
|
"physical_pin": {
|
|
"id": 309,
|
|
"name": "probe78",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_15",
|
|
"physical_pin": {
|
|
"id": 310,
|
|
"name": "probe79",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_16",
|
|
"physical_pin": {
|
|
"id": 311,
|
|
"name": "probe80",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_17",
|
|
"physical_pin": {
|
|
"id": 312,
|
|
"name": "probe81",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_18",
|
|
"physical_pin": {
|
|
"id": 313,
|
|
"name": "probe82",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_19",
|
|
"physical_pin": {
|
|
"id": 314,
|
|
"name": "probe83",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_2",
|
|
"physical_pin": {
|
|
"id": 297,
|
|
"name": "probe66",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_3",
|
|
"physical_pin": {
|
|
"id": 298,
|
|
"name": "probe67",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_4",
|
|
"physical_pin": {
|
|
"id": 299,
|
|
"name": "probe68",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_5",
|
|
"physical_pin": {
|
|
"id": 300,
|
|
"name": "probe69",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_6",
|
|
"physical_pin": {
|
|
"id": 301,
|
|
"name": "probe70",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_7",
|
|
"physical_pin": {
|
|
"id": 302,
|
|
"name": "probe71",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_8",
|
|
"physical_pin": {
|
|
"id": 303,
|
|
"name": "probe72",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_bip_err_9",
|
|
"physical_pin": {
|
|
"id": 304,
|
|
"name": "probe73",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_block_lock",
|
|
"physical_pin": {
|
|
"id": 315,
|
|
"name": "probe84",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_broadcast",
|
|
"physical_pin": {
|
|
"id": 316,
|
|
"name": "probe85",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_fragment",
|
|
"physical_pin": {
|
|
"id": 317,
|
|
"name": "probe86",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_0",
|
|
"physical_pin": {
|
|
"id": 318,
|
|
"name": "probe87",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_10",
|
|
"physical_pin": {
|
|
"id": 328,
|
|
"name": "probe97",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_11",
|
|
"physical_pin": {
|
|
"id": 329,
|
|
"name": "probe98",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_12",
|
|
"physical_pin": {
|
|
"id": 330,
|
|
"name": "probe99",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_13",
|
|
"physical_pin": {
|
|
"id": 331,
|
|
"name": "probe100",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_14",
|
|
"physical_pin": {
|
|
"id": 332,
|
|
"name": "probe101",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_15",
|
|
"physical_pin": {
|
|
"id": 333,
|
|
"name": "probe102",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_16",
|
|
"physical_pin": {
|
|
"id": 334,
|
|
"name": "probe103",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_17",
|
|
"physical_pin": {
|
|
"id": 335,
|
|
"name": "probe104",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_18",
|
|
"physical_pin": {
|
|
"id": 336,
|
|
"name": "probe105",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_19",
|
|
"physical_pin": {
|
|
"id": 337,
|
|
"name": "probe106",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_1",
|
|
"physical_pin": {
|
|
"id": 319,
|
|
"name": "probe88",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_2",
|
|
"physical_pin": {
|
|
"id": 320,
|
|
"name": "probe89",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_3",
|
|
"physical_pin": {
|
|
"id": 321,
|
|
"name": "probe90",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_4",
|
|
"physical_pin": {
|
|
"id": 322,
|
|
"name": "probe91",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_5",
|
|
"physical_pin": {
|
|
"id": 323,
|
|
"name": "probe92",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_6",
|
|
"physical_pin": {
|
|
"id": 324,
|
|
"name": "probe93",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_7",
|
|
"physical_pin": {
|
|
"id": 325,
|
|
"name": "probe94",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_8",
|
|
"physical_pin": {
|
|
"id": 326,
|
|
"name": "probe95",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_9",
|
|
"physical_pin": {
|
|
"id": 327,
|
|
"name": "probe96",
|
|
"leftBit": 0,
|
|
"width": 2
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_0",
|
|
"physical_pin": {
|
|
"id": 338,
|
|
"name": "probe107",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_1",
|
|
"physical_pin": {
|
|
"id": 339,
|
|
"name": "probe108",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_10",
|
|
"physical_pin": {
|
|
"id": 348,
|
|
"name": "probe117",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_11",
|
|
"physical_pin": {
|
|
"id": 349,
|
|
"name": "probe118",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_12",
|
|
"physical_pin": {
|
|
"id": 350,
|
|
"name": "probe119",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_13",
|
|
"physical_pin": {
|
|
"id": 351,
|
|
"name": "probe120",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_14",
|
|
"physical_pin": {
|
|
"id": 352,
|
|
"name": "probe121",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_15",
|
|
"physical_pin": {
|
|
"id": 353,
|
|
"name": "probe122",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_16",
|
|
"physical_pin": {
|
|
"id": 354,
|
|
"name": "probe123",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_17",
|
|
"physical_pin": {
|
|
"id": 355,
|
|
"name": "probe124",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_18",
|
|
"physical_pin": {
|
|
"id": 356,
|
|
"name": "probe125",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_19",
|
|
"physical_pin": {
|
|
"id": 357,
|
|
"name": "probe126",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_2",
|
|
"physical_pin": {
|
|
"id": 340,
|
|
"name": "probe109",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_3",
|
|
"physical_pin": {
|
|
"id": 341,
|
|
"name": "probe110",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_4",
|
|
"physical_pin": {
|
|
"id": 342,
|
|
"name": "probe111",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_5",
|
|
"physical_pin": {
|
|
"id": 343,
|
|
"name": "probe112",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_6",
|
|
"physical_pin": {
|
|
"id": 344,
|
|
"name": "probe113",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_7",
|
|
"physical_pin": {
|
|
"id": 345,
|
|
"name": "probe114",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_8",
|
|
"physical_pin": {
|
|
"id": 346,
|
|
"name": "probe115",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_framing_err_valid_9",
|
|
"physical_pin": {
|
|
"id": 347,
|
|
"name": "probe116",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_got_signal_os",
|
|
"physical_pin": {
|
|
"id": 358,
|
|
"name": "probe127",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_hi_ber",
|
|
"physical_pin": {
|
|
"id": 359,
|
|
"name": "probe128",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_inrangeerr",
|
|
"physical_pin": {
|
|
"id": 360,
|
|
"name": "probe129",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_internal_local_fault",
|
|
"physical_pin": {
|
|
"id": 361,
|
|
"name": "probe130",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_jabber",
|
|
"physical_pin": {
|
|
"id": 362,
|
|
"name": "probe131",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_local_fault",
|
|
"physical_pin": {
|
|
"id": 363,
|
|
"name": "probe132",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_err",
|
|
"physical_pin": {
|
|
"id": 364,
|
|
"name": "probe133",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_len_err",
|
|
"physical_pin": {
|
|
"id": 365,
|
|
"name": "probe134",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_mf_repeat_err",
|
|
"physical_pin": {
|
|
"id": 366,
|
|
"name": "probe135",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_misaligned",
|
|
"physical_pin": {
|
|
"id": 367,
|
|
"name": "probe136",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_multicast",
|
|
"physical_pin": {
|
|
"id": 368,
|
|
"name": "probe137",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_oversize",
|
|
"physical_pin": {
|
|
"id": 369,
|
|
"name": "probe138",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1024_1518_bytes",
|
|
"physical_pin": {
|
|
"id": 375,
|
|
"name": "probe144",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_128_255_bytes",
|
|
"physical_pin": {
|
|
"id": 372,
|
|
"name": "probe141",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1519_1522_bytes",
|
|
"physical_pin": {
|
|
"id": 376,
|
|
"name": "probe145",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1523_1548_bytes",
|
|
"physical_pin": {
|
|
"id": 377,
|
|
"name": "probe146",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_1549_2047_bytes",
|
|
"physical_pin": {
|
|
"id": 378,
|
|
"name": "probe147",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_2048_4095_bytes",
|
|
"physical_pin": {
|
|
"id": 379,
|
|
"name": "probe148",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_256_511_bytes",
|
|
"physical_pin": {
|
|
"id": 373,
|
|
"name": "probe142",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_4096_8191_bytes",
|
|
"physical_pin": {
|
|
"id": 380,
|
|
"name": "probe149",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_512_1023_bytes",
|
|
"physical_pin": {
|
|
"id": 374,
|
|
"name": "probe143",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_64_bytes",
|
|
"physical_pin": {
|
|
"id": 370,
|
|
"name": "probe139",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_65_127_bytes",
|
|
"physical_pin": {
|
|
"id": 371,
|
|
"name": "probe140",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_8192_9215_bytes",
|
|
"physical_pin": {
|
|
"id": 381,
|
|
"name": "probe150",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_bad_fcs",
|
|
"physical_pin": {
|
|
"id": 382,
|
|
"name": "probe151",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_large",
|
|
"physical_pin": {
|
|
"id": 383,
|
|
"name": "probe152",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_packet_small",
|
|
"physical_pin": {
|
|
"id": 384,
|
|
"name": "probe153",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause",
|
|
"physical_pin": {
|
|
"id": 385,
|
|
"name": "probe154",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta0",
|
|
"physical_pin": {
|
|
"id": 386,
|
|
"name": "probe155",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta1",
|
|
"physical_pin": {
|
|
"id": 387,
|
|
"name": "probe156",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta2",
|
|
"physical_pin": {
|
|
"id": 388,
|
|
"name": "probe157",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta3",
|
|
"physical_pin": {
|
|
"id": 389,
|
|
"name": "probe158",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta4",
|
|
"physical_pin": {
|
|
"id": 390,
|
|
"name": "probe159",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta5",
|
|
"physical_pin": {
|
|
"id": 391,
|
|
"name": "probe160",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta6",
|
|
"physical_pin": {
|
|
"id": 392,
|
|
"name": "probe161",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta7",
|
|
"physical_pin": {
|
|
"id": 393,
|
|
"name": "probe162",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_quanta8",
|
|
"physical_pin": {
|
|
"id": 394,
|
|
"name": "probe163",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_req",
|
|
"physical_pin": {
|
|
"id": 395,
|
|
"name": "probe164",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pause_valid",
|
|
"physical_pin": {
|
|
"id": 396,
|
|
"name": "probe165",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_demuxed",
|
|
"physical_pin": {
|
|
"id": 397,
|
|
"name": "probe166",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_0",
|
|
"physical_pin": {
|
|
"id": 398,
|
|
"name": "probe167",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_10",
|
|
"physical_pin": {
|
|
"id": 408,
|
|
"name": "probe177",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_11",
|
|
"physical_pin": {
|
|
"id": 409,
|
|
"name": "probe178",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_12",
|
|
"physical_pin": {
|
|
"id": 410,
|
|
"name": "probe179",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_13",
|
|
"physical_pin": {
|
|
"id": 411,
|
|
"name": "probe180",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_14",
|
|
"physical_pin": {
|
|
"id": 412,
|
|
"name": "probe181",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_15",
|
|
"physical_pin": {
|
|
"id": 413,
|
|
"name": "probe182",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_16",
|
|
"physical_pin": {
|
|
"id": 414,
|
|
"name": "probe183",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_17",
|
|
"physical_pin": {
|
|
"id": 415,
|
|
"name": "probe184",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_18",
|
|
"physical_pin": {
|
|
"id": 416,
|
|
"name": "probe185",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_19",
|
|
"physical_pin": {
|
|
"id": 417,
|
|
"name": "probe186",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_1",
|
|
"physical_pin": {
|
|
"id": 399,
|
|
"name": "probe168",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_2",
|
|
"physical_pin": {
|
|
"id": 400,
|
|
"name": "probe169",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_3",
|
|
"physical_pin": {
|
|
"id": 401,
|
|
"name": "probe170",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_4",
|
|
"physical_pin": {
|
|
"id": 402,
|
|
"name": "probe171",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_5",
|
|
"physical_pin": {
|
|
"id": 403,
|
|
"name": "probe172",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_6",
|
|
"physical_pin": {
|
|
"id": 404,
|
|
"name": "probe173",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_7",
|
|
"physical_pin": {
|
|
"id": 405,
|
|
"name": "probe174",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_8",
|
|
"physical_pin": {
|
|
"id": 406,
|
|
"name": "probe175",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_pcsl_number_9",
|
|
"physical_pin": {
|
|
"id": 407,
|
|
"name": "probe176",
|
|
"leftBit": 0,
|
|
"width": 5
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_received_local_fault",
|
|
"physical_pin": {
|
|
"id": 418,
|
|
"name": "probe187",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_remote_fault",
|
|
"physical_pin": {
|
|
"id": 419,
|
|
"name": "probe188",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_status",
|
|
"physical_pin": {
|
|
"id": 420,
|
|
"name": "probe189",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_stomped_fcs",
|
|
"physical_pin": {
|
|
"id": 421,
|
|
"name": "probe190",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_synced",
|
|
"physical_pin": {
|
|
"id": 422,
|
|
"name": "probe191",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_synced_err",
|
|
"physical_pin": {
|
|
"id": 423,
|
|
"name": "probe192",
|
|
"leftBit": 0,
|
|
"width": 20
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_test_pattern_mismatch",
|
|
"physical_pin": {
|
|
"id": 424,
|
|
"name": "probe193",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_toolong",
|
|
"physical_pin": {
|
|
"id": 425,
|
|
"name": "probe194",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_bytes",
|
|
"physical_pin": {
|
|
"id": 426,
|
|
"name": "probe195",
|
|
"leftBit": 0,
|
|
"width": 7
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_good_bytes",
|
|
"physical_pin": {
|
|
"id": 427,
|
|
"name": "probe196",
|
|
"leftBit": 0,
|
|
"width": 14
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_good_packets",
|
|
"physical_pin": {
|
|
"id": 428,
|
|
"name": "probe197",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_total_packets",
|
|
"physical_pin": {
|
|
"id": 429,
|
|
"name": "probe198",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_truncated",
|
|
"physical_pin": {
|
|
"id": 430,
|
|
"name": "probe199",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_undersize",
|
|
"physical_pin": {
|
|
"id": 431,
|
|
"name": "probe200",
|
|
"leftBit": 0,
|
|
"width": 3
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_unicast",
|
|
"physical_pin": {
|
|
"id": 432,
|
|
"name": "probe201",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_user_pause",
|
|
"physical_pin": {
|
|
"id": 433,
|
|
"name": "probe202",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "stat_rx_vlan",
|
|
"physical_pin": {
|
|
"id": 434,
|
|
"name": "probe203",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_4_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "cmac_axis_rx",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 435,
|
|
"name": "probe204",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TKEEP",
|
|
"physical_pin": {
|
|
"id": 436,
|
|
"name": "probe205",
|
|
"leftBit": 0,
|
|
"width": 64
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 439,
|
|
"name": "probe208",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 437,
|
|
"name": "probe206",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 438,
|
|
"name": "probe207",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "SLOT_5_AXIS",
|
|
"vlnv": "xilinx.com:interface:axis:1.0",
|
|
"connectedBus": "unpacker_m_axis",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "TDATA",
|
|
"physical_pin": {
|
|
"id": 440,
|
|
"name": "probe209",
|
|
"leftBit": 0,
|
|
"width": 512
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TLAST",
|
|
"physical_pin": {
|
|
"id": 443,
|
|
"name": "probe212",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TUSER",
|
|
"physical_pin": {
|
|
"id": 441,
|
|
"name": "probe210",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
},
|
|
{
|
|
"logical_port": "TVALID",
|
|
"physical_pin": {
|
|
"id": 442,
|
|
"name": "probe211",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"native_ports": [
|
|
{
|
|
"name": "probe0",
|
|
"connectedBus": "cmac_usplus_i_gt_powergoodout",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe0",
|
|
"physical_pin": {
|
|
"id": 231,
|
|
"name": "probe0",
|
|
"leftBit": 0,
|
|
"width": 4
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe10",
|
|
"connectedBus": "rx_fifo_wr_data_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe10",
|
|
"physical_pin": {
|
|
"id": 241,
|
|
"name": "probe10",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe11",
|
|
"connectedBus": "ETH_regs_prog_full_on",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe11",
|
|
"physical_pin": {
|
|
"id": 242,
|
|
"name": "probe11",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe12",
|
|
"connectedBus": "ETH_regs_prog_full_off",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe12",
|
|
"physical_pin": {
|
|
"id": 243,
|
|
"name": "probe12",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe13",
|
|
"connectedBus": "eth_frame_packer_i_tx_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe13",
|
|
"physical_pin": {
|
|
"id": 244,
|
|
"name": "probe13",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe14",
|
|
"connectedBus": "eth_flowctrl_rx_0_rx_pause_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe14",
|
|
"physical_pin": {
|
|
"id": 245,
|
|
"name": "probe14",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe15",
|
|
"connectedBus": "eth_flowctrl_rx_0_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe15",
|
|
"physical_pin": {
|
|
"id": 246,
|
|
"name": "probe15",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe16",
|
|
"connectedBus": "cmac_usplus_i_stat_rx_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe16",
|
|
"physical_pin": {
|
|
"id": 247,
|
|
"name": "probe16",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe17",
|
|
"connectedBus": "cmac_usplus_i_stat_rx_pause_quanta8",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe17",
|
|
"physical_pin": {
|
|
"id": 248,
|
|
"name": "probe17",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe18",
|
|
"connectedBus": "eth_frame_unpacker_i_rx_frame_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe18",
|
|
"physical_pin": {
|
|
"id": 249,
|
|
"name": "probe18",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe19",
|
|
"connectedBus": "eth_flowctrl_tx_i_tx_pause_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe19",
|
|
"physical_pin": {
|
|
"id": 250,
|
|
"name": "probe19",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe1",
|
|
"connectedBus": "packer_underrun_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe1",
|
|
"physical_pin": {
|
|
"id": 232,
|
|
"name": "probe1",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe2",
|
|
"connectedBus": "rx_fifo_overflow",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe2",
|
|
"physical_pin": {
|
|
"id": 233,
|
|
"name": "probe2",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe3",
|
|
"connectedBus": "unpacker_rx_frame_err_cnt",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe3",
|
|
"physical_pin": {
|
|
"id": 234,
|
|
"name": "probe3",
|
|
"leftBit": 0,
|
|
"width": 32
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe4",
|
|
"connectedBus": "eth_regs_dest_addr",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe4",
|
|
"physical_pin": {
|
|
"id": 235,
|
|
"name": "probe4",
|
|
"leftBit": 0,
|
|
"width": 48
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe5",
|
|
"connectedBus": "eth_regs_source_addr",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe5",
|
|
"physical_pin": {
|
|
"id": 236,
|
|
"name": "probe5",
|
|
"leftBit": 0,
|
|
"width": 48
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe6",
|
|
"connectedBus": "eth_regs_EtherType",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe6",
|
|
"physical_pin": {
|
|
"id": 237,
|
|
"name": "probe6",
|
|
"leftBit": 0,
|
|
"width": 16
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe7",
|
|
"connectedBus": "prog_full_manual",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe7",
|
|
"physical_pin": {
|
|
"id": 238,
|
|
"name": "probe7",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe8",
|
|
"connectedBus": "ctl_tx_resend_pause",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe8",
|
|
"physical_pin": {
|
|
"id": 239,
|
|
"name": "probe8",
|
|
"leftBit": 0,
|
|
"width": 1
|
|
}
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"name": "probe9",
|
|
"connectedBus": "ctl_tx_pause_req",
|
|
"protocol": "PROBE",
|
|
"port_maps": [
|
|
{
|
|
"logical_port": "probe9",
|
|
"physical_pin": {
|
|
"id": 240,
|
|
"name": "probe9",
|
|
"leftBit": 0,
|
|
"width": 9
|
|
}
|
|
}
|
|
]
|
|
}
|
|
]
|
|
}
|
|
]
|
|
}
|
|
]
|
|
}
|
|
} |