moving repo from git to local repo
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#####################################
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#
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# VCU128 Rev1.0 XDC
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# Date: 01/24/2018
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#
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####################################
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###################################
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create_clock -period 6.40 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
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create_clock -period 6.40 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
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create_clock -period 6.40 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
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create_clock -period 6.40 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
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### J79
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set_property PACKAGE_PIN L33 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 CLK0_N
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set_property PACKAGE_PIN L32 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 CLK0_P
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set_property PACKAGE_PIN G42 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131
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set_property PACKAGE_PIN G41 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131
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set_property PACKAGE_PIN F40 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131
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set_property PACKAGE_PIN F39 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131
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set_property PACKAGE_PIN E42 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131
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set_property PACKAGE_PIN E41 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131
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set_property PACKAGE_PIN D40 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131
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set_property PACKAGE_PIN D39 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131
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set_property PACKAGE_PIN H35 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131
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set_property PACKAGE_PIN H34 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131
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set_property PACKAGE_PIN G37 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131
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set_property PACKAGE_PIN G36 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131
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set_property PACKAGE_PIN F35 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131
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set_property PACKAGE_PIN F34 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131
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set_property PACKAGE_PIN E37 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131
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set_property PACKAGE_PIN E36 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_MODPRSL_LS"] ;#
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### J78
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set_property PACKAGE_PIN R33 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 - MGTREFCLK0N_130 CLK1_N
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set_property PACKAGE_PIN R32 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130 CLK1_P
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# set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130
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# set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130
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set_property PACKAGE_PIN L42 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
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set_property PACKAGE_PIN L41 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
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set_property PACKAGE_PIN K40 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
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set_property PACKAGE_PIN K39 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
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set_property PACKAGE_PIN J42 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
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set_property PACKAGE_PIN J41 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
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set_property PACKAGE_PIN H40 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
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set_property PACKAGE_PIN H39 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130
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set_property PACKAGE_PIN M35 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
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set_property PACKAGE_PIN M34 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
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set_property PACKAGE_PIN L37 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
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set_property PACKAGE_PIN L36 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
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set_property PACKAGE_PIN K35 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
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set_property PACKAGE_PIN K34 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
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set_property PACKAGE_PIN J37 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
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set_property PACKAGE_PIN J36 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130
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set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_MODPRSL_LS"] ;#
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|
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### J77
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set_property PACKAGE_PIN W33 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129 CLK3_N
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set_property PACKAGE_PIN W32 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129 CLK3_P
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# set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129
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# set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129
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set_property PACKAGE_PIN R42 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
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set_property PACKAGE_PIN R41 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
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set_property PACKAGE_PIN P40 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
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set_property PACKAGE_PIN P39 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
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set_property PACKAGE_PIN N42 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
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set_property PACKAGE_PIN N41 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
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set_property PACKAGE_PIN M40 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
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set_property PACKAGE_PIN M39 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129
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set_property PACKAGE_PIN T35 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
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set_property PACKAGE_PIN T34 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
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set_property PACKAGE_PIN R37 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
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set_property PACKAGE_PIN R36 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
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set_property PACKAGE_PIN P35 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
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set_property PACKAGE_PIN P34 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
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set_property PACKAGE_PIN N37 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
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set_property PACKAGE_PIN N36 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129
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set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_MODPRSL_LS"] ;#
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# set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;
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# set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;
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### J76
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set_property PACKAGE_PIN AB35 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 128 - MGTREFCLK0N_128 CLK2_N
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set_property PACKAGE_PIN AB34 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 128 - MGTREFCLK0P_128 CLK2_P
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set_property PACKAGE_PIN W42 [get_ports "QSFP1_RX1_N"] ;# Bank 128 - MGTYRXN0_128
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set_property PACKAGE_PIN W41 [get_ports "QSFP1_RX1_P"] ;# Bank 128 - MGTYRXP0_128
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set_property PACKAGE_PIN V40 [get_ports "QSFP1_RX2_N"] ;# Bank 128 - MGTYRXN1_128
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set_property PACKAGE_PIN V39 [get_ports "QSFP1_RX2_P"] ;# Bank 128 - MGTYRXP1_128
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set_property PACKAGE_PIN U42 [get_ports "QSFP1_RX3_N"] ;# Bank 128 - MGTYRXN2_128
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set_property PACKAGE_PIN U41 [get_ports "QSFP1_RX3_P"] ;# Bank 128 - MGTYRXP2_128
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set_property PACKAGE_PIN T40 [get_ports "QSFP1_RX4_N"] ;# Bank 128 - MGTYRXN3_128
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set_property PACKAGE_PIN T39 [get_ports "QSFP1_RX4_P"] ;# Bank 128 - MGTYRXP3_128
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set_property PACKAGE_PIN Y35 [get_ports "QSFP1_TX1_N"] ;# Bank 128 - MGTYTXN0_128
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set_property PACKAGE_PIN Y34 [get_ports "QSFP1_TX1_P"] ;# Bank 128 - MGTYTXP0_128
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set_property PACKAGE_PIN W37 [get_ports "QSFP1_TX2_N"] ;# Bank 128 - MGTYTXN1_128
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set_property PACKAGE_PIN W36 [get_ports "QSFP1_TX2_P"] ;# Bank 128 - MGTYTXP1_128
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set_property PACKAGE_PIN V35 [get_ports "QSFP1_TX3_N"] ;# Bank 128 - MGTYTXN2_128
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set_property PACKAGE_PIN V34 [get_ports "QSFP1_TX3_P"] ;# Bank 128 - MGTYTXP2_128
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set_property PACKAGE_PIN U37 [get_ports "QSFP1_TX4_N"] ;# Bank 128 - MGTYTXN3_128
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set_property PACKAGE_PIN U36 [get_ports "QSFP1_TX4_P"] ;# Bank 128 - MGTYTXP3_128
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set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_MODPRSL_LS"] ;#
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# set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;#
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@@ -0,0 +1,101 @@
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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#
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## mxfe
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#
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set_property -dict {PACKAGE_PIN AR24 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L14P_T2L_N2_GC_65 FMC2_LA17_CC_P D20
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set_property -dict {PACKAGE_PIN AR25 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L14N_T2L_N3_GC_65 FMC2_LA17_CC_N D21
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set_property -dict {PACKAGE_PIN AU25 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L11P_T1U_N8_GC_65 FMC2_LA18_CC_P C22
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set_property -dict {PACKAGE_PIN AU26 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L11N_T1U_N9_GC_65 FMC2_LA18_CC_N C23
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set_property -dict {PACKAGE_PIN AU28 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L10P_T1U_N6_QBC_AD4P_65 FMC2_LA20_P G21
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set_property -dict {PACKAGE_PIN AV28 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L10N_T1U_N7_QBC_AD4N_65 FMC2_LA20_N G22
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set_property -dict {PACKAGE_PIN BB24 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L2P_T0L_N2_65 FMC2_LA21_P H25
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set_property -dict {PACKAGE_PIN BB25 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L2N_T0L_N3_65 FMC2_LA21_N H26
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set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_n ] ; ## IO_L13N_T2L_N1_GC_QBC_65 FMC2_CLK1_M2C_N G3
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set_property -dict {PACKAGE_PIN AR27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_p ] ; ## IO_L13P_T2L_N0_GC_QBC_65 FMC2_CLK1_M2C_P G2
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set_property -dict {PACKAGE_PIN AK11 } [get_ports clkin8_n ] ; ## MGTREFCLK0N_224 FMC2_GBTCLK1_M2C_N B21
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set_property -dict {PACKAGE_PIN AK12 } [get_ports clkin8_p ] ; ## MGTREFCLK0P_224 FMC2_GBTCLK1_M2C_P B20
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set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_n ] ; ## IO_L11N_T1U_N9_GC_64 LA00_N_CC G7
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set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_p ] ; ## IO_L11P_T1U_N8_GC_64 LA00_P_CC G6
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set_property -dict {PACKAGE_PIN AH11 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_225 FMC2_GBTCLK0_M2C_C_N D5
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set_property -dict {PACKAGE_PIN AH12 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_225 FMC2_GBTCLK0_M2C_C_P D4
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set_property -quiet -dict {PACKAGE_PIN AP3 } [get_ports rx_data_n[2] ] ; ## MGTHRXN2_225 FPGA_SERDIN_0_N FMC2_DP2_M2C_n A7
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set_property -quiet -dict {PACKAGE_PIN AP4 } [get_ports rx_data_p[2] ] ; ## MGTHRXP2_225 FPGA_SERDIN_0_P FMC2_DP2_M2C_P A6
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set_property -quiet -dict {PACKAGE_PIN AR1 } [get_ports rx_data_n[0] ] ; ## MGTHRXN1_225 FPGA_SERDIN_1_N FMC2_DP0_M2C_n C7
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||||
set_property -quiet -dict {PACKAGE_PIN AR2 } [get_ports rx_data_p[0] ] ; ## MGTHRXP1_225 FPGA_SERDIN_1_P FMC2_DP0_M2C_P C6
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||||
set_property -quiet -dict {PACKAGE_PIN AU1 } [get_ports rx_data_n[7] ] ; ## MGTHRXN3_224 FPGA_SERDIN_2_N FMC2_DP7_M2C_N B13
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set_property -quiet -dict {PACKAGE_PIN AU2 } [get_ports rx_data_p[7] ] ; ## MGTHRXP3_224 FPGA_SERDIN_2_P FMC2_DP7_M2C_P B12
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||||
set_property -quiet -dict {PACKAGE_PIN AW1 } [get_ports rx_data_n[6] ] ; ## MGTHRXN1_224 FPGA_SERDIN_3_N FMC2_DP6_M2C_N B17
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||||
set_property -quiet -dict {PACKAGE_PIN AW2 } [get_ports rx_data_p[6] ] ; ## MGTHRXP1_224 FPGA_SERDIN_3_P FMC2_DP6_M2C_P B16
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||||
set_property -quiet -dict {PACKAGE_PIN BA1 } [get_ports rx_data_n[5] ] ; ## MGTHRXN0_224 FPGA_SERDIN_4_N FMC2_DP5_M2C_N A19
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||||
set_property -quiet -dict {PACKAGE_PIN BA2 } [get_ports rx_data_p[5] ] ; ## MGTHRXP0_224 FPGA_SERDIN_4_P FMC2_DP5_M2C_P A18
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||||
set_property -quiet -dict {PACKAGE_PIN AV3 } [get_ports rx_data_n[4] ] ; ## MGTHRXN2_224 FPGA_SERDIN_5_N FMC2_DP4_M2C_N A15
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||||
set_property -quiet -dict {PACKAGE_PIN AV4 } [get_ports rx_data_p[4] ] ; ## MGTHRXP2_224 FPGA_SERDIN_5_P FMC2_DP4_M2C_P A14
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||||
set_property -quiet -dict {PACKAGE_PIN AT3 } [get_ports rx_data_n[3] ] ; ## MGTHRXN0_225 FPGA_SERDIN_6_N FMC2_DP3_M2C_n A11
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||||
set_property -quiet -dict {PACKAGE_PIN AT4 } [get_ports rx_data_p[3] ] ; ## MGTHRXP0_225 FPGA_SERDIN_6_P FMC2_DP3_M2C_P A10
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||||
set_property -quiet -dict {PACKAGE_PIN AN1 } [get_ports rx_data_n[1] ] ; ## MGTHRXN3_225 FPGA_SERDIN_7_N FMC2_DP1_M2C_n A3
|
||||
set_property -quiet -dict {PACKAGE_PIN AN2 } [get_ports rx_data_p[1] ] ; ## MGTHRXP3_225 FPGA_SERDIN_7_P FMC2_DP1_M2C_P A2
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||||
set_property -quiet -dict {PACKAGE_PIN AP7 } [get_ports tx_data_n[0] ] ; ## MGTHTXN1_225 FPGA_SERDOUT_0_N FMC2_DP0_C2M_n C3
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||||
set_property -quiet -dict {PACKAGE_PIN AP8 } [get_ports tx_data_p[0] ] ; ## MGTHTXP1_225 FPGA_SERDOUT_0_P FMC2_DP0_C2M_P C2
|
||||
set_property -quiet -dict {PACKAGE_PIN AN5 } [get_ports tx_data_n[2] ] ; ## MGTHTXN2_225 FPGA_SERDOUT_1_N FMC2_DP2_C2M_n A27
|
||||
set_property -quiet -dict {PACKAGE_PIN AN6 } [get_ports tx_data_p[2] ] ; ## MGTHTXP2_225 FPGA_SERDOUT_1_P FMC2_DP2_C2M_P A26
|
||||
set_property -quiet -dict {PACKAGE_PIN AT7 } [get_ports tx_data_n[7] ] ; ## MGTHTXN3_224 FPGA_SERDOUT_2_N FMC2_DP7_C2M_N B33
|
||||
set_property -quiet -dict {PACKAGE_PIN AT8 } [get_ports tx_data_p[7] ] ; ## MGTHTXP3_224 FPGA_SERDOUT_2_P FMC2_DP7_C2M_P B32
|
||||
set_property -quiet -dict {PACKAGE_PIN AW5 } [get_ports tx_data_n[6] ] ; ## MGTHTXN1_224 FPGA_SERDOUT_3_N FMC2_DP6_C2M_N B37
|
||||
set_property -quiet -dict {PACKAGE_PIN AW6 } [get_ports tx_data_p[6] ] ; ## MGTHTXP1_224 FPGA_SERDOUT_3_P FMC2_DP6_C2M_P B36
|
||||
set_property -quiet -dict {PACKAGE_PIN AM7 } [get_ports tx_data_n[1] ] ; ## MGTHTXN3_225 FPGA_SERDOUT_4_N FMC2_DP1_C2M_n A23
|
||||
set_property -quiet -dict {PACKAGE_PIN AM8 } [get_ports tx_data_p[1] ] ; ## MGTHTXP3_225 FPGA_SERDOUT_4_P FMC2_DP1_C2M_P A22
|
||||
set_property -quiet -dict {PACKAGE_PIN AY3 } [get_ports tx_data_n[5] ] ; ## MGTHTXN0_224 FPGA_SERDOUT_5_N FMC2_DP5_C2M_N A39
|
||||
set_property -quiet -dict {PACKAGE_PIN AY4 } [get_ports tx_data_p[5] ] ; ## MGTHTXP0_224 FPGA_SERDOUT_5_P FMC2_DP5_C2M_P A38
|
||||
set_property -quiet -dict {PACKAGE_PIN AU5 } [get_ports tx_data_n[4] ] ; ## MGTHTXN2_224 FPGA_SERDOUT_6_N FMC2_DP4_C2M_N A35
|
||||
set_property -quiet -dict {PACKAGE_PIN AU6 } [get_ports tx_data_p[4] ] ; ## MGTHTXP2_224 FPGA_SERDOUT_6_P FMC2_DP4_C2M_P A34
|
||||
set_property -quiet -dict {PACKAGE_PIN AR5 } [get_ports tx_data_n[3] ] ; ## MGTHTXN0_225 FPGA_SERDOUT_7_N FMC2_DP3_C2M_n A31
|
||||
set_property -quiet -dict {PACKAGE_PIN AR6 } [get_ports tx_data_p[3] ] ; ## MGTHTXP0_225 FPGA_SERDOUT_7_P FMC2_DP3_C2M_P A30
|
||||
set_property -quiet -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## IO_L7N_T1L_N1_QBC_AD13N_64 FMC2_LA02_n H8
|
||||
set_property -quiet -dict {PACKAGE_PIN AU23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## IO_L7P_T1L_N0_QBC_AD13P_64 FMC2_LA02_P H7
|
||||
set_property -quiet -dict {PACKAGE_PIN AW19 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## IO_L9N_T1L_N5_AD12N_64 FMC2_LA03_n G10
|
||||
set_property -quiet -dict {PACKAGE_PIN AW20 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## IO_L9P_T1L_N4_AD12P_64 FMC2_LA03_P G9
|
||||
set_property -quiet -dict {PACKAGE_PIN AV19 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## IO_L12N_T1U_N11_GC_64 FMC2_LA01_CC_n D9
|
||||
set_property -quiet -dict {PACKAGE_PIN AU20 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## IO_L12P_T1U_N10_GC_64 FMC2_LA01_CC_P D8
|
||||
set_property -quiet -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## IO_L2N_T0L_N3_64 FMC2_LA06_n C11
|
||||
set_property -quiet -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## IO_L2P_T0L_N2_64 FMC2_LA06_P C10
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L20P_T3L_N2_AD1P_64 FMC2_LA15_P H19
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L20N_T3L_N3_AD1N_64 FMC2_LA15_N H20
|
||||
set_property -dict {PACKAGE_PIN AV27 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L9P_T1L_N4_AD12P_65 FMC2_LA19_P H22
|
||||
set_property -dict {PACKAGE_PIN AW27 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L9N_T1L_N5_AD12N_65 FMC2_LA19_N H23
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L23P_T3U_N8_64 FMC2_LA13_P D17
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L23N_T3U_N9_64 FMC2_LA13_N D18
|
||||
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_64 FMC2_LA14_P C18
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_64 FMC2_LA14_N C19
|
||||
set_property -dict {PACKAGE_PIN AL22 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L21P_T3L_N4_AD8P_64 FMC2_LA16_P G18
|
||||
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L21N_T3L_N5_AD8N_64 FMC2_LA16_N G19
|
||||
set_property -dict {PACKAGE_PIN BB26 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_65 FMC2_LA22_N G25
|
||||
set_property -dict {PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L22N_T3U_N7_DBC_AD0N_64 FMC2_LA11_N H17
|
||||
set_property -dict {PACKAGE_PIN BA21 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L3N_T0L_N5_AD15N_64 FMC2_LA07_N H14
|
||||
set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L5P_T0U_N8_AD14P_64 FMC2_LA08_P G12
|
||||
set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L5N_T0U_N9_AD14N_64 FMC2_LA08_N G13
|
||||
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L3P_T0L_N4_AD15P_64 FMC2_LA07_P H13
|
||||
set_property -dict {PACKAGE_PIN BA18 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L6P_T0U_N10_AD6P_64 FMC2_LA10_P C14
|
||||
set_property -dict {PACKAGE_PIN BB18 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L6N_T0U_N11_AD6N_64 FMC2_LA10_N C15
|
||||
set_property -dict {PACKAGE_PIN AY19 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L10P_T1U_N6_QBC_AD4P_64 FMC2_LA05_P D11
|
||||
set_property -dict {PACKAGE_PIN AY18 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L10N_T1U_N7_QBC_AD4N_64 FMC2_LA05_N D12
|
||||
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L16P_T2U_N6_QBC_AD3P_64 FMC2_LA04_P H10
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L16N_T2U_N7_QBC_AD3N_64 FMC2_LA04_N H11
|
||||
set_property -dict {PACKAGE_PIN BA23 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L1P_T0L_N0_DBC_64 FMC2_LA12_P G15
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L22P_T3U_N6_DBC_AD0P_64 FMC2_LA11_P H16
|
||||
set_property -dict {PACKAGE_PIN BB23 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L1N_T0L_N1_DBC_64 FMC2_LA12_N G16
|
||||
set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_64 FMC2_CLK0_M2C_n H5
|
||||
set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_64 FMC2_CLK0_M2C_P H4
|
||||
set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_64 FMC2_LA09_P D14
|
||||
set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_64 FMC2_LA09_N D15
|
||||
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports pll_scl ] ; ## IO_L12N_AD8N_91
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports pll_sda ] ; ## IO_L12N_AD8P_91
|
||||
|
||||
@@ -0,0 +1,153 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]; # 775.194 MHz ????
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 2.66 [get_ports clkin6_p];# 2.58 2.66 ns = 375MHz
|
||||
create_clock -name rx_device_clk -period 2.66 [get_ports clkin10_p];#
|
||||
create_clock -name clkin8 -period 2.0 [get_ports clkin8_p]
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
|
||||
# Define SPI clock
|
||||
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
|
||||
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
|
||||
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks tx_device_clk]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_1]
|
||||
set_false_path -from [get_clocks clk_pl_1] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks clkin8] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks refclk] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks refclk] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+5501
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,651 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: raw_eth_test
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2023.2
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
|
||||
|
||||
} else {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source raw_eth_test_script.tcl
|
||||
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:cmac_usplus:3.1\
|
||||
xilinx.com:ip:system_ila:1.1\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:c_counter_binary:12.0\
|
||||
xilinx.com:ip:smartconnect:1.0\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
user:user:axi_regs_32:1.0\
|
||||
xilinx.com:ip:xlslice:1.0\
|
||||
xilinx.com:ip:xlconcat:2.1\
|
||||
xilinx.com:ip:xpm_cdc_gen:1.0\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
eth_flowctrl_rx\
|
||||
eth_frame_packer\
|
||||
eth_flowctrl_tx\
|
||||
eth_frame_unpacker\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
# Hierarchical cell: ETH_regs
|
||||
proc create_hier_cell_ETH_regs { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O -from 47 -to 0 dest_addr
|
||||
create_bd_pin -dir O -from 47 -to 0 source_addr
|
||||
create_bd_pin -dir O -from 15 -to 0 EtherType
|
||||
create_bd_pin -dir I cmac_clk
|
||||
create_bd_pin -dir I aclk
|
||||
create_bd_pin -dir I aresetn
|
||||
create_bd_pin -dir O -from 0 -to 0 prog_full_manual
|
||||
create_bd_pin -dir O -from 31 -to 0 prog_full_on
|
||||
create_bd_pin -dir O -from 31 -to 0 prog_full_off
|
||||
create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt
|
||||
create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt
|
||||
|
||||
# Create instance: axi_regs_32_0, and set properties
|
||||
set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ]
|
||||
|
||||
# Create instance: xlslice_0, and set properties
|
||||
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
||||
set_property CONFIG.DIN_FROM {15} $xlslice_0
|
||||
|
||||
|
||||
# Create instance: xlconcat_0, and set properties
|
||||
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.IN0_WIDTH {32} \
|
||||
CONFIG.IN1_WIDTH {16} \
|
||||
] $xlconcat_0
|
||||
|
||||
|
||||
# Create instance: xlconcat_1, and set properties
|
||||
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.IN0_WIDTH {32} \
|
||||
CONFIG.IN1_WIDTH {16} \
|
||||
] $xlconcat_1
|
||||
|
||||
|
||||
# Create instance: xlslice_1, and set properties
|
||||
set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
|
||||
set_property CONFIG.DIN_FROM {15} $xlslice_1
|
||||
|
||||
|
||||
# Create instance: xlslice_2, and set properties
|
||||
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
|
||||
set_property CONFIG.DIN_FROM {15} $xlslice_2
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_0, and set properties
|
||||
set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {48} \
|
||||
] $xpm_cdc_gen_0
|
||||
|
||||
|
||||
# Create instance: const_1b0, and set properties
|
||||
set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ]
|
||||
set_property CONFIG.CONST_VAL {0} $const_1b0
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_1, and set properties
|
||||
set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {48} \
|
||||
] $xpm_cdc_gen_1
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_2, and set properties
|
||||
set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {16} \
|
||||
] $xpm_cdc_gen_2
|
||||
|
||||
|
||||
# Create instance: const_32b0, and set properties
|
||||
set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CONST_VAL {0} \
|
||||
CONFIG.CONST_WIDTH {32} \
|
||||
] $const_32b0
|
||||
|
||||
|
||||
# Create instance: xlslice_3, and set properties
|
||||
set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ]
|
||||
set_property CONFIG.DIN_FROM {0} $xlslice_3
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_3, and set properties
|
||||
set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {1} \
|
||||
] $xpm_cdc_gen_3
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_4, and set properties
|
||||
set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_4
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_5, and set properties
|
||||
set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_5
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_16, and set properties
|
||||
set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_16
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_17, and set properties
|
||||
set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_17
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_18, and set properties
|
||||
set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_18
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_19, and set properties
|
||||
set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_19
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_20, and set properties
|
||||
set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_20
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_21, and set properties
|
||||
set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_21
|
||||
|
||||
|
||||
# Create instance: xpm_cdc_gen_22, and set properties
|
||||
set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DEST_SYNC_FF {2} \
|
||||
CONFIG.SIM_ASSERT_CHK {false} \
|
||||
CONFIG.SRC_INPUT_REG {false} \
|
||||
CONFIG.WIDTH {32} \
|
||||
] $xpm_cdc_gen_22
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk]
|
||||
connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN]
|
||||
connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in]
|
||||
connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in]
|
||||
connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk]
|
||||
connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk]
|
||||
connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in]
|
||||
connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in]
|
||||
connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in]
|
||||
connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in]
|
||||
connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in]
|
||||
connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in]
|
||||
connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in]
|
||||
connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in]
|
||||
connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in]
|
||||
connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in]
|
||||
connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1]
|
||||
connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1]
|
||||
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in]
|
||||
connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in]
|
||||
connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr]
|
||||
connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in]
|
||||
connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in]
|
||||
connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr]
|
||||
connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in]
|
||||
connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in]
|
||||
connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in]
|
||||
connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType]
|
||||
connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual]
|
||||
connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on]
|
||||
connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off]
|
||||
connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in]
|
||||
connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: Ethernet
|
||||
proc create_hier_cell_Ethernet { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O -type clk axis_aclk
|
||||
create_bd_pin -dir O -from 0 -to 0 axis_aresetn
|
||||
create_bd_pin -dir I -type clk axil_clk
|
||||
create_bd_pin -dir I clk_100_reset
|
||||
create_bd_pin -dir I clk_100
|
||||
create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt
|
||||
create_bd_pin -dir I -type rst axil_resetn
|
||||
create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow
|
||||
|
||||
# Create instance: eth_flowctrl_rx_i, and set properties
|
||||
set block_name eth_flowctrl_rx
|
||||
set block_cell_name eth_flowctrl_rx_i
|
||||
if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $eth_flowctrl_rx_i eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: cmac_usplus_i, and set properties
|
||||
set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CMAC_CAUI4_MODE {1} \
|
||||
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
|
||||
CONFIG.ENABLE_AXI_INTERFACE {1} \
|
||||
CONFIG.ENABLE_PIPELINE_REG {1} \
|
||||
CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \
|
||||
CONFIG.GT_REF_CLK_FREQ {156.25} \
|
||||
CONFIG.RX_CHECK_ACK {0} \
|
||||
CONFIG.RX_FLOW_CONTROL {1} \
|
||||
CONFIG.TX_FLOW_CONTROL {1} \
|
||||
CONFIG.TX_SA_GPP {0x000000000000} \
|
||||
CONFIG.TX_SA_PPP {0x000000000000} \
|
||||
CONFIG.USER_INTERFACE {AXIS} \
|
||||
] $cmac_usplus_i
|
||||
|
||||
|
||||
# Create instance: eth_frame_packer_i, and set properties
|
||||
set block_name eth_frame_packer
|
||||
set block_cell_name eth_frame_packer_i
|
||||
if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $eth_frame_packer_i eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: eth_flowctrl_tx_i, and set properties
|
||||
set block_name eth_flowctrl_tx
|
||||
set block_cell_name eth_flowctrl_tx_i
|
||||
if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $eth_flowctrl_tx_i eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: eth_frame_unpacker_i, and set properties
|
||||
set block_name eth_frame_unpacker
|
||||
set block_cell_name eth_frame_unpacker_i
|
||||
if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $eth_frame_unpacker_i eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: system_ila_i, and set properties
|
||||
set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_MON_TYPE {MIX} \
|
||||
CONFIG.C_NUM_MONITOR_SLOTS {6} \
|
||||
CONFIG.C_NUM_OF_PROBES {20} \
|
||||
CONFIG.C_SLOT {5} \
|
||||
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
||||
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
||||
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
||||
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
||||
CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
||||
CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
||||
] $system_ila_i
|
||||
|
||||
|
||||
# Create instance: ETH_regs
|
||||
create_hier_cell_ETH_regs $hier_obj ETH_regs
|
||||
|
||||
# Create instance: rst_inv_i, and set properties
|
||||
set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $rst_inv_i
|
||||
|
||||
|
||||
# Create instance: counter_i, and set properties
|
||||
set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CE {true} \
|
||||
CONFIG.Fb_Latency_Configuration {Automatic} \
|
||||
CONFIG.Latency_Configuration {Automatic} \
|
||||
CONFIG.Load {false} \
|
||||
CONFIG.Load_Sense {Active_High} \
|
||||
CONFIG.Output_Width {32} \
|
||||
CONFIG.Restrict_Count {false} \
|
||||
CONFIG.SCLR {true} \
|
||||
CONFIG.SSET {false} \
|
||||
CONFIG.Sync_Threshold_Output {false} \
|
||||
] $counter_i
|
||||
|
||||
|
||||
# Create instance: smartcon_i, and set properties
|
||||
set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ]
|
||||
set_property -dict [list \
|
||||
CONFIG.NUM_MI {2} \
|
||||
CONFIG.NUM_SI {1} \
|
||||
] $smartcon_i
|
||||
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL]
|
||||
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI]
|
||||
connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis]
|
||||
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS]
|
||||
connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk]
|
||||
connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis]
|
||||
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS]
|
||||
connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx]
|
||||
connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS]
|
||||
connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI]
|
||||
connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS]
|
||||
connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off]
|
||||
connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on]
|
||||
connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk]
|
||||
connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn]
|
||||
connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk]
|
||||
connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset]
|
||||
connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in]
|
||||
connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn]
|
||||
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt]
|
||||
connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0]
|
||||
connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||||
connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins eth_flowctrl_rx_i/rx_pause] [get_bd_pins system_ila_i/probe16]
|
||||
connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8] [get_bd_pins system_ila_i/probe17]
|
||||
connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt]
|
||||
connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9]
|
||||
connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8]
|
||||
connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins eth_frame_packer_i/pause] [get_bd_pins system_ila_i/probe15]
|
||||
connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14]
|
||||
connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19]
|
||||
connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13]
|
||||
connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18]
|
||||
connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type]
|
||||
connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac]
|
||||
connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac]
|
||||
connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt]
|
||||
connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE]
|
||||
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR]
|
||||
connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual]
|
||||
connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset]
|
||||
connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
|
||||
proc available_tcl_procs { } {
|
||||
puts "##################################################################"
|
||||
puts "# Available Tcl procedures to recreate hierarchical blocks:"
|
||||
puts "#"
|
||||
puts "# create_hier_cell_Ethernet parentCell nameHier"
|
||||
puts "# create_hier_cell_ETH_regs parentCell nameHier"
|
||||
puts "#"
|
||||
puts "##################################################################"
|
||||
}
|
||||
|
||||
available_tcl_procs
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
package global_types is
|
||||
type data_vc1_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type data_vc2_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type mask_vcx_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type addr_si5341_type is array (511 downto 0) of std_logic_vector(15 downto 0);
|
||||
type data_si5341_type is array (511 downto 0) of std_logic_vector(7 downto 0);
|
||||
end global_types;
|
||||
package body global_types is
|
||||
end global_types;
|
||||
@@ -0,0 +1,305 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c is
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coafficien (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end entity i2c;
|
||||
|
||||
architecture translated of i2c is
|
||||
|
||||
component IOBUF
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
IO : inout std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component OBUFT
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component i2c_st
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end component;
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
function length_ct (int_length : integer) return positive is
|
||||
variable conv_length : std_logic_vector(9 downto 0);
|
||||
variable index : positive:= 1;
|
||||
begin
|
||||
conv_length := CONV_STD_LOGIC_VECTOR(int_length, 10);
|
||||
for i in 9 downto 1 loop
|
||||
index:= i;
|
||||
exit when conv_length(i) = '1';
|
||||
end loop;
|
||||
return index;
|
||||
end length_ct;
|
||||
|
||||
|
||||
|
||||
|
||||
signal cntr : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal cntr_length : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal scl_tick : std_logic;
|
||||
signal wrd_addr : std_logic_vector(7 downto 0);
|
||||
signal wrd_dat : std_logic_vector(7 downto 0);
|
||||
signal dev_addr_int : std_logic_vector(6 downto 0);
|
||||
signal ENAPH : std_logic;
|
||||
signal scl_cnt_en : std_logic;
|
||||
signal i2c_go : std_logic;
|
||||
signal sda_in : std_logic;
|
||||
signal sda_o : std_logic;
|
||||
signal scl_o : std_logic;
|
||||
signal wr_l_int : std_logic;
|
||||
signal port_switch : std_logic:= '0';
|
||||
signal sda_o_spd : std_logic;
|
||||
signal scl_o_spd : std_logic;
|
||||
signal GND : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
GND <= '0';
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- CLOCK DIVIDER SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
cntr_length <= CONV_STD_LOGIC_VECTOR(count_div, (length_ct(count_div)+1));
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr <= (others => '0') after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (scl_cnt_en = '1') then
|
||||
cntr <= cntr + 1 after 1 * sim_timescale;
|
||||
else
|
||||
cntr <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (cntr = cntr_length) then
|
||||
scl_tick <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- ADDRESS REGISTERS SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then wrd_addr <= ADDR_IN after 1 * sim_timescale;
|
||||
dev_addr_int <= DEV_ADDR after 1 * sim_timescale;
|
||||
wr_l_int <= WR_OP after 1 * sim_timescale;
|
||||
wrd_dat <= DAT_IN after 1 * sim_timescale;
|
||||
ENAPH <= AP_EN after 1 * sim_timescale;
|
||||
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then port_switch <= (DEV_ADDR(3) and not DEV_ADDR(2) and DEV_ADDR(1) and not DEV_ADDR(0)) after 1 * sim_timescale; -- "1010" (SPD)
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
-- send ack right back
|
||||
|
||||
if (RST = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then
|
||||
i2c_go <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (scl_cnt_en = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then ACK_L <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- I2C STATE MACHINE SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
MAIN_FSM : i2c_st
|
||||
port map(
|
||||
WRD_ADD => wrd_addr,
|
||||
WRD_DAT => wrd_dat,
|
||||
DEV_ADDR => dev_addr_int,
|
||||
CONTINUE => CONTINUE,
|
||||
ENAPH => ENAPH,
|
||||
WR_L => wr_l_int,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
SCL_TICK => scl_tick,
|
||||
I2C_GO => i2c_go,
|
||||
SDA_PIN => sda_in,
|
||||
|
||||
I2C_RDATA => I2C_RDATA,
|
||||
SDA => sda_o,
|
||||
SCL => scl_o,
|
||||
SCL_CNT_EN => scl_cnt_en,
|
||||
I2C_RDY => I2C_RDY,
|
||||
I2C_ACT => I2C_ACT,
|
||||
ACK_ERR => ACK_ERR
|
||||
);
|
||||
|
||||
|
||||
sda_o_spd <= sda_o;
|
||||
scl_o_spd <= scl_o;
|
||||
|
||||
--SDA_BUF: IOBUF
|
||||
-- port map
|
||||
-- (
|
||||
-- O => sda_in,
|
||||
-- IO => SDA,
|
||||
-- I => GND,
|
||||
-- T => sda_o_spd
|
||||
-- );
|
||||
|
||||
|
||||
sda_in <= I_SDA_I;
|
||||
O_SDA_O <= GND;
|
||||
O_SDA_T <= sda_o_spd;
|
||||
|
||||
--SCL_BUF: OBUFT
|
||||
-- port map
|
||||
-- (
|
||||
-- O => SCL,
|
||||
-- I => GND,
|
||||
-- T => scl_o_spd
|
||||
-- );
|
||||
|
||||
-- scl_in <= I_SCL_I
|
||||
O_SCL_O <= GND;
|
||||
O_SCL_T <= scl_o_spd;
|
||||
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,435 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller Top level
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c_st.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c_st is
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end entity i2c_st;
|
||||
|
||||
architecture translated of i2c_st is
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
---------------------------------------------------------------------
|
||||
type st_type is (idle, en_clk, start1, dev_id1, ack_id1, w_add, w_dat, ack_wr, ack_add, wait1,
|
||||
dis_clk1, start2, dev_id2, ack_id2, data, ack_rd, stop1, ack_rd_mult);
|
||||
|
||||
signal i2c_state : st_type:= idle;
|
||||
signal bit_cntr : std_logic_vector(2 downto 0);
|
||||
signal scl_en : std_logic;
|
||||
signal en_cntr : std_logic;
|
||||
signal cntr_done : std_logic;
|
||||
signal sda_int : std_logic;
|
||||
signal scl_int : std_logic;
|
||||
signal scl_cnt_en_int : std_logic;
|
||||
signal i2c_rdy_int : std_logic;
|
||||
signal i2c_act_int : std_logic;
|
||||
signal i2c_rdata_int : std_logic_vector(7 downto 0);
|
||||
signal ack_err_int : std_logic;
|
||||
signal id_sel : std_logic_vector(7 downto 0);
|
||||
signal id_code_op : std_logic_vector(7 downto 0);
|
||||
|
||||
attribute syn_useioff : boolean;
|
||||
attribute syn_useioff of translated : architecture is true;
|
||||
---------------------------------------------------------------------
|
||||
|
||||
|
||||
begin
|
||||
|
||||
id_sel <= DEV_ADDR & '0';
|
||||
id_code_op <= DEV_ADDR & '1';
|
||||
|
||||
|
||||
|
||||
SRL16E_inst : SRL16E
|
||||
generic map (
|
||||
INIT => X"1111")
|
||||
port map (
|
||||
Q => SDA, -- SRL data output
|
||||
A0 => '1', -- Select[0] input
|
||||
A1 => '1', -- Select[1] input
|
||||
A2 => '1', -- Select[2] input
|
||||
A3 => '1', -- Select[3] input
|
||||
CE => '1', -- Clock enable input
|
||||
CLK => CLK, -- Clock input
|
||||
D => sda_int -- SRL data input
|
||||
);
|
||||
-- SDA <= sda_int;
|
||||
SCL <= scl_int;
|
||||
SCL_CNT_EN <= scl_cnt_en_int;
|
||||
I2C_RDY <= i2c_rdy_int;
|
||||
I2C_ACT <= i2c_act_int;
|
||||
I2C_RDATA <= i2c_rdata_int;
|
||||
ACK_ERR <= ack_err_int;
|
||||
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- state machine
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
case i2c_state is
|
||||
when idle =>
|
||||
if (I2C_GO = '1') then
|
||||
i2c_state <= en_clk after 1 * sim_timescale;
|
||||
else i2c_state <= idle;
|
||||
end if;
|
||||
when en_clk =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start1 after 1 * sim_timescale;
|
||||
else i2c_state <= en_clk;
|
||||
end if;
|
||||
when start1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= start1;
|
||||
end if;
|
||||
when dev_id1 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id1;
|
||||
end if;
|
||||
when ack_id1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
if ENAPH = '1' then
|
||||
i2c_state <= w_add after 1 * sim_timescale;
|
||||
else
|
||||
i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end if;
|
||||
else i2c_state <= ack_id1;
|
||||
end if;
|
||||
when w_add =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_add after 1 * sim_timescale;
|
||||
else i2c_state <= w_add;
|
||||
end if;
|
||||
when ack_add =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
case WR_L is
|
||||
when '1' => i2c_state <= dis_clk1 after 1 * sim_timescale;
|
||||
when others => i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end case;
|
||||
else i2c_state <= ack_add;
|
||||
end if;
|
||||
when w_dat =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_wr after 1 * sim_timescale;
|
||||
else i2c_state <= w_dat;
|
||||
end if;
|
||||
when ack_wr =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_wr;
|
||||
end if;
|
||||
when dis_clk1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= wait1 after 1 * sim_timescale;
|
||||
else i2c_state <= dis_clk1;
|
||||
end if;
|
||||
when wait1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start2 after 1 * sim_timescale;
|
||||
else i2c_state <= wait1;
|
||||
end if;
|
||||
when start2 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= start2;
|
||||
end if;
|
||||
when dev_id2 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id2;
|
||||
end if;
|
||||
when ack_id2 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_id2;
|
||||
end if;
|
||||
when data =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
case CONTINUE is
|
||||
when '1' => i2c_state <= ack_rd_mult after 1 * sim_timescale; --
|
||||
when others => i2c_state <= ack_rd after 1 * sim_timescale;--
|
||||
end case;
|
||||
else i2c_state <= data;
|
||||
end if;
|
||||
when ack_rd =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd;
|
||||
end if;
|
||||
when ack_rd_mult =>
|
||||
if ((SCL_TICK and scl_int) = '1')
|
||||
then i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd_mult;
|
||||
end if;
|
||||
when stop1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
else i2c_state <= stop1;
|
||||
end if;
|
||||
when others =>
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- bit counter
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
bit_cntr <= "111" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((en_cntr and scl_int) and SCL_TICK) = '1') then
|
||||
bit_cntr <= bit_cntr - "001" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((bit_cntr = "000") and (scl_int = '1')) then
|
||||
cntr_done <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
---------------------------------------------------------------------
|
||||
-- SCL generation
|
||||
-- enable CLK divider
|
||||
|
||||
if (RST = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = dev_id1) or (i2c_state = w_add) or (i2c_state =
|
||||
dev_id2) or (i2c_state = data) or (i2c_state = w_dat)) then
|
||||
en_cntr <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (cntr_done = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = en_clk) then
|
||||
scl_cnt_en_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = idle) then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- enables tick divider
|
||||
|
||||
--process (CLK, RST)
|
||||
--begin
|
||||
-- if (RST = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- elsif (CLK'event and CLK = '1') then
|
||||
-- if (i2c_state = start1) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = dis_clk1) and (SCL_TICK = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = start2) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = stop1) and (scl_int = '1')
|
||||
-- then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = start1) or (i2c_state = start2) then
|
||||
scl_en <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if ((i2c_state = dis_clk1) and (SCL_TICK = '1')) or ((i2c_state = stop1) and (scl_int = '1')) then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- tick divider
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((scl_en and SCL_TICK) = '1') then
|
||||
scl_int <= not scl_int after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = start1) or (i2c_state = start2) or (i2c_state = stop1) or (i2c_state = ack_rd_mult))
|
||||
then sda_int <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = dev_id1) then
|
||||
sda_int <= id_sel(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = dev_id2) then
|
||||
sda_int <= id_code_op(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_add) then
|
||||
sda_int <= WRD_ADD(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_dat) then
|
||||
sda_int <= WRD_DAT(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = data) and (scl_int = '1') then
|
||||
i2c_rdata_int(conv_integer(bit_cntr)) <= SDA_PIN after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = stop1) and (scl_int = '1')) or
|
||||
((i2c_state = ack_rd_mult) and (scl_int and not SDA_PIN and WR_L) = '1')) then
|
||||
i2c_rdy_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
-- if (I2C_GO = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = ack_id1) or (i2c_state = ack_add) or (i2c_state = ack_id2) or (i2c_state = ack_rd_mult) or (i2c_state = ack_wr))
|
||||
and (scl_int and SDA_PIN) = '1') then
|
||||
ack_err_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i2c_act_int <= '0' when i2c_state = idle else '1';
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,126 @@
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity si5332_wrapper is
|
||||
port(
|
||||
clk_100_in : in std_logic;
|
||||
clk_100_areset_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic
|
||||
);
|
||||
end entity si5332_wrapper;
|
||||
|
||||
architecture imp of si5332_wrapper is
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
signal man_clk_gen_en : std_logic := '0';
|
||||
signal man_clk_gen_cfg_reset : std_logic := '0';
|
||||
|
||||
|
||||
signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-----------------------------------
|
||||
i_si5341_clk_conf : entity work.si5341_clk_configurator
|
||||
port map (
|
||||
sys_clk100_in => clk_100_in,
|
||||
tick_1ms_in => tick_1ms,
|
||||
|
||||
sda_in => sda_in,
|
||||
sda_out => sda_out,
|
||||
sda_t_out => sda_t_out,
|
||||
|
||||
scl_in => scl_in,
|
||||
scl_out => scl_out,
|
||||
scl_t_out => scl_t_out,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
man_clk_gen_en_in => man_clk_gen_en,
|
||||
man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_100_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
|
||||
-- i_vio_3 : entity work.vio_3
|
||||
-- port map (
|
||||
-- clk => clk_100_in,
|
||||
-- probe_in0(0) => i2c_mux_access_ok, -- 1
|
||||
-- probe_in1(0) => si5341_access_ok, -- 1
|
||||
-- probe_in2(0) => si5341_config_done, -- 1
|
||||
-- probe_in3(0) => si5341_config_error, -- 1
|
||||
-- probe_in4 => clk_100_freq_r, -- 32
|
||||
-- probe_in5 => clk_100_cnt_r, -- 32
|
||||
-- probe_in6 => qsfp2_freq_r, -- 32
|
||||
-- probe_in7 => qsfp2_cnt_r, -- 32
|
||||
-- probe_in8 => qsfp3_freq_r, -- 32
|
||||
-- probe_in9 => qsfp3_cnt_r, -- 32
|
||||
|
||||
-- probe_out0(0) => man_clk_gen_en, -- 1
|
||||
-- probe_out1(0) => man_clk_gen_cfg_reset -- 1
|
||||
-- );
|
||||
|
||||
process(clk_100_in)
|
||||
begin
|
||||
if (rising_edge(clk_100_in)) then
|
||||
clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_100_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_100_freq_r <= clk_100_cnt_r;
|
||||
clk_100_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_100_cnt_r <= clk_100_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,183 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity si5341_clk_configurator is
|
||||
port (
|
||||
sys_clk100_in : in std_logic;
|
||||
tick_1ms_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic;
|
||||
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
man_clk_gen_en_in : in std_logic;
|
||||
man_clk_gen_cfg_reset_in : in std_logic;
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity si5341_clk_configurator;
|
||||
|
||||
architecture imp of si5341_clk_configurator is
|
||||
|
||||
signal clk_gen_cfg_reset_d : std_logic := '0';
|
||||
signal clk_gen_cfg_reset : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
type fsm_state_sm is (idle_st, si5341_reset_lo_st, si5341_reset_hi_st, si5341_config_st, si5341_config_wait_st,
|
||||
si5341_config_check_st, done_st);
|
||||
signal state_d : fsm_state_sm := idle_st;
|
||||
signal tick_cnt_d : integer;
|
||||
|
||||
signal state_test_r : std_logic_vector(2 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
clk_gen_cfg_reset <= man_clk_gen_cfg_reset_in when man_clk_gen_en_in = '1' else clk_gen_cfg_reset_d;
|
||||
|
||||
i_clk_gen_cfg : entity work.clk_gen_cfg
|
||||
generic map (
|
||||
simulation_mode => '0'
|
||||
)
|
||||
port map (
|
||||
sys_clk_in => sys_clk100_in,
|
||||
reset_in => clk_gen_cfg_reset,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
I_SDA_I => sda_in,
|
||||
O_SDA_O => sda_out,
|
||||
O_SDA_T => sda_t_out,
|
||||
|
||||
I_SCL_I => scl_in,
|
||||
O_SCL_O => scl_out,
|
||||
O_SCL_T => scl_t_out
|
||||
);
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok;
|
||||
si5341_access_ok_out <= si5341_access_ok;
|
||||
si5341_config_done_out <= si5341_config_done;
|
||||
si5341_config_error_out <= si5341_config_error;
|
||||
|
||||
process(state_d)
|
||||
begin
|
||||
case state_d is
|
||||
when idle_st => state_test_r <= "000";
|
||||
when si5341_reset_lo_st => state_test_r <= "001";
|
||||
when si5341_reset_hi_st => state_test_r <= "010";
|
||||
when si5341_config_st => state_test_r <= "011";
|
||||
when si5341_config_wait_st => state_test_r <= "100";
|
||||
when si5341_config_check_st => state_test_r <= "101";
|
||||
when done_st => state_test_r <= "110";
|
||||
when others => state_test_r <= "111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_0 : entity work.ila_0
|
||||
-- port map (
|
||||
-- clk => sys_clk100_in,
|
||||
-- probe0 => state_test_r, --3
|
||||
-- probe1(0) => i2c_mux_access_ok, --1
|
||||
-- probe2(0) => si5341_access_ok, --1
|
||||
-- probe3(0) => si5341_config_done, --1
|
||||
-- probe4(0) => si5341_config_error, --1
|
||||
-- probe5(0) => clk_gen_cfg_reset, --1
|
||||
-- probe7(0) => clk_gen_cfg_reset_d, --1
|
||||
-- probe9(0) => tick_1ms_in --1
|
||||
-- );
|
||||
|
||||
process(sys_clk100_in)
|
||||
begin
|
||||
if (rising_edge(sys_clk100_in)) then
|
||||
if (reset_in = '1') then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 500;
|
||||
state_d <= idle_st;
|
||||
else
|
||||
if (tick_1ms_in = '1') then
|
||||
tick_cnt_d <= tick_cnt_d - 1;
|
||||
end if;
|
||||
|
||||
case state_d is
|
||||
when idle_st => --0
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_reset_lo_st;
|
||||
else
|
||||
state_d <= idle_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_lo_st => --1
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 100;
|
||||
state_d <= si5341_reset_hi_st;
|
||||
else
|
||||
state_d <= si5341_reset_lo_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_hi_st => --2
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '1';
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_config_st;
|
||||
else
|
||||
state_d <= si5341_reset_hi_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_st => --3
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_wait_st;
|
||||
else
|
||||
state_d <= si5341_config_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_wait_st => --4
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_check_st;
|
||||
else
|
||||
state_d <= si5341_config_wait_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_check_st => --5
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= idle_st;
|
||||
elsif (i2c_mux_access_ok = '1' and si5341_access_ok = '1' and si5341_config_done = '1' and si5341_config_error = '0') then
|
||||
state_d <= done_st;
|
||||
else
|
||||
state_d <= si5341_config_check_st;
|
||||
end if;
|
||||
|
||||
when done_st => --6
|
||||
state_d <= done_st;
|
||||
|
||||
when others => --7
|
||||
state_d <= idle_st;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,380 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: Silicon Lab Si5341 Clock Generator Configuration Design
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project: HTG-ZRF8
|
||||
-- File name: si5341_gen_cfg.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose: Configures Si5341 Clock Generators on Start-up
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Xilinx Vivado
|
||||
-- Synthesis: Xilinx Vivado
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 1.00
|
||||
-- Modification date: 20/10/2018
|
||||
-- Limitation: Design requires 12.5MHz input clock.
|
||||
-- Change COUNT_DIV value for other bus frequency.
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
use work.global_types.all;
|
||||
|
||||
entity si5341_gen_cfg is
|
||||
generic (
|
||||
COUNT_DIV : integer range 0 to 1023 := 512; -- sysclk divide coefficient (Valid Values: 2 to 1023)
|
||||
SIZ5341 : integer range 0 to 511 := 511; -- Real Address/Data Array Size (Valid Values: 1 to 511)
|
||||
ADR5341 : addr_si5341_type := (others => (others => '0'));
|
||||
DAT5341 : data_si5341_type := (others => (others => '0'));
|
||||
simulation_mode : std_logic := '0'
|
||||
);
|
||||
port (
|
||||
-- System signals
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
-- External Operation Control
|
||||
START : in std_logic; -- Run Start-Up Clock Genrators Configuration
|
||||
|
||||
-- Status Output
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
-- I2C Bus
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic
|
||||
);
|
||||
end entity si5341_gen_cfg;
|
||||
|
||||
architecture si5341_gen_cfg_arch of si5341_gen_cfg is
|
||||
|
||||
component i2c
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coefficient (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
|
||||
type fsm_state is (IDLE, SI5341_NEW, SI5341_NEW_WR, SI5341_NEW_INC, FINISH, ERROR);
|
||||
|
||||
signal state_r : fsm_state := IDLE;
|
||||
|
||||
signal i2c_rdata : std_logic_vector(7 downto 0);
|
||||
|
||||
signal si5341_adr_arr : addr_si5341_type := ADR5341;
|
||||
signal si5341_dat_arr : data_si5341_type := DAT5341;
|
||||
|
||||
signal dev_addr : std_logic_vector(6 downto 0);
|
||||
|
||||
signal new_adr : std_logic_vector(7 downto 0);
|
||||
signal cur_addr : integer range 0 to 511 := 0;
|
||||
signal inc_adr : std_logic;
|
||||
signal new_da : std_logic_vector(6 downto 0):= (others => '0');
|
||||
signal addr : std_logic_vector(8 downto 0);
|
||||
signal new_dat : std_logic_vector(7 downto 0);
|
||||
signal new_wr : std_logic;
|
||||
signal new_op : std_logic;
|
||||
signal new_apen : std_logic := '0';
|
||||
signal ap_en : std_logic;
|
||||
|
||||
signal dat_in : std_logic_vector(7 downto 0);
|
||||
|
||||
signal word_addr : std_logic_vector(7 downto 0);
|
||||
signal we_i2c : std_logic;
|
||||
signal wr_i2c : std_logic;
|
||||
|
||||
signal ack_err : std_logic;
|
||||
signal i2c_rdy : std_logic;
|
||||
signal i2c_act : std_logic;
|
||||
signal CONTINUE : std_logic;
|
||||
signal ACK_L : std_logic;
|
||||
|
||||
signal i2c_busy : std_logic;
|
||||
signal i2c_act_fall : std_logic := '0';
|
||||
signal i2c_act_rg : std_logic := '0';
|
||||
|
||||
signal addr_itg : integer range 0 to 511;
|
||||
signal si5341_size : integer range 0 to 511;
|
||||
signal si5341_data : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr : std_logic_vector(15 downto 0);
|
||||
signal si5341_addr_h : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr_l : std_logic_vector(7 downto 0);
|
||||
|
||||
signal state_test_r : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
signal i2c_mux_access_ok_r : std_logic := '0';
|
||||
signal si5341_access_ok_r : std_logic := '0';
|
||||
signal si5341_config_done_r : std_logic := '0';
|
||||
signal si5341_config_error_r : std_logic := '0';
|
||||
|
||||
|
||||
begin
|
||||
|
||||
addr_itg <= CONV_INTEGER(cur_addr);
|
||||
si5341_addr <= si5341_adr_arr(addr_itg);
|
||||
si5341_data <= si5341_dat_arr(addr_itg);
|
||||
si5341_size <= SIZ5341;
|
||||
si5341_addr_h <= si5341_addr(15 downto 8); -- Page Number
|
||||
si5341_addr_l <= si5341_addr( 7 downto 0); -- Byte Address
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok_r;
|
||||
si5341_access_ok_out <= si5341_access_ok_r;
|
||||
si5341_config_done_out <= si5341_config_done_r;
|
||||
si5341_config_error_out <= si5341_config_error_r;
|
||||
|
||||
process(state_r)
|
||||
begin
|
||||
case state_r is
|
||||
when IDLE => state_test_r <= "0000";
|
||||
when SI5341_NEW => state_test_r <= "0011";
|
||||
when SI5341_NEW_WR => state_test_r <= "0101";
|
||||
when SI5341_NEW_INC => state_test_r <= "0110";
|
||||
when FINISH => state_test_r <= "1000";
|
||||
when ERROR => state_test_r <= "1001";
|
||||
when others => state_test_r <= "1111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_1 : entity work.ila_1
|
||||
-- port map (
|
||||
-- clk => CLK,
|
||||
-- probe0 => state_test_r, --4
|
||||
-- probe1 => new_da, --7
|
||||
-- probe2 => new_dat, --8
|
||||
-- probe3(0) => new_wr, --1
|
||||
-- probe4(0) => i2c_busy, --1
|
||||
-- probe7(0) => i2c_rdy, --1
|
||||
-- probe8(0) => i2c_act, --1
|
||||
-- probe9(0) => ack_err, --1
|
||||
-- probe10(0) => START, --1
|
||||
-- probe13 => new_adr -- 8
|
||||
-- );
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
-- I2C Mudule
|
||||
---------------------------------------------------------------------------------------------
|
||||
|
||||
SPD_READ_UNIT: i2c
|
||||
generic map(
|
||||
count_div => COUNT_DIV -- sysclk divide coafficien (2 to 1023 max)
|
||||
)
|
||||
port map(
|
||||
ADDR_IN => word_addr, -- word address
|
||||
DAT_IN => DAT_IN, -- write data
|
||||
DEV_ADDR => dev_addr, -- device address
|
||||
CONTINUE => CONTINUE, -- continue read operation from ADDR_IN
|
||||
AP_EN => ap_en, -- Enable Address Phase During Write
|
||||
WR_OP => wr_i2c, -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN => we_i2c, -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK => CLK, -- main clock
|
||||
RST => RST, -- system reset
|
||||
|
||||
I2C_RDATA => i2c_rdata, -- i2c read data
|
||||
ACK_L => ACK_L, -- acknowledge WR_EN (active '0')
|
||||
|
||||
I_SDA_I => I_SDA_I,
|
||||
O_SDA_O => O_SDA_O,
|
||||
O_SDA_T => O_SDA_T,
|
||||
|
||||
I_SCL_I => I_SCL_I,
|
||||
O_SCL_O => O_SCL_O,
|
||||
O_SCL_T => O_SCL_T,
|
||||
|
||||
I2C_RDY => i2c_rdy, -- i2c ready
|
||||
I2C_ACT => i2c_act, -- i2c cycle active
|
||||
ACK_ERR => ack_err -- i2c(ack) error
|
||||
);
|
||||
|
||||
CONTINUE <= '0';
|
||||
word_addr <= new_adr;
|
||||
dev_addr <= new_da;
|
||||
we_i2c <= new_wr;
|
||||
wr_i2c <= new_op;
|
||||
dat_in <= new_dat;
|
||||
ap_en <= new_apen;
|
||||
|
||||
I2C_BUSY_RG: process (RST, CLK)
|
||||
begin
|
||||
if RST = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if i2c_act_fall = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif new_wr = '1' then
|
||||
i2c_busy <= '1';
|
||||
end if;
|
||||
i2c_act_rg <= i2c_act;
|
||||
i2c_act_fall <= i2c_act_rg and not i2c_act;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_mux_access_ok_r <= '0';
|
||||
si5341_access_ok_r <= '0';
|
||||
si5341_config_done_r <= '0';
|
||||
si5341_config_error_r <= '0';
|
||||
|
||||
cur_addr <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(CLK)) then
|
||||
if inc_adr = '1' then
|
||||
cur_addr <= cur_addr + 1;
|
||||
end if;
|
||||
|
||||
case state_r is
|
||||
|
||||
when IDLE => --0
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= X"55"; -- selects SC0/SD0 from I2C Mux U22 on ZCU208
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (START = '1') then
|
||||
new_da <= "1101010"; -- 6Ah - Si5332 Access
|
||||
new_apen <= '1';
|
||||
new_wr <= '0';
|
||||
i2c_mux_access_ok_r <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SI5341_NEW => --3
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
if (cur_addr = si5341_size) then
|
||||
state_r <= FINISH;
|
||||
else
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Write Register Value
|
||||
when SI5341_NEW_WR => --5
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if (ack_err = '1') then
|
||||
state_r <= ERROR;
|
||||
new_wr <= '0';
|
||||
else
|
||||
si5341_access_ok_r <= '1';
|
||||
new_wr <= '1';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Increment Counter
|
||||
when SI5341_NEW_INC => --6
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if ack_err = '1' then
|
||||
inc_adr <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
inc_adr <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
end if;
|
||||
else
|
||||
inc_adr <= '0';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
|
||||
when FINISH => --8
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_done_r <= '1';
|
||||
state_r <= FINISH;
|
||||
|
||||
when ERROR => --9
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_error_r <= '1';
|
||||
state_r <= ERROR;
|
||||
|
||||
when others => --f
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end si5341_gen_cfg_arch;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,839 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axi_regs_32 is
|
||||
generic (
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
reg0_out : out std_logic_vector(31 downto 0);
|
||||
reg1_out : out std_logic_vector(31 downto 0);
|
||||
reg2_out : out std_logic_vector(31 downto 0);
|
||||
reg3_out : out std_logic_vector(31 downto 0);
|
||||
reg4_out : out std_logic_vector(31 downto 0);
|
||||
reg5_out : out std_logic_vector(31 downto 0);
|
||||
reg6_out : out std_logic_vector(31 downto 0);
|
||||
reg7_out : out std_logic_vector(31 downto 0);
|
||||
reg8_out : out std_logic_vector(31 downto 0);
|
||||
reg9_out : out std_logic_vector(31 downto 0);
|
||||
reg10_out : out std_logic_vector(31 downto 0);
|
||||
reg11_out : out std_logic_vector(31 downto 0);
|
||||
reg12_out : out std_logic_vector(31 downto 0);
|
||||
reg13_out : out std_logic_vector(31 downto 0);
|
||||
reg14_out : out std_logic_vector(31 downto 0);
|
||||
reg15_out : out std_logic_vector(31 downto 0);
|
||||
reg16_out : out std_logic_vector(31 downto 0);
|
||||
reg17_out : out std_logic_vector(31 downto 0);
|
||||
reg18_out : out std_logic_vector(31 downto 0);
|
||||
reg19_out : out std_logic_vector(31 downto 0);
|
||||
reg20_out : out std_logic_vector(31 downto 0);
|
||||
reg21_out : out std_logic_vector(31 downto 0);
|
||||
reg22_out : out std_logic_vector(31 downto 0);
|
||||
reg23_out : out std_logic_vector(31 downto 0);
|
||||
reg24_out : out std_logic_vector(31 downto 0);
|
||||
reg25_out : out std_logic_vector(31 downto 0);
|
||||
reg26_out : out std_logic_vector(31 downto 0);
|
||||
reg27_out : out std_logic_vector(31 downto 0);
|
||||
reg28_out : out std_logic_vector(31 downto 0);
|
||||
reg29_out : out std_logic_vector(31 downto 0);
|
||||
reg30_out : out std_logic_vector(31 downto 0);
|
||||
reg31_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
reg0_in : in std_logic_vector(31 downto 0);
|
||||
reg1_in : in std_logic_vector(31 downto 0);
|
||||
reg2_in : in std_logic_vector(31 downto 0);
|
||||
reg3_in : in std_logic_vector(31 downto 0);
|
||||
reg4_in : in std_logic_vector(31 downto 0);
|
||||
reg5_in : in std_logic_vector(31 downto 0);
|
||||
reg6_in : in std_logic_vector(31 downto 0);
|
||||
reg7_in : in std_logic_vector(31 downto 0);
|
||||
reg8_in : in std_logic_vector(31 downto 0);
|
||||
reg9_in : in std_logic_vector(31 downto 0);
|
||||
reg10_in : in std_logic_vector(31 downto 0);
|
||||
reg11_in : in std_logic_vector(31 downto 0);
|
||||
reg12_in : in std_logic_vector(31 downto 0);
|
||||
reg13_in : in std_logic_vector(31 downto 0);
|
||||
reg14_in : in std_logic_vector(31 downto 0);
|
||||
reg15_in : in std_logic_vector(31 downto 0);
|
||||
reg16_in : in std_logic_vector(31 downto 0);
|
||||
reg17_in : in std_logic_vector(31 downto 0);
|
||||
reg18_in : in std_logic_vector(31 downto 0);
|
||||
reg19_in : in std_logic_vector(31 downto 0);
|
||||
reg20_in : in std_logic_vector(31 downto 0);
|
||||
reg21_in : in std_logic_vector(31 downto 0);
|
||||
reg22_in : in std_logic_vector(31 downto 0);
|
||||
reg23_in : in std_logic_vector(31 downto 0);
|
||||
reg24_in : in std_logic_vector(31 downto 0);
|
||||
reg25_in : in std_logic_vector(31 downto 0);
|
||||
reg26_in : in std_logic_vector(31 downto 0);
|
||||
reg27_in : in std_logic_vector(31 downto 0);
|
||||
reg28_in : in std_logic_vector(31 downto 0);
|
||||
reg29_in : in std_logic_vector(31 downto 0);
|
||||
reg30_in : in std_logic_vector(31 downto 0);
|
||||
reg31_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end axi_regs_32;
|
||||
|
||||
architecture arch_imp of axi_regs_32 is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 4;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 32
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= (others => '0');
|
||||
slv_reg2 <= (others => '0');
|
||||
slv_reg3 <= (others => '0');
|
||||
slv_reg4 <= (others => '0');
|
||||
slv_reg5 <= (others => '0');
|
||||
slv_reg6 <= (others => '0');
|
||||
slv_reg7 <= (others => '0');
|
||||
slv_reg8 <= (others => '0');
|
||||
slv_reg9 <= (others => '0');
|
||||
slv_reg10 <= (others => '0');
|
||||
slv_reg11 <= (others => '0');
|
||||
slv_reg12 <= (others => '0');
|
||||
slv_reg13 <= (others => '0');
|
||||
slv_reg14 <= (others => '0');
|
||||
slv_reg15 <= (others => '0');
|
||||
slv_reg16 <= (others => '0');
|
||||
slv_reg17 <= (others => '0');
|
||||
slv_reg18 <= (others => '0');
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
slv_reg24 <= (others => '0');
|
||||
slv_reg25 <= (others => '0');
|
||||
slv_reg26 <= (others => '0');
|
||||
slv_reg27 <= (others => '0');
|
||||
slv_reg28 <= (others => '0');
|
||||
slv_reg29 <= (others => '0');
|
||||
slv_reg30 <= (others => '0');
|
||||
slv_reg31 <= (others => '0');
|
||||
else
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 24
|
||||
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 25
|
||||
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 26
|
||||
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 27
|
||||
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 28
|
||||
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 29
|
||||
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 30
|
||||
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 31
|
||||
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
slv_reg24 <= slv_reg24;
|
||||
slv_reg25 <= slv_reg25;
|
||||
slv_reg26 <= slv_reg26;
|
||||
slv_reg27 <= slv_reg27;
|
||||
slv_reg28 <= slv_reg28;
|
||||
slv_reg29 <= slv_reg29;
|
||||
slv_reg30 <= slv_reg30;
|
||||
slv_reg31 <= slv_reg31;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (reg0_in, reg1_in, reg2_in, reg3_in, reg4_in, reg5_in, reg6_in, reg7_in, reg8_in, reg9_in, reg10_in, reg11_in, reg12_in, reg13_in, reg14_in, reg15_in, reg16_in, reg17_in, reg18_in, reg19_in, reg20_in, reg21_in, reg22_in, reg23_in, reg24_in, reg25_in, reg26_in, reg27_in, reg28_in, reg29_in, reg30_in, reg31_in, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= reg0_in;
|
||||
when b"00001" =>
|
||||
reg_data_out <= reg1_in;
|
||||
when b"00010" =>
|
||||
reg_data_out <= reg2_in;
|
||||
when b"00011" =>
|
||||
reg_data_out <= reg3_in;
|
||||
when b"00100" =>
|
||||
reg_data_out <= reg4_in;
|
||||
when b"00101" =>
|
||||
reg_data_out <= reg5_in;
|
||||
when b"00110" =>
|
||||
reg_data_out <= reg6_in;
|
||||
when b"00111" =>
|
||||
reg_data_out <= reg7_in;
|
||||
when b"01000" =>
|
||||
reg_data_out <= reg8_in;
|
||||
when b"01001" =>
|
||||
reg_data_out <= reg9_in;
|
||||
when b"01010" =>
|
||||
reg_data_out <= reg10_in;
|
||||
when b"01011" =>
|
||||
reg_data_out <= reg11_in;
|
||||
when b"01100" =>
|
||||
reg_data_out <= reg12_in;
|
||||
when b"01101" =>
|
||||
reg_data_out <= reg13_in;
|
||||
when b"01110" =>
|
||||
reg_data_out <= reg14_in;
|
||||
when b"01111" =>
|
||||
reg_data_out <= reg15_in;
|
||||
when b"10000" =>
|
||||
reg_data_out <= reg16_in;
|
||||
when b"10001" =>
|
||||
reg_data_out <= reg17_in;
|
||||
when b"10010" =>
|
||||
reg_data_out <= reg18_in;
|
||||
when b"10011" =>
|
||||
reg_data_out <= reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= reg23_in;
|
||||
when b"11000" =>
|
||||
reg_data_out <= reg24_in;
|
||||
when b"11001" =>
|
||||
reg_data_out <= reg25_in;
|
||||
when b"11010" =>
|
||||
reg_data_out <= reg26_in;
|
||||
when b"11011" =>
|
||||
reg_data_out <= reg27_in;
|
||||
when b"11100" =>
|
||||
reg_data_out <= reg28_in;
|
||||
when b"11101" =>
|
||||
reg_data_out <= reg29_in;
|
||||
when b"11110" =>
|
||||
reg_data_out <= reg30_in;
|
||||
when b"11111" =>
|
||||
reg_data_out <= reg31_in;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reg0_out <= slv_reg0;
|
||||
reg1_out <= slv_reg1;
|
||||
reg2_out <= slv_reg2;
|
||||
reg3_out <= slv_reg3;
|
||||
reg4_out <= slv_reg4;
|
||||
reg5_out <= slv_reg5;
|
||||
reg6_out <= slv_reg6;
|
||||
reg7_out <= slv_reg7;
|
||||
reg8_out <= slv_reg8;
|
||||
reg9_out <= slv_reg9;
|
||||
reg10_out <= slv_reg10;
|
||||
reg11_out <= slv_reg11;
|
||||
reg12_out <= slv_reg12;
|
||||
reg13_out <= slv_reg13;
|
||||
reg14_out <= slv_reg14;
|
||||
reg15_out <= slv_reg15;
|
||||
reg16_out <= slv_reg16;
|
||||
reg17_out <= slv_reg17;
|
||||
reg18_out <= slv_reg18;
|
||||
reg19_out <= slv_reg19;
|
||||
reg20_out <= slv_reg20;
|
||||
reg21_out <= slv_reg21;
|
||||
reg22_out <= slv_reg22;
|
||||
reg23_out <= slv_reg23;
|
||||
reg24_out <= slv_reg24;
|
||||
reg25_out <= slv_reg25;
|
||||
reg26_out <= slv_reg26;
|
||||
reg27_out <= slv_reg27;
|
||||
reg28_out <= slv_reg28;
|
||||
reg29_out <= slv_reg29;
|
||||
reg30_out <= slv_reg30;
|
||||
reg31_out <= slv_reg31;
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
|
||||
|
||||
create_clock -period 10.000 -name S_AXI_ACLK [get_ports S_AXI_ACLK];
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,192 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_afifo_32x240",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_data_afifo_32x240",
|
||||
"parameters": {
|
||||
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@@ -0,0 +1,175 @@
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|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,173 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x512",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../test_sim/project_1.gen/sources_1/ip/axis_data_fifo_32x512",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x512", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825765936", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../test_sim/project_1.gen/sources_1/ip/axis_data_fifo_32x512" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
|
||||
"almost_empty": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: axis_demux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m0_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m0_axis_tvalid : out std_logic;
|
||||
m0_axis_tready : in std_logic;
|
||||
|
||||
m1_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m1_axis_tvalid : out std_logic;
|
||||
m1_axis_tready : in std_logic
|
||||
);
|
||||
end axis_demux;
|
||||
|
||||
architecture imp of axis_demux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
--signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
m0_axis_tdata <= s_axis_tdata;
|
||||
m1_axis_tdata <= s_axis_tdata;
|
||||
|
||||
m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
|
||||
m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
|
||||
|
||||
s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
|
||||
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,488 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_demux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m0_axis:m1_axis:s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_demux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>57ba02cc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_demux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>16ec46fd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c6faabd4</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aselect</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>DWIDTH</spirit:name>
|
||||
<spirit:displayName>Dwidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWIDTH">512</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_16ec46fd</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_demux_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_c6faabd4</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_demux_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DWIDTH</spirit:name>
|
||||
<spirit:displayName>DWIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWIDTH">512</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_demux_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axis_demux_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2021-06-22T18:00:02Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@27b453f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1258db51_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@53d4f02b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a095752_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e2c012e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@32a42669_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1640d25f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1f86641f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7df1d869_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a3f7179_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@78b50c76_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e487608_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@70e25a99_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@14ea36d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2e26ac35_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1f47c38d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4dc9792_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55f4ea14_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@cdc4a77_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="05d5a589"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4b08030d"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="d2fc399b"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="55dda66a"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_dwidth_converter_128b_to_512b",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_128b_to_512b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_dwidth_converter_128b_to_512b", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_128b_to_512b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
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|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 05/18/2021 11:43:02 AM
|
||||
-- Design Name:
|
||||
-- Module Name: axis_mux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_mux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s0_axis_tvalid : in std_logic;
|
||||
s0_axis_tready : out std_logic;
|
||||
s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s1_axis_tvalid : in std_logic;
|
||||
s1_axis_tready : out std_logic;
|
||||
m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end axis_mux;
|
||||
|
||||
architecture imp of axis_mux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
aselect_int <= aselect;
|
||||
|
||||
m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
|
||||
m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
|
||||
s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
|
||||
s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,542 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_mux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s0_axis:s1_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_mux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
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<xilinx:tag xilinx:name="ui.data.coregen.dd@577fb6a6_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c89838f_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a031008_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3a834977_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@74a96827_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@781e86fd_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6c15b577_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4d9fef3d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@16ac630d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4cec9a36_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55a12c39_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@632873ed_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@68071b83_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@43775ef0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1946983d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@502a5174_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@46e8cbd5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6af1b794_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1892dd8b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4af08e99_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@762583a1_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64c4fdab_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4846b579_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@160330b9_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@23247587_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1542fbd2_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@714d5df2_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1fd79205_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6b73b80e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1a0555de_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1b12cc6d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7505fb14_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@301a3b59_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@359c295b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2033e680_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@63fadde1_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@774e9648_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@25b4503c_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4372da5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47ed35b3_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@48531ae8_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@8313885_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5478ac48_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="24797529"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e6992404"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="04f2586c"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="e7b1dc92"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
Executable
+115
@@ -0,0 +1,115 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 05/18/2021 11:43:02 AM
|
||||
-- Design Name:
|
||||
-- Module Name: axis_mux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_mux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s0_axis_tvalid : in std_logic;
|
||||
s0_axis_tready : out std_logic;
|
||||
s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s1_axis_tvalid : in std_logic;
|
||||
s1_axis_tready : out std_logic;
|
||||
m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end axis_mux;
|
||||
|
||||
architecture imp of axis_mux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
aselect_int <= aselect;
|
||||
|
||||
m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
|
||||
m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
|
||||
s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
|
||||
s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
|
||||
|
||||
|
||||
end imp;
|
||||
Executable
BIN
Binary file not shown.
@@ -0,0 +1,164 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_mux_256b",
|
||||
"component_reference": "xilinx.com:user:axis_mux:1.0",
|
||||
"ip_revision": "6",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "axis_mux_256b", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWIDTH": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DWIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "6" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"aselect": [ { "direction": "in" } ],
|
||||
"s0_axis_tdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
|
||||
"s0_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s0_axis_tready": [ { "direction": "out" } ],
|
||||
"s1_axis_tdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
|
||||
"s1_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s1_axis_tready": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s0_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s0_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s0_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s0_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s1_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s1_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s1_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s1_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri Sep 19 16:06:04 2025
|
||||
// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axis_mux_256b -prefix
|
||||
// axis_mux_256b_ axis_mux_256b_stub.v
|
||||
// Design : axis_mux_256b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xczu19eg-ffvc1760-2-i
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_mux,Vivado 2023.2" *)
|
||||
module axis_mux_256b(aclk, aresetn, aselect, s0_axis_tdata,
|
||||
s0_axis_tvalid, s0_axis_tready, s1_axis_tdata, s1_axis_tvalid, s1_axis_tready,
|
||||
m_axis_tdata, m_axis_tvalid, m_axis_tready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input aselect;
|
||||
input [255:0]s0_axis_tdata;
|
||||
input s0_axis_tvalid;
|
||||
output s0_axis_tready;
|
||||
input [255:0]s1_axis_tdata;
|
||||
input s1_axis_tvalid;
|
||||
output s1_axis_tready;
|
||||
output [255:0]m_axis_tdata;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
endmodule
|
||||
@@ -0,0 +1,42 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
-- Date : Fri Sep 19 16:06:04 2025
|
||||
-- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top axis_mux_256b -prefix
|
||||
-- axis_mux_256b_ axis_mux_256b_stub.vhdl
|
||||
-- Design : axis_mux_256b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xczu19eg-ffvc1760-2-i
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_mux_256b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
|
||||
end axis_mux_256b;
|
||||
|
||||
architecture stub of axis_mux_256b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axis_mux,Vivado 2023.2";
|
||||
begin
|
||||
end;
|
||||
Executable
+16
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,140 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_mux:1.0
|
||||
-- IP Revision: 6
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_mux_256b IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
aselect : IN STD_LOGIC;
|
||||
s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
s0_axis_tvalid : IN STD_LOGIC;
|
||||
s0_axis_tready : OUT STD_LOGIC;
|
||||
s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
s1_axis_tvalid : IN STD_LOGIC;
|
||||
s1_axis_tready : OUT STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC
|
||||
);
|
||||
END axis_mux_256b;
|
||||
|
||||
ARCHITECTURE axis_mux_256b_arch OF axis_mux_256b IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_mux_256b_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_mux IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
aselect : IN STD_LOGIC;
|
||||
s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
s0_axis_tvalid : IN STD_LOGIC;
|
||||
s0_axis_tready : OUT STD_LOGIC;
|
||||
s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
s1_axis_tvalid : IN STD_LOGIC;
|
||||
s1_axis_tready : OUT STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_mux;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux,Vivado 2023.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_mux_256b_arch : ARCHITECTURE IS "axis_mux_256b,axis_mux,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux_256b,axis_mux,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_mux,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DWIDTH=256}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF axis_mux_256b_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s0_axis:s1_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_tdata: SIGNAL IS "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s0_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s0_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s1_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s1_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
BEGIN
|
||||
U0 : axis_mux
|
||||
GENERIC MAP (
|
||||
DWIDTH => 256
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
aselect => aselect,
|
||||
s0_axis_tdata => s0_axis_tdata,
|
||||
s0_axis_tvalid => s0_axis_tvalid,
|
||||
s0_axis_tready => s0_axis_tready,
|
||||
s1_axis_tdata => s1_axis_tdata,
|
||||
s1_axis_tvalid => s1_axis_tvalid,
|
||||
s1_axis_tready => s1_axis_tready,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tready => m_axis_tready
|
||||
);
|
||||
END axis_mux_256b_arch;
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_128b",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_register_slice_128b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_register_slice_128b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_240b",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_register_slice_240b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">319</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b952dd62</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/dig_iq_decoder_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>dig_iq_decoder_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dig_iq_decoder_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>dig_iq_decoder_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2021-06-22T17:47:25Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f062d2d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@10cd760_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64b4837a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1edcc17e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7024ec49_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ee4ccf6_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@702143e0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7318cb6e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47f9d0d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@467c2891_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@79d4f659_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8005bf8b"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6945f44e"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b2bb5fab"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c99d0644"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,114 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_decoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_decoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
select_12b : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(319 downto 0);
|
||||
m_axis_tvalid : out std_logic
|
||||
);
|
||||
end dig_iq_decoder;
|
||||
|
||||
architecture imp of dig_iq_decoder is
|
||||
|
||||
signal tvalid_int : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= tvalid_int;
|
||||
|
||||
|
||||
process(aclk, aresetn)
|
||||
begin
|
||||
if(aresetn = '0')then
|
||||
tvalid_int <= '0';
|
||||
elsif(rising_edge(aclk))then
|
||||
tvalid_int <= s_axis_tvalid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(aclk)
|
||||
begin
|
||||
|
||||
if(rising_edge(aclk))then
|
||||
|
||||
if(select_12b = '0')then
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(32 downto 17 ); -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(49 downto 34 ); -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(66 downto 51 ); -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(83 downto 68 ); -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(100 downto 85 ); -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(117 downto 102 ); -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(134 downto 119 ); -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(151 downto 136 ); -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(168 downto 153 ); -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(185 downto 170 ); -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(202 downto 187 ); -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(219 downto 204 ); -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(236 downto 221 ); -- IMAG[6]
|
||||
else
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(11 downto 0 ) & "0000"; -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(23 downto 12 ) & "0000"; -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(35 downto 24 ) & "0000"; -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(47 downto 36 ) & "0000"; -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(59 downto 48 ) & "0000"; -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(71 downto 60 ) & "0000"; -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(83 downto 72 ) & "0000"; -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(95 downto 84 ) & "0000"; -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(107 downto 96 ) & "0000"; -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(119 downto 108 ) & "0000"; -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(131 downto 120 ) & "0000"; -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(143 downto 132 ) & "0000"; -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(155 downto 144 ) & "0000"; -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(167 downto 156 ) & "0000"; -- IMAG[6]
|
||||
end if;
|
||||
|
||||
m_axis_tdata(239 downto 224 ) <= s_axis_tdata(179 downto 168 ) & "0000"; -- REAL[7]
|
||||
m_axis_tdata(255 downto 240 ) <= s_axis_tdata(191 downto 180 ) & "0000"; -- IMAG[7]
|
||||
m_axis_tdata(271 downto 256 ) <= s_axis_tdata(203 downto 192 ) & "0000"; -- REAL[8]
|
||||
m_axis_tdata(287 downto 272 ) <= s_axis_tdata(215 downto 204 ) & "0000"; -- IMAG[8]
|
||||
m_axis_tdata(303 downto 288 ) <= s_axis_tdata(227 downto 216 ) & "0000"; -- REAL[9]
|
||||
m_axis_tdata(319 downto 304 ) <= s_axis_tdata(239 downto 228 ) & "0000"; -- IMAG[9]
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,391 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>dig_iq_encoder</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ"/>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>dig_iq_encoder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b68be7df</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>dig_iq_encoder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>5aaee39c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>f64a5dae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">223</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_encoder_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_encoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_5aaee39c</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_encoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/dig_iq_encoder_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>dig_iq_encoder_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dig_iq_encoder_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>dig_iq_encoder_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>3</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-06-11T17:48:40Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6e6d4cbb_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@e49357d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@34052da1_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ffc5723_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@133f1d15_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4ccdb19d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4c501b04_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7bad693e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@269aa86e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@52aee63e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@19d8462a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4a463799_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7d6c4a4_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5cb28e8b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@24d3dd02_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a26e029_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@62e4f812_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4bf2fd0d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
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||||
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|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e4a5332_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
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||||
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|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@be2d17a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@495c4edc_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@373b9f6a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="fba468ca"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="70608935"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="42694d49"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="0b76f1bb"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_encoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_encoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(223 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end dig_iq_encoder;
|
||||
|
||||
architecture imp of dig_iq_encoder is
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= s_axis_tvalid;
|
||||
s_axis_tready <= m_axis_tready;
|
||||
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(16) <= '0';
|
||||
m_axis_tdata(32 downto 17 ) <= s_axis_tdata(31 downto 16 ); -- IMAG[0]
|
||||
m_axis_tdata(33) <= '0';
|
||||
m_axis_tdata(49 downto 34 ) <= s_axis_tdata(47 downto 32 ); -- REAL[1]
|
||||
m_axis_tdata(50) <= '0';
|
||||
m_axis_tdata(66 downto 51 ) <= s_axis_tdata(63 downto 48 ); -- IMAG[1]
|
||||
m_axis_tdata(67) <= '0';
|
||||
m_axis_tdata(83 downto 68 ) <= s_axis_tdata(79 downto 64 ); -- REAL[2]
|
||||
m_axis_tdata(84) <= '0';
|
||||
m_axis_tdata(100 downto 85 ) <= s_axis_tdata(95 downto 80 ); -- IMAG[2]
|
||||
m_axis_tdata(101) <= '0';
|
||||
m_axis_tdata(117 downto 102 ) <= s_axis_tdata(111 downto 96 ); -- REAL[3]
|
||||
m_axis_tdata(118) <= '0';
|
||||
m_axis_tdata(134 downto 119 ) <= s_axis_tdata(127 downto 112 ); -- IMAG[3]
|
||||
m_axis_tdata(135) <= '0';
|
||||
m_axis_tdata(151 downto 136 ) <= s_axis_tdata(143 downto 128 ); -- REAL[4]
|
||||
m_axis_tdata(152) <= '0';
|
||||
m_axis_tdata(168 downto 153 ) <= s_axis_tdata(159 downto 144 ); -- IMAG[4]
|
||||
m_axis_tdata(169) <= '0';
|
||||
m_axis_tdata(185 downto 170 ) <= s_axis_tdata(175 downto 160 ); -- REAL[5]
|
||||
m_axis_tdata(186) <= '0';
|
||||
m_axis_tdata(202 downto 187 ) <= s_axis_tdata(191 downto 176 ); -- IMAG[5]
|
||||
m_axis_tdata(203) <= '0';
|
||||
m_axis_tdata(219 downto 204 ) <= s_axis_tdata(207 downto 192 ); -- REAL[6]
|
||||
m_axis_tdata(220) <= '0';
|
||||
m_axis_tdata(236 downto 221 ) <= s_axis_tdata(223 downto 208 ); -- IMAG[6]
|
||||
m_axis_tdata(139 downto 237 ) <= (others => '0');
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,978 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_240b_to_512b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_240b_to_512b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_axis_demux_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_axis_mux_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>caff039b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_240b_to_512b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_demux_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_mux_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="438683d4"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2dc76fda"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="9ba06220"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="a3693994"/>
|
||||
<xilinx:targetDRCs>
|
||||
<xilinx:targetDRC xilinx:tool="ipi">
|
||||
<xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
|
||||
</xilinx:targetDRC>
|
||||
</xilinx:targetDRCs>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,357 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component iq_240b_to_512b_axis_demux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_demux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component iq_240b_to_512b_iq_decoder_12b_16b_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_iq_decoder_12b_16b_0;
|
||||
component iq_240b_to_512b_axis_mux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_mux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component iq_240b_to_512b_axis_demux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component iq_240b_to_512b_axis_mux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component iq_240b_to_512b_iq_decoder_12b_16b_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,367 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready_out : out std_logic;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_demux;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component dig_iq_decoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component dig_iq_decoder;
|
||||
component axis_mux is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_mux;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
|
||||
s_axis_tready_out <= axis_data_fifo_0_M_AXIS_TREADY;
|
||||
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component axis_demux
|
||||
generic map (
|
||||
DWIDTH => 320
|
||||
)
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component axis_mux
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component dig_iq_decoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_data_fifo_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_axis_data_fifo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
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|
||||
}
|
||||
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|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+158
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_register_slice_28B_0",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
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|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
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|
||||
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|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
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|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+158
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_register_slice_40B_0",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_iq_decoder_12b_16b_0",
|
||||
"cell_name": "iq_decoder_12b_16b",
|
||||
"component_reference": "xilinx.com:user:dig_iq_decoder:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_iq_decoder_12b_16b_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplus", "usage": "all" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "", "usage": "all" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "", "usage": "all" } ],
|
||||
"DEVICE": [ { "value": "xcvu13p", "usage": "all" } ],
|
||||
"PACKAGE": [ { "value": "figd2104", "usage": "all" } ],
|
||||
"PREFHDL": [ { "value": "VHDL", "usage": "all" } ],
|
||||
"SILICON_REVISION": [ { "value": "", "usage": "all" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED", "usage": "all" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2", "usage": "all" } ],
|
||||
"STATIC_POWER": [ { "value": "", "usage": "all" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E", "usage": "all" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"select_12b": [ { "direction": "in" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+169
@@ -0,0 +1,169 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_overflow_detect_0",
|
||||
"component_reference": "xilinx.com:ip:axis_subset_converter:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TREADY": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_REMAP": [ { "value": "tdata[319:0]", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TDEST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TKEEP_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TSTRB_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TLAST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_overflow_detect_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
|
||||
"transfer_dropped": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlconstant_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlslice_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlslice:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_WIDTH": [ { "value": "320", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DOUT_WIDTH": [ { "value": "224", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DIN_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"Din": [ { "direction": "in", "size_left": "319", "size_right": "0" } ],
|
||||
"Dout": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_static_text $IPINST -name "TEXT1" -parent ${Page_0} -text {sel_12b_16bn = 0 -- 16-bit FSW data (Fs <= 600MHz)
|
||||
|
||||
|
||||
|
||||
sel_12b_16bn = 1 -- 12-bit FSW data (Fs = 1200MHz)}
|
||||
|
||||
|
||||
}
|
||||
@@ -0,0 +1,564 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_512b_to_240b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>083caf21</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b25fa64d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>f64a5dae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>SCOPED_TO_REF_iq_512b_to_240b</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_3d51e471</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/iq_512b_to_240b_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>iq_512b_to_240b</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">iq_512b_to_240b_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>iq_512b_to_240b</xilinx:displayName>
|
||||
<xilinx:definitionSource>IPI</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-24T16:38:16Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5a5f56fc"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2a3456f"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c875ab87"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ca8f49ff"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component iq_512b_to_240b_dig_iq_encoder_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_512b_to_240b_dig_iq_encoder_0_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component dig_iq_encoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component dig_iq_encoder;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component dig_iq_encoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_axis_dwidth_converter_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_encoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_encoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(223 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end dig_iq_encoder;
|
||||
|
||||
architecture imp of dig_iq_encoder is
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= s_axis_tvalid;
|
||||
s_axis_tready <= m_axis_tready;
|
||||
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(16) <= '0';
|
||||
m_axis_tdata(32 downto 17 ) <= s_axis_tdata(31 downto 16 ); -- IMAG[0]
|
||||
m_axis_tdata(33) <= '0';
|
||||
m_axis_tdata(49 downto 34 ) <= s_axis_tdata(47 downto 32 ); -- REAL[1]
|
||||
m_axis_tdata(50) <= '0';
|
||||
m_axis_tdata(66 downto 51 ) <= s_axis_tdata(63 downto 48 ); -- IMAG[1]
|
||||
m_axis_tdata(67) <= '0';
|
||||
m_axis_tdata(83 downto 68 ) <= s_axis_tdata(79 downto 64 ); -- REAL[2]
|
||||
m_axis_tdata(84) <= '0';
|
||||
m_axis_tdata(100 downto 85 ) <= s_axis_tdata(95 downto 80 ); -- IMAG[2]
|
||||
m_axis_tdata(101) <= '0';
|
||||
m_axis_tdata(117 downto 102 ) <= s_axis_tdata(111 downto 96 ); -- REAL[3]
|
||||
m_axis_tdata(118) <= '0';
|
||||
m_axis_tdata(134 downto 119 ) <= s_axis_tdata(127 downto 112 ); -- IMAG[3]
|
||||
m_axis_tdata(135) <= '0';
|
||||
m_axis_tdata(151 downto 136 ) <= s_axis_tdata(143 downto 128 ); -- REAL[4]
|
||||
m_axis_tdata(152) <= '0';
|
||||
m_axis_tdata(168 downto 153 ) <= s_axis_tdata(159 downto 144 ); -- IMAG[4]
|
||||
m_axis_tdata(169) <= '0';
|
||||
m_axis_tdata(185 downto 170 ) <= s_axis_tdata(175 downto 160 ); -- REAL[5]
|
||||
m_axis_tdata(186) <= '0';
|
||||
m_axis_tdata(202 downto 187 ) <= s_axis_tdata(191 downto 176 ); -- IMAG[5]
|
||||
m_axis_tdata(203) <= '0';
|
||||
m_axis_tdata(219 downto 204 ) <= s_axis_tdata(207 downto 192 ); -- REAL[6]
|
||||
m_axis_tdata(220) <= '0';
|
||||
m_axis_tdata(236 downto 221 ) <= s_axis_tdata(223 downto 208 ); -- IMAG[6]
|
||||
m_axis_tdata(139 downto 237 ) <= (others => '0');
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_dig_iq_encoder_0_0",
|
||||
"component_reference": "xilinx.com:user:dig_iq_encoder:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_dig_iq_encoder_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
proc init { cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
set full_sbusif_list [list ]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
||||
set busif_param_list [list]
|
||||
set busif_name [get_property NAME $busif]
|
||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
||||
continue
|
||||
}
|
||||
foreach tparam $axi_standard_param_list {
|
||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
||||
}
|
||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc pre_propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
if { $val_on_cell != "" } {
|
||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
||||
if { $val_on_cell_intf_pin != "" } {
|
||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity qsfp_init_fsm is
|
||||
port(
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_aresetn_in : in std_logic;
|
||||
|
||||
mode_50g_40g_n_in : in std_logic;
|
||||
qsfp1_reset_n_in : in std_logic;
|
||||
qsfp4_reset_n_in : in std_logic;
|
||||
|
||||
cmd_strb_out : out std_logic;
|
||||
cmd_addr_out : out std_logic_vector(11 downto 0);
|
||||
cmd_write_out : out std_logic;
|
||||
cmd_sel_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_wdata_out : out std_logic_vector(31 downto 0);
|
||||
cmd_ready_in : in std_logic;
|
||||
fsm_running_out : out std_logic
|
||||
);
|
||||
end entity qsfp_init_fsm;
|
||||
|
||||
architecture imp of qsfp_init_fsm is
|
||||
|
||||
type fsm_state is (IDLE, QSFP1_INIT_WAIT, QSFP1_INIT, QSFP4_INIT_WAIT, QSFP4_INIT, DONE, ERROR);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
signal qsfp1_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp4_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp1_reset_r : std_logic := '0';
|
||||
|
||||
signal qsfp4_reset_r : std_logic := '0';
|
||||
|
||||
signal cmd_addr_r : std_logic_vector (11 downto 0) := (others => '0');
|
||||
signal cmd_sel_r : std_logic_vector ( 2 downto 0) := (others => '0');
|
||||
signal cmd_strb_r : std_logic := '0';
|
||||
signal cmd_wdata_r : std_logic_vector (31 downto 0) := (others => '0');
|
||||
signal cmd_write_r : std_logic := '0';
|
||||
|
||||
signal fsm_running_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
cmd_strb_out <= cmd_strb_r;
|
||||
cmd_addr_out <= cmd_addr_r;
|
||||
cmd_write_out <= cmd_write_r;
|
||||
cmd_sel_out <= cmd_sel_r;
|
||||
cmd_wdata_out <= cmd_wdata_r;
|
||||
fsm_running_out <= fsm_running_r;
|
||||
|
||||
--
|
||||
qsfp1_reset_n(0) <= qsfp1_reset_n_in;
|
||||
|
||||
i_cdc_qsfp1_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp1_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp1_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp1_reset_n_r <= qsfp1_reset_n_r(1 to 31) & qsfp1_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
qsfp4_reset_n(0) <= qsfp4_reset_n_in;
|
||||
|
||||
i_cdc_qsfp4_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp4_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp4_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp4_reset_n_r <= qsfp4_reset_n_r(1 to 31) & qsfp4_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (clk_125_aresetn_in = '0') then
|
||||
qsfp1_reset_r <= '0';
|
||||
qsfp4_reset_r <= '0';
|
||||
|
||||
cmd_sel_r <= (others => '0');
|
||||
cmd_addr_r <= (others => '0');
|
||||
cmd_wdata_r <= (others => '0');
|
||||
cmd_write_r <= '0';
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
state_cnt_r <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(clk_125_in)) then
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
if (qsfp1_reset_n_r(1) = '1' and qsfp1_reset_n_r(0) = '0') then
|
||||
qsfp1_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
if (qsfp4_reset_n_r(1) = '1' and qsfp4_reset_n_r(0) = '0') then
|
||||
qsfp4_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (qsfp1_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "000";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
elsif (qsfp4_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "001";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
else
|
||||
fsm_running_r <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP1_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP4_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when ERROR =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,480 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
--use ieee.numeric_std.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
entity qsfp_intfc_v1_1 is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0603_2024";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_reset_n_in : in std_logic;
|
||||
|
||||
clk_250_in : in std_logic;
|
||||
clk_250_reset_n_in : in std_logic;
|
||||
|
||||
rx_device_clk_in : in std_logic;
|
||||
tx_device_clk_in : in std_logic;
|
||||
|
||||
clkin8_in : in std_logic;
|
||||
-- sysref_in : in std_logic;
|
||||
ref_clk_div2_in : in std_logic;
|
||||
|
||||
QSFP1_RESETL_LS : out std_logic;
|
||||
QSFP1_MODPRSL_LS : in std_logic;
|
||||
QSFP1_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP2_RESETL_LS : out std_logic;
|
||||
QSFP2_MODPRSL_LS : in std_logic;
|
||||
QSFP2_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP3_RESETL_LS : out std_logic;
|
||||
QSFP3_MODPRSL_LS : in std_logic;
|
||||
QSFP3_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP4_RESETL_LS : out std_logic;
|
||||
QSFP4_MODPRSL_LS : in std_logic;
|
||||
QSFP4_INTL_LS : in std_logic;
|
||||
----
|
||||
cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_4_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_rx_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
mem_xfer_tx_upload_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dac_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
adc_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_4_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cnt_reset_out : out std_logic;
|
||||
|
||||
slv_reg9_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg31_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg38_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg45_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg52_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Ports of Axi Slave Bus Interface S00_AXI
|
||||
sys_cpu_clk_in : in std_logic;
|
||||
s00_axi_aresetn_in : in std_logic;
|
||||
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_awprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_awvalid : in std_logic;
|
||||
s00_axi_awready : out std_logic;
|
||||
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
s00_axi_wvalid : in std_logic;
|
||||
s00_axi_wready : out std_logic;
|
||||
s00_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_bvalid : out std_logic;
|
||||
s00_axi_bready : in std_logic;
|
||||
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_arprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_arvalid : in std_logic;
|
||||
s00_axi_arready : out std_logic;
|
||||
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_rresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_rvalid : out std_logic;
|
||||
s00_axi_rready : in std_logic
|
||||
);
|
||||
end qsfp_intfc_v1_1;
|
||||
|
||||
architecture arch_imp of qsfp_intfc_v1_1 is
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
--
|
||||
signal qsfp1_reset_n : std_logic;
|
||||
signal qsfp1_modprsl : std_logic;
|
||||
signal qsfp1_intl : std_logic;
|
||||
|
||||
signal qsfp2_reset_n : std_logic;
|
||||
signal qsfp2_modprsl : std_logic;
|
||||
signal qsfp2_intl : std_logic;
|
||||
|
||||
signal qsfp3_reset_n : std_logic;
|
||||
signal qsfp3_modprsl : std_logic;
|
||||
signal qsfp3_intl : std_logic;
|
||||
|
||||
signal qsfp4_reset_n : std_logic;
|
||||
signal qsfp4_modprsl : std_logic;
|
||||
signal qsfp4_intl : std_logic;
|
||||
--
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal rx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal rx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal rx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal tx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal tx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clkin8_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clkin8_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clkin8_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal sys_cpu_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal sys_cpu_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal sys_cpu_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal ref_clk_div2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal ref_clk_div2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal ref_clk_div2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg3 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg4 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg5 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg6 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg7 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg8 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal vio_cnt_reset : std_logic;
|
||||
signal cnt_rst : std_logic;
|
||||
|
||||
|
||||
|
||||
signal s00_axi_areset : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
cnt_reset_out <= cnt_rst;--vio_cnt_reset when vio_enable = '1' else cnt_rst;
|
||||
s00_axi_areset <= not s00_axi_aresetn_in;
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
|
||||
slv_reg0_in => slv_reg0, -- 0x8000_0000
|
||||
slv_reg1_in => slv_reg1, -- 0x8000_0004
|
||||
slv_reg2_in => slv_reg2, -- 0x8000_0008
|
||||
slv_reg3_out => slv_reg3, -- 0x8000_000C
|
||||
slv_reg4_out => slv_reg4, -- 0x8000_0010
|
||||
slv_reg5_out => slv_reg5, -- 0x8000_0014
|
||||
slv_reg6_out => slv_reg6, -- 0x8000_0018
|
||||
slv_reg7_out => slv_reg7, -- 0x8000_001C
|
||||
slv_reg8_out => slv_reg8, -- 0x8000_0020
|
||||
|
||||
slv_reg9_out => slv_reg9_out, -- 0x8000_0024
|
||||
slv_reg10_out => slv_reg10_out, -- 0x8000_0028
|
||||
|
||||
slv_reg11_in => clk_125_freq_r, -- 0x8000_002C
|
||||
slv_reg12_in => clk_125_cnt_r, -- 0x8000_0030
|
||||
slv_reg13_in => clk_250_freq_r, -- 0x8000_0034
|
||||
slv_reg14_in => clk_250_cnt_r, -- 0x8000_0038
|
||||
slv_reg15_in => rx_device_clk_freq_r, -- 0x8000_003C
|
||||
slv_reg16_in => tx_device_clk_freq_r, -- 0x8000_0040
|
||||
slv_reg17_in => (others => '0'), -- 0x8000_0044
|
||||
slv_reg18_in => (others => '0'), -- 0x8000_0048
|
||||
slv_reg19_in => (others => '0'), -- 0x8000_004C
|
||||
slv_reg20_in => (others => '0'), -- 0x8000_0050
|
||||
|
||||
slv_reg21_in => (others => '0'), -- 0x8000_0054
|
||||
slv_reg22_in => (others => '0'), -- 0x8000_0058
|
||||
slv_reg23_in => (others => '0'), -- 0x8000_005C
|
||||
slv_reg24_in => (others => '0'), -- 0x8000_0060
|
||||
|
||||
slv_reg25_in => (others => '0'), -- 0x8000_0064
|
||||
slv_reg26_in => (others => '0'), -- 0x8000_0068
|
||||
slv_reg27_in => (others => '0'), -- 0x8000_006C
|
||||
slv_reg28_in => (others => '0'), -- 0x8000_0070
|
||||
slv_reg29_in => (others => '0'), -- 0x8000_0074
|
||||
slv_reg30_in => (others => '0'), -- 0x8000_0078
|
||||
slv_reg31_in => (others => '0'), -- 0x8000_007C
|
||||
|
||||
slv_reg32_in => (others => '0'), -- 0x8000_0080
|
||||
slv_reg33_in => (others => '0'), -- 0x8000_0084
|
||||
slv_reg34_in => (others => '0'), -- 0x8000_0088
|
||||
slv_reg35_in => (others => '0'), -- 0x8000_008C
|
||||
slv_reg36_in => (others => '0'), -- 0x8000_0090
|
||||
slv_reg37_in => (others => '0'), -- 0x8000_0094
|
||||
slv_reg38_in => (others => '0'), -- 0x8000_0098
|
||||
|
||||
slv_reg39_in => (others => '0'), -- 0x8000_009C
|
||||
slv_reg40_in => (others => '0'), -- 0x8000_00A0
|
||||
slv_reg41_in => (others => '0'), -- 0x8000_00A4
|
||||
slv_reg42_in => (others => '0'), -- 0x8000_00A8
|
||||
slv_reg43_in => (others => '0'), -- 0x8000_00AC
|
||||
slv_reg44_in => (others => '0'), -- 0x8000_00B0
|
||||
slv_reg45_in => (others => '0'), -- 0x8000_00B4
|
||||
|
||||
slv_reg46_in => (others => '0'), -- 0x8000_00B8
|
||||
slv_reg47_in => (others => '0'), -- 0x8000_00BC
|
||||
slv_reg48_in => (others => '0'), -- 0x8000_00C0
|
||||
slv_reg49_in => (others => '0'), -- 0x8000_00C4
|
||||
slv_reg50_in => (others => '0'), -- 0x8000_00C8
|
||||
slv_reg51_in => (others => '0'), -- 0x8000_00CC
|
||||
slv_reg52_in => (others => '0'), -- 0x8000_00D0
|
||||
|
||||
slv_reg53_in => adc_tvalid_256b_cnt_in, -- 0x8000_00D4
|
||||
slv_reg54_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00D8
|
||||
slv_reg55_in => cmac_4_tx_tvalid_512b_cnt_in, -- 0x8000_00DC
|
||||
slv_reg56_in => cmac_rx_tvalid_256b_cnt_in, -- 0x8000_00E0
|
||||
slv_reg57_in => mem_xfer_tx_upload_tvalid_256b_cnt_in,-- 0x8000_00E4
|
||||
slv_reg58_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00E8
|
||||
slv_reg59_in => cmac_4_rx_tvalid_512b_cnt_in, -- 0x8000_00EC
|
||||
slv_reg60_in => dac_tvalid_256b_cnt_in, -- 0x8000_00F0
|
||||
slv_reg61_in => (others => '0'), -- 0x8000_00F4
|
||||
slv_reg62_in => (others => '0'), -- 0x8000_00F8
|
||||
slv_reg63_in => (others => '0'), -- 0x8000_00FC
|
||||
|
||||
S_AXI_ACLK => sys_cpu_clk_in,
|
||||
S_AXI_ARESETN => s00_axi_aresetn_in,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
------------
|
||||
slv_reg0 <= fpga_revision_date_r; -- 0x8000_0000
|
||||
------------
|
||||
slv_reg1(0) <= '0';
|
||||
slv_reg1(1) <= qsfp1_modprsl;
|
||||
slv_reg1(2) <= qsfp1_intl;
|
||||
slv_reg1(3) <= '0';
|
||||
slv_reg1(4) <= '0';
|
||||
slv_reg1(5) <= qsfp2_modprsl;
|
||||
slv_reg1(6) <= qsfp2_intl;
|
||||
slv_reg1(7) <= '0';
|
||||
slv_reg1(8) <= '0';
|
||||
slv_reg1(9) <= qsfp3_modprsl;
|
||||
slv_reg1(10) <= qsfp3_intl;
|
||||
slv_reg1(11) <= '0';
|
||||
slv_reg1(12) <= '0';
|
||||
slv_reg1(13) <= qsfp4_modprsl;
|
||||
slv_reg1(14) <= qsfp4_intl;
|
||||
slv_reg1(15) <= '0';
|
||||
|
||||
slv_reg1(23 downto 16) <= (others => '0');
|
||||
slv_reg1(31 downto 24) <= minor_rev_r; -- 0x8000_0004
|
||||
------------
|
||||
slv_reg2 <= (others => '0'); -- 0x8000_0008
|
||||
------------
|
||||
--
|
||||
-- <= slv_reg3(17 downto 16);
|
||||
-- <= slv_reg3(12); -- 0x8000_0014
|
||||
-- <= slv_reg3(11 downto 0); -- 0x8000_000C
|
||||
------------
|
||||
-- <= slv_reg4(17 downto 16); -- 0x8000_0010
|
||||
------------
|
||||
qsfp1_reset_n <= slv_reg5(0); -- 0x8000_0014
|
||||
-- <= slv_reg5(3 dwonto 1);
|
||||
qsfp2_reset_n <= slv_reg5(4);
|
||||
-- <= slv_reg5(7 dwonto 5);
|
||||
qsfp3_reset_n <= slv_reg5(8);
|
||||
-- <= slv_reg5(11 dwonto 9);
|
||||
qsfp4_reset_n <= slv_reg5(12);
|
||||
-- <= slv_reg5(31 dwonto 13);
|
||||
------------
|
||||
-- <= slv_reg6(31 downto 0); -- 0x8000_0018
|
||||
------------
|
||||
-- <= slv_reg7(0); -- 0x8000_001C
|
||||
------------
|
||||
-- <= slv_reg8(0); -- 0x8000_0020
|
||||
-- <= slv_reg8(24);
|
||||
-- <= slv_reg8(28);
|
||||
cnt_rst <= slv_reg8(31);
|
||||
|
||||
QSFP1_RESETL_LS <= qsfp1_reset_n;
|
||||
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
|
||||
qsfp1_intl <= QSFP1_INTL_LS;
|
||||
-------
|
||||
|
||||
QSFP2_RESETL_LS <= qsfp2_reset_n;
|
||||
qsfp2_modprsl <= QSFP2_MODPRSL_LS;
|
||||
qsfp2_intl <= QSFP2_INTL_LS;
|
||||
-------
|
||||
|
||||
QSFP3_RESETL_LS <= qsfp3_reset_n;
|
||||
qsfp3_modprsl <= QSFP3_MODPRSL_LS;
|
||||
qsfp3_intl <= QSFP3_INTL_LS;
|
||||
-------
|
||||
|
||||
QSFP4_RESETL_LS <= qsfp4_reset_n;
|
||||
qsfp4_modprsl <= QSFP4_MODPRSL_LS;
|
||||
qsfp4_intl <= QSFP4_INTL_LS;
|
||||
|
||||
------------------------------------------------
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => sys_cpu_clk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => s00_axi_areset
|
||||
);
|
||||
|
||||
process(sys_cpu_clk_in)
|
||||
begin
|
||||
if (rising_edge(sys_cpu_clk_in)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_125_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_125_freq_r <= clk_125_cnt_r;
|
||||
clk_125_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_125_cnt_r <= clk_125_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_250_in)
|
||||
begin
|
||||
if (rising_edge(clk_250_in)) then
|
||||
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_250_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_250_freq_r <= clk_250_cnt_r;
|
||||
clk_250_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_250_cnt_r <= clk_250_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(rx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(rx_device_clk_in)) then
|
||||
rx_device_clk_tick_1ms_r <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
rx_device_clk_freq_r <= rx_device_clk_cnt_r;
|
||||
rx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
rx_device_clk_cnt_r <= rx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(tx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(tx_device_clk_in)) then
|
||||
tx_device_clk_tick_1ms_r <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
tx_device_clk_freq_r <= tx_device_clk_cnt_r;
|
||||
tx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
tx_device_clk_cnt_r <= tx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clkin8_in)
|
||||
begin
|
||||
if (rising_edge(clkin8_in)) then
|
||||
clkin8_tick_1ms_r <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clkin8_tick_1ms_r(0 to 1) = "01") then
|
||||
clkin8_freq_r <= clkin8_cnt_r;
|
||||
clkin8_cnt_r <= (others => '0');
|
||||
else
|
||||
clkin8_cnt_r <= clkin8_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(sys_cpu_clk_in)
|
||||
begin
|
||||
if (rising_edge(sys_cpu_clk_in)) then
|
||||
sys_cpu_clk_tick_1ms_r <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
sys_cpu_clk_freq_r <= sys_cpu_clk_cnt_r;
|
||||
sys_cpu_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
sys_cpu_clk_cnt_r <= sys_cpu_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(ref_clk_div2_in)
|
||||
begin
|
||||
if (rising_edge(ref_clk_div2_in)) then
|
||||
ref_clk_div2_tick_1ms_r <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then
|
||||
ref_clk_div2_freq_r <= ref_clk_div2_cnt_r;
|
||||
ref_clk_div2_cnt_r <= (others => '0');
|
||||
else
|
||||
ref_clk_div2_cnt_r <= ref_clk_div2_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user