5706 lines
297 KiB
Tcl
5706 lines
297 KiB
Tcl
#*****************************************************************************************
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# Vivado (TM) v2023.2 (64-bit)
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#
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# create_proj.tcl: Tcl script for re-creating project 'ad9082_fmca_ebz_alinx_z19'
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#
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# Generated by Vivado on Tue Jun 16 00:27:30 EDT 2026
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# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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#*****************************************************************************************
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# NOTE: In order to use this script for source control purposes, please make sure that the
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# following files are added to the source control system:-
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#
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# 1. This project restoration tcl script (create_proj.tcl) that was generated.
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#
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# <none>
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_mux_256b/axis_mux_256b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/ila_5/ila_5.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/ad_3w_spi.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/ad_iobuf.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/raw_eth_wrapper_cmac_4.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/axis_mux_chan_sel.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/global_types.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/i2c.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/i2c_st.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/tick_gen.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/Si5332/src/si5332_wrapper.vhd"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/system_raw_eth_top.v"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/system_constr.xdc"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/qsfp_constr.xdc"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/constraints/timing_constr.xdc"
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# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/sim/test_bench.vhd"
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#
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#*****************************************************************************************
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# Check file required for this script exists
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proc checkRequiredFiles { origin_dir} {
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set status true
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set files [list \
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"[file normalize "$origin_dir/source/eth_flowctrl_rx.vhd"]"\
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"[file normalize "$origin_dir/source/eth_frame_packer.vhd"]"\
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"[file normalize "$origin_dir/source/eth_flowctrl_tx.vhd"]"\
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"[file normalize "$origin_dir/source/eth_frame_unpacker.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"]"\
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"[file normalize "$origin_dir/ip_repo/axis_mux_256b/axis_mux_256b.xci"]"\
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"[file normalize "$origin_dir/ip_repo/ila_5/ila_5.xci"]"\
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"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\
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"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\
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"[file normalize "$origin_dir/source/ad_3w_spi.v"]"\
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"[file normalize "$origin_dir/source/ad_iobuf.v"]"\
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"[file normalize "$origin_dir/source/raw_eth_wrapper_cmac_4.v"]"\
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"[file normalize "$origin_dir/source/axis_mux_chan_sel.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/global_types.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/i2c.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/i2c_st.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"]"\
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"[file normalize "$origin_dir/source/tick_gen.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_clk_configurator.vhd"]"\
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"[file normalize "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"]"\
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"[file normalize "$origin_dir/source/system_raw_eth_top.v"]"\
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"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"]"\
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"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"]"\
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"[file normalize "$origin_dir/constraints/system_constr.xdc"]"\
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"[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"\
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"[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\
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"[file normalize "$origin_dir/sim/test_bench.vhd"]"\
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]
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foreach ifile $files {
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if { ![file isfile $ifile] } {
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puts " Could not find remote file $ifile "
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set status false
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}
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}
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set paths [list \
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"[file normalize "$origin_dir/[file normalize "$origin_dir/../../adi/hdl/library"]"]"\
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"[file normalize "$origin_dir/[file normalize "$origin_dir/ip_repo"]"]"\
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]
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foreach ipath $paths {
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if { ![file isdirectory $ipath] } {
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puts " Could not access $ipath "
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set status false
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}
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}
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return $status
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}
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir "."
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# Use origin directory path location variable, if specified in the tcl shell
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if { [info exists ::origin_dir_loc] } {
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set origin_dir $::origin_dir_loc
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}
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# Set the project name
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set _xil_proj_name_ "ad9082_fmca_ebz_alinx_z19"
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# Use project name variable, if specified in the tcl shell
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if { [info exists ::user_project_name] } {
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set _xil_proj_name_ $::user_project_name
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}
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variable script_file
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set script_file "create_proj.tcl"
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# Help information for this script
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proc print_help {} {
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variable script_file
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puts "\nDescription:"
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puts "Recreate a Vivado project from this script. The created project will be"
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puts "functionally equivalent to the original project for which this script was"
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puts "generated. The script contains commands for creating a project, filesets,"
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puts "runs, adding/importing sources and setting properties on various objects.\n"
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puts "Syntax:"
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puts "$script_file"
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puts "$script_file -tclargs \[--origin_dir <path>\]"
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puts "$script_file -tclargs \[--project_name <name>\]"
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puts "$script_file -tclargs \[--help\]\n"
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puts "Usage:"
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puts "Name Description"
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puts "-------------------------------------------------------------------------"
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puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
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puts " origin_dir path value is \".\", otherwise, the value"
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puts " that was set with the \"-paths_relative_to\" switch"
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puts " when this script was generated.\n"
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puts "\[--project_name <name>\] Create project with the specified name. Default"
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puts " name is the name of the project from where this"
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puts " script was generated.\n"
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puts "\[--help\] Print help information for this script"
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puts "-------------------------------------------------------------------------\n"
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exit 0
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}
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if { $::argc > 0 } {
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for {set i 0} {$i < $::argc} {incr i} {
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set option [string trim [lindex $::argv $i]]
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switch -regexp -- $option {
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"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
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"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
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"--help" { print_help }
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default {
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if { [regexp {^-} $option] } {
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puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
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return 1
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}
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}
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}
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}
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}
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize "$origin_dir/ad9082_fmca_ebz_alinx_z19"]"
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# Check for paths and files needed for project creation
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set validate_required 0
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if { $validate_required } {
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if { [checkRequiredFiles $origin_dir] } {
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puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
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} else {
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puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
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return
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}
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}
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# Create project
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create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu19eg-ffvc1760-2-i
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Reconstruct message rules
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set_msg_config -id {Vivado 12-1790} -string {{Evaluation} {features} {should} {NOT} {be} {used} {in} {production} {systems.}} -new_severity {WARNING} -ruleid {1} -source 2
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set_msg_config -id {Designutils 20-3303} -string {{HDPYFinalizeIO}} -new_severity {INFO} -ruleid {10} -source 2
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set_msg_config -id {Place 30-73} -string {{axi_spi}} -new_severity {WARNING} -ruleid {11} -source 2
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set_msg_config -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}} -new_severity {WARNING} -ruleid {12} -source 2
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set_msg_config -id {BD 41-1343} -new_severity {WARNING} -ruleid {2} -source 2
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set_msg_config -id {BD 41-1306} -new_severity {WARNING} -ruleid {3} -source 2
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set_msg_config -id {BD 41-1276} -severity {CRITICAL WARNING} -new_severity {ERROR} -ruleid {4} -source 2
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set_msg_config -id {IP_Flow 19-3656} -new_severity {INFO} -ruleid {5} -source 2
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set_msg_config -id {IP_Flow 19-4623} -new_severity {INFO} -ruleid {6} -source 2
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set_msg_config -id {IP_Flow 19-459} -new_severity {INFO} -ruleid {7} -source 2
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set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2
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set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2
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# Set project properties
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set obj [current_project]
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set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
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set_property -name "enable_resource_estimation" -value "0" -objects $obj
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set_property -name "enable_vhdl_2008" -value "1" -objects $obj
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set_property -name "feature_set" -value "FeatureSet_Classic" -objects $obj
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set_property -name "ip_cache_permissions" -value "read write" -objects $obj
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set_property -name "ip_output_repo" -value "/home/nsantana/adi/hdl/ipcache" -objects $obj
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set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
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set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj
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set_property -name "revised_directory_structure" -value "1" -objects $obj
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set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
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set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
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set_property -name "simulator_language" -value "Mixed" -objects $obj
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set_property -name "sim_compile_state" -value "1" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.questa_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.riviera_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.vcs_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
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set_property -name "webtalk.xsim_export_sim" -value "51" -objects $obj
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set_property -name "webtalk.xsim_launch_sim" -value "4" -objects $obj
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set_property -name "xpm_libraries" -value "XPM_CDC XPM_COMP_DECL XPM_FIFO XPM_MEMORY" -objects $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set IP repository paths
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set obj [get_filesets sources_1]
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if { $obj != {} } {
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set_property "ip_repo_paths" "[file normalize "$origin_dir/../../adi/hdl/library"] [file normalize "$origin_dir/ip_repo"]" $obj
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# Rebuild user ip_repo's index before adding any source files
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update_ip_catalog -rebuild
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}
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "${origin_dir}/source/eth_flowctrl_rx.vhd"] \
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[file normalize "${origin_dir}/source/eth_frame_packer.vhd"] \
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[file normalize "${origin_dir}/source/eth_flowctrl_tx.vhd"] \
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[file normalize "${origin_dir}/source/eth_frame_unpacker.vhd"] \
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[file normalize "${origin_dir}/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"] \
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[file normalize "${origin_dir}/ip_repo/axis_mux_256b/axis_mux_256b.xci"] \
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[file normalize "${origin_dir}/ip_repo/ila_5/ila_5.xci"] \
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[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \
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[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \
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[file normalize "${origin_dir}/source/ad_3w_spi.v"] \
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[file normalize "${origin_dir}/source/ad_iobuf.v"] \
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[file normalize "${origin_dir}/source/raw_eth_wrapper_cmac_4.v"] \
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[file normalize "${origin_dir}/source/axis_mux_chan_sel.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/global_types.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_gen_cfg.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/i2c.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/i2c_st.vhd"] \
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[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"] \
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[file normalize "${origin_dir}/source/tick_gen.vhd"] \
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[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_clk_configurator.vhd"] \
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[file normalize "${origin_dir}/ip_repo/Si5332/src/si5332_wrapper.vhd"] \
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[file normalize "${origin_dir}/source/system_raw_eth_top.v"] \
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[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"] \
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[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"] \
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]
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add_files -norecurse -fileset $obj $files
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# Set 'sources_1' fileset file properties for remote files
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set file "$origin_dir/source/eth_flowctrl_rx.vhd"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "VHDL" -objects $file_obj
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set file "$origin_dir/source/eth_frame_packer.vhd"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "VHDL" -objects $file_obj
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set file "$origin_dir/source/eth_flowctrl_tx.vhd"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "file_type" -value "VHDL" -objects $file_obj
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|
|
|
set file "$origin_dir/source/eth_frame_unpacker.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_mux_256b/axis_mux_256b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/ila_5/ila_5.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/source/axis_mux_chan_sel.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/global_types.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/i2c.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/i2c_st.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/source/tick_gen.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
|
|
# Set 'sources_1' fileset file properties for local files
|
|
# None
|
|
|
|
# Set 'sources_1' fileset properties
|
|
set obj [get_filesets sources_1]
|
|
set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
|
|
set_property -name "generic" -value "JESD_MODE=8B10B RX_LANE_RATE=15 TX_LANE_RATE=15 RX_JESD_M=4 RX_JESD_L=8 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=4 TX_JESD_L=8 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH" -objects $obj
|
|
set_property -name "top" -value "system_raw_eth_top" -objects $obj
|
|
set_property -name "top_auto_set" -value "0" -objects $obj
|
|
set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=15 TX_LANE_RATE=15 RX_JESD_M=4 RX_JESD_L=8 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=4 TX_JESD_L=8 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH" -objects $obj
|
|
|
|
# Create 'constrs_1' fileset (if not found)
|
|
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
|
create_fileset -constrset constrs_1
|
|
}
|
|
|
|
# Set 'constrs_1' fileset object
|
|
set obj [get_filesets constrs_1]
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/system_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/system_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/qsfp_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/timing_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/timing_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Set 'constrs_1' fileset properties
|
|
set obj [get_filesets constrs_1]
|
|
set_property -name "target_part" -value "xczu19eg-ffvc1760-2-i" -objects $obj
|
|
|
|
# Create 'sim_1' fileset (if not found)
|
|
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
|
create_fileset -simset sim_1
|
|
}
|
|
|
|
# Set 'sim_1' fileset object
|
|
set obj [get_filesets sim_1]
|
|
set files [list \
|
|
[file normalize "${origin_dir}/sim/test_bench.vhd"] \
|
|
]
|
|
add_files -norecurse -fileset $obj $files
|
|
|
|
# Set 'sim_1' fileset file properties for remote files
|
|
set file "$origin_dir/sim/test_bench.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
|
|
# Set 'sim_1' fileset file properties for local files
|
|
# None
|
|
|
|
# Set 'sim_1' fileset properties
|
|
set obj [get_filesets sim_1]
|
|
set_property -name "top" -value "test_bench" -objects $obj
|
|
set_property -name "top_auto_set" -value "0" -objects $obj
|
|
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
|
|
|
# Set 'utils_1' fileset object
|
|
set obj [get_filesets utils_1]
|
|
# Empty (no sources present)
|
|
|
|
# Set 'utils_1' fileset properties
|
|
set obj [get_filesets utils_1]
|
|
|
|
|
|
# Adding sources referenced in BDs, if not already added
|
|
if { [get_files [list eth_flowctrl_rx.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
|
}
|
|
if { [get_files [list eth_frame_packer.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
|
}
|
|
if { [get_files [list eth_flowctrl_tx.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
|
}
|
|
if { [get_files [list eth_frame_unpacker.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
|
}
|
|
|
|
|
|
# Proc to create BD raw_eth_cmac_4
|
|
proc cr_bd_raw_eth_cmac_4 { parentCell } {
|
|
# The design that will be created by this Tcl proc contains the following
|
|
# module references:
|
|
# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker
|
|
|
|
|
|
|
|
# CHANGE DESIGN NAME HERE
|
|
set design_name raw_eth_cmac_4
|
|
|
|
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
|
|
create_bd_design $design_name
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:axis_register_slice:1.1\
|
|
xilinx.com:ip:axis_subset_converter:1.1\
|
|
xilinx.com:ip:axis_data_fifo:2.0\
|
|
xilinx.com:ip:cmac_usplus:3.1\
|
|
xilinx.com:ip:system_ila:1.1\
|
|
xilinx.com:ip:util_vector_logic:2.0\
|
|
xilinx.com:ip:c_counter_binary:12.0\
|
|
xilinx.com:ip:smartconnect:1.0\
|
|
xilinx.com:ip:proc_sys_reset:5.0\
|
|
user:user:axi_regs_32:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
xilinx.com:ip:xlconcat:2.1\
|
|
xilinx.com:ip:xpm_cdc_gen:1.0\
|
|
xilinx.com:ip:xlconstant:1.1\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
##################################################################
|
|
# CHECK Modules
|
|
##################################################################
|
|
set bCheckModules 1
|
|
if { $bCheckModules == 1 } {
|
|
set list_check_mods "\
|
|
eth_flowctrl_rx\
|
|
eth_frame_packer\
|
|
eth_flowctrl_tx\
|
|
eth_frame_unpacker\
|
|
"
|
|
|
|
set list_mods_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
|
|
|
foreach mod_vlnv $list_check_mods {
|
|
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
|
lappend list_mods_missing $mod_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_mods_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
|
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
|
set bCheckIPsPassed 0
|
|
}
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
|
|
# Hierarchical cell: ETH_regs
|
|
proc create_hier_cell_ETH_regs { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -from 47 -to 0 dest_addr
|
|
create_bd_pin -dir O -from 47 -to 0 source_addr
|
|
create_bd_pin -dir O -from 15 -to 0 EtherType
|
|
create_bd_pin -dir I cmac_clk
|
|
create_bd_pin -dir I aclk
|
|
create_bd_pin -dir I aresetn
|
|
create_bd_pin -dir O -from 0 -to 0 prog_full_manual
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_on
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_off
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt
|
|
|
|
# Create instance: axi_regs_32_0, and set properties
|
|
set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ]
|
|
|
|
# Create instance: xlslice_0, and set properties
|
|
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_0
|
|
|
|
|
|
# Create instance: xlconcat_0, and set properties
|
|
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_0
|
|
|
|
|
|
# Create instance: xlconcat_1, and set properties
|
|
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_1
|
|
|
|
|
|
# Create instance: xlslice_1, and set properties
|
|
set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_1
|
|
|
|
|
|
# Create instance: xlslice_2, and set properties
|
|
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_2
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_0, and set properties
|
|
set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_0
|
|
|
|
|
|
# Create instance: const_1b0, and set properties
|
|
set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ]
|
|
set_property CONFIG.CONST_VAL {0} $const_1b0
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_1, and set properties
|
|
set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_1
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_2, and set properties
|
|
set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {16} \
|
|
] $xpm_cdc_gen_2
|
|
|
|
|
|
# Create instance: const_32b0, and set properties
|
|
set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {32} \
|
|
] $const_32b0
|
|
|
|
|
|
# Create instance: xlslice_3, and set properties
|
|
set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ]
|
|
set_property CONFIG.DIN_FROM {0} $xlslice_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_3, and set properties
|
|
set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {1} \
|
|
] $xpm_cdc_gen_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_4, and set properties
|
|
set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_4
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_5, and set properties
|
|
set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_5
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_16, and set properties
|
|
set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_16
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_17, and set properties
|
|
set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_17
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_18, and set properties
|
|
set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_18
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_19, and set properties
|
|
set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_19
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_20, and set properties
|
|
set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_20
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_21, and set properties
|
|
set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_21
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_22, and set properties
|
|
set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_22
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk]
|
|
connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN]
|
|
connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in]
|
|
connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in]
|
|
connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in]
|
|
connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in]
|
|
connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in]
|
|
connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in]
|
|
connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in]
|
|
connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in]
|
|
connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk]
|
|
connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk]
|
|
connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in]
|
|
connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in]
|
|
connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in]
|
|
connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in]
|
|
connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in]
|
|
connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in]
|
|
connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in]
|
|
connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in]
|
|
connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in]
|
|
connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in]
|
|
connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1]
|
|
connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1]
|
|
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in]
|
|
connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in]
|
|
connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr]
|
|
connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in]
|
|
connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in]
|
|
connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr]
|
|
connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in]
|
|
connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in]
|
|
connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in]
|
|
connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType]
|
|
connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual]
|
|
connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on]
|
|
connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off]
|
|
connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in]
|
|
connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: Ethernet
|
|
proc create_hier_cell_Ethernet { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -type clk axis_aclk
|
|
create_bd_pin -dir O -from 0 -to 0 axis_aresetn
|
|
create_bd_pin -dir I -type clk axil_clk
|
|
create_bd_pin -dir I clk_100_reset
|
|
create_bd_pin -dir I clk_100
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt
|
|
create_bd_pin -dir I -type rst axil_resetn
|
|
create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow
|
|
|
|
# Create instance: eth_flowctrl_rx_i, and set properties
|
|
set block_name eth_flowctrl_rx
|
|
set block_cell_name eth_flowctrl_rx_i
|
|
if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_rx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: cmac_usplus_i, and set properties
|
|
set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CMAC_CAUI4_MODE {1} \
|
|
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y2} \
|
|
CONFIG.ENABLE_AXI_INTERFACE {1} \
|
|
CONFIG.ENABLE_PIPELINE_REG {1} \
|
|
CONFIG.GT_GROUP_SELECT {X0Y16~X0Y19} \
|
|
CONFIG.GT_REF_CLK_FREQ {156.25} \
|
|
CONFIG.RX_CHECK_ACK {0} \
|
|
CONFIG.RX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_SA_GPP {0x000000000000} \
|
|
CONFIG.TX_SA_PPP {0x000000000000} \
|
|
CONFIG.USER_INTERFACE {AXIS} \
|
|
] $cmac_usplus_i
|
|
|
|
|
|
# Create instance: eth_frame_packer_i, and set properties
|
|
set block_name eth_frame_packer
|
|
set block_cell_name eth_frame_packer_i
|
|
if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_packer_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_flowctrl_tx_i, and set properties
|
|
set block_name eth_flowctrl_tx
|
|
set block_cell_name eth_flowctrl_tx_i
|
|
if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_tx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_frame_unpacker_i, and set properties
|
|
set block_name eth_frame_unpacker
|
|
set block_cell_name eth_frame_unpacker_i
|
|
if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_unpacker_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: system_ila_i, and set properties
|
|
set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_MON_TYPE {MIX} \
|
|
CONFIG.C_NUM_MONITOR_SLOTS {6} \
|
|
CONFIG.C_NUM_OF_PROBES {20} \
|
|
CONFIG.C_SLOT {5} \
|
|
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
] $system_ila_i
|
|
|
|
|
|
# Create instance: ETH_regs
|
|
create_hier_cell_ETH_regs $hier_obj ETH_regs
|
|
|
|
# Create instance: rst_inv_i, and set properties
|
|
set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rst_inv_i
|
|
|
|
|
|
# Create instance: counter_i, and set properties
|
|
set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CE {true} \
|
|
CONFIG.Fb_Latency_Configuration {Automatic} \
|
|
CONFIG.Latency_Configuration {Automatic} \
|
|
CONFIG.Load {false} \
|
|
CONFIG.Load_Sense {Active_High} \
|
|
CONFIG.Output_Width {32} \
|
|
CONFIG.Restrict_Count {false} \
|
|
CONFIG.SCLR {true} \
|
|
CONFIG.SSET {false} \
|
|
CONFIG.Sync_Threshold_Output {false} \
|
|
] $counter_i
|
|
|
|
|
|
# Create instance: smartcon_i, and set properties
|
|
set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {2} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $smartcon_i
|
|
|
|
|
|
# Create instance: proc_sys_reset_0, and set properties
|
|
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL]
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI]
|
|
connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk]
|
|
connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS]
|
|
connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI]
|
|
connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off]
|
|
connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on]
|
|
connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk]
|
|
connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn]
|
|
connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk]
|
|
connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset]
|
|
connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in]
|
|
connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn]
|
|
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt]
|
|
connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0]
|
|
connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins system_ila_i/probe16] [get_bd_pins eth_flowctrl_rx_i/rx_pause]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins system_ila_i/probe17] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8]
|
|
connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt]
|
|
connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9]
|
|
connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8]
|
|
connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins system_ila_i/probe15]
|
|
connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14]
|
|
connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19]
|
|
connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13]
|
|
connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18]
|
|
connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type]
|
|
connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac]
|
|
connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac]
|
|
connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt]
|
|
connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE]
|
|
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR]
|
|
connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual]
|
|
connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset]
|
|
connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: srl2
|
|
proc create_hier_cell_srl2 { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_srl2() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk axis_clk
|
|
create_bd_pin -dir I -type rst axis_resetn
|
|
create_bd_pin -dir I -type clk axil_clk
|
|
create_bd_pin -dir I -type rst axil_resetn
|
|
create_bd_pin -dir I clk_100
|
|
create_bd_pin -dir I clk_100_reset
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst aresetn_0
|
|
|
|
# Create instance: axis_reg_0_i, and set properties
|
|
set axis_reg_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_0_i ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $axis_reg_0_i
|
|
|
|
|
|
# Create instance: axis_ss_conv_0_i, and set properties
|
|
set axis_ss_conv_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_0_i ]
|
|
set_property -dict [list \
|
|
CONFIG.DEFAULT_TLAST {16} \
|
|
CONFIG.M_HAS_TKEEP {0} \
|
|
CONFIG.M_HAS_TLAST {1} \
|
|
CONFIG.M_HAS_TREADY {1} \
|
|
CONFIG.M_HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.M_TDEST_WIDTH {0} \
|
|
CONFIG.M_TID_WIDTH {0} \
|
|
CONFIG.M_TUSER_WIDTH {0} \
|
|
CONFIG.S_HAS_TKEEP {0} \
|
|
CONFIG.S_HAS_TLAST {0} \
|
|
CONFIG.S_HAS_TREADY {1} \
|
|
CONFIG.S_HAS_TSTRB {0} \
|
|
CONFIG.S_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDEST_WIDTH {0} \
|
|
CONFIG.S_TID_WIDTH {0} \
|
|
CONFIG.S_TUSER_WIDTH {0} \
|
|
] $axis_ss_conv_0_i
|
|
|
|
|
|
# Create instance: cmac_rx_fifo_i, and set properties
|
|
set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ]
|
|
set_property -dict [list \
|
|
CONFIG.FIFO_DEPTH {8192} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.HAS_WR_DATA_COUNT {1} \
|
|
CONFIG.IS_ACLK_ASYNC {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $cmac_rx_fifo_i
|
|
|
|
|
|
# Create instance: axis_ss_conv_1_i, and set properties
|
|
set axis_ss_conv_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_1_i ]
|
|
set_property -dict [list \
|
|
CONFIG.M_HAS_TKEEP {0} \
|
|
CONFIG.M_HAS_TLAST {0} \
|
|
CONFIG.M_HAS_TREADY {1} \
|
|
CONFIG.M_HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.M_TDEST_WIDTH {0} \
|
|
CONFIG.M_TID_WIDTH {0} \
|
|
CONFIG.M_TUSER_WIDTH {0} \
|
|
CONFIG.S_HAS_TKEEP {0} \
|
|
CONFIG.S_HAS_TLAST {1} \
|
|
CONFIG.S_HAS_TREADY {0} \
|
|
CONFIG.S_HAS_TSTRB {0} \
|
|
CONFIG.S_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDEST_WIDTH {0} \
|
|
CONFIG.S_TID_WIDTH {0} \
|
|
CONFIG.S_TUSER_WIDTH {1} \
|
|
] $axis_ss_conv_1_i
|
|
|
|
|
|
# Create instance: axis_reg_1_i, and set properties
|
|
set axis_reg_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_1_i ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $axis_reg_1_i
|
|
|
|
|
|
# Create instance: cmac_tx_fifo_i, and set properties
|
|
set cmac_tx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_tx_fifo_i ]
|
|
set_property -dict [list \
|
|
CONFIG.FIFO_DEPTH {32} \
|
|
CONFIG.FIFO_MODE {2} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.IS_ACLK_ASYNC {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $cmac_tx_fifo_i
|
|
|
|
|
|
# Create instance: Ethernet
|
|
create_hier_cell_Ethernet $hier_obj Ethernet
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Ethernet_M_AXIS [get_bd_intf_pins Ethernet/M_AXIS] [get_bd_intf_pins axis_ss_conv_1_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net Ethernet_cmac_gt [get_bd_intf_pins cmac_gt] [get_bd_intf_pins Ethernet/cmac_gt]
|
|
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins cmac_rx_fifo_i/M_AXIS] [get_bd_intf_pins axis_reg_1_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_reg_1_i_M_AXIS [get_bd_intf_pins m_axis] [get_bd_intf_pins axis_reg_1_i/M_AXIS]
|
|
connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_reg_0_i/M_AXIS] [get_bd_intf_pins axis_ss_conv_0_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_ss_conv_0_i_M_AXIS [get_bd_intf_pins axis_ss_conv_0_i/M_AXIS] [get_bd_intf_pins cmac_tx_fifo_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS1 [get_bd_intf_pins axis_ss_conv_1_i/M_AXIS] [get_bd_intf_pins cmac_rx_fifo_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_refclk_1 [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins Ethernet/cmac_refclk]
|
|
connect_bd_intf_net -intf_net cmac_tx_fifo_i_M_AXIS [get_bd_intf_pins cmac_tx_fifo_i/M_AXIS] [get_bd_intf_pins Ethernet/S_AXIS]
|
|
connect_bd_intf_net -intf_net s_axil_1 [get_bd_intf_pins s_axil] [get_bd_intf_pins Ethernet/S_AXIL]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins axis_reg_0_i/S_AXIS]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net Ethernet_axis_aclk [get_bd_pins Ethernet/axis_aclk] [get_bd_pins axis_ss_conv_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/s_axis_aclk] [get_bd_pins cmac_tx_fifo_i/m_axis_aclk]
|
|
connect_bd_net -net Ethernet_axis_aresetn [get_bd_pins Ethernet/axis_aresetn] [get_bd_pins cmac_rx_fifo_i/s_axis_aresetn] [get_bd_pins axis_ss_conv_1_i/aresetn]
|
|
connect_bd_net -net Net [get_bd_pins m_axis_aclk] [get_bd_pins axis_reg_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/m_axis_aclk]
|
|
connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins axis_reg_1_i/aresetn]
|
|
connect_bd_net -net clk_100_1 [get_bd_pins clk_100] [get_bd_pins Ethernet/clk_100]
|
|
connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset] [get_bd_pins Ethernet/clk_100_reset]
|
|
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins cmac_rx_fifo_i/axis_wr_data_count] [get_bd_pins Ethernet/rx_fifo_wr_data_cnt]
|
|
connect_bd_net -net cmac_rx_overflow [get_bd_pins axis_ss_conv_1_i/transfer_dropped] [get_bd_pins Ethernet/rx_fifo_overflow]
|
|
connect_bd_net -net s_axi_sreset_1 [get_bd_pins axil_resetn] [get_bd_pins Ethernet/axil_resetn]
|
|
connect_bd_net -net s_axilite_dsp_clk [get_bd_pins axil_clk] [get_bd_pins Ethernet/axil_clk]
|
|
connect_bd_net -net s_axis_dsp_clk [get_bd_pins axis_clk] [get_bd_pins axis_reg_0_i/aclk] [get_bd_pins axis_ss_conv_0_i/aclk] [get_bd_pins cmac_tx_fifo_i/s_axis_aclk]
|
|
connect_bd_net -net s_axis_dsp_resetn [get_bd_pins axis_resetn] [get_bd_pins axis_reg_0_i/aresetn] [get_bd_pins axis_ss_conv_0_i/aresetn] [get_bd_pins cmac_tx_fifo_i/s_axis_aresetn]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: hier_0
|
|
proc create_hier_cell_hier_0 { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hier_0() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk axis_clk_0
|
|
create_bd_pin -dir I -type rst axis_resetn_0
|
|
create_bd_pin -dir I -type clk axil_clk_0
|
|
create_bd_pin -dir I -type rst axil_resetn_0
|
|
create_bd_pin -dir I clk_100_0
|
|
create_bd_pin -dir I clk_100_reset_0
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst aresetn_0
|
|
|
|
# Create instance: srl2
|
|
create_hier_cell_srl2 $hier_obj srl2
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins srl2/cmac_gt] [get_bd_intf_pins cmac_gt_0]
|
|
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins srl2/m_axis] [get_bd_intf_pins m_axis_0]
|
|
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins srl2/s_axil] [get_bd_intf_pins s_axil_0]
|
|
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins srl2/s_axis] [get_bd_intf_pins s_axis_0]
|
|
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins srl2/cmac_refclk] [get_bd_intf_pins cmac_refclk_0]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins srl2/aresetn_0]
|
|
connect_bd_net -net axil_clk_1 [get_bd_pins axil_clk_0] [get_bd_pins srl2/axil_clk]
|
|
connect_bd_net -net axil_resetn_1 [get_bd_pins axil_resetn_0] [get_bd_pins srl2/axil_resetn]
|
|
connect_bd_net -net axis_clk_1 [get_bd_pins axis_clk_0] [get_bd_pins srl2/axis_clk]
|
|
connect_bd_net -net axis_resetn_1 [get_bd_pins axis_resetn_0] [get_bd_pins srl2/axis_resetn]
|
|
connect_bd_net -net clk_100_1 [get_bd_pins clk_100_0] [get_bd_pins srl2/clk_100]
|
|
connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset_0] [get_bd_pins srl2/clk_100_reset]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins srl2/m_axis_aclk]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
set cmac_gt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 ]
|
|
|
|
set m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {375000000} \
|
|
] $m_axis
|
|
|
|
set s_axil_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.ARUSER_WIDTH {0} \
|
|
CONFIG.AWUSER_WIDTH {0} \
|
|
CONFIG.BUSER_WIDTH {0} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.HAS_BRESP {1} \
|
|
CONFIG.HAS_BURST {1} \
|
|
CONFIG.HAS_CACHE {1} \
|
|
CONFIG.HAS_LOCK {1} \
|
|
CONFIG.HAS_PROT {1} \
|
|
CONFIG.HAS_QOS {1} \
|
|
CONFIG.HAS_REGION {1} \
|
|
CONFIG.HAS_RRESP {1} \
|
|
CONFIG.HAS_WSTRB {1} \
|
|
CONFIG.ID_WIDTH {0} \
|
|
CONFIG.MAX_BURST_LENGTH {1} \
|
|
CONFIG.NUM_READ_OUTSTANDING {1} \
|
|
CONFIG.NUM_READ_THREADS {1} \
|
|
CONFIG.NUM_WRITE_OUTSTANDING {1} \
|
|
CONFIG.NUM_WRITE_THREADS {1} \
|
|
CONFIG.PROTOCOL {AXI4LITE} \
|
|
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
|
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
|
CONFIG.RUSER_WIDTH {0} \
|
|
CONFIG.SUPPORTS_NARROW_BURST {0} \
|
|
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
|
CONFIG.WUSER_WIDTH {0} \
|
|
] $s_axil_0
|
|
|
|
set s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {375000000} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.LAYERED_METADATA {undef} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $s_axis
|
|
|
|
set cmac_refclk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {156250000} \
|
|
] $cmac_refclk_0
|
|
|
|
|
|
# Create ports
|
|
set s_axis_clk [ create_bd_port -dir I -type clk -freq_hz 375000000 s_axis_clk ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {s_axis} \
|
|
CONFIG.ASSOCIATED_RESET {s_axis_aresetn} \
|
|
] $s_axis_clk
|
|
set s_axis_aresetn [ create_bd_port -dir I -type rst s_axis_aresetn ]
|
|
set axil_clk_0 [ create_bd_port -dir I -type clk axil_clk_0 ]
|
|
set axil_resetn_0 [ create_bd_port -dir I -type rst axil_resetn_0 ]
|
|
set clk_100_0 [ create_bd_port -dir I clk_100_0 ]
|
|
set clk_100_reset_0 [ create_bd_port -dir I clk_100_reset_0 ]
|
|
set m_axis_aclk [ create_bd_port -dir I -type clk -freq_hz 375000000 m_axis_aclk ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {m_axis} \
|
|
CONFIG.ASSOCIATED_RESET {m_axis_aresetn} \
|
|
CONFIG.CLK_DOMAIN {raw_eth_cmac_4_axis_clk_0} \
|
|
] $m_axis_aclk
|
|
set m_axis_aresetn [ create_bd_port -dir I -type rst m_axis_aresetn ]
|
|
|
|
# Create instance: hier_0
|
|
create_hier_cell_hier_0 [current_bd_instance .] hier_0
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net cmac_refclk_0_1 [get_bd_intf_ports cmac_refclk_0] [get_bd_intf_pins hier_0/cmac_refclk_0]
|
|
connect_bd_intf_net -intf_net hier_0_cmac_gt_0 [get_bd_intf_ports cmac_gt_0] [get_bd_intf_pins hier_0/cmac_gt_0]
|
|
connect_bd_intf_net -intf_net hier_0_m_axis_0 [get_bd_intf_ports m_axis] [get_bd_intf_pins hier_0/m_axis_0]
|
|
connect_bd_intf_net -intf_net s_axil_0_1 [get_bd_intf_ports s_axil_0] [get_bd_intf_pins hier_0/s_axil_0]
|
|
connect_bd_intf_net -intf_net s_axis_0_1 [get_bd_intf_ports s_axis] [get_bd_intf_pins hier_0/s_axis_0]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aresetn_0_1 [get_bd_ports m_axis_aresetn] [get_bd_pins hier_0/aresetn_0]
|
|
connect_bd_net -net axil_clk_0_1 [get_bd_ports axil_clk_0] [get_bd_pins hier_0/axil_clk_0]
|
|
connect_bd_net -net axil_resetn_0_1 [get_bd_ports axil_resetn_0] [get_bd_pins hier_0/axil_resetn_0]
|
|
connect_bd_net -net axis_clk_0_1 [get_bd_ports s_axis_clk] [get_bd_pins hier_0/axis_clk_0]
|
|
connect_bd_net -net axis_resetn_0_1 [get_bd_ports s_axis_aresetn] [get_bd_pins hier_0/axis_resetn_0]
|
|
connect_bd_net -net clk_100_0_1 [get_bd_ports clk_100_0] [get_bd_pins hier_0/clk_100_0]
|
|
connect_bd_net -net clk_100_reset_0_1 [get_bd_ports clk_100_reset_0] [get_bd_pins hier_0/clk_100_reset_0]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_ports m_axis_aclk] [get_bd_pins hier_0/m_axis_aclk]
|
|
|
|
# Create address segments
|
|
assign_bd_address -offset 0x82000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force
|
|
assign_bd_address -offset 0x82010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force
|
|
|
|
# Perform GUI Layout
|
|
regenerate_bd_layout -layout_string {
|
|
"ActiveEmotionalView":"Default View",
|
|
"Default View_ScaleFactor":"1.0",
|
|
"Default View_TopLeft":"2611,887",
|
|
"ExpandedHierarchyInLayout":"/hier_0|/hier_0/srl2|/hier_0/srl2/Ethernet",
|
|
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
|
# -string -flagsOSRD
|
|
preplace port cmac_gt_0 -pg 1 -lvl 2 -x 5180 -y 150 -defaultsOSRD
|
|
preplace port m_axis -pg 1 -lvl 2 -x 5180 -y 170 -defaultsOSRD
|
|
preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
|
preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
|
|
preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
|
preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
|
|
preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
|
|
preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
|
|
preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
|
|
preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD
|
|
preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
|
|
preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
|
preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
|
|
preplace inst hier_0 -pg 1 -lvl 1 -x 360 -y 162 -defaultsOSRD
|
|
preplace inst hier_0|srl2 -pg 1 -lvl 1 -x 600 -y 194 -defaultsOSRD
|
|
preplace inst hier_0|srl2|axis_reg_0_i -pg 1 -lvl 1 -x 670 -y 144 -defaultsOSRD
|
|
preplace inst hier_0|srl2|axis_ss_conv_0_i -pg 1 -lvl 2 -x 950 -y 164 -defaultsOSRD
|
|
preplace inst hier_0|srl2|cmac_rx_fifo_i -pg 1 -lvl 6 -x 4480 -y 564 -defaultsOSRD
|
|
preplace inst hier_0|srl2|axis_ss_conv_1_i -pg 1 -lvl 5 -x 4100 -y 544 -defaultsOSRD
|
|
preplace inst hier_0|srl2|axis_reg_1_i -pg 1 -lvl 7 -x 4780 -y 574 -defaultsOSRD
|
|
preplace inst hier_0|srl2|cmac_tx_fifo_i -pg 1 -lvl 3 -x 1250 -y 194 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet -pg 1 -lvl 4 -x 1740 -y 326 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|eth_flowctrl_rx_i -pg 1 -lvl 1 -x 1910 -y 1366 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|cmac_usplus_i -pg 1 -lvl 2 -x 2550 -y 1096 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|eth_frame_packer_i -pg 1 -lvl 1 -x 1910 -y 336 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|eth_flowctrl_tx_i -pg 1 -lvl 1 -x 1910 -y 606 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|eth_frame_unpacker_i -pg 1 -lvl 3 -x 3070 -y 1366 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|system_ila_i -pg 1 -lvl 4 -x 3550 -y 1186 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|ETH_regs -pg 1 -lvl 2 -x 2550 -y 656 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|rst_inv_i -pg 1 -lvl 1 -x 1910 -y 1056 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|counter_i -pg 1 -lvl 1 -x 1910 -y 1176 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|smartcon_i -pg 1 -lvl 1 -x 1910 -y 806 -defaultsOSRD
|
|
preplace inst hier_0|srl2|Ethernet|proc_sys_reset_0 -pg 1 -lvl 3 -x 3070 -y 1166 -defaultsOSRD
|
|
preplace netloc aresetn_0_1 1 0 1 20J 260n
|
|
preplace netloc axil_clk_0_1 1 0 1 70J 160n
|
|
preplace netloc axil_resetn_0_1 1 0 1 60J 180n
|
|
preplace netloc axis_clk_0_1 1 0 1 90J 120n
|
|
preplace netloc axis_resetn_0_1 1 0 1 80J 140n
|
|
preplace netloc clk_100_0_1 1 0 1 50J 200n
|
|
preplace netloc clk_100_reset_0_1 1 0 1 40J 220n
|
|
preplace netloc m_axis_aclk_1 1 0 1 30J 240n
|
|
preplace netloc cmac_refclk_0_1 1 0 1 100J 100n
|
|
preplace netloc hier_0_cmac_gt_0 1 1 1 5150J 150n
|
|
preplace netloc hier_0_m_axis_0 1 1 1 5160J 170n
|
|
preplace netloc s_axil_0_1 1 0 1 120J 60n
|
|
preplace netloc s_axis_0_1 1 0 1 110J 80n
|
|
preplace netloc hier_0|aresetn_0_1 1 0 1 280 292n
|
|
preplace netloc hier_0|axil_clk_1 1 0 1 330 192n
|
|
preplace netloc hier_0|axil_resetn_1 1 0 1 320 212n
|
|
preplace netloc hier_0|axis_clk_1 1 0 1 350 152n
|
|
preplace netloc hier_0|axis_resetn_1 1 0 1 340 172n
|
|
preplace netloc hier_0|clk_100_1 1 0 1 310 232n
|
|
preplace netloc hier_0|clk_100_reset_1 1 0 1 300 252n
|
|
preplace netloc hier_0|m_axis_aclk_1 1 0 1 290 272n
|
|
preplace netloc hier_0|Conn1 1 1 1 5010 182n
|
|
preplace netloc hier_0|Conn2 1 1 1 5020 202n
|
|
preplace netloc hier_0|Conn3 1 0 1 380 92n
|
|
preplace netloc hier_0|Conn4 1 0 1 370 112n
|
|
preplace netloc hier_0|Conn5 1 0 1 360 132n
|
|
preplace netloc hier_0|srl2|Ethernet_axis_aclk 1 2 4 1130 474 1370J 1598 3900 644 4310J
|
|
preplace netloc hier_0|srl2|Ethernet_axis_aresetn 1 4 2 3890 634 4290J
|
|
preplace netloc hier_0|srl2|Net 1 0 7 NJ 454 NJ 454 NJ 454 1400J 1578 3860J 454 4300 474 4660
|
|
preplace netloc hier_0|srl2|aresetn_0_1 1 0 7 NJ 474 NJ 474 1110J 464 1380J 1588 3880J 464 NJ 464 4670
|
|
preplace netloc hier_0|srl2|clk_100_1 1 0 4 NJ 404 NJ 404 NJ 404 1410
|
|
preplace netloc hier_0|srl2|clk_100_reset_1 1 0 4 530J 484 NJ 484 NJ 484 1390
|
|
preplace netloc hier_0|srl2|cmac_rx_fifo_i_axis_wr_data_count 1 3 4 1440 1778 3920J 654 NJ 654 4650
|
|
preplace netloc hier_0|srl2|cmac_rx_overflow 1 3 3 1460 1748 3910J 624 4280
|
|
preplace netloc hier_0|srl2|s_axi_sreset_1 1 0 4 NJ 384 NJ 384 NJ 384 1420
|
|
preplace netloc hier_0|srl2|s_axilite_dsp_clk 1 0 4 NJ 364 NJ 364 NJ 364 1430
|
|
preplace netloc hier_0|srl2|s_axis_dsp_clk 1 0 3 540 314 780 254 1120J
|
|
preplace netloc hier_0|srl2|s_axis_dsp_resetn 1 0 3 560 324 790 244 1110J
|
|
preplace netloc hier_0|srl2|Ethernet_M_AXIS 1 4 1 3870 524n
|
|
preplace netloc hier_0|srl2|Ethernet_cmac_gt 1 4 4 3850 294 NJ 294 NJ 294 NJ
|
|
preplace netloc hier_0|srl2|axis_data_fifo_0_M_AXIS 1 6 1 N 554
|
|
preplace netloc hier_0|srl2|axis_reg_1_i_M_AXIS 1 7 1 N 574
|
|
preplace netloc hier_0|srl2|axis_register_slice_1_M_AXIS 1 1 1 N 144
|
|
preplace netloc hier_0|srl2|axis_ss_conv_0_i_M_AXIS 1 2 1 N 164
|
|
preplace netloc hier_0|srl2|axis_subset_converter_0_M_AXIS1 1 5 1 N 534
|
|
preplace netloc hier_0|srl2|cmac_refclk_1 1 0 4 NJ 304 NJ 304 NJ 304 1450
|
|
preplace netloc hier_0|srl2|cmac_tx_fifo_i_M_AXIS 1 3 1 1460 194n
|
|
preplace netloc hier_0|srl2|s_axil_1 1 0 4 550J 284 NJ 284 NJ 284 1440
|
|
preplace netloc hier_0|srl2|s_axis_1 1 0 1 530 124n
|
|
preplace netloc hier_0|srl2|Ethernet|ETH_regs_prog_full_off 1 0 4 1710 716 2290J 806 2850 986 3350J
|
|
preplace netloc hier_0|srl2|Ethernet|ETH_regs_prog_full_on 1 0 4 1700 486 NJ 486 2870 996 3340J
|
|
preplace netloc hier_0|srl2|Ethernet|axil_clk 1 0 2 1640 896 2310
|
|
preplace netloc hier_0|srl2|Ethernet|axil_resetn 1 0 2 1660 996 2160
|
|
preplace netloc hier_0|srl2|Ethernet|clk_100 1 0 2 NJ 986 2170
|
|
preplace netloc hier_0|srl2|Ethernet|clk_100_reset 1 0 2 NJ 966 2220
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_reset 1 2 1 2820 1146n
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_resetn 1 0 5 1670 1276 2120J 1396 2890 1526 3280 1516 NJ
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_rx_fifo_i_axis_wr_data_count 1 0 4 1630 1476 NJ 1476 NJ 1476 3360
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_gt_powergoodout 1 2 2 2800 1016 3280J
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_gt_txusrclk2 1 0 5 1680 906 2270 1436 2830 1026 3400 856 3690J
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx_pause 1 0 4 1710 1456 2120J 1406 2770 1536 3400J
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx_pause_quanta8 1 0 4 1700 1466 2130J 1416 2780 1516 3270J
|
|
preplace netloc hier_0|srl2|Ethernet|counter_i_Q 1 1 1 2230 756n
|
|
preplace netloc hier_0|srl2|Ethernet|ctl_tx_pause_req 1 1 3 2180 1446 NJ 1446 3330J
|
|
preplace netloc hier_0|srl2|Ethernet|ctl_tx_resend_pause 1 1 3 2190 1456 NJ 1456 3260J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_rx_0_pause 1 1 3 2110 1506 NJ 1506 3390J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_rx_0_rx_pause_cnt 1 1 3 2250 1486 NJ 1486 3380J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_flowctrl_tx_i_tx_pause_cnt 1 1 3 2140 1546 NJ 1546 3410J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_frame_packer_i_tx_cnt 1 1 3 2210 1466 NJ 1466 3370J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_frame_unpacker_i_rx_frame_cnt 1 1 3 2320 1496 NJ 1496 3250
|
|
preplace netloc hier_0|srl2|Ethernet|eth_regs_EtherType 1 0 4 1690 476 NJ 476 2880 1006 3390J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_regs_dest_addr 1 0 4 1710 456 NJ 456 2890 1036 3380J
|
|
preplace netloc hier_0|srl2|Ethernet|eth_regs_source_addr 1 0 4 1700 466 NJ 466 2860 1056 3250J
|
|
preplace netloc hier_0|srl2|Ethernet|packer_underrun_cnt 1 1 3 2260 1366 2810J 1046 3360J
|
|
preplace netloc hier_0|srl2|Ethernet|probe2_1 1 0 4 1620 1266 2130J 1386 2870J 1276 3300
|
|
preplace netloc hier_0|srl2|Ethernet|proc_sys_reset_0_peripheral_reset 1 0 4 1710 1256 2150J 1376 2850J 1266 3250
|
|
preplace netloc hier_0|srl2|Ethernet|prog_full_manual 1 0 4 1710 496 NJ 496 2840 1066 3310J
|
|
preplace netloc hier_0|srl2|Ethernet|rst_inv_i_Res 1 1 1 2200 1056n
|
|
preplace netloc hier_0|srl2|Ethernet|unpacker_rx_frame_err_cnt 1 1 3 2330 1426 2880J 1286 3320
|
|
preplace netloc hier_0|srl2|Ethernet|Conn1 1 0 1 N 786
|
|
preplace netloc hier_0|srl2|Ethernet|S_AXI_1 1 1 1 2150 556n
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_axis_rx 1 2 2 2790 956 3380
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_refclk 1 0 2 NJ 726 2280
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_tx_fifo_M_AXIS 1 0 4 1650 886 2220J 816 NJ 816 3410
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_0_gt_serial_port 1 2 3 2800 826 NJ 826 NJ
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_rx 1 2 2 2770J 976 N
|
|
preplace netloc hier_0|srl2|Ethernet|cmac_usplus_i_stat_tx 1 2 2 NJ 966 3390
|
|
preplace netloc hier_0|srl2|Ethernet|packer_m_axis 1 1 3 2300 826 2790J 836 3380
|
|
preplace netloc hier_0|srl2|Ethernet|smartcon_i_M00_AXI 1 1 1 2240 796n
|
|
preplace netloc hier_0|srl2|Ethernet|unpacker_m_axis 1 3 2 3290 846 NJ
|
|
levelinfo -pg 1 0 360 5180
|
|
levelinfo -hier hier_0 * 600 *
|
|
levelinfo -hier hier_0|srl2 * 670 950 1250 1740 4100 4480 4780 *
|
|
levelinfo -hier hier_0|srl2|Ethernet * 1910 2550 3070 3550 *
|
|
pagesize -pg 1 -db -bbox -sgen -170 0 5310 1850
|
|
pagesize -hier hier_0 -db -bbox -sgen 250 32 5050 1822
|
|
pagesize -hier hier_0|srl2 -db -bbox -sgen 500 64 4920 1794
|
|
pagesize -hier hier_0|srl2|Ethernet -db -bbox -sgen 1590 216 3720 1556
|
|
"
|
|
}
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_raw_eth_cmac_4()
|
|
|
|
cr_bd_raw_eth_cmac_4 ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files raw_eth_cmac_4.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files raw_eth_cmac_4.bd ]
|
|
|
|
if { [get_files [list eth_flowctrl_rx.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_rx.vhd
|
|
}
|
|
if { [get_files [list eth_frame_packer.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_packer.vhd
|
|
}
|
|
if { [get_files [list eth_flowctrl_tx.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_flowctrl_tx.vhd
|
|
}
|
|
if { [get_files [list eth_frame_unpacker.vhd]] == "" } {
|
|
import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9082/source/eth_frame_unpacker.vhd
|
|
}
|
|
|
|
|
|
# Proc to create BD raw_eth
|
|
proc cr_bd_raw_eth { parentCell } {
|
|
# The design that will be created by this Tcl proc contains the following
|
|
# module references:
|
|
# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker
|
|
|
|
|
|
|
|
# CHANGE DESIGN NAME HERE
|
|
set design_name raw_eth
|
|
|
|
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
|
|
create_bd_design $design_name
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:axis_register_slice:1.1\
|
|
xilinx.com:ip:axis_subset_converter:1.1\
|
|
xilinx.com:ip:axis_data_fifo:2.0\
|
|
xilinx.com:ip:cmac_usplus:3.1\
|
|
xilinx.com:ip:system_ila:1.1\
|
|
xilinx.com:ip:util_vector_logic:2.0\
|
|
xilinx.com:ip:c_counter_binary:12.0\
|
|
xilinx.com:ip:smartconnect:1.0\
|
|
xilinx.com:ip:proc_sys_reset:5.0\
|
|
user:user:axi_regs_32:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
xilinx.com:ip:xlconcat:2.1\
|
|
xilinx.com:ip:xpm_cdc_gen:1.0\
|
|
xilinx.com:ip:xlconstant:1.1\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
##################################################################
|
|
# CHECK Modules
|
|
##################################################################
|
|
set bCheckModules 1
|
|
if { $bCheckModules == 1 } {
|
|
set list_check_mods "\
|
|
eth_flowctrl_rx\
|
|
eth_frame_packer\
|
|
eth_flowctrl_tx\
|
|
eth_frame_unpacker\
|
|
"
|
|
|
|
set list_mods_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
|
|
|
foreach mod_vlnv $list_check_mods {
|
|
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
|
lappend list_mods_missing $mod_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_mods_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
|
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
|
set bCheckIPsPassed 0
|
|
}
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
|
|
# Hierarchical cell: ETH_regs
|
|
proc create_hier_cell_ETH_regs { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -from 47 -to 0 dest_addr
|
|
create_bd_pin -dir O -from 47 -to 0 source_addr
|
|
create_bd_pin -dir O -from 15 -to 0 EtherType
|
|
create_bd_pin -dir I cmac_clk
|
|
create_bd_pin -dir I aclk
|
|
create_bd_pin -dir I aresetn
|
|
create_bd_pin -dir O -from 0 -to 0 prog_full_manual
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_on
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_off
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt
|
|
|
|
# Create instance: axi_regs_32_0, and set properties
|
|
set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ]
|
|
|
|
# Create instance: xlslice_0, and set properties
|
|
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_0
|
|
|
|
|
|
# Create instance: xlconcat_0, and set properties
|
|
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_0
|
|
|
|
|
|
# Create instance: xlconcat_1, and set properties
|
|
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_1
|
|
|
|
|
|
# Create instance: xlslice_1, and set properties
|
|
set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_1
|
|
|
|
|
|
# Create instance: xlslice_2, and set properties
|
|
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_2
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_0, and set properties
|
|
set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_0
|
|
|
|
|
|
# Create instance: const_1b0, and set properties
|
|
set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ]
|
|
set_property CONFIG.CONST_VAL {0} $const_1b0
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_1, and set properties
|
|
set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_1
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_2, and set properties
|
|
set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {16} \
|
|
] $xpm_cdc_gen_2
|
|
|
|
|
|
# Create instance: const_32b0, and set properties
|
|
set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {32} \
|
|
] $const_32b0
|
|
|
|
|
|
# Create instance: xlslice_3, and set properties
|
|
set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ]
|
|
set_property CONFIG.DIN_FROM {0} $xlslice_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_3, and set properties
|
|
set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {1} \
|
|
] $xpm_cdc_gen_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_4, and set properties
|
|
set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_4
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_5, and set properties
|
|
set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_5
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_16, and set properties
|
|
set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_16
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_17, and set properties
|
|
set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_17
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_18, and set properties
|
|
set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_18
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_19, and set properties
|
|
set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_19
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_20, and set properties
|
|
set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_20
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_21, and set properties
|
|
set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_21
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_22, and set properties
|
|
set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_22
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk]
|
|
connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN]
|
|
connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in]
|
|
connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in]
|
|
connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in]
|
|
connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in]
|
|
connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in]
|
|
connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in]
|
|
connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in]
|
|
connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in]
|
|
connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk]
|
|
connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk]
|
|
connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in]
|
|
connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in]
|
|
connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in]
|
|
connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in]
|
|
connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in]
|
|
connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in]
|
|
connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in]
|
|
connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in]
|
|
connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in]
|
|
connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in]
|
|
connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1]
|
|
connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1]
|
|
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in]
|
|
connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in]
|
|
connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr]
|
|
connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in]
|
|
connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in]
|
|
connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr]
|
|
connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in]
|
|
connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in]
|
|
connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in]
|
|
connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType]
|
|
connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual]
|
|
connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on]
|
|
connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off]
|
|
connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in]
|
|
connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: Ethernet
|
|
proc create_hier_cell_Ethernet { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -type clk axis_aclk
|
|
create_bd_pin -dir O -from 0 -to 0 axis_aresetn
|
|
create_bd_pin -dir I -type clk axil_clk
|
|
create_bd_pin -dir I clk_100_reset
|
|
create_bd_pin -dir I clk_100
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt
|
|
create_bd_pin -dir I -type rst axil_resetn
|
|
create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow
|
|
|
|
# Create instance: eth_flowctrl_rx_i, and set properties
|
|
set block_name eth_flowctrl_rx
|
|
set block_cell_name eth_flowctrl_rx_i
|
|
if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_rx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: cmac_usplus_i, and set properties
|
|
set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CMAC_CAUI4_MODE {1} \
|
|
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
|
|
CONFIG.ENABLE_AXI_INTERFACE {1} \
|
|
CONFIG.ENABLE_PIPELINE_REG {1} \
|
|
CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \
|
|
CONFIG.GT_REF_CLK_FREQ {156.25} \
|
|
CONFIG.RX_CHECK_ACK {0} \
|
|
CONFIG.RX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_SA_GPP {0x000000000000} \
|
|
CONFIG.TX_SA_PPP {0x000000000000} \
|
|
CONFIG.USER_INTERFACE {AXIS} \
|
|
] $cmac_usplus_i
|
|
|
|
|
|
# Create instance: eth_frame_packer_i, and set properties
|
|
set block_name eth_frame_packer
|
|
set block_cell_name eth_frame_packer_i
|
|
if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_packer_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_flowctrl_tx_i, and set properties
|
|
set block_name eth_flowctrl_tx
|
|
set block_cell_name eth_flowctrl_tx_i
|
|
if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_tx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_frame_unpacker_i, and set properties
|
|
set block_name eth_frame_unpacker
|
|
set block_cell_name eth_frame_unpacker_i
|
|
if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_unpacker_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: system_ila_i, and set properties
|
|
set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_MON_TYPE {MIX} \
|
|
CONFIG.C_NUM_MONITOR_SLOTS {6} \
|
|
CONFIG.C_NUM_OF_PROBES {20} \
|
|
CONFIG.C_SLOT {5} \
|
|
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
] $system_ila_i
|
|
|
|
|
|
# Create instance: ETH_regs
|
|
create_hier_cell_ETH_regs $hier_obj ETH_regs
|
|
|
|
# Create instance: rst_inv_i, and set properties
|
|
set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rst_inv_i
|
|
|
|
|
|
# Create instance: counter_i, and set properties
|
|
set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CE {true} \
|
|
CONFIG.Fb_Latency_Configuration {Automatic} \
|
|
CONFIG.Latency_Configuration {Automatic} \
|
|
CONFIG.Load {false} \
|
|
CONFIG.Load_Sense {Active_High} \
|
|
CONFIG.Output_Width {32} \
|
|
CONFIG.Restrict_Count {false} \
|
|
CONFIG.SCLR {true} \
|
|
CONFIG.SSET {false} \
|
|
CONFIG.Sync_Threshold_Output {false} \
|
|
] $counter_i
|
|
|
|
|
|
# Create instance: smartcon_i, and set properties
|
|
set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {2} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $smartcon_i
|
|
|
|
|
|
# Create instance: proc_sys_reset_0, and set properties
|
|
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL]
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI]
|
|
connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk]
|
|
connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS]
|
|
connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI]
|
|
connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off]
|
|
connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on]
|
|
connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk]
|
|
connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn]
|
|
connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk]
|
|
connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset]
|
|
connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in]
|
|
connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn]
|
|
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt]
|
|
connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0]
|
|
connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins system_ila_i/probe16] [get_bd_pins eth_flowctrl_rx_i/rx_pause]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins system_ila_i/probe17] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8]
|
|
connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt]
|
|
connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9]
|
|
connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8]
|
|
connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins system_ila_i/probe15]
|
|
connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14]
|
|
connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19]
|
|
connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13]
|
|
connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18]
|
|
connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type]
|
|
connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac]
|
|
connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac]
|
|
connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt]
|
|
connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE]
|
|
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR]
|
|
connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual]
|
|
connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset]
|
|
connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: srl2
|
|
proc create_hier_cell_srl2 { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_srl2() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk axis_clk
|
|
create_bd_pin -dir I -type rst axis_resetn
|
|
create_bd_pin -dir I -type clk axil_clk
|
|
create_bd_pin -dir I -type rst axil_resetn
|
|
create_bd_pin -dir I clk_100
|
|
create_bd_pin -dir I clk_100_reset
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst aresetn_0
|
|
|
|
# Create instance: axis_reg_0_i, and set properties
|
|
set axis_reg_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_0_i ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $axis_reg_0_i
|
|
|
|
|
|
# Create instance: axis_ss_conv_0_i, and set properties
|
|
set axis_ss_conv_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_0_i ]
|
|
set_property -dict [list \
|
|
CONFIG.DEFAULT_TLAST {16} \
|
|
CONFIG.M_HAS_TKEEP {0} \
|
|
CONFIG.M_HAS_TLAST {1} \
|
|
CONFIG.M_HAS_TREADY {1} \
|
|
CONFIG.M_HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.M_TDEST_WIDTH {0} \
|
|
CONFIG.M_TID_WIDTH {0} \
|
|
CONFIG.M_TUSER_WIDTH {0} \
|
|
CONFIG.S_HAS_TKEEP {0} \
|
|
CONFIG.S_HAS_TLAST {0} \
|
|
CONFIG.S_HAS_TREADY {1} \
|
|
CONFIG.S_HAS_TSTRB {0} \
|
|
CONFIG.S_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDEST_WIDTH {0} \
|
|
CONFIG.S_TID_WIDTH {0} \
|
|
CONFIG.S_TUSER_WIDTH {0} \
|
|
] $axis_ss_conv_0_i
|
|
|
|
|
|
# Create instance: cmac_rx_fifo_i, and set properties
|
|
set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ]
|
|
set_property -dict [list \
|
|
CONFIG.FIFO_DEPTH {8192} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.HAS_WR_DATA_COUNT {1} \
|
|
CONFIG.IS_ACLK_ASYNC {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $cmac_rx_fifo_i
|
|
|
|
|
|
# Create instance: axis_ss_conv_1_i, and set properties
|
|
set axis_ss_conv_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_1_i ]
|
|
set_property -dict [list \
|
|
CONFIG.M_HAS_TKEEP {0} \
|
|
CONFIG.M_HAS_TLAST {0} \
|
|
CONFIG.M_HAS_TREADY {1} \
|
|
CONFIG.M_HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.M_TDEST_WIDTH {0} \
|
|
CONFIG.M_TID_WIDTH {0} \
|
|
CONFIG.M_TUSER_WIDTH {0} \
|
|
CONFIG.S_HAS_TKEEP {0} \
|
|
CONFIG.S_HAS_TLAST {1} \
|
|
CONFIG.S_HAS_TREADY {0} \
|
|
CONFIG.S_HAS_TSTRB {0} \
|
|
CONFIG.S_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDEST_WIDTH {0} \
|
|
CONFIG.S_TID_WIDTH {0} \
|
|
CONFIG.S_TUSER_WIDTH {1} \
|
|
] $axis_ss_conv_1_i
|
|
|
|
|
|
# Create instance: axis_reg_1_i, and set properties
|
|
set axis_reg_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_1_i ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $axis_reg_1_i
|
|
|
|
|
|
# Create instance: cmac_tx_fifo_i, and set properties
|
|
set cmac_tx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_tx_fifo_i ]
|
|
set_property -dict [list \
|
|
CONFIG.FIFO_DEPTH {32} \
|
|
CONFIG.FIFO_MODE {2} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.IS_ACLK_ASYNC {1} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $cmac_tx_fifo_i
|
|
|
|
|
|
# Create instance: Ethernet
|
|
create_hier_cell_Ethernet $hier_obj Ethernet
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Ethernet_M_AXIS [get_bd_intf_pins Ethernet/M_AXIS] [get_bd_intf_pins axis_ss_conv_1_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net Ethernet_cmac_gt [get_bd_intf_pins cmac_gt] [get_bd_intf_pins Ethernet/cmac_gt]
|
|
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins cmac_rx_fifo_i/M_AXIS] [get_bd_intf_pins axis_reg_1_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_reg_1_i_M_AXIS [get_bd_intf_pins m_axis] [get_bd_intf_pins axis_reg_1_i/M_AXIS]
|
|
connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_reg_0_i/M_AXIS] [get_bd_intf_pins axis_ss_conv_0_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_ss_conv_0_i_M_AXIS [get_bd_intf_pins axis_ss_conv_0_i/M_AXIS] [get_bd_intf_pins cmac_tx_fifo_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS1 [get_bd_intf_pins axis_ss_conv_1_i/M_AXIS] [get_bd_intf_pins cmac_rx_fifo_i/S_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_refclk_1 [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins Ethernet/cmac_refclk]
|
|
connect_bd_intf_net -intf_net cmac_tx_fifo_i_M_AXIS [get_bd_intf_pins cmac_tx_fifo_i/M_AXIS] [get_bd_intf_pins Ethernet/S_AXIS]
|
|
connect_bd_intf_net -intf_net s_axil_1 [get_bd_intf_pins s_axil] [get_bd_intf_pins Ethernet/S_AXIL]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins axis_reg_0_i/S_AXIS]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net Ethernet_axis_aclk [get_bd_pins Ethernet/axis_aclk] [get_bd_pins axis_ss_conv_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/s_axis_aclk] [get_bd_pins cmac_tx_fifo_i/m_axis_aclk]
|
|
connect_bd_net -net Ethernet_axis_aresetn [get_bd_pins Ethernet/axis_aresetn] [get_bd_pins cmac_rx_fifo_i/s_axis_aresetn] [get_bd_pins axis_ss_conv_1_i/aresetn]
|
|
connect_bd_net -net Net [get_bd_pins m_axis_aclk] [get_bd_pins axis_reg_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/m_axis_aclk]
|
|
connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins axis_reg_1_i/aresetn]
|
|
connect_bd_net -net clk_100_1 [get_bd_pins clk_100] [get_bd_pins Ethernet/clk_100]
|
|
connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset] [get_bd_pins Ethernet/clk_100_reset]
|
|
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins cmac_rx_fifo_i/axis_wr_data_count] [get_bd_pins Ethernet/rx_fifo_wr_data_cnt]
|
|
connect_bd_net -net cmac_rx_overflow [get_bd_pins axis_ss_conv_1_i/transfer_dropped] [get_bd_pins Ethernet/rx_fifo_overflow]
|
|
connect_bd_net -net s_axi_sreset_1 [get_bd_pins axil_resetn] [get_bd_pins Ethernet/axil_resetn]
|
|
connect_bd_net -net s_axilite_dsp_clk [get_bd_pins axil_clk] [get_bd_pins Ethernet/axil_clk]
|
|
connect_bd_net -net s_axis_dsp_clk [get_bd_pins axis_clk] [get_bd_pins axis_reg_0_i/aclk] [get_bd_pins axis_ss_conv_0_i/aclk] [get_bd_pins cmac_tx_fifo_i/s_axis_aclk]
|
|
connect_bd_net -net s_axis_dsp_resetn [get_bd_pins axis_resetn] [get_bd_pins axis_reg_0_i/aresetn] [get_bd_pins axis_ss_conv_0_i/aresetn] [get_bd_pins cmac_tx_fifo_i/s_axis_aresetn]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: hier_0
|
|
proc create_hier_cell_hier_0 { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hier_0() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk axis_clk_0
|
|
create_bd_pin -dir I -type rst axis_resetn_0
|
|
create_bd_pin -dir I -type clk axil_clk_0
|
|
create_bd_pin -dir I -type rst axil_resetn_0
|
|
create_bd_pin -dir I clk_100_0
|
|
create_bd_pin -dir I clk_100_reset_0
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst aresetn_0
|
|
|
|
# Create instance: srl2
|
|
create_hier_cell_srl2 $hier_obj srl2
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins srl2/cmac_gt] [get_bd_intf_pins cmac_gt_0]
|
|
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins srl2/m_axis] [get_bd_intf_pins m_axis_0]
|
|
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins srl2/s_axil] [get_bd_intf_pins s_axil_0]
|
|
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins srl2/s_axis] [get_bd_intf_pins s_axis_0]
|
|
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins srl2/cmac_refclk] [get_bd_intf_pins cmac_refclk_0]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins srl2/aresetn_0]
|
|
connect_bd_net -net axil_clk_1 [get_bd_pins axil_clk_0] [get_bd_pins srl2/axil_clk]
|
|
connect_bd_net -net axil_resetn_1 [get_bd_pins axil_resetn_0] [get_bd_pins srl2/axil_resetn]
|
|
connect_bd_net -net axis_clk_1 [get_bd_pins axis_clk_0] [get_bd_pins srl2/axis_clk]
|
|
connect_bd_net -net axis_resetn_1 [get_bd_pins axis_resetn_0] [get_bd_pins srl2/axis_resetn]
|
|
connect_bd_net -net clk_100_1 [get_bd_pins clk_100_0] [get_bd_pins srl2/clk_100]
|
|
connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset_0] [get_bd_pins srl2/clk_100_reset]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins srl2/m_axis_aclk]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
set cmac_gt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 ]
|
|
|
|
set m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {375000000} \
|
|
] $m_axis
|
|
|
|
set s_axil_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.ARUSER_WIDTH {0} \
|
|
CONFIG.AWUSER_WIDTH {0} \
|
|
CONFIG.BUSER_WIDTH {0} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.HAS_BRESP {1} \
|
|
CONFIG.HAS_BURST {1} \
|
|
CONFIG.HAS_CACHE {1} \
|
|
CONFIG.HAS_LOCK {1} \
|
|
CONFIG.HAS_PROT {1} \
|
|
CONFIG.HAS_QOS {1} \
|
|
CONFIG.HAS_REGION {1} \
|
|
CONFIG.HAS_RRESP {1} \
|
|
CONFIG.HAS_WSTRB {1} \
|
|
CONFIG.ID_WIDTH {0} \
|
|
CONFIG.MAX_BURST_LENGTH {1} \
|
|
CONFIG.NUM_READ_OUTSTANDING {1} \
|
|
CONFIG.NUM_READ_THREADS {1} \
|
|
CONFIG.NUM_WRITE_OUTSTANDING {1} \
|
|
CONFIG.NUM_WRITE_THREADS {1} \
|
|
CONFIG.PROTOCOL {AXI4LITE} \
|
|
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
|
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
|
CONFIG.RUSER_WIDTH {0} \
|
|
CONFIG.SUPPORTS_NARROW_BURST {0} \
|
|
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
|
CONFIG.WUSER_WIDTH {0} \
|
|
] $s_axil_0
|
|
|
|
set s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {375000000} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.LAYERED_METADATA {undef} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $s_axis
|
|
|
|
set cmac_refclk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {156250000} \
|
|
] $cmac_refclk_0
|
|
|
|
|
|
# Create ports
|
|
set s_axis_clk [ create_bd_port -dir I -type clk -freq_hz 375000000 s_axis_clk ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {s_axis} \
|
|
CONFIG.ASSOCIATED_RESET {s_axis_aresetn} \
|
|
] $s_axis_clk
|
|
set s_axis_aresetn [ create_bd_port -dir I -type rst s_axis_aresetn ]
|
|
set axil_clk_0 [ create_bd_port -dir I -type clk axil_clk_0 ]
|
|
set axil_resetn_0 [ create_bd_port -dir I -type rst axil_resetn_0 ]
|
|
set clk_100_0 [ create_bd_port -dir I clk_100_0 ]
|
|
set clk_100_reset_0 [ create_bd_port -dir I clk_100_reset_0 ]
|
|
set m_axis_aclk [ create_bd_port -dir I -type clk -freq_hz 375000000 m_axis_aclk ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {m_axis} \
|
|
CONFIG.ASSOCIATED_RESET {m_axis_aresetn} \
|
|
CONFIG.CLK_DOMAIN {raw_eth_axis_clk_0} \
|
|
] $m_axis_aclk
|
|
set m_axis_aresetn [ create_bd_port -dir I -type rst m_axis_aresetn ]
|
|
|
|
# Create instance: hier_0
|
|
create_hier_cell_hier_0 [current_bd_instance .] hier_0
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net cmac_refclk_0_1 [get_bd_intf_ports cmac_refclk_0] [get_bd_intf_pins hier_0/cmac_refclk_0]
|
|
connect_bd_intf_net -intf_net hier_0_cmac_gt_0 [get_bd_intf_ports cmac_gt_0] [get_bd_intf_pins hier_0/cmac_gt_0]
|
|
connect_bd_intf_net -intf_net hier_0_m_axis_0 [get_bd_intf_ports m_axis] [get_bd_intf_pins hier_0/m_axis_0]
|
|
connect_bd_intf_net -intf_net s_axil_0_1 [get_bd_intf_ports s_axil_0] [get_bd_intf_pins hier_0/s_axil_0]
|
|
connect_bd_intf_net -intf_net s_axis_0_1 [get_bd_intf_ports s_axis] [get_bd_intf_pins hier_0/s_axis_0]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aresetn_0_1 [get_bd_ports m_axis_aresetn] [get_bd_pins hier_0/aresetn_0]
|
|
connect_bd_net -net axil_clk_0_1 [get_bd_ports axil_clk_0] [get_bd_pins hier_0/axil_clk_0]
|
|
connect_bd_net -net axil_resetn_0_1 [get_bd_ports axil_resetn_0] [get_bd_pins hier_0/axil_resetn_0]
|
|
connect_bd_net -net axis_clk_0_1 [get_bd_ports s_axis_clk] [get_bd_pins hier_0/axis_clk_0]
|
|
connect_bd_net -net axis_resetn_0_1 [get_bd_ports s_axis_aresetn] [get_bd_pins hier_0/axis_resetn_0]
|
|
connect_bd_net -net clk_100_0_1 [get_bd_ports clk_100_0] [get_bd_pins hier_0/clk_100_0]
|
|
connect_bd_net -net clk_100_reset_0_1 [get_bd_ports clk_100_reset_0] [get_bd_pins hier_0/clk_100_reset_0]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_ports m_axis_aclk] [get_bd_pins hier_0/m_axis_aclk]
|
|
|
|
# Create address segments
|
|
assign_bd_address -offset 0x81000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force
|
|
assign_bd_address -offset 0x81010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force
|
|
|
|
# Perform GUI Layout
|
|
regenerate_bd_layout -layout_string {
|
|
"ActiveEmotionalView":"Default View",
|
|
"Default View_ScaleFactor":"1.0",
|
|
"Default View_TopLeft":"1175,1945",
|
|
"ExpandedHierarchyInLayout":"",
|
|
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
|
# -string -flagsOSRD
|
|
preplace port cmac_gt_0 -pg 1 -lvl 2 -x 520 -y 150 -defaultsOSRD
|
|
preplace port m_axis -pg 1 -lvl 2 -x 520 -y 170 -defaultsOSRD
|
|
preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD
|
|
preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD
|
|
preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD
|
|
preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
|
|
preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
|
|
preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
|
|
preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD
|
|
preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD
|
|
preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD
|
|
preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
|
|
preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
|
|
preplace inst hier_0 -pg 1 -lvl 1 -x 360 -y 160 -defaultsOSRD
|
|
preplace netloc aresetn_0_1 1 0 1 NJ 260
|
|
preplace netloc axil_clk_0_1 1 0 1 NJ 160
|
|
preplace netloc axil_resetn_0_1 1 0 1 NJ 180
|
|
preplace netloc axis_clk_0_1 1 0 1 NJ 120
|
|
preplace netloc axis_resetn_0_1 1 0 1 NJ 140
|
|
preplace netloc clk_100_0_1 1 0 1 NJ 200
|
|
preplace netloc clk_100_reset_0_1 1 0 1 NJ 220
|
|
preplace netloc m_axis_aclk_1 1 0 1 NJ 240
|
|
preplace netloc cmac_refclk_0_1 1 0 1 NJ 100
|
|
preplace netloc hier_0_cmac_gt_0 1 1 1 NJ 150
|
|
preplace netloc hier_0_m_axis_0 1 1 1 NJ 170
|
|
preplace netloc s_axil_0_1 1 0 1 NJ 60
|
|
preplace netloc s_axis_0_1 1 0 1 NJ 80
|
|
levelinfo -pg 1 0 360 520
|
|
pagesize -pg 1 -db -bbox -sgen -170 0 6880 3140
|
|
"
|
|
}
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_raw_eth()
|
|
|
|
cr_bd_raw_eth ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files raw_eth.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files raw_eth.bd ]
|
|
|
|
|
|
|
|
# Proc to create BD system
|
|
proc cr_bd_system { parentCell } {
|
|
|
|
# CHANGE DESIGN NAME HERE
|
|
set design_name system
|
|
|
|
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
|
|
create_bd_design $design_name
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:zynq_ultra_ps_e:3.5\
|
|
xilinx.com:ip:proc_sys_reset:5.0\
|
|
xilinx.com:ip:xlconcat:2.1\
|
|
xilinx.com:ip:xlconstant:1.1\
|
|
analog.com:user:axi_sysid:1.0\
|
|
analog.com:user:sysid_rom:1.0\
|
|
xilinx.com:ip:smartconnect:1.0\
|
|
analog.com:user:util_adxcvr:1.0\
|
|
analog.com:user:axi_adxcvr:1.0\
|
|
analog.com:user:util_cpack2:1.0\
|
|
analog.com:user:axi_dmac:1.0\
|
|
analog.com:user:util_upack2:1.0\
|
|
xilinx.com:ip:util_vector_logic:2.0\
|
|
xilinx.com:ip:util_reduced_logic:2.0\
|
|
analog.com:user:axi_jesd204_rx:1.0\
|
|
analog.com:user:jesd204_rx:1.0\
|
|
analog.com:user:ad_ip_jesd204_tpl_adc:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
analog.com:user:data_offload:1.0\
|
|
analog.com:user:util_do_ram:1.0\
|
|
analog.com:user:axi_jesd204_tx:1.0\
|
|
analog.com:user:jesd204_tx:1.0\
|
|
analog.com:user:ad_ip_jesd204_tpl_dac:1.0\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
|
|
# Hierarchical cell: mxfe_tx_data_offload
|
|
proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_CYCLIC_EN {true} \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.MEM_SIZE_LOG2 {19} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {1} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.LENGTH_WIDTH {19} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: tx_mxfe_tpl_core
|
|
proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I dac_dunf
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_0
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_1
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_2
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_3
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_3
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O dac_sync_manual_req_out
|
|
create_bd_pin -dir I dac_sync_manual_req_in
|
|
create_bd_pin -dir O dac_rst
|
|
|
|
# Create instance: dac_tpl_core, and set properties
|
|
set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.IQCORRECTION_DISABLE {0} \
|
|
CONFIG.NUM_CHANNELS {4} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.OCTETS_PER_BEAT {4} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $dac_tpl_core
|
|
|
|
|
|
# Create instance: data_concat0, and set properties
|
|
set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ]
|
|
set_property CONFIG.NUM_PORTS {4} $data_concat0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins dac_tpl_core/link] [get_bd_intf_pins link]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0]
|
|
connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1]
|
|
connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2]
|
|
connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3]
|
|
connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf]
|
|
connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in]
|
|
connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_tpl_core/dac_rst] [get_bd_pins dac_rst]
|
|
connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] [get_bd_pins dac_sync_manual_req_out]
|
|
connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din]
|
|
connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din]
|
|
connect_bd_net -net data_concat0_dout [get_bd_pins data_concat0/dout] [get_bd_pins dac_tpl_core/dac_ddata]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins dac_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins dac_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins dac_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins dac_enable_3]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins dac_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins dac_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins dac_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins dac_valid_3]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_tx_jesd
|
|
proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy4
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy5
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy6
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy7
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir I -from 0 -to 0 sync
|
|
create_bd_pin -dir I sysref
|
|
|
|
# Create instance: tx_axi, and set properties
|
|
set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $tx_axi
|
|
|
|
|
|
# Create instance: tx, and set properties
|
|
set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {4} \
|
|
] $tx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi]
|
|
connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx_axi/tx_cfg] [get_bd_intf_pins tx/tx_cfg]
|
|
connect_bd_intf_net -intf_net tx_axi_tx_ctrl [get_bd_intf_pins tx_axi/tx_ctrl] [get_bd_intf_pins tx/tx_ctrl]
|
|
connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data]
|
|
connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event]
|
|
connect_bd_intf_net -intf_net tx_tx_ilas_config [get_bd_intf_pins tx/tx_ilas_config] [get_bd_intf_pins tx_axi/tx_ilas_config]
|
|
connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx/tx_phy0] [get_bd_intf_pins tx_phy0]
|
|
connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx/tx_phy1] [get_bd_intf_pins tx_phy1]
|
|
connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx/tx_phy2] [get_bd_intf_pins tx_phy2]
|
|
connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx/tx_phy3] [get_bd_intf_pins tx_phy3]
|
|
connect_bd_intf_net -intf_net tx_tx_phy4 [get_bd_intf_pins tx/tx_phy4] [get_bd_intf_pins tx_phy4]
|
|
connect_bd_intf_net -intf_net tx_tx_phy5 [get_bd_intf_pins tx/tx_phy5] [get_bd_intf_pins tx_phy5]
|
|
connect_bd_intf_net -intf_net tx_tx_phy6 [get_bd_intf_pins tx/tx_phy6] [get_bd_intf_pins tx_phy6]
|
|
connect_bd_intf_net -intf_net tx_tx_phy7 [get_bd_intf_pins tx/tx_phy7] [get_bd_intf_pins tx_phy7]
|
|
connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx/device_clk] [get_bd_pins tx_axi/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx/clk] [get_bd_pins tx_axi/core_clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sync_1 [get_bd_pins sync] [get_bd_pins tx/sync]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref]
|
|
connect_bd_net -net tx_axi_core_reset [get_bd_pins tx_axi/core_reset] [get_bd_pins tx/reset]
|
|
connect_bd_net -net tx_axi_device_reset [get_bd_pins tx_axi/device_reset] [get_bd_pins tx/device_reset]
|
|
connect_bd_net -net tx_axi_irq [get_bd_pins tx_axi/irq] [get_bd_pins irq]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: mxfe_rx_data_offload
|
|
proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.MEM_SIZE_LOG2 {19} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {0} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.LENGTH_WIDTH {19} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: rx_mxfe_tpl_core
|
|
proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -from 3 -to 0 link_sof
|
|
create_bd_pin -dir I link_valid
|
|
create_bd_pin -dir I -from 255 -to 0 link_data
|
|
create_bd_pin -dir I adc_dovf
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_0
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_1
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_2
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_3
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_3
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O adc_sync_manual_req_out
|
|
create_bd_pin -dir I adc_sync_manual_req_in
|
|
create_bd_pin -dir O adc_rst
|
|
|
|
# Create instance: adc_tpl_core, and set properties
|
|
set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.NUM_CHANNELS {4} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.OCTETS_PER_BEAT {4} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $adc_tpl_core
|
|
|
|
|
|
# Create instance: data_slice_0, and set properties
|
|
set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {63} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: data_slice_1, and set properties
|
|
set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {127} \
|
|
CONFIG.DIN_TO {64} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: data_slice_2, and set properties
|
|
set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {191} \
|
|
CONFIG.DIN_TO {128} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: data_slice_3, and set properties
|
|
set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {255} \
|
|
CONFIG.DIN_TO {192} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_3
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf]
|
|
connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in]
|
|
connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din]
|
|
connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_tpl_core/adc_rst] [get_bd_pins adc_rst]
|
|
connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] [get_bd_pins adc_sync_manual_req_out]
|
|
connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din]
|
|
connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din]
|
|
connect_bd_net -net data_slice_0_Dout [get_bd_pins data_slice_0/Dout] [get_bd_pins adc_data_0]
|
|
connect_bd_net -net data_slice_1_Dout [get_bd_pins data_slice_1/Dout] [get_bd_pins adc_data_1]
|
|
connect_bd_net -net data_slice_2_Dout [get_bd_pins data_slice_2/Dout] [get_bd_pins adc_data_2]
|
|
connect_bd_net -net data_slice_3_Dout [get_bd_pins data_slice_3/Dout] [get_bd_pins adc_data_3]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins adc_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins adc_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins adc_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins adc_enable_3]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk]
|
|
connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data]
|
|
connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof]
|
|
connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins adc_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins adc_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins adc_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins adc_valid_3]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_rx_jesd
|
|
proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy4
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy5
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy6
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy7
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir O -from 0 -to 0 sync
|
|
create_bd_pin -dir I sysref
|
|
create_bd_pin -dir O phy_en_char_align
|
|
create_bd_pin -dir O -from 3 -to 0 rx_eof
|
|
create_bd_pin -dir O -from 3 -to 0 rx_sof
|
|
create_bd_pin -dir O rx_data_tvalid
|
|
create_bd_pin -dir O -from 255 -to 0 rx_data_tdata
|
|
|
|
# Create instance: rx_axi, and set properties
|
|
set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $rx_axi
|
|
|
|
|
|
# Create instance: rx, and set properties
|
|
set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_INPUT_PIPELINE {1} \
|
|
CONFIG.NUM_LANES {8} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {4} \
|
|
] $rx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx_axi/rx_cfg] [get_bd_intf_pins rx/rx_cfg]
|
|
connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx/rx_phy0] [get_bd_intf_pins rx_phy0]
|
|
connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx/rx_phy1] [get_bd_intf_pins rx_phy1]
|
|
connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx/rx_phy2] [get_bd_intf_pins rx_phy2]
|
|
connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx/rx_phy3] [get_bd_intf_pins rx_phy3]
|
|
connect_bd_intf_net -intf_net rx_phy4_1 [get_bd_intf_pins rx/rx_phy4] [get_bd_intf_pins rx_phy4]
|
|
connect_bd_intf_net -intf_net rx_phy5_1 [get_bd_intf_pins rx/rx_phy5] [get_bd_intf_pins rx_phy5]
|
|
connect_bd_intf_net -intf_net rx_phy6_1 [get_bd_intf_pins rx/rx_phy6] [get_bd_intf_pins rx_phy6]
|
|
connect_bd_intf_net -intf_net rx_phy7_1 [get_bd_intf_pins rx/rx_phy7] [get_bd_intf_pins rx_phy7]
|
|
connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event]
|
|
connect_bd_intf_net -intf_net rx_rx_ilas_config [get_bd_intf_pins rx/rx_ilas_config] [get_bd_intf_pins rx_axi/rx_ilas_config]
|
|
connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx/device_clk] [get_bd_pins rx_axi/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx/clk] [get_bd_pins rx_axi/core_clk]
|
|
connect_bd_net -net rx_axi_core_reset [get_bd_pins rx_axi/core_reset] [get_bd_pins rx/reset]
|
|
connect_bd_net -net rx_axi_device_reset [get_bd_pins rx_axi/device_reset] [get_bd_pins rx/device_reset]
|
|
connect_bd_net -net rx_axi_irq [get_bd_pins rx_axi/irq] [get_bd_pins irq]
|
|
connect_bd_net -net rx_phy_en_char_align [get_bd_pins rx/phy_en_char_align] [get_bd_pins phy_en_char_align]
|
|
connect_bd_net -net rx_rx_data [get_bd_pins rx/rx_data] [get_bd_pins rx_data_tdata]
|
|
connect_bd_net -net rx_rx_eof [get_bd_pins rx/rx_eof] [get_bd_pins rx_eof]
|
|
connect_bd_net -net rx_rx_sof [get_bd_pins rx/rx_sof] [get_bd_pins rx_sof]
|
|
connect_bd_net -net rx_rx_valid [get_bd_pins rx/rx_valid] [get_bd_pins rx_data_tvalid]
|
|
connect_bd_net -net rx_sync [get_bd_pins rx/sync] [get_bd_pins sync]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
set util_mxfe_upack_s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 util_mxfe_upack_s_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.LAYERED_METADATA {undef} \
|
|
CONFIG.TDATA_NUM_BYTES {32} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $util_mxfe_upack_s_axis
|
|
|
|
set mxfe_tx_data_offload_m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 mxfe_tx_data_offload_m_axis ]
|
|
|
|
set M11_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M11_AXI_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.PROTOCOL {AXI4LITE} \
|
|
] $M11_AXI_0
|
|
|
|
set M12_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M12_AXI_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.PROTOCOL {AXI4LITE} \
|
|
] $M12_AXI_0
|
|
|
|
set M13_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M13_AXI_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.PROTOCOL {AXI4LITE} \
|
|
] $M13_AXI_0
|
|
|
|
|
|
# Create ports
|
|
set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ]
|
|
set spi0_sclk [ create_bd_port -dir O spi0_sclk ]
|
|
set spi0_mosi [ create_bd_port -dir O spi0_mosi ]
|
|
set spi0_miso [ create_bd_port -dir I spi0_miso ]
|
|
set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ]
|
|
set spi1_sclk [ create_bd_port -dir O spi1_sclk ]
|
|
set spi1_mosi [ create_bd_port -dir O spi1_mosi ]
|
|
set spi1_miso [ create_bd_port -dir I spi1_miso ]
|
|
set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ]
|
|
set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ]
|
|
set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ]
|
|
set rx_device_clk [ create_bd_port -dir I rx_device_clk ]
|
|
set tx_device_clk [ create_bd_port -dir I tx_device_clk ]
|
|
set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ]
|
|
set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ]
|
|
set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ]
|
|
set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ]
|
|
set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ]
|
|
set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ]
|
|
set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ]
|
|
set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ]
|
|
set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ]
|
|
set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ]
|
|
set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ]
|
|
set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ]
|
|
set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ]
|
|
set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ]
|
|
set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ]
|
|
set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ]
|
|
set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ]
|
|
set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ]
|
|
set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ]
|
|
set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ]
|
|
set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ]
|
|
set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ]
|
|
set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ]
|
|
set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ]
|
|
set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ]
|
|
set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ]
|
|
set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ]
|
|
set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ]
|
|
set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ]
|
|
set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ]
|
|
set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ]
|
|
set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ]
|
|
set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ]
|
|
set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ]
|
|
set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ]
|
|
set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ]
|
|
set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ]
|
|
set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ]
|
|
set ext_sync_in [ create_bd_port -dir I ext_sync_in ]
|
|
set tx_device_clk_out [ create_bd_port -dir O -type clk tx_device_clk_out ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {mxfe_tx_data_offload_m_axis:util_mxfe_upack_s_axis} \
|
|
] $tx_device_clk_out
|
|
set rx_device_clk_out [ create_bd_port -dir O -type clk rx_device_clk_out ]
|
|
set rx_device_clk_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst rx_device_clk_aresetn_out ]
|
|
set packed_fifo_wr_overflow_out [ create_bd_port -dir O packed_fifo_wr_overflow_out ]
|
|
set packed_fifo_wr_en_out [ create_bd_port -dir O packed_fifo_wr_en_out ]
|
|
set packed_fifo_wr_data_out [ create_bd_port -dir O -from 255 -to 0 -type data packed_fifo_wr_data_out ]
|
|
set sys_cpu_clk_out [ create_bd_port -dir O -type clk sys_cpu_clk_out ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {M11_AXI_0:M12_AXI_0:M13_AXI_0} \
|
|
] $sys_cpu_clk_out
|
|
set sys_cpu_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst sys_cpu_aresetn_out ]
|
|
set pl_clk2_clk125_out [ create_bd_port -dir O -type clk pl_clk2_clk125_out ]
|
|
set pl_clk2_clk125_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst pl_clk2_clk125_aresetn_out ]
|
|
set tx_device_clk_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst tx_device_clk_aresetn_out ]
|
|
set pl_clk1_clk250_out [ create_bd_port -dir O -type clk pl_clk1_clk250_out ]
|
|
set pl_clk1_clk250_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst pl_clk1_clk250_aresetn_out ]
|
|
set Res_0 [ create_bd_port -dir O -from 0 -to 0 Res_0 ]
|
|
|
|
# Create instance: sys_ps8, and set properties
|
|
set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 sys_ps8 ]
|
|
set_property -dict [list \
|
|
CONFIG.CAN0_BOARD_INTERFACE {custom} \
|
|
CONFIG.CAN1_BOARD_INTERFACE {custom} \
|
|
CONFIG.CSU_BOARD_INTERFACE {custom} \
|
|
CONFIG.DP_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM0_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM1_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM2_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM3_BOARD_INTERFACE {custom} \
|
|
CONFIG.GPIO_BOARD_INTERFACE {custom} \
|
|
CONFIG.IIC0_BOARD_INTERFACE {custom} \
|
|
CONFIG.IIC1_BOARD_INTERFACE {custom} \
|
|
CONFIG.NAND_BOARD_INTERFACE {custom} \
|
|
CONFIG.PCIE_BOARD_INTERFACE {custom} \
|
|
CONFIG.PJTAG_BOARD_INTERFACE {custom} \
|
|
CONFIG.PMU_BOARD_INTERFACE {custom} \
|
|
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR {0x1FFFFFFFF} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
|
|
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
|
|
CONFIG.PSU_IMPORT_BOARD_PRESET {} \
|
|
CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_0_SLEW {slow} \
|
|
CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_10_SLEW {slow} \
|
|
CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_11_SLEW {slow} \
|
|
CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_12_SLEW {slow} \
|
|
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_13_SLEW {slow} \
|
|
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_14_SLEW {slow} \
|
|
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_15_SLEW {slow} \
|
|
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_16_SLEW {slow} \
|
|
CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_17_SLEW {slow} \
|
|
CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_18_SLEW {slow} \
|
|
CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_19_SLEW {slow} \
|
|
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_1_SLEW {slow} \
|
|
CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_20_SLEW {slow} \
|
|
CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_21_SLEW {slow} \
|
|
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_22_SLEW {slow} \
|
|
CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_23_SLEW {slow} \
|
|
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_24_SLEW {slow} \
|
|
CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_25_SLEW {slow} \
|
|
CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_26_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_26_SLEW {slow} \
|
|
CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_27_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_27_SLEW {slow} \
|
|
CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_28_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_28_SLEW {fast} \
|
|
CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_29_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_29_SLEW {slow} \
|
|
CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_2_SLEW {slow} \
|
|
CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_30_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_30_SLEW {fast} \
|
|
CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_31_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_31_SLEW {slow} \
|
|
CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_32_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_32_SLEW {slow} \
|
|
CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_33_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_33_SLEW {fast} \
|
|
CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_35_SLEW {slow} \
|
|
CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_36_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_36_SLEW {slow} \
|
|
CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_37_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_37_SLEW {fast} \
|
|
CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_39_SLEW {slow} \
|
|
CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_3_SLEW {slow} \
|
|
CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_40_SLEW {slow} \
|
|
CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_42_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_42_SLEW {fast} \
|
|
CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_43_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_43_SLEW {slow} \
|
|
CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_44_SLEW {slow} \
|
|
CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_46_SLEW {slow} \
|
|
CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_47_SLEW {slow} \
|
|
CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_48_SLEW {slow} \
|
|
CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_49_SLEW {slow} \
|
|
CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_4_SLEW {slow} \
|
|
CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_50_SLEW {slow} \
|
|
CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_51_SLEW {slow} \
|
|
CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_54_SLEW {slow} \
|
|
CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_56_SLEW {slow} \
|
|
CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_57_SLEW {slow} \
|
|
CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_58_SLEW {slow} \
|
|
CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_59_SLEW {slow} \
|
|
CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_5_SLEW {slow} \
|
|
CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_60_SLEW {slow} \
|
|
CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_61_SLEW {slow} \
|
|
CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_62_SLEW {slow} \
|
|
CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_63_SLEW {slow} \
|
|
CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_64_SLEW {slow} \
|
|
CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_65_SLEW {slow} \
|
|
CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_66_SLEW {slow} \
|
|
CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_67_SLEW {slow} \
|
|
CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_68_SLEW {slow} \
|
|
CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_69_SLEW {slow} \
|
|
CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_6_SLEW {slow} \
|
|
CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_76_SLEW {fast} \
|
|
CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_77_SLEW {fast} \
|
|
CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_7_SLEW {slow} \
|
|
CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_8_SLEW {slow} \
|
|
CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
|
|
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_9_SLEW {slow} \
|
|
CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
|
|
SPI Flash#Quad SPI Flash#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 1#I2C 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#CAN 0#CAN 0#GPIO1 MIO#GPIO1 MIO#UART\
|
|
0#UART 0#CAN 1#CAN 1#GPIO1 MIO#GPIO1 MIO#USB0 Reset#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
|
|
3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
|
|
CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#scl_out#sda_out#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#phy_rx#phy_tx#gpio1[36]#gpio1[37]#rxd#txd#phy_tx#phy_rx#gpio1[42]#gpio1[43]#reset#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
|
|
\
|
|
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
|
|
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
|
|
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
|
|
CONFIG.PSU_SMC_CYCLE_T0 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T1 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T2 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T3 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T4 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T5 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T6 {NA} \
|
|
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
|
|
CONFIG.PSU_VALUE_SILVERSION {3} \
|
|
CONFIG.PSU__ACPU0__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU1__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU2__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU3__POWER__ON {1} \
|
|
CONFIG.PSU__ACTUAL__IP {1} \
|
|
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1200.000000} \
|
|
CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
|
|
CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
|
|
CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__CAN0__PERIPHERAL__IO {MIO 34 .. 35} \
|
|
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 40 .. 41} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1050.000000} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {75.000000} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300.000000} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
|
|
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
|
|
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__DDRC__AL {0} \
|
|
CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
|
|
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
|
|
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
|
|
CONFIG.PSU__DDRC__CL {16} \
|
|
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
|
|
CONFIG.PSU__DDRC__COMPONENTS {Components} \
|
|
CONFIG.PSU__DDRC__CWL {12} \
|
|
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
|
|
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
|
|
CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
|
|
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
|
|
CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
|
|
CONFIG.PSU__DDRC__ECC {Disabled} \
|
|
CONFIG.PSU__DDRC__ECC_SCRUB {0} \
|
|
CONFIG.PSU__DDRC__ENABLE {1} \
|
|
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
|
|
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
|
|
CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
|
|
CONFIG.PSU__DDRC__FGRM {1X} \
|
|
CONFIG.PSU__DDRC__FREQ_MHZ {1} \
|
|
CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
|
|
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
|
|
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
|
|
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
|
|
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
|
|
CONFIG.PSU__DDRC__PLL_BYPASS {0} \
|
|
CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
|
|
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
|
|
CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
|
|
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {17} \
|
|
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
|
|
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \
|
|
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
|
|
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
|
|
CONFIG.PSU__DDRC__T_FAW {30.0} \
|
|
CONFIG.PSU__DDRC__T_RAS_MIN {32} \
|
|
CONFIG.PSU__DDRC__T_RC {45.32} \
|
|
CONFIG.PSU__DDRC__T_RCD {16} \
|
|
CONFIG.PSU__DDRC__T_RP {16} \
|
|
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
|
|
CONFIG.PSU__DDRC__VREF {1} \
|
|
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
|
|
CONFIG.PSU__DDR_QOS_ENABLE {0} \
|
|
CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
|
|
CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
|
|
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \
|
|
CONFIG.PSU__DEVICE_TYPE {EG} \
|
|
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__DLL__ISUSED {1} \
|
|
CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
|
|
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
|
|
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
|
|
CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
|
|
CONFIG.PSU__EN_EMIO_TRACE {0} \
|
|
CONFIG.PSU__EP__IP {0} \
|
|
CONFIG.PSU__EXPAND__CORESIGHT {0} \
|
|
CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
|
|
CONFIG.PSU__EXPAND__GIC {0} \
|
|
CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
|
|
CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
|
|
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL2_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
|
|
CONFIG.PSU__FP__POWER__ON {1} \
|
|
CONFIG.PSU__FTM__CTI_IN_0 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_1 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_2 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_3 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_0 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_1 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_2 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_3 {0} \
|
|
CONFIG.PSU__FTM__GPI {0} \
|
|
CONFIG.PSU__FTM__GPO {0} \
|
|
CONFIG.PSU__GEM3_COHERENCY {0} \
|
|
CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__GEM__TSU__ENABLE {0} \
|
|
CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
|
|
CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
|
|
CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
|
|
CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
|
|
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
|
|
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \
|
|
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
|
|
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
|
|
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
|
|
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
|
|
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
|
|
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 24 .. 25} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
|
|
CONFIG.PSU__L2_BANK0__POWER__ON {1} \
|
|
CONFIG.PSU__LPDMA0_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA1_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA2_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA3_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA4_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA5_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA6_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA7_COHERENCY {0} \
|
|
CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
|
|
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
|
|
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
|
|
CONFIG.PSU__NUM_FABRIC_RESETS {1} \
|
|
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
|
|
CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
|
|
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
|
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
|
|
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
|
|
CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
|
|
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
|
|
CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
|
|
CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__PCIE__REVISION_ID {0x0} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK1_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK2_BUF {TRUE} \
|
|
CONFIG.PSU__PL__POWER__ON {1} \
|
|
CONFIG.PSU__PMU__GPO2__POLARITY {high} \
|
|
CONFIG.PSU__PMU__GPO3__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO4__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO5__POLARITY {low} \
|
|
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__PRESET_APPLIED {1} \
|
|
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
|
|
CONFIG.PSU__PROTECTION__ENABLE {0} \
|
|
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
|
|
subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
|
|
Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
|
|
| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
|
|
| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
|
|
subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
|
|
Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
|
|
SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
|
|
; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
|
|
; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
|
|
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
|
|
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
|
|
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
|
|
Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;97FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;1|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
|
|
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
|
|
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \
|
|
CONFIG.PSU__QSPI_COHERENCY {0} \
|
|
CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
|
|
CONFIG.PSU__REPORT__DBGLOG {0} \
|
|
CONFIG.PSU__RPU_COHERENCY {0} \
|
|
CONFIG.PSU__RPU__POWER__ON {1} \
|
|
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SD0_COHERENCY {0} \
|
|
CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
|
|
CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x12} \
|
|
CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x6} \
|
|
CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
|
|
CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x6} \
|
|
CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \
|
|
CONFIG.PSU__SD0__GRP_POW__ENABLE {1} \
|
|
CONFIG.PSU__SD0__GRP_POW__IO {MIO 23} \
|
|
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \
|
|
CONFIG.PSU__SD0__RESET__ENABLE {1} \
|
|
CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \
|
|
CONFIG.PSU__SD1_COHERENCY {0} \
|
|
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
|
|
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
|
|
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
|
|
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
|
|
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
|
|
CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
|
|
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
|
|
CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
|
|
CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
|
|
CONFIG.PSU__TCM0A__POWER__ON {1} \
|
|
CONFIG.PSU__TCM0B__POWER__ON {1} \
|
|
CONFIG.PSU__TCM1A__POWER__ON {1} \
|
|
CONFIG.PSU__TCM1B__POWER__ON {1} \
|
|
CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
|
|
CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__TRISTATE__INVERTED {1} \
|
|
CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
|
|
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
|
|
CONFIG.PSU__UART0__BAUD_RATE {115200} \
|
|
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 38 .. 39} \
|
|
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__USB0_COHERENCY {0} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
|
|
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
|
|
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
|
|
CONFIG.PSU__USB0__RESET__ENABLE {1} \
|
|
CONFIG.PSU__USB0__RESET__IO {MIO 44} \
|
|
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane1} \
|
|
CONFIG.PSU__USB__RESET__MODE {Shared MIO Pin} \
|
|
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
|
|
CONFIG.PSU__USE__ADMA {0} \
|
|
CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
|
|
CONFIG.PSU__USE__AUDIO {0} \
|
|
CONFIG.PSU__USE__CLK {0} \
|
|
CONFIG.PSU__USE__CLK0 {0} \
|
|
CONFIG.PSU__USE__CLK1 {0} \
|
|
CONFIG.PSU__USE__CLK2 {0} \
|
|
CONFIG.PSU__USE__CLK3 {0} \
|
|
CONFIG.PSU__USE__CROSS_TRIGGER {0} \
|
|
CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
|
|
CONFIG.PSU__USE__DEBUG__TEST {0} \
|
|
CONFIG.PSU__USE__EVENT_RPU {0} \
|
|
CONFIG.PSU__USE__FABRIC__RST {1} \
|
|
CONFIG.PSU__USE__FTM {0} \
|
|
CONFIG.PSU__USE__GDMA {0} \
|
|
CONFIG.PSU__USE__IRQ {0} \
|
|
CONFIG.PSU__USE__IRQ0 {1} \
|
|
CONFIG.PSU__USE__IRQ1 {1} \
|
|
CONFIG.PSU__USE__M_AXI_GP0 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP1 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
|
|
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
|
|
CONFIG.PSU__USE__RST0 {0} \
|
|
CONFIG.PSU__USE__RST1 {0} \
|
|
CONFIG.PSU__USE__RST2 {0} \
|
|
CONFIG.PSU__USE__RST3 {0} \
|
|
CONFIG.PSU__USE__RTC {0} \
|
|
CONFIG.PSU__USE__STM {0} \
|
|
CONFIG.PSU__USE__S_AXI_ACE {0} \
|
|
CONFIG.PSU__USE__S_AXI_ACP {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP0 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP1 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP3 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP4 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP5 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP6 {0} \
|
|
CONFIG.PSU__USE__USB3_0_HUB {0} \
|
|
CONFIG.PSU__USE__USB3_1_HUB {0} \
|
|
CONFIG.PSU__USE__VIDEO {0} \
|
|
CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
|
|
CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.QSPI_BOARD_INTERFACE {custom} \
|
|
CONFIG.SATA_BOARD_INTERFACE {custom} \
|
|
CONFIG.SD0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SD1_BOARD_INTERFACE {custom} \
|
|
CONFIG.SPI0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SPI1_BOARD_INTERFACE {custom} \
|
|
CONFIG.SUBPRESET1 {Custom} \
|
|
CONFIG.SUBPRESET2 {Custom} \
|
|
CONFIG.SWDT0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SWDT1_BOARD_INTERFACE {custom} \
|
|
CONFIG.TRACE_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC0_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC1_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC2_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC3_BOARD_INTERFACE {custom} \
|
|
CONFIG.UART0_BOARD_INTERFACE {custom} \
|
|
CONFIG.UART1_BOARD_INTERFACE {custom} \
|
|
CONFIG.USB0_BOARD_INTERFACE {custom} \
|
|
CONFIG.USB1_BOARD_INTERFACE {custom} \
|
|
] $sys_ps8
|
|
|
|
|
|
# Create instance: sys_rstgen, and set properties
|
|
set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen
|
|
|
|
|
|
# Create instance: sys_250m_rstgen, and set properties
|
|
set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen
|
|
|
|
|
|
# Create instance: spi0_csn_concat, and set properties
|
|
set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat
|
|
|
|
|
|
# Create instance: VCC_1, and set properties
|
|
set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {1} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $VCC_1
|
|
|
|
|
|
# Create instance: GND_1, and set properties
|
|
set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $GND_1
|
|
|
|
|
|
# Create instance: spi1_csn_concat, and set properties
|
|
set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat
|
|
|
|
|
|
# Create instance: axi_sysid_0, and set properties
|
|
set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ]
|
|
set_property CONFIG.ROM_ADDR_BITS {10} $axi_sysid_0
|
|
|
|
|
|
# Create instance: rom_sys_0, and set properties
|
|
set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.PATH_TO_FILE {/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9082/mem_init_sys.txt} \
|
|
CONFIG.ROM_ADDR_BITS {10} \
|
|
] $rom_sys_0
|
|
|
|
|
|
# Create instance: axi_cpu_interconnect, and set properties
|
|
set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {14} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_cpu_interconnect
|
|
|
|
|
|
# Create instance: sys_concat_intc_0, and set properties
|
|
set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0
|
|
|
|
|
|
# Create instance: sys_concat_intc_1, and set properties
|
|
set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1
|
|
|
|
|
|
# Create instance: axi_hp0_interconnect, and set properties
|
|
set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp0_interconnect
|
|
|
|
|
|
# Create instance: util_mxfe_xcvr, and set properties
|
|
set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.A_TXDIFFCTRL {0x0C} \
|
|
CONFIG.CH_HSPMUX {0x6868} \
|
|
CONFIG.CPLL_CFG0 {0x01FA} \
|
|
CONFIG.CPLL_CFG1 {0x0023} \
|
|
CONFIG.CPLL_CFG2 {0x0002} \
|
|
CONFIG.CPLL_FBDIV {2} \
|
|
CONFIG.CPLL_FBDIV_4_5 {5} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.POR_CFG {0x0000} \
|
|
CONFIG.PPF0_CFG {0x0F00} \
|
|
CONFIG.PREIQ_FREQ_BST {1} \
|
|
CONFIG.QPLL_CFG0 {0x333c} \
|
|
CONFIG.QPLL_CFG4 {0x0045} \
|
|
CONFIG.QPLL_CP {0x0FF} \
|
|
CONFIG.QPLL_CP_G3 {0x00F} \
|
|
CONFIG.QPLL_FBDIV {"0000010100"} \
|
|
CONFIG.QPLL_LPF {0x2FF} \
|
|
CONFIG.QPLL_REFCLK_DIV {1} \
|
|
CONFIG.RTX_BUF_CML_CTRL {000} \
|
|
CONFIG.RXCDR_CFG0 {0x0003} \
|
|
CONFIG.RXCDR_CFG2_GEN2 {0x265} \
|
|
CONFIG.RXCDR_CFG2_GEN4 {0x0164} \
|
|
CONFIG.RXCDR_CFG3 {0x001A} \
|
|
CONFIG.RXCDR_CFG3_GEN2 {0x1A} \
|
|
CONFIG.RXCDR_CFG3_GEN3 {0x001A} \
|
|
CONFIG.RXCDR_CFG3_GEN4 {0x0012} \
|
|
CONFIG.RXPI_CFG0 {0x0004} \
|
|
CONFIG.RXPI_CFG1 {0x0000} \
|
|
CONFIG.RX_CLK25_DIV {31} \
|
|
CONFIG.RX_LANE_RATE {15} \
|
|
CONFIG.RX_NUM_OF_LANES {8} \
|
|
CONFIG.RX_OUT_DIV {1} \
|
|
CONFIG.TXPI_CFG {0x0000} \
|
|
CONFIG.TX_CLK25_DIV {31} \
|
|
CONFIG.TX_LANE_RATE {15} \
|
|
CONFIG.TX_NUM_OF_LANES {8} \
|
|
CONFIG.TX_PI_BIASSET {3} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $util_mxfe_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_xcvr, and set properties
|
|
set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.FPGA_VOLTAGE {850} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.LPM_OR_DFE_N {1} \
|
|
CONFIG.NUM_OF_LANES {8} \
|
|
CONFIG.QPLL_ENABLE {0} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {0} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $axi_mxfe_rx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_jesd
|
|
create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd
|
|
|
|
# Create instance: rx_mxfe_tpl_core
|
|
create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_cpack, and set properties
|
|
set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {4} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {4} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_cpack
|
|
|
|
|
|
# Create instance: mxfe_rx_data_offload
|
|
create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload
|
|
|
|
# Create instance: axi_mxfe_rx_dma, and set properties
|
|
set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.ALLOW_ASYM_MEM {1} \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {false} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {256} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {256} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {0} \
|
|
CONFIG.DMA_TYPE_SRC {1} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
CONFIG.SYNC_TRANSFER_START {false} \
|
|
] $axi_mxfe_rx_dma
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_xcvr, and set properties
|
|
set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.FPGA_VOLTAGE {850} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {1} \
|
|
CONFIG.NUM_OF_LANES {8} \
|
|
CONFIG.QPLL_ENABLE {1} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {1} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $axi_mxfe_tx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_jesd
|
|
create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd
|
|
|
|
# Create instance: tx_mxfe_tpl_core
|
|
create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_upack, and set properties
|
|
set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {4} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {4} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_upack
|
|
|
|
|
|
# Create instance: mxfe_tx_data_offload
|
|
create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload
|
|
|
|
# Create instance: axi_mxfe_tx_dma, and set properties
|
|
set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.ALLOW_ASYM_MEM {1} \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {true} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {256} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {256} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {1} \
|
|
CONFIG.DMA_TYPE_SRC {0} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
] $axi_mxfe_tx_dma
|
|
|
|
|
|
# Create instance: rx_device_clk_rstgen, and set properties
|
|
set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ]
|
|
|
|
# Create instance: tx_device_clk_rstgen, and set properties
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set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ]
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# Create instance: axi_hp1_interconnect, and set properties
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set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ]
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|
set_property -dict [list \
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|
CONFIG.NUM_CLKS {2} \
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CONFIG.NUM_MI {1} \
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CONFIG.NUM_SI {1} \
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] $axi_hp1_interconnect
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# Create instance: axi_hp2_interconnect, and set properties
|
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set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
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|
CONFIG.NUM_SI {1} \
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] $axi_hp2_interconnect
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# Create instance: manual_sync_or, and set properties
|
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set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {1} \
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] $manual_sync_or
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# Create instance: cpack_rst_logic, and set properties
|
|
set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
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|
CONFIG.C_SIZE {3} \
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|
] $cpack_rst_logic
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# Create instance: rx_do_rstout_logic, and set properties
|
|
set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rx_do_rstout_logic
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# Create instance: cpack_reset_sources, and set properties
|
|
set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ]
|
|
set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources
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# Create instance: upack_rst_logic, and set properties
|
|
set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {2} \
|
|
] $upack_rst_logic
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|
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# Create instance: upack_reset_sources, and set properties
|
|
set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ]
|
|
set_property CONFIG.NUM_PORTS {2} $upack_reset_sources
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# Create instance: pl_clk2_clk125_rstgen, and set properties
|
|
set pl_clk2_clk125_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 pl_clk2_clk125_rstgen ]
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# Create interface connections
|
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connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi]
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|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi]
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|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi]
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|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_ports M11_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M12_AXI [get_bd_intf_ports M12_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M12_AXI]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M13_AXI [get_bd_intf_ports M13_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M13_AXI]
|
|
connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD]
|
|
connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD]
|
|
connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_4 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_4] [get_bd_intf_pins util_mxfe_xcvr/up_rx_4]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_5 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_5] [get_bd_intf_pins util_mxfe_xcvr/up_rx_5]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_6 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_6] [get_bd_intf_pins util_mxfe_xcvr/up_rx_6]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_7 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_7] [get_bd_intf_pins util_mxfe_xcvr/up_rx_7]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1]
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|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2]
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|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_4 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_4] [get_bd_intf_pins util_mxfe_xcvr/up_es_4]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_5 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_5] [get_bd_intf_pins util_mxfe_xcvr/up_es_5]
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|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_6 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_6] [get_bd_intf_pins util_mxfe_xcvr/up_es_6]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_7 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_7] [get_bd_intf_pins util_mxfe_xcvr/up_es_7]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins util_mxfe_xcvr/tx_0] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins util_mxfe_xcvr/tx_1] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins util_mxfe_xcvr/tx_2] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins util_mxfe_xcvr/tx_3] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy4 [get_bd_intf_pins util_mxfe_xcvr/tx_4] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy4]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy5 [get_bd_intf_pins util_mxfe_xcvr/tx_5] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy5]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy6 [get_bd_intf_pins util_mxfe_xcvr/tx_6] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy6]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy7 [get_bd_intf_pins util_mxfe_xcvr/tx_7] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy7]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_4 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_4] [get_bd_intf_pins util_mxfe_xcvr/up_tx_4]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_5 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_5] [get_bd_intf_pins util_mxfe_xcvr/up_tx_5]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_6 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_6] [get_bd_intf_pins util_mxfe_xcvr/up_tx_6]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_7 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_7] [get_bd_intf_pins util_mxfe_xcvr/up_tx_7]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_4 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_4] [get_bd_intf_pins util_mxfe_xcvr/up_cm_4]
|
|
connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins mxfe_rx_data_offload/m_axis] [get_bd_intf_pins axi_mxfe_rx_dma/s_axis]
|
|
connect_bd_intf_net -intf_net mxfe_tx_data_offload_m_axis [get_bd_intf_ports mxfe_tx_data_offload_m_axis] [get_bd_intf_pins mxfe_tx_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net s_axis_0_1 [get_bd_intf_ports util_mxfe_upack_s_axis] [get_bd_intf_pins util_mxfe_upack/s_axis]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins mxfe_tx_data_offload/s_axis] [get_bd_intf_pins axi_mxfe_tx_dma/m_axis]
|
|
connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD]
|
|
connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins tx_mxfe_tpl_core/link] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins util_mxfe_xcvr/rx_0] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins util_mxfe_xcvr/rx_1] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins util_mxfe_xcvr/rx_2] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins util_mxfe_xcvr/rx_3] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_4 [get_bd_intf_pins util_mxfe_xcvr/rx_4] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy4]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_5 [get_bd_intf_pins util_mxfe_xcvr/rx_5] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy5]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_6 [get_bd_intf_pins util_mxfe_xcvr/rx_6] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy6]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_7 [get_bd_intf_pins util_mxfe_xcvr/rx_7] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy7]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i]
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|
connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n]
|
|
connect_bd_net -net adc_dovf_1 [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] [get_bd_pins rx_mxfe_tpl_core/adc_dovf] [get_bd_ports packed_fifo_wr_overflow_out]
|
|
connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_phy_en_char_align [get_bd_pins axi_mxfe_rx_jesd/phy_en_char_align] [get_bd_pins util_mxfe_xcvr/rx_calign_0] [get_bd_pins util_mxfe_xcvr/rx_calign_1] [get_bd_pins util_mxfe_xcvr/rx_calign_2] [get_bd_pins util_mxfe_xcvr/rx_calign_3] [get_bd_pins util_mxfe_xcvr/rx_calign_4] [get_bd_pins util_mxfe_xcvr/rx_calign_5] [get_bd_pins util_mxfe_xcvr/rx_calign_6] [get_bd_pins util_mxfe_xcvr/rx_calign_7]
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|
connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data]
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|
connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid]
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|
connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_sync [get_bd_pins axi_mxfe_rx_jesd/sync] [get_bd_ports rx_sync_0]
|
|
connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_4] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_5] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_6] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_7]
|
|
connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4]
|
|
connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2]
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connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_4]
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connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr]
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connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1]
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connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset]
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connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in]
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connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i]
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connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req]
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connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req]
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connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in]
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connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1]
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connect_bd_net -net pl_clk2_clk125_rstgen_peripheral_aresetn [get_bd_pins pl_clk2_clk125_rstgen/peripheral_aresetn] [get_bd_ports pl_clk2_clk125_aresetn_out]
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connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3]
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connect_bd_net -net ref_clk_q1_1 [get_bd_ports ref_clk_q1] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_4] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_4] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_5] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_6] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_7]
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connect_bd_net -net rom_sys_0_rom_data [get_bd_pins rom_sys_0/rom_data] [get_bd_pins axi_sysid_0/sys_rom_data]
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connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n]
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connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p]
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connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n]
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connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p]
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connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n]
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connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p]
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connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n]
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connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p]
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connect_bd_net -net rx_data_4_n_1 [get_bd_ports rx_data_4_n] [get_bd_pins util_mxfe_xcvr/rx_4_n]
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connect_bd_net -net rx_data_4_p_1 [get_bd_ports rx_data_4_p] [get_bd_pins util_mxfe_xcvr/rx_4_p]
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connect_bd_net -net rx_data_5_n_1 [get_bd_ports rx_data_5_n] [get_bd_pins util_mxfe_xcvr/rx_5_n]
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connect_bd_net -net rx_data_5_p_1 [get_bd_ports rx_data_5_p] [get_bd_pins util_mxfe_xcvr/rx_5_p]
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connect_bd_net -net rx_data_6_n_1 [get_bd_ports rx_data_6_n] [get_bd_pins util_mxfe_xcvr/rx_6_n]
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connect_bd_net -net rx_data_6_p_1 [get_bd_ports rx_data_6_p] [get_bd_pins util_mxfe_xcvr/rx_6_p]
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connect_bd_net -net rx_data_7_n_1 [get_bd_ports rx_data_7_n] [get_bd_pins util_mxfe_xcvr/rx_7_n]
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connect_bd_net -net rx_data_7_p_1 [get_bd_ports rx_data_7_p] [get_bd_pins util_mxfe_xcvr/rx_7_p]
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connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_cpack/clk] [get_bd_ports rx_device_clk_out]
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connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] [get_bd_ports rx_device_clk_aresetn_out]
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connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins rx_device_clk_rstgen/peripheral_reset] [get_bd_pins cpack_reset_sources/In0]
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connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins rx_do_rstout_logic/Res] [get_bd_ports Res_0]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3]
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connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins rx_mxfe_tpl_core/adc_rst] [get_bd_pins cpack_reset_sources/In1] [get_bd_pins cpack_reset_sources/In2]
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connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] [get_bd_pins manual_sync_or/Op1]
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connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en]
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connect_bd_net -net spi0_csn_concat_dout [get_bd_pins spi0_csn_concat/dout] [get_bd_ports spi0_csn]
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connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i]
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connect_bd_net -net spi1_csn_concat_dout [get_bd_pins spi1_csn_concat/dout] [get_bd_ports spi1_csn]
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connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i]
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connect_bd_net -net sync_1 [get_bd_ports tx_sync_0] [get_bd_pins axi_mxfe_tx_jesd/sync]
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connect_bd_net -net sys_250m_clk [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/saxihp2_fpd_aclk] [get_bd_ports pl_clk1_clk250_out]
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connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset]
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connect_bd_net -net sys_250m_resetn [get_bd_pins sys_250m_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_pins axi_hp2_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn] [get_bd_ports pl_clk1_clk250_aresetn_out]
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connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0]
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connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_xcvr/up_clk] [get_bd_ports sys_cpu_clk_out]
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connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins util_mxfe_xcvr/up_rstn] [get_bd_ports sys_cpu_aresetn_out]
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connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_pins sys_ps8/emio_gpio_o] [get_bd_ports gpio_o]
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connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_pins sys_ps8/emio_gpio_t] [get_bd_ports gpio_t]
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connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_pins sys_ps8/emio_spi0_m_o] [get_bd_ports spi0_mosi]
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connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_pins sys_ps8/emio_spi0_sclk_o] [get_bd_ports spi0_sclk]
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connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] [get_bd_pins spi0_csn_concat/In1]
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connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] [get_bd_pins spi0_csn_concat/In2]
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connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins sys_ps8/emio_spi0_ss_o_n] [get_bd_pins spi0_csn_concat/In0]
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connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_pins sys_ps8/emio_spi1_m_o] [get_bd_ports spi1_mosi]
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connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_pins sys_ps8/emio_spi1_sclk_o] [get_bd_ports spi1_sclk]
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connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] [get_bd_pins spi1_csn_concat/In1]
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connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] [get_bd_pins spi1_csn_concat/In2]
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connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins sys_ps8/emio_spi1_ss_o_n] [get_bd_pins spi1_csn_concat/In0]
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connect_bd_net -net sys_ps8_pl_clk2 [get_bd_pins sys_ps8/pl_clk2] [get_bd_ports pl_clk2_clk125_out] [get_bd_pins pl_clk2_clk125_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins pl_clk2_clk125_rstgen/ext_reset_in]
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connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref]
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connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref]
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connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_upack/clk] [get_bd_ports tx_device_clk_out]
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connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] [get_bd_ports tx_device_clk_aresetn_out]
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connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2]
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connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3]
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connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1]
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connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] [get_bd_pins manual_sync_or/Op2]
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connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en]
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connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1]
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connect_bd_net -net upack_rst_logic_Res [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset]
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connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] [get_bd_ports packed_fifo_wr_data_out]
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connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] [get_bd_ports packed_fifo_wr_en_out]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins util_mxfe_upack/fifo_rd_data_0] [get_bd_pins tx_mxfe_tpl_core/dac_data_0]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins util_mxfe_upack/fifo_rd_data_1] [get_bd_pins tx_mxfe_tpl_core/dac_data_1]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins util_mxfe_upack/fifo_rd_data_2] [get_bd_pins tx_mxfe_tpl_core/dac_data_2]
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connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins util_mxfe_upack/fifo_rd_data_3] [get_bd_pins tx_mxfe_tpl_core/dac_data_3]
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connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] [get_bd_pins axi_mxfe_rx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3] [get_bd_pins util_mxfe_xcvr/rx_clk_4] [get_bd_pins util_mxfe_xcvr/rx_clk_5] [get_bd_pins util_mxfe_xcvr/rx_clk_6] [get_bd_pins util_mxfe_xcvr/rx_clk_7]
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connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_pins util_mxfe_xcvr/tx_0_n] [get_bd_ports tx_data_0_n]
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connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_pins util_mxfe_xcvr/tx_0_p] [get_bd_ports tx_data_0_p]
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connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_pins util_mxfe_xcvr/tx_1_n] [get_bd_ports tx_data_1_n]
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connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_pins util_mxfe_xcvr/tx_1_p] [get_bd_ports tx_data_1_p]
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connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_pins util_mxfe_xcvr/tx_2_n] [get_bd_ports tx_data_2_n]
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|
connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_pins util_mxfe_xcvr/tx_2_p] [get_bd_ports tx_data_2_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_pins util_mxfe_xcvr/tx_3_n] [get_bd_ports tx_data_3_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_pins util_mxfe_xcvr/tx_3_p] [get_bd_ports tx_data_3_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_4_n [get_bd_pins util_mxfe_xcvr/tx_4_n] [get_bd_ports tx_data_4_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_4_p [get_bd_pins util_mxfe_xcvr/tx_4_p] [get_bd_ports tx_data_4_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_5_n [get_bd_pins util_mxfe_xcvr/tx_5_n] [get_bd_ports tx_data_5_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_5_p [get_bd_pins util_mxfe_xcvr/tx_5_p] [get_bd_ports tx_data_5_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_6_n [get_bd_pins util_mxfe_xcvr/tx_6_n] [get_bd_ports tx_data_6_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_6_p [get_bd_pins util_mxfe_xcvr/tx_6_p] [get_bd_ports tx_data_6_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_7_n [get_bd_pins util_mxfe_xcvr/tx_7_n] [get_bd_ports tx_data_7_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_7_p [get_bd_pins util_mxfe_xcvr/tx_7_p] [get_bd_ports tx_data_7_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] [get_bd_pins axi_mxfe_tx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3] [get_bd_pins util_mxfe_xcvr/tx_clk_4] [get_bd_pins util_mxfe_xcvr/tx_clk_5] [get_bd_pins util_mxfe_xcvr/tx_clk_6] [get_bd_pins util_mxfe_xcvr/tx_clk_7]
|
|
|
|
# Create address segments
|
|
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M11_AXI_0/Reg] -force
|
|
assign_bd_address -offset 0x81000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M12_AXI_0/Reg] -force
|
|
assign_bd_address -offset 0x82000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M13_AXI_0/Reg] -force
|
|
assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C430000 -range 0x00001000 -with_name SEG_data_axi_mxfe_tx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_tx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_tx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x85000000 -range 0x00010000 -with_name SEG_data_axi_sysid_0 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C450000 -range 0x00010000 -with_name SEG_data_mxfe_rx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C440000 -range 0x00010000 -with_name SEG_data_mxfe_tx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A10000 -range 0x00002000 -with_name SEG_data_rx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B10000 -range 0x00002000 -with_name SEG_data_tx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force
|
|
|
|
# Exclude Address Segments
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH]
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH]
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH]
|
|
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_system()
|
|
|
|
cr_bd_system ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ]
|
|
|
|
#call make_wrapper to create wrapper files
|
|
if { [get_property IS_LOCKED [ get_files -norecurse [list raw_eth.bd]] ] == 1 } {
|
|
import_files -fileset sources_1 [file normalize "${origin_dir}/ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/bd/raw_eth/hdl/raw_eth_wrapper.v" ]
|
|
} else {
|
|
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse [list raw_eth.bd]] -top]
|
|
add_files -norecurse -fileset sources_1 $wrapper_path
|
|
}
|
|
|
|
|
|
set idrFlowPropertiesConstraints ""
|
|
catch {
|
|
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
|
|
set_param runs.disableIDRFlowPropertyConstraints 1
|
|
}
|
|
|
|
# Create 'synth_1' run (if not found)
|
|
if {[string equal [get_runs -quiet synth_1] ""]} {
|
|
create_run -name synth_1 -part xczu19eg-ffvc1760-2-i -flow {Vivado Synthesis 2023} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
|
} else {
|
|
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
|
set_property flow "Vivado Synthesis 2023" [get_runs synth_1]
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
|
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj
|
|
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
|
|
|
# Create 'synth_5' run (if not found)
|
|
if {[string equal [get_runs -quiet synth_5] ""]} {
|
|
create_run -name synth_5 -part xczu19eg-ffvc1760-2-i -flow {Vivado Synthesis 2023} -strategy "Flow_AreaMultThresholdDSP" -report_strategy {No Reports} -constrset constrs_1
|
|
} else {
|
|
set_property strategy "Flow_AreaMultThresholdDSP" [get_runs synth_5]
|
|
set_property flow "Vivado Synthesis 2023" [get_runs synth_5]
|
|
}
|
|
set obj [get_runs synth_5]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'synth_5_synth_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs synth_5] synth_5_synth_report_utilization_0] "" ] } {
|
|
create_report_config -report_name synth_5_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_5
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs synth_5] synth_5_synth_report_utilization_0]
|
|
if { $obj != "" } {
|
|
set_property -name "display_name" -value "synth_5_synth_report_utilization_0" -objects $obj
|
|
|
|
}
|
|
set obj [get_runs synth_5]
|
|
set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj
|
|
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Flow_AreaMultThresholdDSP" -objects $obj
|
|
set_property -name "steps.synth_design.args.directive" -value "AreaMultThresholdDSP" -objects $obj
|
|
|
|
# set the current synth run
|
|
current_run -synthesis [get_runs synth_1]
|
|
|
|
# Create 'impl_1' run (if not found)
|
|
if {[string equal [get_runs -quiet impl_1] ""]} {
|
|
create_run -name impl_1 -part xczu19eg-ffvc1760-2-i -flow {Vivado Implementation 2023} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
|
} else {
|
|
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
|
set_property flow "Vivado Implementation 2023" [get_runs impl_1]
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_io_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.verbose" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_power_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
|
|
|
# set the current impl run
|
|
current_run -implementation [get_runs impl_1]
|
|
catch {
|
|
if { $idrFlowPropertiesConstraints != {} } {
|
|
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
|
|
}
|
|
}
|
|
|
|
puts "INFO: Project created:${_xil_proj_name_}"
|
|
# Create 'drc_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {drc_1} -type drc
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
|
|
|
# Create 'methodology_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {methodology_1} -type methodology
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
|
|
|
# Create 'power_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {power_1} -type power
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
|
|
|
# Create 'timing_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {timing_1} -type timing
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
|
|
|
# Create 'utilization_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_1} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
|
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
|
set_property -name "run.step" -value "synth_design" -objects $obj
|
|
set_property -name "run.type" -value "synthesis" -objects $obj
|
|
|
|
# Create 'utilization_2' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_2} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
|
|
|
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
|
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
|
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
|
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
|
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
|
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|