moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,455 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use ieee.std_logic_textio.all;
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Library xpm;
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use xpm.vcomponents.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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entity axi_lite_traffic_gen is
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generic (
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C_M_AXI_ADDR_WIDTH : integer := 32;
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C_M_AXI_DATA_WIDTH : integer := 32
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);
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port (
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m_axi_aclk : in std_logic;
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m_axi_aresetn : in std_logic;
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-- Master Interface Write Address
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m_axi_awaddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
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m_axi_awprot : out std_logic_vector (2 downto 0);
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m_axi_awvalid : out std_logic;
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m_axi_awready : in std_logic;
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-- master interface write data
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m_axi_wdata : out std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
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m_axi_wstrb : out std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0);
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m_axi_wvalid : out std_logic;
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m_axi_wready : in std_logic;
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-- master interface write response
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m_axi_bresp : in std_logic_vector (1 downto 0);
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m_axi_bvalid : in std_logic;
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m_axi_bready : out std_logic;
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-- master interface read address
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m_axi_araddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
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m_axi_arprot : out std_logic_vector (2 downto 0);
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m_axi_arvalid : out std_logic;
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m_axi_arready : in std_logic;
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-- master interface read data
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m_axi_rdata : in std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
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m_axi_rresp : in std_logic_vector (1 downto 0);
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m_axi_rvalid : in std_logic;
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m_axi_rready : out std_logic;
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num_burst_cnt_out : out std_logic_vector(7 downto 0);
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xfer_en_out : out std_logic;
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xfer_done_in : in std_logic;
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dma_xfer_done_in : in std_logic;
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buffer_rdy_intr_in : in std_logic
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);
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end entity axi_lite_traffic_gen;
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architecture impl of axi_lite_traffic_gen is
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procedure writeReg (
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addr : in std_logic_vector(31 downto 0);
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wr_data : in std_logic_vector(31 downto 0);
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signal m_axi_aclk : in std_logic;
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signal awaddr : out std_logic_vector(31 downto 0);
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signal wdata : out std_logic_vector(31 downto 0);
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signal wstrb : out std_logic_vector( 3 downto 0);
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signal awvalid : out std_logic;
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signal wvalid : out std_logic;
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signal bready : out std_logic;
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signal awready : in std_logic;
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signal wready : in std_logic;
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signal bvalid : in std_logic;
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signal done : out std_logic
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) is
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begin
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wait until rising_edge(m_axi_aclk);
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done <= '0';
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awaddr <= addr;
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wdata <= wr_data;
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wstrb <= x"F";
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wait until rising_edge(m_axi_aclk);
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awvalid <= '1';
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wvalid <= '1';
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bready <= '1';
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wait until rising_edge(m_axi_aclk);
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wait until wready = '1' and awready = '1';
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awvalid <= '0';
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wvalid <= '0';
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wait until bvalid = '1';
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wait until rising_edge(m_axi_aclk);
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done <= '1';
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wait until rising_edge(m_axi_aclk);
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done <= '0';
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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end procedure writeReg;
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procedure readReg (
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addr : in std_logic_vector(31 downto 0);
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signal m_axi_aclk : in std_logic;
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signal araddr : out std_logic_vector(31 downto 0);
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signal rready : out std_logic;
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signal arvalid : out std_logic;
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signal arready : in std_logic;
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signal rvalid : in std_logic;
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signal rdata : in std_logic_vector(31 downto 0);
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signal rd_data : out std_logic_vector(31 downto 0);
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signal done : out std_logic
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) is
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begin
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wait until rising_edge(m_axi_aclk);
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done <= '0';
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araddr <= addr;
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wait until rising_edge(m_axi_aclk);
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rready <= '1';
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arvalid <= '1';
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wait until rising_edge(m_axi_aclk);
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wait until arready = '1';
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wait until rising_edge(m_axi_aclk);
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arvalid <= '0';
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-- wait until rising_edge(m_axi_aclk);
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wait until rvalid = '1';
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wait until rising_edge(m_axi_aclk);
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rready <= '0';
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rd_data <= rdata;
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done <= '1';
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wait until rising_edge(m_axi_aclk);
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done <= '0';
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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wait until rising_edge(m_axi_aclk);
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end procedure readReg;
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signal m_axi_awaddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal m_axi_awvalid_i : std_logic := '0';
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signal m_axi_wdata_i : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
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signal m_axi_wstrb_i : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
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signal m_axi_wvalid_i : std_logic := '0';
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signal m_axi_bready_i : std_logic := '0';
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signal m_axi_araddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal m_axi_arvalid_i : std_logic := '0';
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signal m_axi_rready_i : std_logic := '0';
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signal read_complete : std_logic := '0';
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signal read_complete_r : std_logic := '0';
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signal rd_data : std_logic_vector(31 downto 0);
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signal write_complete : std_logic := '0';
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signal write_complete_r : std_logic := '0';
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signal num_burst_cnt : std_logic_vector(7 downto 0) := (others => '0');
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signal xfer_en : std_logic := '0';
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signal buffer_rdy_intr_r : std_logic;
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signal m_axi_awaddr_ii : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal m_axi_awvalid_ii : std_logic := '0';
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signal m_axi_wdata_ii : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
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signal m_axi_wstrb_ii : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
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signal m_axi_wvalid_ii : std_logic := '0';
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signal m_axi_bready_ii : std_logic := '0';
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signal s2mm_cmd_en : std_logic := '0';
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begin
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m_axi_awaddr <= m_axi_awaddr_i when s2mm_cmd_en = '0' else m_axi_awaddr_ii;
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m_axi_awvalid <= m_axi_awvalid_i when s2mm_cmd_en = '0' else m_axi_awvalid_ii;
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m_axi_wdata <= m_axi_wdata_i when s2mm_cmd_en = '0' else m_axi_wdata_ii;
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m_axi_wstrb <= m_axi_wstrb_i when s2mm_cmd_en = '0' else m_axi_wstrb_ii;
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m_axi_wvalid <= m_axi_wvalid_i when s2mm_cmd_en = '0' else m_axi_wvalid_ii;
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m_axi_bready <= m_axi_bready_i when s2mm_cmd_en = '0' else m_axi_bready_ii;
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m_axi_araddr <= m_axi_araddr_i;
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m_axi_arvalid <= m_axi_arvalid_i;
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m_axi_rready <= m_axi_rready_i;
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m_axi_awprot <= "000";
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m_axi_arprot <= "000";
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num_burst_cnt_out <= num_burst_cnt;
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xfer_en_out <= xfer_en;
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process
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variable my_line : line;
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begin
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wait for 10 us;
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----------------------
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write(my_line, string'("reading REG_VERSION at 0x00")); -- read REG_VERSION
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writeline(output, my_line);
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readReg(x"0000_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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write(my_line, string'("reading REG_CONFIG at 0x0C")); -- read REG_CONFIG
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writeline(output, my_line);
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readReg(x"0000_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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write(my_line, string'("reading REG_PPS_IRQ_MASK at 0x10")); -- read REG_PPS_IRQ_MASK
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writeline(output, my_line);
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readReg(x"0000_0010", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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write(my_line, string'("reading REG_FPGA_INFO at 0x1C")); -- read REG_FPGA_INFO
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writeline(output, my_line);
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readReg(x"0000_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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wait for 5 us;
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write(my_line, string'("reading REG_STATUS1 at 0x54")); -- read REG_STATUS1
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writeline(output, my_line);
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readReg(x"0000_0054", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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write(my_line, string'("reading REG_STATUS2 at 0x58")); -- read REG_STATUS2
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writeline(output, my_line);
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readReg(x"0000_0058", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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write(my_line, string'("reading REG_STATUS3 at 0x5C")); -- read REG_STATUS3
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writeline(output, my_line);
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readReg(x"0000_005C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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wait for 10 us;
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write(my_line, string'("writing REG_RSTN at 0x040")); -- write REG_RSTN
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writeline(output, my_line);
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writeReg(x"0000_0040", x"0000_0003", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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wait for 5 us;
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write(my_line, string'("writing REG_TPL_DESCRIPTOR_1 at 0x240")); -- write REG_TPL_DESCRIPTOR_1
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writeline(output, my_line);
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writeReg(x"0000_0240", x"0401_0408", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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write(my_line, string'("writing REG_TPL_DESCRIPTOR_2 at 0x244")); -- write REG_TPL_DESCRIPTOR_2
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writeline(output, my_line);
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writeReg(x"0000_0244", x"0000_1010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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----sending user data
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wait for 1 us;
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write(my_line, string'("writing REG_USR_CNTRL_3 at 0x420")); -- write REG_USR_CNTRL_3
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writeline(output, my_line);
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writeReg(x"0000_0420", x"0200_8010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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wait for 1 us;
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write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write CHAN 0 - REG_CHAN_CNTRL_7 -- input data (DMA)
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writeline(output, my_line);
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writeReg(x"0000_0418", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x458")); -- write CHAN 1 - write REG_CHAN_CNTRL_7 -- input data (DMA)
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writeline(output, my_line);
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writeReg(x"0000_0458", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x498")); -- write CHAN 2 - write REG_CHAN_CNTRL_7 -- input data (DMA)
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writeline(output, my_line);
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writeReg(x"0000_0498", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x4D8")); -- write CHAN 3 - write REG_CHAN_CNTRL_7 -- input data (DMA)
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writeline(output, my_line);
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writeReg(x"0000_04D8", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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-- wait for 1 us;
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--
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-- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 - inverted pn15
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-- writeline(output, my_line);
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-- writeReg(x"0000_0418", x"0000_0005", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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-- write(my_line, string'("writing REG_CHAN_CNTRL_5 at 0x410")); -- write REG_CHAN_CNTRL_5
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-- writeline(output, my_line);
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-- writeReg(x"0000_0410", x"DEAD_BEEF", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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--
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-- wait for 1 us;
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--
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-- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 -- pattern (SED)
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-- writeline(output, my_line);
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-- writeReg(x"0000_0418", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
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-- write(my_line, string'("reading TDFV at 0x0C")); -- read Transmit Data FIFO Vacancy
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-- writeline(output, my_line);
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-- readReg(x"0003_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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--
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-- write(my_line, string'("reading RDFO at 0x1C")); -- Receive Data FIFO Occupancy
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-- writeline(output, my_line);
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-- readReg(x"0003_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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--
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-- write(my_line, string'("reading RLR at 0x24")); -- Receive Length Register
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-- writeline(output, my_line);
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-- readReg(x"0003_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
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--
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--
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--
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||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("writing (TDFR) at 0x8")); --Transmit Data FIFO Reset
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0008", x"0000_00A5", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
--
|
||||
--
|
||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("-----------------------------------"));
|
||||
-- writeline(output, my_line);
|
||||
-- write(my_line, string'("writing TDFD at 0x10")); -- Transmit Data FIFO 32-bit Wide Data Write Port
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0010", x"dead_beef", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing TLR at 0x14")); --MM2S Source Address. Lower 32 bits of address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0014", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- wait for 1 us;
|
||||
-- write(my_line, string'("reading ISR at 0x00")); -- read Interrupt Status Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0003_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- wait for 500 ns;
|
||||
-- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RLR at 0x20")); -- read Receive Data FIFO 32-bit Wide Data Read Port
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0020", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
-- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register
|
||||
-- writeline(output, my_line);
|
||||
-- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete);
|
||||
--
|
||||
|
||||
-- write(my_line, string'("writing MM2S_SA_MSB at 0x1C")); -- MM2S Source Address. Upper 32 bits of address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_001C", x"0000_0000", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- -- dma transfer starts here (1)
|
||||
-- write(my_line, string'("writing MM2S_LENGTH at 0x28")); -- MM2S Transfer Length (Bytes)
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0028", conv_std_logic_vector(16, 32), m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
-- -- 2048+8 ==> 8 is packet length
|
||||
--
|
||||
-- wait until dma_xfer_done_in = '1';
|
||||
-- wait for 50 us;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wait; -- wait here forever
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
-- process
|
||||
-- variable my_line : line;
|
||||
-- begin
|
||||
---- if(rising_edge(m_axi_aclk)) then
|
||||
---- buffer_rdy_intr_r <= buffer_rdy_intr_in;
|
||||
---- if(buffer_rdy_intr_in = '1' and buffer_rdy_intr_r = '0') then
|
||||
--
|
||||
--
|
||||
-- -- dma the data **********From Stream to Memory ****************
|
||||
-- wait until buffer_rdy_intr_in = '1';
|
||||
-- s2mm_cmd_en <= '1';
|
||||
-- wait for 100 ns;
|
||||
-- write(my_line, string'("-----------------------------------"));
|
||||
-- writeline(output, my_line);
|
||||
--
|
||||
-- -- 0x34 S2MM DMA Status register
|
||||
--
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DMACR at 0x30")); -- S2MM DMA Control register
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0030", x"0000_7001", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DA at 0x48")); -- S2MM Destination Address. Lower 32 bit address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0048", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- write(my_line, string'("writing S2MM_DA_MSB at 0x4C")); -- S2MM Destination Address. Upper 32 bit address.
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_004C", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- -- dma transfer starts here
|
||||
-- write(my_line, string'("writing S2MM_LENGTH at 0x58")); -- S2MM Buffer Length (Bytes)
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0058", x"0000_0800", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
-- wait for 100 ns;
|
||||
-- -- dma transfer starts here
|
||||
-- write(my_line, string'("writing S2MM_LENGTH at 0x58"));
|
||||
-- writeline(output, my_line);
|
||||
-- writeReg(x"0000_0058", x"0000_1000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete);
|
||||
--
|
||||
--
|
||||
-- wait for 100 ns;
|
||||
-- s2mm_cmd_en <= '0';
|
||||
--
|
||||
-- wait; -- wait here forever
|
||||
-- end process;
|
||||
|
||||
|
||||
|
||||
process(m_axi_aclk)
|
||||
variable my_line : line;
|
||||
begin
|
||||
read_complete_r <= read_complete;
|
||||
write_complete_r <= write_complete;
|
||||
|
||||
if(read_complete = '1' and read_complete_r = '0') then
|
||||
write(my_line, string'("Read Complete: "));
|
||||
hwrite(my_line, rd_data);
|
||||
writeline(output, my_line);
|
||||
end if;
|
||||
|
||||
if(write_complete = '1' and write_complete_r = '0') then
|
||||
write(my_line, string'("Write Complete: "));
|
||||
writeline(output, my_line);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture impl;
|
||||
@@ -0,0 +1,557 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:53:22 03/24/2017
|
||||
-- Design Name:
|
||||
-- Module Name:
|
||||
-- Project Name: xem7350
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: dac_interface
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
entity tb_fifos is
|
||||
end tb_fifos;
|
||||
|
||||
architecture behavior of tb_fifos is
|
||||
|
||||
constant C_M_AXI_DATA_WIDTH : integer := 32;
|
||||
constant C_M_AXI_ADDR_WIDTH : integer := 32;
|
||||
|
||||
-- Clock period definitions
|
||||
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
|
||||
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
|
||||
|
||||
|
||||
signal m_axis_aclk : std_logic := '0';
|
||||
signal reset_n : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal reset : std_logic;
|
||||
|
||||
signal s00_axi_aclk : std_logic := '0';
|
||||
|
||||
|
||||
|
||||
signal dds_pulse_data_0 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_0 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_0 : std_logic;
|
||||
|
||||
signal dds_pulse_data_1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_1 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_1 : std_logic;
|
||||
|
||||
signal dds_pulse_data_2 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_2 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_2 : std_logic;
|
||||
|
||||
signal dds_pulse_data_3 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_dval_3 : std_logic := '0';
|
||||
|
||||
signal m_axis_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m_axis_tvalid_3 : std_logic;
|
||||
|
||||
signal dds_pulse_data_word : std_logic_vector(127 downto 0);
|
||||
signal dds_pulse_data_word_dval : std_logic;
|
||||
signal dds_pulse_data_word_tready : std_logic;
|
||||
signal dds_pulse_data_word_tready_valid : std_logic;
|
||||
|
||||
signal m_axis_tdata_i : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid_i : std_logic;
|
||||
signal m_axis_tready_i : std_logic;
|
||||
|
||||
signal s_axis_tready_0 : std_logic;
|
||||
signal s_axis_tready_1 : std_logic;
|
||||
signal s_axis_tready_2 : std_logic;
|
||||
signal s_axis_tready_3 : std_logic;
|
||||
|
||||
signal fifo_en : std_logic := '1';
|
||||
|
||||
signal fifo_rd_data_0 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_1 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_2 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_3 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_4 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_5 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_6 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_7 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_8 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_9 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_10 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_11 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_12 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_13 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_14 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_15 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_16 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_17 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_18 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_19 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_20 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_21 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_22 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_23 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_24 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_25 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_26 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_27 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_28 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_29 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_30 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_31 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_32 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_33 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_34 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_35 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_36 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_37 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_38 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_39 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_40 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_41 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_42 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_43 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_44 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_45 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_46 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_47 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_48 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_49 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_50 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_51 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_52 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_53 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_54 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_55 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_56 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_57 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_58 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_59 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_60 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_61 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_62 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_63 : std_logic_vector(15 downto 0);
|
||||
|
||||
signal fifo_rd_valid : std_logic;
|
||||
signal fifo_rd_underflow : std_logic;
|
||||
|
||||
signal cmd_send_0 : std_logic := '0';
|
||||
signal dac_holdoff_0 : std_logic := '1';
|
||||
|
||||
signal fifo_rd_en : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_aclk <= not m_axis_aclk after M_AXI_ACLK_PERIOD/2;
|
||||
s00_axi_aclk <= not s00_axi_aclk after S_AXI_ACLK_PERIOD/2;
|
||||
|
||||
process(m_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk)) then
|
||||
reset_n <= reset_n(1 to 2) & '1';
|
||||
|
||||
if (reset_n = "111") then
|
||||
fifo_rd_en <= not fifo_rd_en;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reset <= not reset_n(0);
|
||||
|
||||
-- i_pdw_wrapper_0 : entity work.pdw_wrapper
|
||||
-- generic map (
|
||||
-- SIM_ENABLED => FALSE,
|
||||
-- FPGA_REVISION_DATE => x"0528_2024",
|
||||
-- MINOR_REV => x"01"
|
||||
-- )
|
||||
-- port map (
|
||||
-- s_axi_aclk_in => s00_axi_aclk,
|
||||
-- s_axi_aresetn_in => reset_n(0),
|
||||
-- cmd_idx_in => "010",
|
||||
-- cmd_send_in => cmd_send_0,
|
||||
-- loop_mode_en_in => x"00",
|
||||
--
|
||||
-- mode_in => '0',
|
||||
-- scale_in => x"8000",
|
||||
-- dac_holdoff_in => dac_holdoff_0,
|
||||
--
|
||||
-- reserv1_in => x"00000000",
|
||||
-- dds_phase_inc_dwell_time_in => x"00000000",
|
||||
-- dds_phase_inc_step_size_in => x"00000000",
|
||||
-- idle_samples_in => x"00000000",
|
||||
-- dds_samples_in => x"000004E2",
|
||||
-- phase_inc_in => x"0624DD2F",
|
||||
-- phase_off_in => x"00000000",
|
||||
-- swap_sf_in => x"00008000",
|
||||
-- latch_en_in => '0',
|
||||
--
|
||||
-- reserv1_out => open,
|
||||
-- dds_phase_inc_dwell_time_out => open,
|
||||
-- dds_phase_inc_step_size_out => open,
|
||||
-- idle_samples_out => open,
|
||||
-- dds_samples_out => open,
|
||||
-- phase_inc_out => open,
|
||||
-- phase_off_out => open,
|
||||
-- swap_sf_out => open,
|
||||
--
|
||||
-- m_axis_aclk_in => m_axis_aclk,
|
||||
-- dds_pulse_data_out => dds_pulse_data_0,
|
||||
-- dds_pulse_dval_out => dds_pulse_dval_0,
|
||||
--
|
||||
-- cmd_send_cnt_out => open,
|
||||
-- pipe_in_ch1_fifo_rden_cnt_out => open,
|
||||
-- dds_pulse_data_cnt_out => open,
|
||||
-- dds_done_out => open,
|
||||
--
|
||||
-- trigger_mode_in => "00", -- 00 = internal, 01 = external, 10 = internal
|
||||
-- ext_trigger_in => '0',
|
||||
-- prog_us_tick_in => x"0000_0100",
|
||||
-- duration_ms_cnt_in => x"0000_0064",
|
||||
--
|
||||
-- reset_in => reset
|
||||
-- );
|
||||
|
||||
i_fifo_0 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_0,
|
||||
s_axis_tvalid => dds_pulse_dval_0,
|
||||
s_axis_tready => s_axis_tready_0,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_0,
|
||||
m_axis_tvalid => m_axis_tvalid_0,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
|
||||
i_fifo_1 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_1,
|
||||
s_axis_tvalid => dds_pulse_dval_1,
|
||||
s_axis_tready => s_axis_tready_1,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_1,
|
||||
m_axis_tvalid => m_axis_tvalid_1,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
i_fifo_2 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_2,
|
||||
s_axis_tvalid => dds_pulse_dval_2,
|
||||
s_axis_tready => s_axis_tready_2,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_2,
|
||||
m_axis_tvalid => m_axis_tvalid_2,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
|
||||
i_fifo_3 : entity work.axis_data_fifo_32x32
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_3,
|
||||
s_axis_tvalid => dds_pulse_dval_3,
|
||||
s_axis_tready => s_axis_tready_3,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_3,
|
||||
m_axis_tvalid => m_axis_tvalid_3,
|
||||
m_axis_tready => dds_pulse_data_word_tready_valid
|
||||
);
|
||||
|
||||
dds_pulse_data_word <= m_axis_tdata_3 & m_axis_tdata_2 & m_axis_tdata_1 & m_axis_tdata_0;
|
||||
dds_pulse_data_word_dval <= m_axis_tvalid_3 and m_axis_tvalid_2 and m_axis_tvalid_1 and m_axis_tvalid_0;
|
||||
|
||||
dds_pulse_data_word_tready_valid <= '1' when dds_pulse_data_word_dval = '1' and dds_pulse_data_word_tready = '1' else '0';
|
||||
|
||||
-- this FIFO is actually 32K by 128
|
||||
i_fifo_out : entity work.axis_data_fifo_512x128
|
||||
port map (
|
||||
s_axis_aclk => m_axis_aclk,
|
||||
s_axis_aresetn => reset_n(0),
|
||||
|
||||
s_axis_tdata => dds_pulse_data_word,
|
||||
s_axis_tvalid => dds_pulse_data_word_dval,
|
||||
s_axis_tready => dds_pulse_data_word_tready,
|
||||
|
||||
m_axis_tdata => m_axis_tdata_i,
|
||||
m_axis_tvalid => m_axis_tvalid_i,
|
||||
m_axis_tready => m_axis_tready_i
|
||||
);
|
||||
|
||||
|
||||
|
||||
i_util_upack2 : entity work.util_upack2
|
||||
generic map (
|
||||
NUM_OF_CHANNELS => 8,
|
||||
SAMPLES_PER_CHANNEL => 1,
|
||||
SAMPLE_DATA_WIDTH => 16
|
||||
)
|
||||
port map (
|
||||
clk => m_axis_aclk, --input
|
||||
reset => reset, -- input
|
||||
enable_0 => fifo_en, -- input
|
||||
enable_1 => fifo_en, -- input
|
||||
enable_2 => fifo_en, -- input
|
||||
enable_3 => fifo_en, -- input
|
||||
enable_4 => fifo_en, -- input
|
||||
enable_5 => fifo_en, -- input
|
||||
enable_6 => fifo_en, -- input
|
||||
enable_7 => fifo_en, -- input
|
||||
enable_8 => '0', -- input
|
||||
enable_9 => '0', -- input
|
||||
enable_10 => '0', -- input
|
||||
enable_11 => '0', -- input
|
||||
enable_12 => '0', -- input
|
||||
enable_13 => '0', -- input
|
||||
enable_14 => '0', -- input
|
||||
enable_15 => '0', -- input
|
||||
enable_16 => '0', -- input
|
||||
enable_17 => '0', -- input
|
||||
enable_18 => '0', -- input
|
||||
enable_19 => '0', -- input
|
||||
enable_20 => '0', -- input
|
||||
enable_21 => '0', -- input
|
||||
enable_22 => '0', -- input
|
||||
enable_23 => '0', -- input
|
||||
enable_24 => '0', -- input
|
||||
enable_25 => '0', -- input
|
||||
enable_26 => '0', -- input
|
||||
enable_27 => '0', -- input
|
||||
enable_28 => '0', -- input
|
||||
enable_29 => '0', -- input
|
||||
enable_30 => '0', -- input
|
||||
enable_31 => '0', -- input
|
||||
enable_32 => '0', -- input
|
||||
enable_33 => '0', -- input
|
||||
enable_34 => '0', -- input
|
||||
enable_35 => '0', -- input
|
||||
enable_36 => '0', -- input
|
||||
enable_37 => '0', -- input
|
||||
enable_38 => '0', -- input
|
||||
enable_39 => '0', -- input
|
||||
enable_40 => '0', -- input
|
||||
enable_41 => '0', -- input
|
||||
enable_42 => '0', -- input
|
||||
enable_43 => '0', -- input
|
||||
enable_44 => '0', -- input
|
||||
enable_45 => '0', -- input
|
||||
enable_46 => '0', -- input
|
||||
enable_47 => '0', -- input
|
||||
enable_48 => '0', -- input
|
||||
enable_49 => '0', -- input
|
||||
enable_50 => '0', -- input
|
||||
enable_51 => '0', -- input
|
||||
enable_52 => '0', -- input
|
||||
enable_53 => '0', -- input
|
||||
enable_54 => '0', -- input
|
||||
enable_55 => '0', -- input
|
||||
enable_56 => '0', -- input
|
||||
enable_57 => '0', -- input
|
||||
enable_58 => '0', -- input
|
||||
enable_59 => '0', -- input
|
||||
enable_60 => '0', -- input
|
||||
enable_61 => '0', -- input
|
||||
enable_62 => '0', -- input
|
||||
enable_63 => '0', -- input
|
||||
|
||||
fifo_rd_en => fifo_rd_en,-- input
|
||||
fifo_rd_valid => fifo_rd_valid , -- output
|
||||
fifo_rd_underflow => fifo_rd_underflow, -- output
|
||||
|
||||
fifo_rd_data_0 => fifo_rd_data_0, --
|
||||
fifo_rd_data_1 => fifo_rd_data_1, --
|
||||
fifo_rd_data_2 => fifo_rd_data_2, --
|
||||
fifo_rd_data_3 => fifo_rd_data_3, --
|
||||
fifo_rd_data_4 => fifo_rd_data_4, --
|
||||
fifo_rd_data_5 => fifo_rd_data_5, --
|
||||
fifo_rd_data_6 => fifo_rd_data_6, --
|
||||
fifo_rd_data_7 => fifo_rd_data_7, --
|
||||
fifo_rd_data_8 => fifo_rd_data_8 , --
|
||||
fifo_rd_data_9 => fifo_rd_data_9 , --
|
||||
fifo_rd_data_10 => fifo_rd_data_10, --
|
||||
fifo_rd_data_11 => fifo_rd_data_11, --
|
||||
fifo_rd_data_12 => fifo_rd_data_12, --
|
||||
fifo_rd_data_13 => fifo_rd_data_13, --
|
||||
fifo_rd_data_14 => fifo_rd_data_14, --
|
||||
fifo_rd_data_15 => fifo_rd_data_15, --
|
||||
fifo_rd_data_16 => fifo_rd_data_16, --
|
||||
fifo_rd_data_17 => fifo_rd_data_17, --
|
||||
fifo_rd_data_18 => fifo_rd_data_18, --
|
||||
fifo_rd_data_19 => fifo_rd_data_19, --
|
||||
fifo_rd_data_20 => fifo_rd_data_20, --
|
||||
fifo_rd_data_21 => fifo_rd_data_21, --
|
||||
fifo_rd_data_22 => fifo_rd_data_22, --
|
||||
fifo_rd_data_23 => fifo_rd_data_23, --
|
||||
fifo_rd_data_24 => fifo_rd_data_24, --
|
||||
fifo_rd_data_25 => fifo_rd_data_25, --
|
||||
fifo_rd_data_26 => fifo_rd_data_26, --
|
||||
fifo_rd_data_27 => fifo_rd_data_27, --
|
||||
fifo_rd_data_28 => fifo_rd_data_28, --
|
||||
fifo_rd_data_29 => fifo_rd_data_29, --
|
||||
fifo_rd_data_30 => fifo_rd_data_30, --
|
||||
fifo_rd_data_31 => fifo_rd_data_31, --
|
||||
fifo_rd_data_32 => fifo_rd_data_32, --
|
||||
fifo_rd_data_33 => fifo_rd_data_33, --
|
||||
fifo_rd_data_34 => fifo_rd_data_34, --
|
||||
fifo_rd_data_35 => fifo_rd_data_35, --
|
||||
fifo_rd_data_36 => fifo_rd_data_36, --
|
||||
fifo_rd_data_37 => fifo_rd_data_37, --
|
||||
fifo_rd_data_38 => fifo_rd_data_38, --
|
||||
fifo_rd_data_39 => fifo_rd_data_39, --
|
||||
fifo_rd_data_40 => fifo_rd_data_40, --
|
||||
fifo_rd_data_41 => fifo_rd_data_41, --
|
||||
fifo_rd_data_42 => fifo_rd_data_42, --
|
||||
fifo_rd_data_43 => fifo_rd_data_43, --
|
||||
fifo_rd_data_44 => fifo_rd_data_44, --
|
||||
fifo_rd_data_45 => fifo_rd_data_45, --
|
||||
fifo_rd_data_46 => fifo_rd_data_46, --
|
||||
fifo_rd_data_47 => fifo_rd_data_47, --
|
||||
fifo_rd_data_48 => fifo_rd_data_48, --
|
||||
fifo_rd_data_49 => fifo_rd_data_49, --
|
||||
fifo_rd_data_50 => fifo_rd_data_50, --
|
||||
fifo_rd_data_51 => fifo_rd_data_51, --
|
||||
fifo_rd_data_52 => fifo_rd_data_52, --
|
||||
fifo_rd_data_53 => fifo_rd_data_53, --
|
||||
fifo_rd_data_54 => fifo_rd_data_54, --
|
||||
fifo_rd_data_55 => fifo_rd_data_55, --
|
||||
fifo_rd_data_56 => fifo_rd_data_56, --
|
||||
fifo_rd_data_57 => fifo_rd_data_57, --
|
||||
fifo_rd_data_58 => fifo_rd_data_58, --
|
||||
fifo_rd_data_59 => fifo_rd_data_59, --
|
||||
fifo_rd_data_60 => fifo_rd_data_60, --
|
||||
fifo_rd_data_61 => fifo_rd_data_61, --
|
||||
fifo_rd_data_62 => fifo_rd_data_62, --
|
||||
fifo_rd_data_63 => fifo_rd_data_63, --
|
||||
|
||||
s_axis_valid => m_axis_tvalid_i,-- input ,
|
||||
s_axis_ready => m_axis_tready_i,-- output ,
|
||||
s_axis_data => m_axis_tdata_i -- output
|
||||
);
|
||||
|
||||
|
||||
|
||||
process
|
||||
begin
|
||||
wait for 200 ns;
|
||||
|
||||
-- cmd_send_0 <= '1';
|
||||
-- wait for 500 ns;
|
||||
-- dac_holdoff_0 <= '0';
|
||||
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"1111_2222";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"3333_4444";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"5555_6666";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= x"7777_8888";
|
||||
dds_pulse_dval_0 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_0 <= (others => '0');
|
||||
dds_pulse_dval_0 <= '0';
|
||||
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"9999_aaaa";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"bbbb_cccc";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"dddd_eeee";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= x"ffff_1234";
|
||||
dds_pulse_dval_1 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_1 <= (others => '0');
|
||||
dds_pulse_dval_1 <= '0';
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"1122_3344";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"5566_7788";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"99aa_bbcc";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= x"ddee_ff00";
|
||||
dds_pulse_dval_2 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_2 <= (others => '0');
|
||||
dds_pulse_dval_2 <= '0';
|
||||
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"0123_4567";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"89ab_cdef";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"fedc_ba98";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= x"7654_3210";
|
||||
dds_pulse_dval_3 <= '1';
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
dds_pulse_data_3 <= (others => '0');
|
||||
dds_pulse_dval_3 <= '0';
|
||||
|
||||
wait for 500 ns;
|
||||
wait until rising_edge(m_axis_aclk);
|
||||
-- m_axis_tready_i <= '1';
|
||||
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
end architecture behavior;
|
||||
@@ -0,0 +1,317 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:53:22 03/24/2017
|
||||
-- Design Name:
|
||||
-- Module Name:
|
||||
-- Project Name: xem7350
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: dac_interface
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
entity test_bench is
|
||||
end test_bench;
|
||||
|
||||
architecture behavior of test_bench is
|
||||
|
||||
constant C_M_AXI_DATA_WIDTH : integer := 32;
|
||||
constant C_M_AXI_ADDR_WIDTH : integer := 32;
|
||||
|
||||
-- Clock period definitions
|
||||
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
|
||||
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
|
||||
|
||||
signal s_axi_aclk : std_logic := '0';
|
||||
signal m_axi_aclk : std_logic := '0';
|
||||
|
||||
signal s_axi_aresetn : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal reset : std_logic_vector(0 to 2) := (others => '1');
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0) := (others => '0');
|
||||
signal cmd_send : std_logic := '0';
|
||||
|
||||
signal mode : std_logic := '0';
|
||||
signal scale : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal dac_holdoff : std_logic := '0';
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal idle_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_samples : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal phase_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal phase_off : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal swap_sf : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal mb_m_axi_awaddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_awprot : std_logic_vector (2 downto 0);
|
||||
signal mb_m_axi_awvalid : std_logic;
|
||||
signal mb_m_axi_awready : std_logic;
|
||||
|
||||
-- master interface write data
|
||||
signal mb_m_axi_wdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_wstrb : std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0);
|
||||
signal mb_m_axi_wvalid : std_logic;
|
||||
signal mb_m_axi_wready : std_logic;
|
||||
|
||||
-- master interface write response
|
||||
signal mb_m_axi_bresp : std_logic_vector (1 downto 0);
|
||||
signal mb_m_axi_bvalid : std_logic;
|
||||
signal mb_m_axi_bready : std_logic;
|
||||
|
||||
-- master interface read address
|
||||
signal mb_m_axi_araddr : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_arprot : std_logic_vector (2 downto 0);
|
||||
signal mb_m_axi_arvalid : std_logic;
|
||||
signal mb_m_axi_arready : std_logic;
|
||||
|
||||
signal mb_m_axi_rdata : std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal mb_m_axi_rresp : std_logic_vector (1 downto 0);
|
||||
signal mb_m_axi_rvalid : std_logic;
|
||||
signal mb_m_axi_rready : std_logic;
|
||||
|
||||
signal m_axis_tdata : std_logic_vector(127 downto 0);
|
||||
signal m_axis_tvalid : std_logic;
|
||||
signal m_axis_tready : std_logic;
|
||||
|
||||
signal fifo_rd_valid : std_logic;
|
||||
signal fifo_rd_underflow : std_logic;
|
||||
signal fifo_rd_data_0 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_1 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_2 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_3 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_4 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_5 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_6 : std_logic_vector(15 downto 0);
|
||||
signal fifo_rd_data_7 : std_logic_vector(15 downto 0);
|
||||
|
||||
signal fifo_rd_enable : std_logic := '0';
|
||||
signal fifo_rd_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
s_axi_aclk <= not s_axi_aclk after S_AXI_ACLK_PERIOD/2;
|
||||
m_axi_aclk <= not m_axi_aclk after M_AXI_ACLK_PERIOD/2;
|
||||
|
||||
process(s_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk)) then
|
||||
s_axi_aresetn <= s_axi_aresetn(1 to 2) & '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axi_aclk)) then
|
||||
reset <= reset(1 to 2) & '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_pulse_wrapper : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
SIM_ENABLED => TRUE,
|
||||
FPGA_REVISION_DATE => x"0911_2023",
|
||||
MINOR_REV => x"01"
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk,
|
||||
s_axi_aresetn_in => s_axi_aresetn(0),
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
mode_in => mode,
|
||||
scale_in => scale,
|
||||
dac_holdoff_in => dac_holdoff,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
m_axis_aclk_in => m_axi_aclk,
|
||||
|
||||
m_axis_tdata_out => m_axis_tdata,
|
||||
m_axis_tvalid_out => m_axis_tvalid,
|
||||
m_axis_tready_in => m_axis_tready,
|
||||
|
||||
cmd_send_cnt_out => open,
|
||||
pipe_in_ch1_fifo_rden_cnt_out => open,
|
||||
m_axis_tvalid_cnt_out => open,
|
||||
dds_pulse_data_cnt_out => open,
|
||||
|
||||
reset_in => reset(0)
|
||||
);
|
||||
|
||||
i_util_upack2_0 : entity work.util_upack2_0
|
||||
port map (
|
||||
clk => m_axi_aclk,
|
||||
reset => reset(0),
|
||||
enable_0 => fifo_rd_enable,
|
||||
enable_1 => fifo_rd_enable,
|
||||
enable_2 => fifo_rd_enable,
|
||||
enable_3 => fifo_rd_enable,
|
||||
enable_4 => fifo_rd_enable,
|
||||
enable_5 => fifo_rd_enable,
|
||||
enable_6 => fifo_rd_enable,
|
||||
enable_7 => fifo_rd_enable,
|
||||
fifo_rd_en => fifo_rd_r,
|
||||
fifo_rd_valid => fifo_rd_valid,
|
||||
fifo_rd_underflow => fifo_rd_underflow,
|
||||
fifo_rd_data_0 => fifo_rd_data_0,
|
||||
fifo_rd_data_1 => fifo_rd_data_1,
|
||||
fifo_rd_data_2 => fifo_rd_data_2,
|
||||
fifo_rd_data_3 => fifo_rd_data_3,
|
||||
fifo_rd_data_4 => fifo_rd_data_4,
|
||||
fifo_rd_data_5 => fifo_rd_data_5,
|
||||
fifo_rd_data_6 => fifo_rd_data_6,
|
||||
fifo_rd_data_7 => fifo_rd_data_7,
|
||||
s_axis_data => m_axis_tdata,
|
||||
s_axis_valid => m_axis_tvalid,
|
||||
s_axis_ready => m_axis_tready
|
||||
);
|
||||
|
||||
process(m_axi_aclk)
|
||||
begin
|
||||
if (rising_edge(m_axi_aclk)) then
|
||||
if (fifo_rd_enable = '1') then
|
||||
fifo_rd_r <= not fifo_rd_r;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait for 1.5 us;
|
||||
|
||||
fifo_rd_enable <= '1';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- i_dds_pulse_intfc_v1_0 : entity work.dds_pulse_intfc_v1_0
|
||||
-- generic map (
|
||||
-- FPGA_REVISION_DATE => x"0911_2023",
|
||||
-- MINOR_REV => x"00",
|
||||
--
|
||||
-- -- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
-- C_S00_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
|
||||
-- C_S00_AXI_ADDR_WIDTH => 6
|
||||
-- )
|
||||
-- port map (
|
||||
-- -- Users to add ports here
|
||||
-- m_axis_aclk => m_axi_aclk,
|
||||
-- reset => reset(0),
|
||||
-- m_axis_tdata => open,
|
||||
-- m_axis_tvalid => open,
|
||||
-- m_axis_tready => '1',
|
||||
-- -- User ports ends
|
||||
-- -- Do not modify the ports beyond this line
|
||||
--
|
||||
--
|
||||
-- -- Ports of Axi Slave Bus Interface S00_AXI
|
||||
-- s00_axi_aclk => s_axi_aclk,
|
||||
-- s00_axi_aresetn => s_axi_aresetn(0),
|
||||
--
|
||||
-- s00_axi_awaddr => mb_m_axi_awaddr(5 DOWNTO 0),-- : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- s00_axi_awprot => mb_m_axi_awprot, --: in std_logic_vector(2 downto 0);
|
||||
-- s00_axi_awvalid => mb_m_axi_awvalid, --: in std_logic;
|
||||
-- s00_axi_awready => mb_m_axi_awready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_wdata => mb_m_axi_wdata, --: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- s00_axi_wstrb => mb_m_axi_wstrb, --: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- s00_axi_wvalid => mb_m_axi_wvalid, --: in std_logic;
|
||||
-- s00_axi_wready => mb_m_axi_wready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_bresp => mb_m_axi_bresp, --: out std_logic_vector(1 downto 0);
|
||||
-- s00_axi_bvalid => mb_m_axi_bvalid, --: out std_logic;
|
||||
-- s00_axi_bready => mb_m_axi_bready, --: in std_logic;
|
||||
--
|
||||
-- s00_axi_araddr => mb_m_axi_araddr(5 DOWNTO 0), --: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- s00_axi_arprot => mb_m_axi_arprot, --: in std_logic_vector(2 downto 0);
|
||||
-- s00_axi_arvalid => mb_m_axi_arvalid, --: in std_logic;
|
||||
-- s00_axi_arready => mb_m_axi_arready, --: out std_logic;
|
||||
--
|
||||
-- s00_axi_rdata => mb_m_axi_rdata, --: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- s00_axi_rresp => mb_m_axi_rresp, --: out std_logic_vector(1 downto 0);
|
||||
-- s00_axi_rvalid => mb_m_axi_rvalid, --: out std_logic;
|
||||
-- s00_axi_rready => mb_m_axi_rready -- : in std_logic
|
||||
-- );
|
||||
|
||||
i_axi_lite_traffic_gen_mb : entity work.axi_lite_traffic_gen
|
||||
generic map (
|
||||
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
|
||||
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH
|
||||
)
|
||||
port map (
|
||||
m_axi_aclk => s_axi_aclk,
|
||||
m_axi_aresetn => s_axi_aresetn(0),
|
||||
|
||||
-- Master Interface Write Address
|
||||
m_axi_awaddr => mb_m_axi_awaddr, -- : out
|
||||
m_axi_awprot => mb_m_axi_awprot, -- : out
|
||||
m_axi_awvalid => mb_m_axi_awvalid, -- : out
|
||||
m_axi_awready => mb_m_axi_awready, -- : in
|
||||
--
|
||||
-- master interface write data --
|
||||
m_axi_wdata => mb_m_axi_wdata, -- : out
|
||||
m_axi_wstrb => mb_m_axi_wstrb, -- : out
|
||||
m_axi_wvalid => mb_m_axi_wvalid, -- : out
|
||||
m_axi_wready => mb_m_axi_wready, -- : in
|
||||
--
|
||||
-- master interface write response --
|
||||
m_axi_bresp => mb_m_axi_bresp, -- : in
|
||||
m_axi_bvalid => mb_m_axi_bvalid, -- : in
|
||||
m_axi_bready => mb_m_axi_bready, -- : out
|
||||
--
|
||||
-- master interface read address --
|
||||
m_axi_araddr => mb_m_axi_araddr, -- : out
|
||||
m_axi_arprot => mb_m_axi_arprot, -- : out
|
||||
m_axi_arvalid => mb_m_axi_arvalid, -- : out
|
||||
m_axi_arready => mb_m_axi_arready, -- : in
|
||||
--
|
||||
-- master interface read data --
|
||||
m_axi_rdata => mb_m_axi_rdata, -- : in
|
||||
m_axi_rresp => mb_m_axi_rresp, -- : in
|
||||
m_axi_rvalid => mb_m_axi_rvalid, -- : in
|
||||
m_axi_rready => mb_m_axi_rready, -- : out
|
||||
|
||||
num_burst_cnt_out => open,
|
||||
xfer_en_out => open,
|
||||
xfer_done_in => '0',
|
||||
dma_xfer_done_in => '0',
|
||||
|
||||
buffer_rdy_intr_in => '0'
|
||||
|
||||
);
|
||||
|
||||
end;
|
||||
Reference in New Issue
Block a user