moving repo from git to local repo
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#####################################
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#
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# VCU128 Rev1.0 XDC
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# Date: 01/24/2018
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#
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####################################
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###################################
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### J79
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set_property PACKAGE_PIN L33 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 CLK0_N
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set_property PACKAGE_PIN L32 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 CLK0_P
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set_property PACKAGE_PIN G42 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131
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set_property PACKAGE_PIN G41 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131
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set_property PACKAGE_PIN F40 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131
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set_property PACKAGE_PIN F39 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131
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set_property PACKAGE_PIN E42 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131
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set_property PACKAGE_PIN E41 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131
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set_property PACKAGE_PIN D40 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131
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set_property PACKAGE_PIN D39 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131
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set_property PACKAGE_PIN H35 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131
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set_property PACKAGE_PIN H34 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131
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set_property PACKAGE_PIN G37 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131
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set_property PACKAGE_PIN G36 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131
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set_property PACKAGE_PIN F35 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131
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set_property PACKAGE_PIN F34 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131
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set_property PACKAGE_PIN E37 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131
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set_property PACKAGE_PIN E36 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_MODPRSL_LS"] ;#
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### J78
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set_property PACKAGE_PIN R33 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 - MGTREFCLK0N_130 CLK1_N
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set_property PACKAGE_PIN R32 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130 CLK1_P
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# set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130
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# set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130
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# set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
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# set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
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# set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
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# set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
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# set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
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# set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
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# set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
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# set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130
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# set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
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# set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
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# set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
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# set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
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# set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
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# set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
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# set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
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# set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130
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### J77
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set_property PACKAGE_PIN W33 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129 CLK3_N
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set_property PACKAGE_PIN W32 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129 CLK3_P
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# set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129
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# set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129
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# set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
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# set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
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# set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
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# set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
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# set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
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# set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
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# set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
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# set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129
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# set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
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# set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
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# set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
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# set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
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# set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
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# set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
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# set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
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# set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129
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# set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;
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# set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;
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### J76
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set_property PACKAGE_PIN AB35 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 128 - MGTREFCLK0N_128 CLK2_N
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set_property PACKAGE_PIN AB34 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 128 - MGTREFCLK0P_128 CLK2_P
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set_property PACKAGE_PIN W42 [get_ports "QSFP1_RX1_N"] ;# Bank 128 - MGTYRXN0_128
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set_property PACKAGE_PIN W41 [get_ports "QSFP1_RX1_P"] ;# Bank 128 - MGTYRXP0_128
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set_property PACKAGE_PIN V40 [get_ports "QSFP1_RX2_N"] ;# Bank 128 - MGTYRXN1_128
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set_property PACKAGE_PIN V39 [get_ports "QSFP1_RX2_P"] ;# Bank 128 - MGTYRXP1_128
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set_property PACKAGE_PIN U42 [get_ports "QSFP1_RX3_N"] ;# Bank 128 - MGTYRXN2_128
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set_property PACKAGE_PIN U41 [get_ports "QSFP1_RX3_P"] ;# Bank 128 - MGTYRXP2_128
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set_property PACKAGE_PIN T40 [get_ports "QSFP1_RX4_N"] ;# Bank 128 - MGTYRXN3_128
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set_property PACKAGE_PIN T39 [get_ports "QSFP1_RX4_P"] ;# Bank 128 - MGTYRXP3_128
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set_property PACKAGE_PIN Y35 [get_ports "QSFP1_TX1_N"] ;# Bank 128 - MGTYTXN0_128
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set_property PACKAGE_PIN Y34 [get_ports "QSFP1_TX1_P"] ;# Bank 128 - MGTYTXP0_128
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set_property PACKAGE_PIN W37 [get_ports "QSFP1_TX2_N"] ;# Bank 128 - MGTYTXN1_128
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set_property PACKAGE_PIN W36 [get_ports "QSFP1_TX2_P"] ;# Bank 128 - MGTYTXP1_128
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set_property PACKAGE_PIN V35 [get_ports "QSFP1_TX3_N"] ;# Bank 128 - MGTYTXN2_128
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set_property PACKAGE_PIN V34 [get_ports "QSFP1_TX3_P"] ;# Bank 128 - MGTYTXP2_128
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set_property PACKAGE_PIN U37 [get_ports "QSFP1_TX4_N"] ;# Bank 128 - MGTYTXN3_128
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set_property PACKAGE_PIN U36 [get_ports "QSFP1_TX4_P"] ;# Bank 128 - MGTYTXP3_128
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set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_MODPRSL_LS"] ;#
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# set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;#
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@@ -0,0 +1,101 @@
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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#
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## mxfe
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#
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set_property -dict {PACKAGE_PIN AR24 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L14P_T2L_N2_GC_65 FMC2_LA17_CC_P D20
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set_property -dict {PACKAGE_PIN AR25 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L14N_T2L_N3_GC_65 FMC2_LA17_CC_N D21
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set_property -dict {PACKAGE_PIN AU25 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L11P_T1U_N8_GC_65 FMC2_LA18_CC_P C22
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set_property -dict {PACKAGE_PIN AU26 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L11N_T1U_N9_GC_65 FMC2_LA18_CC_N C23
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set_property -dict {PACKAGE_PIN AU28 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L10P_T1U_N6_QBC_AD4P_65 FMC2_LA20_P G21
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set_property -dict {PACKAGE_PIN AV28 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L10N_T1U_N7_QBC_AD4N_65 FMC2_LA20_N G22
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set_property -dict {PACKAGE_PIN BB24 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L2P_T0L_N2_65 FMC2_LA21_P H25
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set_property -dict {PACKAGE_PIN BB25 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L2N_T0L_N3_65 FMC2_LA21_N H26
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set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_n ] ; ## IO_L13N_T2L_N1_GC_QBC_65 FMC2_CLK1_M2C_N G3
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set_property -dict {PACKAGE_PIN AR27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_p ] ; ## IO_L13P_T2L_N0_GC_QBC_65 FMC2_CLK1_M2C_P G2
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set_property -dict {PACKAGE_PIN AK11 } [get_ports clkin8_n ] ; ## MGTREFCLK0N_224 FMC2_GBTCLK1_M2C_N B21
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set_property -dict {PACKAGE_PIN AK12 } [get_ports clkin8_p ] ; ## MGTREFCLK0P_224 FMC2_GBTCLK1_M2C_P B20
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set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_n ] ; ## IO_L11N_T1U_N9_GC_64 LA00_N_CC G7
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set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_p ] ; ## IO_L11P_T1U_N8_GC_64 LA00_P_CC G6
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set_property -dict {PACKAGE_PIN AH11 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_225 FMC2_GBTCLK0_M2C_C_N D5
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set_property -dict {PACKAGE_PIN AH12 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_225 FMC2_GBTCLK0_M2C_C_P D4
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set_property -quiet -dict {PACKAGE_PIN AP3 } [get_ports rx_data_n[2] ] ; ## MGTHRXN2_225 FPGA_SERDIN_0_N FMC2_DP2_M2C_n A7
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set_property -quiet -dict {PACKAGE_PIN AP4 } [get_ports rx_data_p[2] ] ; ## MGTHRXP2_225 FPGA_SERDIN_0_P FMC2_DP2_M2C_P A6
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set_property -quiet -dict {PACKAGE_PIN AR1 } [get_ports rx_data_n[0] ] ; ## MGTHRXN1_225 FPGA_SERDIN_1_N FMC2_DP0_M2C_n C7
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set_property -quiet -dict {PACKAGE_PIN AR2 } [get_ports rx_data_p[0] ] ; ## MGTHRXP1_225 FPGA_SERDIN_1_P FMC2_DP0_M2C_P C6
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set_property -quiet -dict {PACKAGE_PIN AU1 } [get_ports rx_data_n[7] ] ; ## MGTHRXN3_224 FPGA_SERDIN_2_N FMC2_DP7_M2C_N B13
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set_property -quiet -dict {PACKAGE_PIN AU2 } [get_ports rx_data_p[7] ] ; ## MGTHRXP3_224 FPGA_SERDIN_2_P FMC2_DP7_M2C_P B12
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set_property -quiet -dict {PACKAGE_PIN AW1 } [get_ports rx_data_n[6] ] ; ## MGTHRXN1_224 FPGA_SERDIN_3_N FMC2_DP6_M2C_N B17
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set_property -quiet -dict {PACKAGE_PIN AW2 } [get_ports rx_data_p[6] ] ; ## MGTHRXP1_224 FPGA_SERDIN_3_P FMC2_DP6_M2C_P B16
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set_property -quiet -dict {PACKAGE_PIN BA1 } [get_ports rx_data_n[5] ] ; ## MGTHRXN0_224 FPGA_SERDIN_4_N FMC2_DP5_M2C_N A19
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set_property -quiet -dict {PACKAGE_PIN BA2 } [get_ports rx_data_p[5] ] ; ## MGTHRXP0_224 FPGA_SERDIN_4_P FMC2_DP5_M2C_P A18
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set_property -quiet -dict {PACKAGE_PIN AV3 } [get_ports rx_data_n[4] ] ; ## MGTHRXN2_224 FPGA_SERDIN_5_N FMC2_DP4_M2C_N A15
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set_property -quiet -dict {PACKAGE_PIN AV4 } [get_ports rx_data_p[4] ] ; ## MGTHRXP2_224 FPGA_SERDIN_5_P FMC2_DP4_M2C_P A14
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set_property -quiet -dict {PACKAGE_PIN AT3 } [get_ports rx_data_n[3] ] ; ## MGTHRXN0_225 FPGA_SERDIN_6_N FMC2_DP3_M2C_n A11
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set_property -quiet -dict {PACKAGE_PIN AT4 } [get_ports rx_data_p[3] ] ; ## MGTHRXP0_225 FPGA_SERDIN_6_P FMC2_DP3_M2C_P A10
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set_property -quiet -dict {PACKAGE_PIN AN1 } [get_ports rx_data_n[1] ] ; ## MGTHRXN3_225 FPGA_SERDIN_7_N FMC2_DP1_M2C_n A3
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set_property -quiet -dict {PACKAGE_PIN AN2 } [get_ports rx_data_p[1] ] ; ## MGTHRXP3_225 FPGA_SERDIN_7_P FMC2_DP1_M2C_P A2
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set_property -quiet -dict {PACKAGE_PIN AP7 } [get_ports tx_data_n[0] ] ; ## MGTHTXN1_225 FPGA_SERDOUT_0_N FMC2_DP0_C2M_n C3
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set_property -quiet -dict {PACKAGE_PIN AP8 } [get_ports tx_data_p[0] ] ; ## MGTHTXP1_225 FPGA_SERDOUT_0_P FMC2_DP0_C2M_P C2
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||||
set_property -quiet -dict {PACKAGE_PIN AN5 } [get_ports tx_data_n[2] ] ; ## MGTHTXN2_225 FPGA_SERDOUT_1_N FMC2_DP2_C2M_n A27
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set_property -quiet -dict {PACKAGE_PIN AN6 } [get_ports tx_data_p[2] ] ; ## MGTHTXP2_225 FPGA_SERDOUT_1_P FMC2_DP2_C2M_P A26
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set_property -quiet -dict {PACKAGE_PIN AT7 } [get_ports tx_data_n[7] ] ; ## MGTHTXN3_224 FPGA_SERDOUT_2_N FMC2_DP7_C2M_N B33
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set_property -quiet -dict {PACKAGE_PIN AT8 } [get_ports tx_data_p[7] ] ; ## MGTHTXP3_224 FPGA_SERDOUT_2_P FMC2_DP7_C2M_P B32
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||||
set_property -quiet -dict {PACKAGE_PIN AW5 } [get_ports tx_data_n[6] ] ; ## MGTHTXN1_224 FPGA_SERDOUT_3_N FMC2_DP6_C2M_N B37
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set_property -quiet -dict {PACKAGE_PIN AW6 } [get_ports tx_data_p[6] ] ; ## MGTHTXP1_224 FPGA_SERDOUT_3_P FMC2_DP6_C2M_P B36
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set_property -quiet -dict {PACKAGE_PIN AM7 } [get_ports tx_data_n[1] ] ; ## MGTHTXN3_225 FPGA_SERDOUT_4_N FMC2_DP1_C2M_n A23
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||||
set_property -quiet -dict {PACKAGE_PIN AM8 } [get_ports tx_data_p[1] ] ; ## MGTHTXP3_225 FPGA_SERDOUT_4_P FMC2_DP1_C2M_P A22
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||||
set_property -quiet -dict {PACKAGE_PIN AY3 } [get_ports tx_data_n[5] ] ; ## MGTHTXN0_224 FPGA_SERDOUT_5_N FMC2_DP5_C2M_N A39
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||||
set_property -quiet -dict {PACKAGE_PIN AY4 } [get_ports tx_data_p[5] ] ; ## MGTHTXP0_224 FPGA_SERDOUT_5_P FMC2_DP5_C2M_P A38
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set_property -quiet -dict {PACKAGE_PIN AU5 } [get_ports tx_data_n[4] ] ; ## MGTHTXN2_224 FPGA_SERDOUT_6_N FMC2_DP4_C2M_N A35
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||||
set_property -quiet -dict {PACKAGE_PIN AU6 } [get_ports tx_data_p[4] ] ; ## MGTHTXP2_224 FPGA_SERDOUT_6_P FMC2_DP4_C2M_P A34
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||||
set_property -quiet -dict {PACKAGE_PIN AR5 } [get_ports tx_data_n[3] ] ; ## MGTHTXN0_225 FPGA_SERDOUT_7_N FMC2_DP3_C2M_n A31
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||||
set_property -quiet -dict {PACKAGE_PIN AR6 } [get_ports tx_data_p[3] ] ; ## MGTHTXP0_225 FPGA_SERDOUT_7_P FMC2_DP3_C2M_P A30
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||||
set_property -quiet -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## IO_L7N_T1L_N1_QBC_AD13N_64 FMC2_LA02_n H8
|
||||
set_property -quiet -dict {PACKAGE_PIN AU23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## IO_L7P_T1L_N0_QBC_AD13P_64 FMC2_LA02_P H7
|
||||
set_property -quiet -dict {PACKAGE_PIN AW19 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## IO_L9N_T1L_N5_AD12N_64 FMC2_LA03_n G10
|
||||
set_property -quiet -dict {PACKAGE_PIN AW20 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## IO_L9P_T1L_N4_AD12P_64 FMC2_LA03_P G9
|
||||
set_property -quiet -dict {PACKAGE_PIN AV19 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## IO_L12N_T1U_N11_GC_64 FMC2_LA01_CC_n D9
|
||||
set_property -quiet -dict {PACKAGE_PIN AU20 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## IO_L12P_T1U_N10_GC_64 FMC2_LA01_CC_P D8
|
||||
set_property -quiet -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## IO_L2N_T0L_N3_64 FMC2_LA06_n C11
|
||||
set_property -quiet -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## IO_L2P_T0L_N2_64 FMC2_LA06_P C10
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L20P_T3L_N2_AD1P_64 FMC2_LA15_P H19
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L20N_T3L_N3_AD1N_64 FMC2_LA15_N H20
|
||||
set_property -dict {PACKAGE_PIN AV27 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L9P_T1L_N4_AD12P_65 FMC2_LA19_P H22
|
||||
set_property -dict {PACKAGE_PIN AW27 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L9N_T1L_N5_AD12N_65 FMC2_LA19_N H23
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L23P_T3U_N8_64 FMC2_LA13_P D17
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L23N_T3U_N9_64 FMC2_LA13_N D18
|
||||
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_64 FMC2_LA14_P C18
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_64 FMC2_LA14_N C19
|
||||
set_property -dict {PACKAGE_PIN AL22 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L21P_T3L_N4_AD8P_64 FMC2_LA16_P G18
|
||||
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L21N_T3L_N5_AD8N_64 FMC2_LA16_N G19
|
||||
set_property -dict {PACKAGE_PIN BB26 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_65 FMC2_LA22_N G25
|
||||
set_property -dict {PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L22N_T3U_N7_DBC_AD0N_64 FMC2_LA11_N H17
|
||||
set_property -dict {PACKAGE_PIN BA21 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L3N_T0L_N5_AD15N_64 FMC2_LA07_N H14
|
||||
set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L5P_T0U_N8_AD14P_64 FMC2_LA08_P G12
|
||||
set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L5N_T0U_N9_AD14N_64 FMC2_LA08_N G13
|
||||
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L3P_T0L_N4_AD15P_64 FMC2_LA07_P H13
|
||||
set_property -dict {PACKAGE_PIN BA18 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L6P_T0U_N10_AD6P_64 FMC2_LA10_P C14
|
||||
set_property -dict {PACKAGE_PIN BB18 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L6N_T0U_N11_AD6N_64 FMC2_LA10_N C15
|
||||
set_property -dict {PACKAGE_PIN AY19 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L10P_T1U_N6_QBC_AD4P_64 FMC2_LA05_P D11
|
||||
set_property -dict {PACKAGE_PIN AY18 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L10N_T1U_N7_QBC_AD4N_64 FMC2_LA05_N D12
|
||||
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L16P_T2U_N6_QBC_AD3P_64 FMC2_LA04_P H10
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L16N_T2U_N7_QBC_AD3N_64 FMC2_LA04_N H11
|
||||
set_property -dict {PACKAGE_PIN BA23 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L1P_T0L_N0_DBC_64 FMC2_LA12_P G15
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L22P_T3U_N6_DBC_AD0P_64 FMC2_LA11_P H16
|
||||
set_property -dict {PACKAGE_PIN BB23 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L1N_T0L_N1_DBC_64 FMC2_LA12_N G16
|
||||
set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_64 FMC2_CLK0_M2C_n H5
|
||||
set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_64 FMC2_CLK0_M2C_P H4
|
||||
set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_64 FMC2_LA09_P D14
|
||||
set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_64 FMC2_LA09_N D15
|
||||
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports pll_scl ] ; ## IO_L12N_AD8N_91
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports pll_sda ] ; ## IO_L12N_AD8P_91
|
||||
|
||||
@@ -0,0 +1,181 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 4.0 [get_ports fpga_refclk_in_p]
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 4.0 [get_ports clkin6_p]
|
||||
create_clock -name rx_device_clk -period 4.0 [get_ports clkin10_p]
|
||||
create_clock -name clkin8 -period 2.0 [get_ports clkin8_p]
|
||||
##create_clock -name sysref2 -period 4.0 [get_ports sysref2_p] # not a clock
|
||||
|
||||
create_clock -period 2.640 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
|
||||
create_clock -period 2.640 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
|
||||
create_clock -period 2.640 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
|
||||
create_clock -period 2.640 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
|
||||
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
|
||||
# Define SPI clock
|
||||
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
|
||||
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks refclk]
|
||||
set_false_path -from [get_clocks refclk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks clkin8]
|
||||
set_false_path -from [get_clocks clkin8] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_1]
|
||||
set_false_path -from [get_clocks clk_pl_1] -to [get_clocks clk_pl_0]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks clk_pl_0]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks i_qsfp_intfc_v1_0/i_bufgce_div/O] -to [get_clocks -of_objects [get_pins QSFP2_SI570_CLOCK_P]]
|
||||
set_false_path -from [get_clocks i_qsfp_intfc_v1_0/i_bufgce_div/O] -to [get_clocks -of_objects [get_pins QSFP3_SI570_CLOCK_P]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks clkin8] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks clkin8]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+4092
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
package global_types is
|
||||
type data_vc1_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type data_vc2_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type mask_vcx_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type addr_si5341_type is array (511 downto 0) of std_logic_vector(15 downto 0);
|
||||
type data_si5341_type is array (511 downto 0) of std_logic_vector(7 downto 0);
|
||||
end global_types;
|
||||
package body global_types is
|
||||
end global_types;
|
||||
@@ -0,0 +1,305 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c is
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coafficien (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end entity i2c;
|
||||
|
||||
architecture translated of i2c is
|
||||
|
||||
component IOBUF
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
IO : inout std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component OBUFT
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component i2c_st
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end component;
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
function length_ct (int_length : integer) return positive is
|
||||
variable conv_length : std_logic_vector(9 downto 0);
|
||||
variable index : positive:= 1;
|
||||
begin
|
||||
conv_length := CONV_STD_LOGIC_VECTOR(int_length, 10);
|
||||
for i in 9 downto 1 loop
|
||||
index:= i;
|
||||
exit when conv_length(i) = '1';
|
||||
end loop;
|
||||
return index;
|
||||
end length_ct;
|
||||
|
||||
|
||||
|
||||
|
||||
signal cntr : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal cntr_length : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal scl_tick : std_logic;
|
||||
signal wrd_addr : std_logic_vector(7 downto 0);
|
||||
signal wrd_dat : std_logic_vector(7 downto 0);
|
||||
signal dev_addr_int : std_logic_vector(6 downto 0);
|
||||
signal ENAPH : std_logic;
|
||||
signal scl_cnt_en : std_logic;
|
||||
signal i2c_go : std_logic;
|
||||
signal sda_in : std_logic;
|
||||
signal sda_o : std_logic;
|
||||
signal scl_o : std_logic;
|
||||
signal wr_l_int : std_logic;
|
||||
signal port_switch : std_logic:= '0';
|
||||
signal sda_o_spd : std_logic;
|
||||
signal scl_o_spd : std_logic;
|
||||
signal GND : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
GND <= '0';
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- CLOCK DIVIDER SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
cntr_length <= CONV_STD_LOGIC_VECTOR(count_div, (length_ct(count_div)+1));
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr <= (others => '0') after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (scl_cnt_en = '1') then
|
||||
cntr <= cntr + 1 after 1 * sim_timescale;
|
||||
else
|
||||
cntr <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (cntr = cntr_length) then
|
||||
scl_tick <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- ADDRESS REGISTERS SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then wrd_addr <= ADDR_IN after 1 * sim_timescale;
|
||||
dev_addr_int <= DEV_ADDR after 1 * sim_timescale;
|
||||
wr_l_int <= WR_OP after 1 * sim_timescale;
|
||||
wrd_dat <= DAT_IN after 1 * sim_timescale;
|
||||
ENAPH <= AP_EN after 1 * sim_timescale;
|
||||
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then port_switch <= (DEV_ADDR(3) and not DEV_ADDR(2) and DEV_ADDR(1) and not DEV_ADDR(0)) after 1 * sim_timescale; -- "1010" (SPD)
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
-- send ack right back
|
||||
|
||||
if (RST = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then
|
||||
i2c_go <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (scl_cnt_en = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then ACK_L <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- I2C STATE MACHINE SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
MAIN_FSM : i2c_st
|
||||
port map(
|
||||
WRD_ADD => wrd_addr,
|
||||
WRD_DAT => wrd_dat,
|
||||
DEV_ADDR => dev_addr_int,
|
||||
CONTINUE => CONTINUE,
|
||||
ENAPH => ENAPH,
|
||||
WR_L => wr_l_int,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
SCL_TICK => scl_tick,
|
||||
I2C_GO => i2c_go,
|
||||
SDA_PIN => sda_in,
|
||||
|
||||
I2C_RDATA => I2C_RDATA,
|
||||
SDA => sda_o,
|
||||
SCL => scl_o,
|
||||
SCL_CNT_EN => scl_cnt_en,
|
||||
I2C_RDY => I2C_RDY,
|
||||
I2C_ACT => I2C_ACT,
|
||||
ACK_ERR => ACK_ERR
|
||||
);
|
||||
|
||||
|
||||
sda_o_spd <= sda_o;
|
||||
scl_o_spd <= scl_o;
|
||||
|
||||
--SDA_BUF: IOBUF
|
||||
-- port map
|
||||
-- (
|
||||
-- O => sda_in,
|
||||
-- IO => SDA,
|
||||
-- I => GND,
|
||||
-- T => sda_o_spd
|
||||
-- );
|
||||
|
||||
|
||||
sda_in <= I_SDA_I;
|
||||
O_SDA_O <= GND;
|
||||
O_SDA_T <= sda_o_spd;
|
||||
|
||||
--SCL_BUF: OBUFT
|
||||
-- port map
|
||||
-- (
|
||||
-- O => SCL,
|
||||
-- I => GND,
|
||||
-- T => scl_o_spd
|
||||
-- );
|
||||
|
||||
-- scl_in <= I_SCL_I
|
||||
O_SCL_O <= GND;
|
||||
O_SCL_T <= scl_o_spd;
|
||||
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,435 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller Top level
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c_st.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c_st is
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end entity i2c_st;
|
||||
|
||||
architecture translated of i2c_st is
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
---------------------------------------------------------------------
|
||||
type st_type is (idle, en_clk, start1, dev_id1, ack_id1, w_add, w_dat, ack_wr, ack_add, wait1,
|
||||
dis_clk1, start2, dev_id2, ack_id2, data, ack_rd, stop1, ack_rd_mult);
|
||||
|
||||
signal i2c_state : st_type:= idle;
|
||||
signal bit_cntr : std_logic_vector(2 downto 0);
|
||||
signal scl_en : std_logic;
|
||||
signal en_cntr : std_logic;
|
||||
signal cntr_done : std_logic;
|
||||
signal sda_int : std_logic;
|
||||
signal scl_int : std_logic;
|
||||
signal scl_cnt_en_int : std_logic;
|
||||
signal i2c_rdy_int : std_logic;
|
||||
signal i2c_act_int : std_logic;
|
||||
signal i2c_rdata_int : std_logic_vector(7 downto 0);
|
||||
signal ack_err_int : std_logic;
|
||||
signal id_sel : std_logic_vector(7 downto 0);
|
||||
signal id_code_op : std_logic_vector(7 downto 0);
|
||||
|
||||
attribute syn_useioff : boolean;
|
||||
attribute syn_useioff of translated : architecture is true;
|
||||
---------------------------------------------------------------------
|
||||
|
||||
|
||||
begin
|
||||
|
||||
id_sel <= DEV_ADDR & '0';
|
||||
id_code_op <= DEV_ADDR & '1';
|
||||
|
||||
|
||||
|
||||
SRL16E_inst : SRL16E
|
||||
generic map (
|
||||
INIT => X"1111")
|
||||
port map (
|
||||
Q => SDA, -- SRL data output
|
||||
A0 => '1', -- Select[0] input
|
||||
A1 => '1', -- Select[1] input
|
||||
A2 => '1', -- Select[2] input
|
||||
A3 => '1', -- Select[3] input
|
||||
CE => '1', -- Clock enable input
|
||||
CLK => CLK, -- Clock input
|
||||
D => sda_int -- SRL data input
|
||||
);
|
||||
-- SDA <= sda_int;
|
||||
SCL <= scl_int;
|
||||
SCL_CNT_EN <= scl_cnt_en_int;
|
||||
I2C_RDY <= i2c_rdy_int;
|
||||
I2C_ACT <= i2c_act_int;
|
||||
I2C_RDATA <= i2c_rdata_int;
|
||||
ACK_ERR <= ack_err_int;
|
||||
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- state machine
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
case i2c_state is
|
||||
when idle =>
|
||||
if (I2C_GO = '1') then
|
||||
i2c_state <= en_clk after 1 * sim_timescale;
|
||||
else i2c_state <= idle;
|
||||
end if;
|
||||
when en_clk =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start1 after 1 * sim_timescale;
|
||||
else i2c_state <= en_clk;
|
||||
end if;
|
||||
when start1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= start1;
|
||||
end if;
|
||||
when dev_id1 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id1;
|
||||
end if;
|
||||
when ack_id1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
if ENAPH = '1' then
|
||||
i2c_state <= w_add after 1 * sim_timescale;
|
||||
else
|
||||
i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end if;
|
||||
else i2c_state <= ack_id1;
|
||||
end if;
|
||||
when w_add =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_add after 1 * sim_timescale;
|
||||
else i2c_state <= w_add;
|
||||
end if;
|
||||
when ack_add =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
case WR_L is
|
||||
when '1' => i2c_state <= dis_clk1 after 1 * sim_timescale;
|
||||
when others => i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end case;
|
||||
else i2c_state <= ack_add;
|
||||
end if;
|
||||
when w_dat =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_wr after 1 * sim_timescale;
|
||||
else i2c_state <= w_dat;
|
||||
end if;
|
||||
when ack_wr =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_wr;
|
||||
end if;
|
||||
when dis_clk1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= wait1 after 1 * sim_timescale;
|
||||
else i2c_state <= dis_clk1;
|
||||
end if;
|
||||
when wait1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start2 after 1 * sim_timescale;
|
||||
else i2c_state <= wait1;
|
||||
end if;
|
||||
when start2 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= start2;
|
||||
end if;
|
||||
when dev_id2 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id2;
|
||||
end if;
|
||||
when ack_id2 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_id2;
|
||||
end if;
|
||||
when data =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
case CONTINUE is
|
||||
when '1' => i2c_state <= ack_rd_mult after 1 * sim_timescale; --
|
||||
when others => i2c_state <= ack_rd after 1 * sim_timescale;--
|
||||
end case;
|
||||
else i2c_state <= data;
|
||||
end if;
|
||||
when ack_rd =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd;
|
||||
end if;
|
||||
when ack_rd_mult =>
|
||||
if ((SCL_TICK and scl_int) = '1')
|
||||
then i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd_mult;
|
||||
end if;
|
||||
when stop1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
else i2c_state <= stop1;
|
||||
end if;
|
||||
when others =>
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- bit counter
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
bit_cntr <= "111" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((en_cntr and scl_int) and SCL_TICK) = '1') then
|
||||
bit_cntr <= bit_cntr - "001" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((bit_cntr = "000") and (scl_int = '1')) then
|
||||
cntr_done <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
---------------------------------------------------------------------
|
||||
-- SCL generation
|
||||
-- enable CLK divider
|
||||
|
||||
if (RST = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = dev_id1) or (i2c_state = w_add) or (i2c_state =
|
||||
dev_id2) or (i2c_state = data) or (i2c_state = w_dat)) then
|
||||
en_cntr <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (cntr_done = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = en_clk) then
|
||||
scl_cnt_en_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = idle) then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- enables tick divider
|
||||
|
||||
--process (CLK, RST)
|
||||
--begin
|
||||
-- if (RST = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- elsif (CLK'event and CLK = '1') then
|
||||
-- if (i2c_state = start1) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = dis_clk1) and (SCL_TICK = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = start2) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = stop1) and (scl_int = '1')
|
||||
-- then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = start1) or (i2c_state = start2) then
|
||||
scl_en <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if ((i2c_state = dis_clk1) and (SCL_TICK = '1')) or ((i2c_state = stop1) and (scl_int = '1')) then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- tick divider
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((scl_en and SCL_TICK) = '1') then
|
||||
scl_int <= not scl_int after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = start1) or (i2c_state = start2) or (i2c_state = stop1) or (i2c_state = ack_rd_mult))
|
||||
then sda_int <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = dev_id1) then
|
||||
sda_int <= id_sel(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = dev_id2) then
|
||||
sda_int <= id_code_op(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_add) then
|
||||
sda_int <= WRD_ADD(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_dat) then
|
||||
sda_int <= WRD_DAT(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = data) and (scl_int = '1') then
|
||||
i2c_rdata_int(conv_integer(bit_cntr)) <= SDA_PIN after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = stop1) and (scl_int = '1')) or
|
||||
((i2c_state = ack_rd_mult) and (scl_int and not SDA_PIN and WR_L) = '1')) then
|
||||
i2c_rdy_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
-- if (I2C_GO = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = ack_id1) or (i2c_state = ack_add) or (i2c_state = ack_id2) or (i2c_state = ack_rd_mult) or (i2c_state = ack_wr))
|
||||
and (scl_int and SDA_PIN) = '1') then
|
||||
ack_err_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i2c_act_int <= '0' when i2c_state = idle else '1';
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,167 @@
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity si5332_wrapper is
|
||||
port(
|
||||
clk_100_in : in std_logic;
|
||||
clk_100_areset_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic;
|
||||
|
||||
qsfp2_clk_in : in std_logic;
|
||||
qsfp3_clk_in : in std_logic
|
||||
|
||||
);
|
||||
end entity si5332_wrapper;
|
||||
|
||||
architecture imp of si5332_wrapper is
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
signal man_clk_gen_en : std_logic;
|
||||
signal man_clk_gen_cfg_reset : std_logic;
|
||||
|
||||
|
||||
signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp3_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp3_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp3_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-----------------------------------
|
||||
i_si5341_clk_conf : entity work.si5341_clk_configurator
|
||||
port map (
|
||||
sys_clk100_in => clk_100_in,
|
||||
tick_1ms_in => tick_1ms,
|
||||
|
||||
sda_in => sda_in,
|
||||
sda_out => sda_out,
|
||||
sda_t_out => sda_t_out,
|
||||
|
||||
scl_in => scl_in,
|
||||
scl_out => scl_out,
|
||||
scl_t_out => scl_t_out,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
man_clk_gen_en_in => man_clk_gen_en,
|
||||
man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_100_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
|
||||
i_vio_3 : entity work.vio_3
|
||||
port map (
|
||||
clk => clk_100_in,
|
||||
probe_in0(0) => i2c_mux_access_ok, -- 1
|
||||
probe_in1(0) => si5341_access_ok, -- 1
|
||||
probe_in2(0) => si5341_config_done, -- 1
|
||||
probe_in3(0) => si5341_config_error, -- 1
|
||||
probe_in4 => clk_100_freq_r, -- 32
|
||||
probe_in5 => clk_100_cnt_r, -- 32
|
||||
probe_in6 => qsfp2_freq_r, -- 32
|
||||
probe_in7 => qsfp2_cnt_r, -- 32
|
||||
probe_in8 => qsfp3_freq_r, -- 32
|
||||
probe_in9 => qsfp3_cnt_r, -- 32
|
||||
|
||||
probe_out0(0) => man_clk_gen_en, -- 1
|
||||
probe_out1(0) => man_clk_gen_cfg_reset -- 1
|
||||
);
|
||||
|
||||
process(clk_100_in)
|
||||
begin
|
||||
if (rising_edge(clk_100_in)) then
|
||||
clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_100_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_100_freq_r <= clk_100_cnt_r;
|
||||
clk_100_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_100_cnt_r <= clk_100_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp2_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp2_clk_in)) then
|
||||
qsfp2_tick_1ms_r <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp2_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp2_freq_r <= qsfp2_cnt_r;
|
||||
qsfp2_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp2_cnt_r <= qsfp2_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp3_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp3_clk_in)) then
|
||||
qsfp3_tick_1ms_r <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp3_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp3_freq_r <= qsfp3_cnt_r;
|
||||
qsfp3_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp3_cnt_r <= qsfp3_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,183 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity si5341_clk_configurator is
|
||||
port (
|
||||
sys_clk100_in : in std_logic;
|
||||
tick_1ms_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic;
|
||||
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
man_clk_gen_en_in : in std_logic;
|
||||
man_clk_gen_cfg_reset_in : in std_logic;
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity si5341_clk_configurator;
|
||||
|
||||
architecture imp of si5341_clk_configurator is
|
||||
|
||||
signal clk_gen_cfg_reset_d : std_logic := '0';
|
||||
signal clk_gen_cfg_reset : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
type fsm_state_sm is (idle_st, si5341_reset_lo_st, si5341_reset_hi_st, si5341_config_st, si5341_config_wait_st,
|
||||
si5341_config_check_st, done_st);
|
||||
signal state_d : fsm_state_sm := idle_st;
|
||||
signal tick_cnt_d : integer;
|
||||
|
||||
signal state_test_r : std_logic_vector(2 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
clk_gen_cfg_reset <= man_clk_gen_cfg_reset_in when man_clk_gen_en_in = '1' else clk_gen_cfg_reset_d;
|
||||
|
||||
i_clk_gen_cfg : entity work.clk_gen_cfg
|
||||
generic map (
|
||||
simulation_mode => '0'
|
||||
)
|
||||
port map (
|
||||
sys_clk_in => sys_clk100_in,
|
||||
reset_in => clk_gen_cfg_reset,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
I_SDA_I => sda_in,
|
||||
O_SDA_O => sda_out,
|
||||
O_SDA_T => sda_t_out,
|
||||
|
||||
I_SCL_I => scl_in,
|
||||
O_SCL_O => scl_out,
|
||||
O_SCL_T => scl_t_out
|
||||
);
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok;
|
||||
si5341_access_ok_out <= si5341_access_ok;
|
||||
si5341_config_done_out <= si5341_config_done;
|
||||
si5341_config_error_out <= si5341_config_error;
|
||||
|
||||
process(state_d)
|
||||
begin
|
||||
case state_d is
|
||||
when idle_st => state_test_r <= "000";
|
||||
when si5341_reset_lo_st => state_test_r <= "001";
|
||||
when si5341_reset_hi_st => state_test_r <= "010";
|
||||
when si5341_config_st => state_test_r <= "011";
|
||||
when si5341_config_wait_st => state_test_r <= "100";
|
||||
when si5341_config_check_st => state_test_r <= "101";
|
||||
when done_st => state_test_r <= "110";
|
||||
when others => state_test_r <= "111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_0 : entity work.ila_0
|
||||
-- port map (
|
||||
-- clk => sys_clk100_in,
|
||||
-- probe0 => state_test_r, --3
|
||||
-- probe1(0) => i2c_mux_access_ok, --1
|
||||
-- probe2(0) => si5341_access_ok, --1
|
||||
-- probe3(0) => si5341_config_done, --1
|
||||
-- probe4(0) => si5341_config_error, --1
|
||||
-- probe5(0) => clk_gen_cfg_reset, --1
|
||||
-- probe7(0) => clk_gen_cfg_reset_d, --1
|
||||
-- probe9(0) => tick_1ms_in --1
|
||||
-- );
|
||||
|
||||
process(sys_clk100_in)
|
||||
begin
|
||||
if (rising_edge(sys_clk100_in)) then
|
||||
if (reset_in = '1') then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 500;
|
||||
state_d <= idle_st;
|
||||
else
|
||||
if (tick_1ms_in = '1') then
|
||||
tick_cnt_d <= tick_cnt_d - 1;
|
||||
end if;
|
||||
|
||||
case state_d is
|
||||
when idle_st => --0
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_reset_lo_st;
|
||||
else
|
||||
state_d <= idle_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_lo_st => --1
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 100;
|
||||
state_d <= si5341_reset_hi_st;
|
||||
else
|
||||
state_d <= si5341_reset_lo_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_hi_st => --2
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '1';
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_config_st;
|
||||
else
|
||||
state_d <= si5341_reset_hi_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_st => --3
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_wait_st;
|
||||
else
|
||||
state_d <= si5341_config_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_wait_st => --4
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_check_st;
|
||||
else
|
||||
state_d <= si5341_config_wait_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_check_st => --5
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= idle_st;
|
||||
elsif (i2c_mux_access_ok = '1' and si5341_access_ok = '1' and si5341_config_done = '1' and si5341_config_error = '0') then
|
||||
state_d <= done_st;
|
||||
else
|
||||
state_d <= si5341_config_check_st;
|
||||
end if;
|
||||
|
||||
when done_st => --6
|
||||
state_d <= done_st;
|
||||
|
||||
when others => --7
|
||||
state_d <= idle_st;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,380 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: Silicon Lab Si5341 Clock Generator Configuration Design
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project: HTG-ZRF8
|
||||
-- File name: si5341_gen_cfg.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose: Configures Si5341 Clock Generators on Start-up
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Xilinx Vivado
|
||||
-- Synthesis: Xilinx Vivado
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 1.00
|
||||
-- Modification date: 20/10/2018
|
||||
-- Limitation: Design requires 12.5MHz input clock.
|
||||
-- Change COUNT_DIV value for other bus frequency.
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
use work.global_types.all;
|
||||
|
||||
entity si5341_gen_cfg is
|
||||
generic (
|
||||
COUNT_DIV : integer range 0 to 1023 := 512; -- sysclk divide coefficient (Valid Values: 2 to 1023)
|
||||
SIZ5341 : integer range 0 to 511 := 511; -- Real Address/Data Array Size (Valid Values: 1 to 511)
|
||||
ADR5341 : addr_si5341_type := (others => (others => '0'));
|
||||
DAT5341 : data_si5341_type := (others => (others => '0'));
|
||||
simulation_mode : std_logic := '0'
|
||||
);
|
||||
port (
|
||||
-- System signals
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
-- External Operation Control
|
||||
START : in std_logic; -- Run Start-Up Clock Genrators Configuration
|
||||
|
||||
-- Status Output
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
-- I2C Bus
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic
|
||||
);
|
||||
end entity si5341_gen_cfg;
|
||||
|
||||
architecture si5341_gen_cfg_arch of si5341_gen_cfg is
|
||||
|
||||
component i2c
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coefficient (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
|
||||
type fsm_state is (IDLE, SI5341_NEW, SI5341_NEW_WR, SI5341_NEW_INC, FINISH, ERROR);
|
||||
|
||||
signal state_r : fsm_state := IDLE;
|
||||
|
||||
signal i2c_rdata : std_logic_vector(7 downto 0);
|
||||
|
||||
signal si5341_adr_arr : addr_si5341_type := ADR5341;
|
||||
signal si5341_dat_arr : data_si5341_type := DAT5341;
|
||||
|
||||
signal dev_addr : std_logic_vector(6 downto 0);
|
||||
|
||||
signal new_adr : std_logic_vector(7 downto 0);
|
||||
signal cur_addr : integer range 0 to 511 := 0;
|
||||
signal inc_adr : std_logic;
|
||||
signal new_da : std_logic_vector(6 downto 0):= (others => '0');
|
||||
signal addr : std_logic_vector(8 downto 0);
|
||||
signal new_dat : std_logic_vector(7 downto 0);
|
||||
signal new_wr : std_logic;
|
||||
signal new_op : std_logic;
|
||||
signal new_apen : std_logic := '0';
|
||||
signal ap_en : std_logic;
|
||||
|
||||
signal dat_in : std_logic_vector(7 downto 0);
|
||||
|
||||
signal word_addr : std_logic_vector(7 downto 0);
|
||||
signal we_i2c : std_logic;
|
||||
signal wr_i2c : std_logic;
|
||||
|
||||
signal ack_err : std_logic;
|
||||
signal i2c_rdy : std_logic;
|
||||
signal i2c_act : std_logic;
|
||||
signal CONTINUE : std_logic;
|
||||
signal ACK_L : std_logic;
|
||||
|
||||
signal i2c_busy : std_logic;
|
||||
signal i2c_act_fall : std_logic := '0';
|
||||
signal i2c_act_rg : std_logic := '0';
|
||||
|
||||
signal addr_itg : integer range 0 to 511;
|
||||
signal si5341_size : integer range 0 to 511;
|
||||
signal si5341_data : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr : std_logic_vector(15 downto 0);
|
||||
signal si5341_addr_h : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr_l : std_logic_vector(7 downto 0);
|
||||
|
||||
signal state_test_r : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
signal i2c_mux_access_ok_r : std_logic := '0';
|
||||
signal si5341_access_ok_r : std_logic := '0';
|
||||
signal si5341_config_done_r : std_logic := '0';
|
||||
signal si5341_config_error_r : std_logic := '0';
|
||||
|
||||
|
||||
begin
|
||||
|
||||
addr_itg <= CONV_INTEGER(cur_addr);
|
||||
si5341_addr <= si5341_adr_arr(addr_itg);
|
||||
si5341_data <= si5341_dat_arr(addr_itg);
|
||||
si5341_size <= SIZ5341;
|
||||
si5341_addr_h <= si5341_addr(15 downto 8); -- Page Number
|
||||
si5341_addr_l <= si5341_addr( 7 downto 0); -- Byte Address
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok_r;
|
||||
si5341_access_ok_out <= si5341_access_ok_r;
|
||||
si5341_config_done_out <= si5341_config_done_r;
|
||||
si5341_config_error_out <= si5341_config_error_r;
|
||||
|
||||
process(state_r)
|
||||
begin
|
||||
case state_r is
|
||||
when IDLE => state_test_r <= "0000";
|
||||
when SI5341_NEW => state_test_r <= "0011";
|
||||
when SI5341_NEW_WR => state_test_r <= "0101";
|
||||
when SI5341_NEW_INC => state_test_r <= "0110";
|
||||
when FINISH => state_test_r <= "1000";
|
||||
when ERROR => state_test_r <= "1001";
|
||||
when others => state_test_r <= "1111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_1 : entity work.ila_1
|
||||
-- port map (
|
||||
-- clk => CLK,
|
||||
-- probe0 => state_test_r, --4
|
||||
-- probe1 => new_da, --7
|
||||
-- probe2 => new_dat, --8
|
||||
-- probe3(0) => new_wr, --1
|
||||
-- probe4(0) => i2c_busy, --1
|
||||
-- probe7(0) => i2c_rdy, --1
|
||||
-- probe8(0) => i2c_act, --1
|
||||
-- probe9(0) => ack_err, --1
|
||||
-- probe10(0) => START, --1
|
||||
-- probe13 => new_adr -- 8
|
||||
-- );
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
-- I2C Mudule
|
||||
---------------------------------------------------------------------------------------------
|
||||
|
||||
SPD_READ_UNIT: i2c
|
||||
generic map(
|
||||
count_div => COUNT_DIV -- sysclk divide coafficien (2 to 1023 max)
|
||||
)
|
||||
port map(
|
||||
ADDR_IN => word_addr, -- word address
|
||||
DAT_IN => DAT_IN, -- write data
|
||||
DEV_ADDR => dev_addr, -- device address
|
||||
CONTINUE => CONTINUE, -- continue read operation from ADDR_IN
|
||||
AP_EN => ap_en, -- Enable Address Phase During Write
|
||||
WR_OP => wr_i2c, -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN => we_i2c, -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK => CLK, -- main clock
|
||||
RST => RST, -- system reset
|
||||
|
||||
I2C_RDATA => i2c_rdata, -- i2c read data
|
||||
ACK_L => ACK_L, -- acknowledge WR_EN (active '0')
|
||||
|
||||
I_SDA_I => I_SDA_I,
|
||||
O_SDA_O => O_SDA_O,
|
||||
O_SDA_T => O_SDA_T,
|
||||
|
||||
I_SCL_I => I_SCL_I,
|
||||
O_SCL_O => O_SCL_O,
|
||||
O_SCL_T => O_SCL_T,
|
||||
|
||||
I2C_RDY => i2c_rdy, -- i2c ready
|
||||
I2C_ACT => i2c_act, -- i2c cycle active
|
||||
ACK_ERR => ack_err -- i2c(ack) error
|
||||
);
|
||||
|
||||
CONTINUE <= '0';
|
||||
word_addr <= new_adr;
|
||||
dev_addr <= new_da;
|
||||
we_i2c <= new_wr;
|
||||
wr_i2c <= new_op;
|
||||
dat_in <= new_dat;
|
||||
ap_en <= new_apen;
|
||||
|
||||
I2C_BUSY_RG: process (RST, CLK)
|
||||
begin
|
||||
if RST = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if i2c_act_fall = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif new_wr = '1' then
|
||||
i2c_busy <= '1';
|
||||
end if;
|
||||
i2c_act_rg <= i2c_act;
|
||||
i2c_act_fall <= i2c_act_rg and not i2c_act;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_mux_access_ok_r <= '0';
|
||||
si5341_access_ok_r <= '0';
|
||||
si5341_config_done_r <= '0';
|
||||
si5341_config_error_r <= '0';
|
||||
|
||||
cur_addr <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(CLK)) then
|
||||
if inc_adr = '1' then
|
||||
cur_addr <= cur_addr + 1;
|
||||
end if;
|
||||
|
||||
case state_r is
|
||||
|
||||
when IDLE => --0
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= X"55"; -- selects SC0/SD0 from I2C Mux U22 on ZCU208
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (START = '1') then
|
||||
new_da <= "1101010"; -- 6Ah - Si5332 Access
|
||||
new_apen <= '1';
|
||||
new_wr <= '0';
|
||||
i2c_mux_access_ok_r <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SI5341_NEW => --3
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
if (cur_addr = si5341_size) then
|
||||
state_r <= FINISH;
|
||||
else
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Write Register Value
|
||||
when SI5341_NEW_WR => --5
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if (ack_err = '1') then
|
||||
state_r <= ERROR;
|
||||
new_wr <= '0';
|
||||
else
|
||||
si5341_access_ok_r <= '1';
|
||||
new_wr <= '1';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Increment Counter
|
||||
when SI5341_NEW_INC => --6
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if ack_err = '1' then
|
||||
inc_adr <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
inc_adr <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
end if;
|
||||
else
|
||||
inc_adr <= '0';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
|
||||
when FINISH => --8
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_done_r <= '1';
|
||||
state_r <= FINISH;
|
||||
|
||||
when ERROR => --9
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_error_r <= '1';
|
||||
state_r <= ERROR;
|
||||
|
||||
when others => --f
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end si5341_gen_cfg_arch;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32kx256",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_data_fifo_32kx256",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "block", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32kx128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "block", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "826355760", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_data_fifo_32kx256" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
|
||||
"almost_empty": [ { "direction": "out" } ],
|
||||
"prog_empty": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,192 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x512",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../test_sim/project_1.gen/sources_1/ip/axis_data_fifo_32x512",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x512", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825765936", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../test_sim/project_1.gen/sources_1/ip/axis_data_fifo_32x512" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
|
||||
"almost_empty": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: axis_demux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m0_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m0_axis_tvalid : out std_logic;
|
||||
m0_axis_tready : in std_logic;
|
||||
|
||||
m1_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m1_axis_tvalid : out std_logic;
|
||||
m1_axis_tready : in std_logic
|
||||
);
|
||||
end axis_demux;
|
||||
|
||||
architecture imp of axis_demux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
--signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
m0_axis_tdata <= s_axis_tdata;
|
||||
m1_axis_tdata <= s_axis_tdata;
|
||||
|
||||
m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
|
||||
m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
|
||||
|
||||
s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
|
||||
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,488 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_demux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m0_axis:m1_axis:s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_demux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>57ba02cc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_demux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>16ec46fd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c6faabd4</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aselect</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m0_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m1_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>DWIDTH</spirit:name>
|
||||
<spirit:displayName>Dwidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWIDTH">512</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_16ec46fd</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axis_demux.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_demux_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_c6faabd4</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_demux_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DWIDTH</spirit:name>
|
||||
<spirit:displayName>DWIDTH</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWIDTH">512</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_demux_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axis_demux_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2021-06-22T18:00:02Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@27b453f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1258db51_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@53d4f02b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a095752_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e2c012e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@32a42669_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1640d25f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1f86641f_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7df1d869_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a3f7179_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@78b50c76_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e487608_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@70e25a99_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@14ea36d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2e26ac35_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1f47c38d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4dc9792_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55f4ea14_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@cdc4a77_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="05d5a589"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4b08030d"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="d2fc399b"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="55dda66a"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_dwidth_converter_256b_to_512b",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_dwidth_converter_256b_to_512b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_dwidth_converter_256b_to_512b", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_dwidth_converter_256b_to_512b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
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|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 05/18/2021 11:43:02 AM
|
||||
-- Design Name:
|
||||
-- Module Name: axis_mux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_mux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s0_axis_tvalid : in std_logic;
|
||||
s0_axis_tready : out std_logic;
|
||||
s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s1_axis_tvalid : in std_logic;
|
||||
s1_axis_tready : out std_logic;
|
||||
m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end axis_mux;
|
||||
|
||||
architecture imp of axis_mux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
aselect_int <= aselect;
|
||||
|
||||
m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
|
||||
m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
|
||||
s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
|
||||
s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,542 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_mux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
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<xilinx:tag xilinx:name="ui.data.coregen.dd@521b75a_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e696d4a_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6822de6c_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6d04f6bb_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@70d8f0cc_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@11b7ade6_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@480ace1b_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@40a7b83_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d1b9e42_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@794ad73b_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@577fb6a6_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c89838f_ARCHIVE_LOCATION">c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2a031008_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3a834977_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@74a96827_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@781e86fd_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6c15b577_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4d9fef3d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@16ac630d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4cec9a36_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@55a12c39_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@632873ed_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@68071b83_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@43775ef0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1946983d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@502a5174_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@46e8cbd5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6af1b794_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1892dd8b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4af08e99_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@762583a1_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64c4fdab_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4846b579_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@160330b9_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@23247587_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1542fbd2_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@714d5df2_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1fd79205_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6b73b80e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1a0555de_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1b12cc6d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7505fb14_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@301a3b59_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@359c295b_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2033e680_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@63fadde1_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@774e9648_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@25b4503c_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4372da5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47ed35b3_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@48531ae8_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@8313885_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5478ac48_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="24797529"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e6992404"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="04f2586c"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="e7b1dc92"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_240b",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_register_slice_240b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_register_slice_240b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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||||
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|
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,344 @@
|
||||
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|
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||||
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||||
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||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>select_12b</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">319</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b952dd62</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>dig_iq_decoder.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/dig_iq_decoder_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>dig_iq_decoder_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dig_iq_decoder_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>dig_iq_decoder_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2021-06-22T17:47:25Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="nopcore"/>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f062d2d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@10cd760_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64b4837a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1edcc17e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7024ec49_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ee4ccf6_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@702143e0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7318cb6e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47f9d0d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@467c2891_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@79d4f659_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8005bf8b"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6945f44e"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b2bb5fab"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c99d0644"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,114 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_decoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_decoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
select_12b : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(319 downto 0);
|
||||
m_axis_tvalid : out std_logic
|
||||
);
|
||||
end dig_iq_decoder;
|
||||
|
||||
architecture imp of dig_iq_decoder is
|
||||
|
||||
signal tvalid_int : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= tvalid_int;
|
||||
|
||||
|
||||
process(aclk, aresetn)
|
||||
begin
|
||||
if(aresetn = '0')then
|
||||
tvalid_int <= '0';
|
||||
elsif(rising_edge(aclk))then
|
||||
tvalid_int <= s_axis_tvalid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(aclk)
|
||||
begin
|
||||
|
||||
if(rising_edge(aclk))then
|
||||
|
||||
if(select_12b = '0')then
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(32 downto 17 ); -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(49 downto 34 ); -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(66 downto 51 ); -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(83 downto 68 ); -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(100 downto 85 ); -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(117 downto 102 ); -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(134 downto 119 ); -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(151 downto 136 ); -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(168 downto 153 ); -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(185 downto 170 ); -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(202 downto 187 ); -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(219 downto 204 ); -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(236 downto 221 ); -- IMAG[6]
|
||||
else
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(11 downto 0 ) & "0000"; -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(23 downto 12 ) & "0000"; -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(35 downto 24 ) & "0000"; -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(47 downto 36 ) & "0000"; -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(59 downto 48 ) & "0000"; -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(71 downto 60 ) & "0000"; -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(83 downto 72 ) & "0000"; -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(95 downto 84 ) & "0000"; -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(107 downto 96 ) & "0000"; -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(119 downto 108 ) & "0000"; -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(131 downto 120 ) & "0000"; -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(143 downto 132 ) & "0000"; -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(155 downto 144 ) & "0000"; -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(167 downto 156 ) & "0000"; -- IMAG[6]
|
||||
end if;
|
||||
|
||||
m_axis_tdata(239 downto 224 ) <= s_axis_tdata(179 downto 168 ) & "0000"; -- REAL[7]
|
||||
m_axis_tdata(255 downto 240 ) <= s_axis_tdata(191 downto 180 ) & "0000"; -- IMAG[7]
|
||||
m_axis_tdata(271 downto 256 ) <= s_axis_tdata(203 downto 192 ) & "0000"; -- REAL[8]
|
||||
m_axis_tdata(287 downto 272 ) <= s_axis_tdata(215 downto 204 ) & "0000"; -- IMAG[8]
|
||||
m_axis_tdata(303 downto 288 ) <= s_axis_tdata(227 downto 216 ) & "0000"; -- REAL[9]
|
||||
m_axis_tdata(319 downto 304 ) <= s_axis_tdata(239 downto 228 ) & "0000"; -- IMAG[9]
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,978 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
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|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_240b_to_512b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:value>
|
||||
</spirit:parameter>
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||||
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||||
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|
||||
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|
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
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|
||||
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|
||||
<spirit:name>PHASE</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
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|
||||
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|
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|
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||||
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|
||||
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||||
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|
||||
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|
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|
||||
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||||
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||||
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|
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<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
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|
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|
||||
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|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
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|
||||
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|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
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|
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|
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|
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|
||||
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|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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|
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|
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|
||||
<spirit:name>RST</spirit:name>
|
||||
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|
||||
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|
||||
<spirit:name>aresetn</spirit:name>
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|
||||
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|
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|
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|
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<spirit:parameter>
|
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|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
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|
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|
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|
||||
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|
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_axis_mux_1_0__ref_view_fileset</spirit:localName>
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<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset</spirit:localName>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>caff039b</spirit:value>
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|
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>79335991</spirit:value>
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<spirit:name>xilinx_implementation</spirit:name>
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<spirit:displayName>Implementation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
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|
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|
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|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
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@@ -0,0 +1,357 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component iq_240b_to_512b_axis_demux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_demux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component iq_240b_to_512b_iq_decoder_12b_16b_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_iq_decoder_12b_16b_0;
|
||||
component iq_240b_to_512b_axis_mux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_mux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component iq_240b_to_512b_axis_demux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component iq_240b_to_512b_axis_mux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component iq_240b_to_512b_iq_decoder_12b_16b_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,367 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready_out : out std_logic;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_demux;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component dig_iq_decoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component dig_iq_decoder;
|
||||
component axis_mux is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_mux;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
|
||||
s_axis_tready_out <= axis_data_fifo_0_M_AXIS_TREADY;
|
||||
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component axis_demux
|
||||
generic map (
|
||||
DWIDTH => 320
|
||||
)
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component axis_mux
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component dig_iq_decoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_data_fifo_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_axis_data_fifo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
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"mode": "slave",
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|
||||
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|
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|
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||||
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||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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||||
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+154
@@ -0,0 +1,154 @@
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"Component_Name": [ { "value": "iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0", "resolve_type": "user", "usage": "all" } ]
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|
||||
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|
||||
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|
||||
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|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
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|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
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|
||||
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|
||||
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|
||||
"ip_revision": "6",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"ARCHITECTURE": [ { "value": "virtexuplus", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s0_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s0_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s0_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s0_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s1_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s1_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s1_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s1_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+158
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_register_slice_28B_0",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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|
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|
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
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|
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|
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|
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+169
@@ -0,0 +1,169 @@
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{
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlconstant_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlslice_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlslice:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_WIDTH": [ { "value": "320", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DOUT_WIDTH": [ { "value": "224", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DIN_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"Din": [ { "direction": "in", "size_left": "319", "size_right": "0" } ],
|
||||
"Dout": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_static_text $IPINST -name "TEXT1" -parent ${Page_0} -text {sel_12b_16bn = 0 -- 16-bit FSW data (Fs <= 600MHz)
|
||||
|
||||
|
||||
|
||||
sel_12b_16bn = 1 -- 12-bit FSW data (Fs = 1200MHz)}
|
||||
|
||||
|
||||
}
|
||||
@@ -0,0 +1,564 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_512b_to_240b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
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|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>iq_512b_to_240b</xilinx:displayName>
|
||||
<xilinx:definitionSource>IPI</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-24T16:38:16Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5a5f56fc"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2a3456f"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c875ab87"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ca8f49ff"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component iq_512b_to_240b_dig_iq_encoder_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_512b_to_240b_dig_iq_encoder_0_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component dig_iq_encoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component dig_iq_encoder;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component dig_iq_encoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1169
File diff suppressed because it is too large
Load Diff
+336
@@ -0,0 +1,336 @@
|
||||
// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
// f_clogb2
|
||||
// f_gcd
|
||||
// f_lcm
|
||||
// f_get_tdata_indx
|
||||
// f_get_tstrb_indx
|
||||
// f_get_tkeep_indx
|
||||
// f_get_tlast_indx
|
||||
// f_get_tid_indx
|
||||
// f_get_tdest_indx
|
||||
// f_get_tuser_indx
|
||||
// f_payload_width
|
||||
// Tasks:
|
||||
// t_display_tdata_error
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Define Signal Set indices
|
||||
localparam G_INDX_SS_TREADY = 0;
|
||||
localparam G_INDX_SS_TDATA = 1;
|
||||
localparam G_INDX_SS_TSTRB = 2;
|
||||
localparam G_INDX_SS_TKEEP = 3;
|
||||
localparam G_INDX_SS_TLAST = 4;
|
||||
localparam G_INDX_SS_TID = 5;
|
||||
localparam G_INDX_SS_TDEST = 6;
|
||||
localparam G_INDX_SS_TUSER = 7;
|
||||
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
|
||||
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
|
||||
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
|
||||
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
|
||||
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
|
||||
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
|
||||
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
|
||||
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
|
||||
|
||||
// Task DRC error levels
|
||||
localparam G_TASK_SEVERITY_ERR = 2;
|
||||
localparam G_TASK_SEVERITY_WARNING = 1;
|
||||
localparam G_TASK_SEVERITY_INFO = 0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Functions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
// Calculates the Greatest Common Divisor between two integers using the
|
||||
// euclidean algorithm.
|
||||
function automatic integer f_gcd (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
if (a == 0) begin
|
||||
f_gcd = b;
|
||||
end else if (b == 0) begin
|
||||
f_gcd = a;
|
||||
end else if (a > b) begin
|
||||
f_gcd = f_gcd(a % b, b);
|
||||
end else begin
|
||||
f_gcd = f_gcd(a, b % a);
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Calculates the Lowest Common Denominator between two integers
|
||||
function integer f_lcm (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
f_lcm = ( a / f_gcd(a, b)) * b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdata_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
f_get_tdata_indx = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tstrb_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
|
||||
// If TDATA exists, then add its width to its base to get the tstrb index
|
||||
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tkeep_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tlast_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tid_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdest_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tuser_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Payload is the sum of all the AXIS signals present except for
|
||||
// TREADY/TVALID
|
||||
function integer f_payload_width (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
|
||||
// Ensure that the return value is never less than 1
|
||||
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
|
||||
end
|
||||
endfunction
|
||||
|
||||
task t_check_tdata_width(
|
||||
input integer data_width,
|
||||
input [8*80-1:0] var_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tdata_width
|
||||
if (data_width%8 != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
|
||||
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
|
||||
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
|
||||
$display(" information.");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task t_check_tuser_width(
|
||||
input integer tuser_width,
|
||||
input [8*80-1:0] tuser_name,
|
||||
input integer tdata_width,
|
||||
input [8*80-1:0] tdata_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tuser_width
|
||||
integer tdata_bytes;
|
||||
tdata_bytes = tdata_width/8;
|
||||
if ((tuser_width%tdata_bytes) != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
|
||||
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
|
||||
$display(" TUSER width in this module is only defined when the TUSER is the");
|
||||
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
|
||||
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
+1318
File diff suppressed because it is too large
Load Diff
+2998
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+152
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_axis_dwidth_converter_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1403
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 5.120 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+99512
File diff suppressed because it is too large
Load Diff
+130586
File diff suppressed because it is too large
Load Diff
+30
@@ -0,0 +1,30 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri Mar 28 20:50:13 2025
|
||||
// Host : Ubuntu-Dev running 64-bit Ubuntu 22.04.5 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top iq_512b_to_240b_axis_dwidth_converter_0_0 -prefix
|
||||
// iq_512b_to_240b_axis_dwidth_converter_0_0_ iq_512b_to_240b_axis_dwidth_converter_0_0_stub.v
|
||||
// Design : iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xczu19eg-ffvc1760-2-i
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2" *)
|
||||
module iq_512b_to_240b_axis_dwidth_converter_0_0(aclk, aresetn, s_axis_tvalid, s_axis_tready,
|
||||
s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[511:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[223:0]" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [511:0]s_axis_tdata;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [223:0]m_axis_tdata;
|
||||
endmodule
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
-- Date : Fri Mar 28 20:50:13 2025
|
||||
-- Host : Ubuntu-Dev running 64-bit Ubuntu 22.04.5 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top iq_512b_to_240b_axis_dwidth_converter_0_0 -prefix
|
||||
-- iq_512b_to_240b_axis_dwidth_converter_0_0_ iq_512b_to_240b_axis_dwidth_converter_0_0_stub.vhdl
|
||||
-- Design : iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xczu19eg-ffvc1760-2-i
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
|
||||
end iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
|
||||
architecture stub of iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[511:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[223:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2";
|
||||
begin
|
||||
end;
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "iq_512b_to_240b_axis_dwidth_converter_0_0,axis_dwidth_converter_v1_1_28_axis_dwidth_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "iq_512b_to_240b_axis_dwidth_converter_0_0,axis_dwidth_converter_v1_1_28_axis_dwidth_converter,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_dwidth_converter,x_ipVersion=1.1,x_ipCoreRevision=28,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_S_AXIS_TDATA_WIDTH=512,C_M_AXIS_TDATA_WIDTH=224,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_S_AXIS_TUSER_WIDTH=1,C_M_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module iq_512b_to_240b_axis_dwidth_converter_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axis_tvalid,
|
||||
s_axis_tready,
|
||||
s_axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tready,
|
||||
m_axis_tdata
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire s_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire s_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [511 : 0] s_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire m_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 28, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [223 : 0] m_axis_tdata;
|
||||
|
||||
axis_dwidth_converter_v1_1_28_axis_dwidth_converter #(
|
||||
.C_FAMILY("zynquplus"),
|
||||
.C_S_AXIS_TDATA_WIDTH(512),
|
||||
.C_M_AXIS_TDATA_WIDTH(224),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_S_AXIS_TUSER_WIDTH(1),
|
||||
.C_M_AXIS_TUSER_WIDTH(1),
|
||||
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'H1),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tstrb(64'HFFFFFFFFFFFFFFFF),
|
||||
.s_axis_tkeep(64'HFFFFFFFFFFFFFFFF),
|
||||
.s_axis_tlast(1'H1),
|
||||
.s_axis_tid(1'H0),
|
||||
.s_axis_tdest(1'H0),
|
||||
.s_axis_tuser(1'H0),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_encoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_encoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(223 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end dig_iq_encoder;
|
||||
|
||||
architecture imp of dig_iq_encoder is
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= s_axis_tvalid;
|
||||
s_axis_tready <= m_axis_tready;
|
||||
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(16) <= '0';
|
||||
m_axis_tdata(32 downto 17 ) <= s_axis_tdata(31 downto 16 ); -- IMAG[0]
|
||||
m_axis_tdata(33) <= '0';
|
||||
m_axis_tdata(49 downto 34 ) <= s_axis_tdata(47 downto 32 ); -- REAL[1]
|
||||
m_axis_tdata(50) <= '0';
|
||||
m_axis_tdata(66 downto 51 ) <= s_axis_tdata(63 downto 48 ); -- IMAG[1]
|
||||
m_axis_tdata(67) <= '0';
|
||||
m_axis_tdata(83 downto 68 ) <= s_axis_tdata(79 downto 64 ); -- REAL[2]
|
||||
m_axis_tdata(84) <= '0';
|
||||
m_axis_tdata(100 downto 85 ) <= s_axis_tdata(95 downto 80 ); -- IMAG[2]
|
||||
m_axis_tdata(101) <= '0';
|
||||
m_axis_tdata(117 downto 102 ) <= s_axis_tdata(111 downto 96 ); -- REAL[3]
|
||||
m_axis_tdata(118) <= '0';
|
||||
m_axis_tdata(134 downto 119 ) <= s_axis_tdata(127 downto 112 ); -- IMAG[3]
|
||||
m_axis_tdata(135) <= '0';
|
||||
m_axis_tdata(151 downto 136 ) <= s_axis_tdata(143 downto 128 ); -- REAL[4]
|
||||
m_axis_tdata(152) <= '0';
|
||||
m_axis_tdata(168 downto 153 ) <= s_axis_tdata(159 downto 144 ); -- IMAG[4]
|
||||
m_axis_tdata(169) <= '0';
|
||||
m_axis_tdata(185 downto 170 ) <= s_axis_tdata(175 downto 160 ); -- REAL[5]
|
||||
m_axis_tdata(186) <= '0';
|
||||
m_axis_tdata(202 downto 187 ) <= s_axis_tdata(191 downto 176 ); -- IMAG[5]
|
||||
m_axis_tdata(203) <= '0';
|
||||
m_axis_tdata(219 downto 204 ) <= s_axis_tdata(207 downto 192 ); -- REAL[6]
|
||||
m_axis_tdata(220) <= '0';
|
||||
m_axis_tdata(236 downto 221 ) <= s_axis_tdata(223 downto 208 ); -- IMAG[6]
|
||||
m_axis_tdata(139 downto 237 ) <= (others => '0');
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_dig_iq_encoder_0_0",
|
||||
"component_reference": "xilinx.com:user:dig_iq_encoder:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_dig_iq_encoder_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,86 @@
|
||||
|
||||
proc init { cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
set full_sbusif_list [list ]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
||||
set busif_param_list [list]
|
||||
set busif_name [get_property NAME $busif]
|
||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
||||
continue
|
||||
}
|
||||
foreach tparam $axi_standard_param_list {
|
||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
||||
}
|
||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc pre_propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
if { $val_on_cell != "" } {
|
||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc propagate {cellpath otherInfo } {
|
||||
|
||||
set cell_handle [get_bd_cells $cellpath]
|
||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
||||
|
||||
foreach busif $all_busif {
|
||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
||||
continue
|
||||
}
|
||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
||||
continue
|
||||
}
|
||||
|
||||
set busif_name [get_property NAME $busif]
|
||||
foreach tparam $axi_standard_param_list {
|
||||
set busif_param_name "C_${busif_name}_${tparam}"
|
||||
|
||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
||||
|
||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
||||
if { $val_on_cell_intf_pin != "" } {
|
||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
OPTION psf_version = 2.1;
|
||||
|
||||
BEGIN DRIVER qsfp_intfc
|
||||
OPTION supported_peripherals = (qsfp_intfc);
|
||||
OPTION copyfiles = all;
|
||||
OPTION VERSION = 1.0;
|
||||
OPTION NAME = qsfp_intfc;
|
||||
END DRIVER
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
|
||||
proc generate {drv_handle} {
|
||||
xdefine_include_file $drv_handle "xparameters.h" "qsfp_intfc" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES=*.h
|
||||
LIBSOURCES=*.c
|
||||
OUTS = *.o
|
||||
|
||||
libs:
|
||||
echo "Compiling qsfp_intfc..."
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
@@ -0,0 +1,6 @@
|
||||
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "qsfp_intfc.h"
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
@@ -0,0 +1,107 @@
|
||||
|
||||
#ifndef QSFP_INTFC_H
|
||||
#define QSFP_INTFC_H
|
||||
|
||||
|
||||
/****************** Include Files ********************/
|
||||
#include "xil_types.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG0_OFFSET 0
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG1_OFFSET 4
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG2_OFFSET 8
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG3_OFFSET 12
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG4_OFFSET 16
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG5_OFFSET 20
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG6_OFFSET 24
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG7_OFFSET 28
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG8_OFFSET 32
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG9_OFFSET 36
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG10_OFFSET 40
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG11_OFFSET 44
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG12_OFFSET 48
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG13_OFFSET 52
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG14_OFFSET 56
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG15_OFFSET 60
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG16_OFFSET 64
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG17_OFFSET 68
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG18_OFFSET 72
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG19_OFFSET 76
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG20_OFFSET 80
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG21_OFFSET 84
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG22_OFFSET 88
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG23_OFFSET 92
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG24_OFFSET 96
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG25_OFFSET 100
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG26_OFFSET 104
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG27_OFFSET 108
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG28_OFFSET 112
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG29_OFFSET 116
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG30_OFFSET 120
|
||||
#define QSFP_INTFC_S00_AXI_SLV_REG31_OFFSET 124
|
||||
|
||||
|
||||
/**************************** Type Definitions *****************************/
|
||||
/**
|
||||
*
|
||||
* Write a value to a QSFP_INTFC register. A 32 bit write is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is written.
|
||||
*
|
||||
* @param BaseAddress is the base address of the QSFP_INTFCdevice.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
* @param Data is the data written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void QSFP_INTFC_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
||||
*
|
||||
*/
|
||||
#define QSFP_INTFC_mWriteReg(BaseAddress, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
||||
|
||||
/**
|
||||
*
|
||||
* Read a value from a QSFP_INTFC register. A 32 bit read is performed.
|
||||
* If the component is implemented in a smaller width, only the least
|
||||
* significant data is read from the register. The most significant data
|
||||
* will be read as 0.
|
||||
*
|
||||
* @param BaseAddress is the base address of the QSFP_INTFC device.
|
||||
* @param RegOffset is the register offset from the base to write to.
|
||||
*
|
||||
* @return Data is the data from the register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 QSFP_INTFC_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
||||
*
|
||||
*/
|
||||
#define QSFP_INTFC_mReadReg(BaseAddress, RegOffset) \
|
||||
Xil_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/************************** Function Prototypes ****************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the QSFP_INTFC instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus QSFP_INTFC_Reg_SelfTest(void * baseaddr_p);
|
||||
|
||||
#endif // QSFP_INTFC_H
|
||||
@@ -0,0 +1,60 @@
|
||||
|
||||
/***************************** Include Files *******************************/
|
||||
#include "qsfp_intfc.h"
|
||||
#include "xparameters.h"
|
||||
#include "stdio.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions ***************************/
|
||||
#define READ_WRITE_MUL_FACTOR 0x10
|
||||
|
||||
/************************** Function Definitions ***************************/
|
||||
/**
|
||||
*
|
||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
||||
* resets of the device are performed.
|
||||
*
|
||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
|
||||
*
|
||||
* @param baseaddr_p is the base address of the QSFP_INTFCinstance to be worked on.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
|
||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
|
||||
*
|
||||
*/
|
||||
XStatus QSFP_INTFC_Reg_SelfTest(void * baseaddr_p)
|
||||
{
|
||||
u32 baseaddr;
|
||||
int write_loop_index;
|
||||
int read_loop_index;
|
||||
int Index;
|
||||
|
||||
baseaddr = (u32) baseaddr_p;
|
||||
|
||||
xil_printf("******************************\n\r");
|
||||
xil_printf("* User Peripheral Self Test\n\r");
|
||||
xil_printf("******************************\n\n\r");
|
||||
|
||||
/*
|
||||
* Write to user logic slave module register(s) and read back
|
||||
*/
|
||||
xil_printf("User logic slave module test...\n\r");
|
||||
|
||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
||||
QSFP_INTFC_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
||||
if ( QSFP_INTFC_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf(" - slave register write/read passed\n\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
proc create_ipi_design { offsetfile design_name } {
|
||||
create_bd_design $design_name
|
||||
open_bd_design $design_name
|
||||
|
||||
# Create Clock and Reset Ports
|
||||
set ACLK [ create_bd_port -dir I -type clk ACLK ]
|
||||
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
|
||||
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
|
||||
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
|
||||
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
|
||||
|
||||
# Create instance: qsfp_intfc_0, and set properties
|
||||
set qsfp_intfc_0 [ create_bd_cell -type ip -vlnv user.org:user:qsfp_intfc:1.0 qsfp_intfc_0]
|
||||
|
||||
# Create instance: master_0, and set properties
|
||||
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
|
||||
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins qsfp_intfc_0/S00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins qsfp_intfc_0/S00_AXI_ACLK]
|
||||
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins qsfp_intfc_0/S00_AXI_ARESETN]
|
||||
set_property target_simulator XSim [current_project]
|
||||
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
|
||||
|
||||
# Auto assign address
|
||||
assign_bd_address
|
||||
|
||||
# Copy all address to interface_address.vh file
|
||||
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
|
||||
upvar 1 $offsetfile offset_file
|
||||
set offset_file "${bd_path}/qsfp_intfc_v1_0_tb_include.svh"
|
||||
set fp [open $offset_file "w"]
|
||||
puts $fp "`ifndef qsfp_intfc_v1_0_tb_include_vh_"
|
||||
puts $fp "`define qsfp_intfc_v1_0_tb_include_vh_\n"
|
||||
puts $fp "//Configuration current bd names"
|
||||
puts $fp "`define BD_NAME ${design_name}"
|
||||
puts $fp "`define BD_INST_NAME ${design_name}_i"
|
||||
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
|
||||
puts $fp "//Configuration address parameters"
|
||||
|
||||
puts $fp "`endif"
|
||||
close $fp
|
||||
}
|
||||
|
||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:qsfp_intfc:1.0]]]]
|
||||
set test_bench_file ${ip_path}/example_designs/bfm_design/qsfp_intfc_v1_0_tb.sv
|
||||
set interface_address_vh_file ""
|
||||
|
||||
# Set IP Repository and Update IP Catalogue
|
||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
||||
update_ip_catalog
|
||||
}
|
||||
|
||||
set design_name ""
|
||||
set all_bd {}
|
||||
set all_bd_files [get_files *.bd -quiet]
|
||||
foreach file $all_bd_files {
|
||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
||||
lappend all_bd $bd_name
|
||||
}
|
||||
|
||||
for { set i 1 } { 1 } { incr i } {
|
||||
set design_name "qsfp_intfc_v1_0_bfm_${i}"
|
||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
create_ipi_design interface_address_vh_file ${design_name}
|
||||
validate_bd_design
|
||||
|
||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
||||
import_files -force -norecurse $wrapper_file
|
||||
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
import_files -fileset sim_1 -norecurse -force $test_bench_file
|
||||
remove_files -quiet -fileset sim_1 qsfp_intfc_v1_0_tb_include.vh
|
||||
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
|
||||
set_property top qsfp_intfc_v1_0_tb [get_filesets sim_1]
|
||||
set_property top_lib {} [get_filesets sim_1]
|
||||
set_property top_file {} [get_filesets sim_1]
|
||||
launch_simulation -simset sim_1 -mode behavioral
|
||||
@@ -0,0 +1,197 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
`include "qsfp_intfc_v1_0_tb_include.svh"
|
||||
|
||||
import axi_vip_pkg::*;
|
||||
import qsfp_intfc_v1_0_bfm_1_master_0_0_pkg::*;
|
||||
|
||||
module qsfp_intfc_v1_0_tb();
|
||||
|
||||
|
||||
xil_axi_uint error_cnt = 0;
|
||||
xil_axi_uint comparison_cnt = 0;
|
||||
axi_transaction wr_transaction;
|
||||
axi_transaction rd_transaction;
|
||||
axi_monitor_transaction mst_monitor_transaction;
|
||||
axi_monitor_transaction master_moniter_transaction_queue[$];
|
||||
xil_axi_uint master_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction mst_scb_transaction;
|
||||
axi_monitor_transaction passthrough_monitor_transaction;
|
||||
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
|
||||
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction passthrough_mst_scb_transaction;
|
||||
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
|
||||
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction passthrough_slv_scb_transaction;
|
||||
axi_monitor_transaction slv_monitor_transaction;
|
||||
axi_monitor_transaction slave_moniter_transaction_queue[$];
|
||||
xil_axi_uint slave_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction slv_scb_transaction;
|
||||
xil_axi_uint mst_agent_verbosity = 0;
|
||||
xil_axi_uint slv_agent_verbosity = 0;
|
||||
xil_axi_uint passthrough_agent_verbosity = 0;
|
||||
bit clock;
|
||||
bit reset;
|
||||
integer result_slave;
|
||||
bit [31:0] S00_AXI_test_data[3:0];
|
||||
localparam LC_AXI_BURST_LENGTH = 8;
|
||||
localparam LC_AXI_DATA_WIDTH = 32;
|
||||
task automatic COMPARE_DATA;
|
||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
|
||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
|
||||
begin
|
||||
if (expected === 'hx || actual === 'hx) begin
|
||||
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
|
||||
result_slave = 0; $stop;
|
||||
end
|
||||
if (actual != expected) begin
|
||||
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
|
||||
result_slave = 0;
|
||||
$stop;
|
||||
end
|
||||
else
|
||||
begin
|
||||
$display("TESTBENCH Passed! Data expected is equal to actual.",
|
||||
" expected = 0x%h",expected, " actual = 0x%h",actual);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
integer i;
|
||||
integer j;
|
||||
xil_axi_uint trans_cnt_before_switch = 48;
|
||||
xil_axi_uint passthrough_cmd_switch_cnt = 0;
|
||||
event passthrough_mastermode_start_event;
|
||||
event passthrough_mastermode_end_event;
|
||||
event passthrough_slavemode_end_event;
|
||||
xil_axi_uint mtestID;
|
||||
xil_axi_ulong mtestADDR;
|
||||
xil_axi_len_t mtestBurstLength;
|
||||
xil_axi_size_t mtestDataSize;
|
||||
xil_axi_burst_t mtestBurstType;
|
||||
xil_axi_lock_t mtestLOCK;
|
||||
xil_axi_cache_t mtestCacheType = 0;
|
||||
xil_axi_prot_t mtestProtectionType = 3'b000;
|
||||
xil_axi_region_t mtestRegion = 4'b000;
|
||||
xil_axi_qos_t mtestQOS = 4'b000;
|
||||
xil_axi_data_beat dbeat;
|
||||
xil_axi_data_beat [255:0] mtestWUSER;
|
||||
xil_axi_data_beat mtestAWUSER = 'h0;
|
||||
xil_axi_data_beat mtestARUSER = 0;
|
||||
xil_axi_data_beat [255:0] mtestRUSER;
|
||||
xil_axi_uint mtestBUSER = 0;
|
||||
xil_axi_resp_t mtestBresp;
|
||||
xil_axi_resp_t[255:0] mtestRresp;
|
||||
bit [63:0] mtestWDataL;
|
||||
bit [63:0] mtestRDataL;
|
||||
axi_transaction pss_wr_transaction;
|
||||
axi_transaction pss_rd_transaction;
|
||||
axi_transaction reactive_transaction;
|
||||
axi_transaction rd_payload_transaction;
|
||||
axi_transaction wr_rand;
|
||||
axi_transaction rd_rand;
|
||||
axi_transaction wr_reactive;
|
||||
axi_transaction rd_reactive;
|
||||
axi_transaction wr_reactive2;
|
||||
axi_transaction rd_reactive2;
|
||||
axi_ready_gen bready_gen;
|
||||
axi_ready_gen rready_gen;
|
||||
axi_ready_gen awready_gen;
|
||||
axi_ready_gen wready_gen;
|
||||
axi_ready_gen arready_gen;
|
||||
axi_ready_gen bready_gen2;
|
||||
axi_ready_gen rready_gen2;
|
||||
axi_ready_gen awready_gen2;
|
||||
axi_ready_gen wready_gen2;
|
||||
axi_ready_gen arready_gen2;
|
||||
xil_axi_payload_byte data_mem[xil_axi_ulong];
|
||||
qsfp_intfc_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
|
||||
|
||||
`BD_WRAPPER DUT(
|
||||
.ARESETN(reset),
|
||||
.ACLK(clock)
|
||||
);
|
||||
|
||||
initial begin
|
||||
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
|
||||
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
|
||||
mst_agent_0.set_agent_tag("Master VIP");
|
||||
mst_agent_0.set_verbosity(mst_agent_verbosity);
|
||||
mst_agent_0.start_master();
|
||||
$timeformat (-12, 1, " ps", 1);
|
||||
end
|
||||
initial begin
|
||||
reset <= 1'b0;
|
||||
#200ns;
|
||||
reset <= 1'b1;
|
||||
repeat (5) @(negedge clock);
|
||||
end
|
||||
always #5 clock <= ~clock;
|
||||
initial begin
|
||||
S_AXI_TEST ( );
|
||||
|
||||
#1ns;
|
||||
$finish;
|
||||
end
|
||||
task automatic S_AXI_TEST;
|
||||
begin
|
||||
#1;
|
||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
|
||||
mtestID = 0;
|
||||
mtestADDR = 64'h00000000;
|
||||
mtestBurstLength = 0;
|
||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
||||
mtestCacheType = 0;
|
||||
mtestProtectionType = 0;
|
||||
mtestRegion = 0;
|
||||
mtestQOS = 0;
|
||||
result_slave = 1;
|
||||
mtestWDataL[31:0] = 32'h00000001;
|
||||
for(int i = 0; i < 4;i++) begin
|
||||
S00_AXI_test_data[i] <= mtestWDataL[31:0];
|
||||
mst_agent_0.AXI4LITE_WRITE_BURST(
|
||||
mtestADDR,
|
||||
mtestProtectionType,
|
||||
mtestWDataL,
|
||||
mtestBresp
|
||||
);
|
||||
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
|
||||
mtestADDR = mtestADDR + 64'h4;
|
||||
end
|
||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
|
||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
|
||||
mtestID = 0;
|
||||
mtestADDR = 64'h00000000;
|
||||
mtestBurstLength = 0;
|
||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
||||
mtestCacheType = 0;
|
||||
mtestProtectionType = 0;
|
||||
mtestRegion = 0;
|
||||
mtestQOS = 0;
|
||||
for(int i = 0; i < 4;i++) begin
|
||||
mst_agent_0.AXI4LITE_READ_BURST(
|
||||
mtestADDR,
|
||||
mtestProtectionType,
|
||||
mtestRDataL,
|
||||
mtestRresp
|
||||
);
|
||||
mtestADDR = mtestADDR + 64'h4;
|
||||
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
|
||||
end
|
||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
|
||||
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
|
||||
$display("---------------------------------------------------------");
|
||||
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
|
||||
if ( result_slave ) begin
|
||||
$display("PTGEN_TEST: PASSED!");
|
||||
end else begin
|
||||
$display("PTGEN_TEST: FAILED!");
|
||||
end
|
||||
$display("---------------------------------------------------------");
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
|
||||
proc create_ipi_design { offsetfile design_name } {
|
||||
|
||||
create_bd_design $design_name
|
||||
open_bd_design $design_name
|
||||
|
||||
# Create and configure Clock/Reset
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
|
||||
|
||||
#Constraints will be provided manually while pin planning.
|
||||
create_bd_port -dir I -type rst reset_rtl
|
||||
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
|
||||
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
|
||||
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
|
||||
set external_reset_port reset_rtl
|
||||
create_bd_port -dir I -type clk clock_rtl
|
||||
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
|
||||
set external_clock_port clock_rtl
|
||||
|
||||
#Avoid IPI DRC, make clock port synchronous to reset
|
||||
if { $external_clock_port ne "" && $external_reset_port ne "" } {
|
||||
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
|
||||
}
|
||||
|
||||
# Connect other sys_reset pins
|
||||
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
|
||||
|
||||
# Create instance: qsfp_intfc_0, and set properties
|
||||
set qsfp_intfc_0 [ create_bd_cell -type ip -vlnv user.org:user:qsfp_intfc:1.0 qsfp_intfc_0 ]
|
||||
|
||||
# Create instance: jtag_axi_0, and set properties
|
||||
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
|
||||
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
|
||||
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
# Create instance: axi_peri_interconnect, and set properties
|
||||
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
|
||||
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
|
||||
|
||||
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
# Connect all clock & reset of qsfp_intfc_0 slave interfaces..
|
||||
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins qsfp_intfc_0/S00_AXI]
|
||||
connect_bd_net [get_bd_pins qsfp_intfc_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins qsfp_intfc_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
|
||||
# Auto assign address
|
||||
assign_bd_address
|
||||
|
||||
# Copy all address to qsfp_intfc_v1_0_include.tcl file
|
||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
||||
upvar 1 $offsetfile offset_file
|
||||
set offset_file "${bd_path}/qsfp_intfc_v1_0_include.tcl"
|
||||
set fp [open $offset_file "w"]
|
||||
puts $fp "# Configuration address parameters"
|
||||
|
||||
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_qsfp_intfc_0_S00_AXI_* ]]
|
||||
puts $fp "set s00_axi_addr ${offset}"
|
||||
|
||||
close $fp
|
||||
}
|
||||
|
||||
# Set IP Repository and Update IP Catalogue
|
||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:qsfp_intfc:1.0]]]]
|
||||
set hw_test_file ${ip_path}/example_designs/debug_hw_design/qsfp_intfc_v1_0_hw_test.tcl
|
||||
|
||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
||||
update_ip_catalog
|
||||
}
|
||||
|
||||
set design_name ""
|
||||
set all_bd {}
|
||||
set all_bd_files [get_files *.bd -quiet]
|
||||
foreach file $all_bd_files {
|
||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
||||
lappend all_bd $bd_name
|
||||
}
|
||||
|
||||
for { set i 1 } { 1 } { incr i } {
|
||||
set design_name "qsfp_intfc_v1_0_hw_${i}"
|
||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
set intf_address_include_file ""
|
||||
create_ipi_design intf_address_include_file ${design_name}
|
||||
save_bd_design
|
||||
validate_bd_design
|
||||
|
||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
||||
import_files -force -norecurse $wrapper_file
|
||||
|
||||
puts "-------------------------------------------------------------------------------------------------"
|
||||
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
|
||||
puts " please perform following steps to test design in targeted board."
|
||||
puts "1. Generate bitstream"
|
||||
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
|
||||
puts "3. Download generated bitstream"
|
||||
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
|
||||
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
|
||||
puts " : source -notrace ${hw_test_file}"
|
||||
puts "-------------------------------------------------------------------------------------------------"
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
# Runtime Tcl commands to interact with - qsfp_intfc_v1_0
|
||||
|
||||
# Sourcing design address info tcl
|
||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
||||
source ${bd_path}/qsfp_intfc_v1_0_include.tcl
|
||||
|
||||
# jtag axi master interface hardware name, change as per your design.
|
||||
set jtag_axi_master hw_axi_1
|
||||
set ec 0
|
||||
|
||||
# hw test script
|
||||
# Delete all previous axis transactions
|
||||
if { [llength [get_hw_axi_txns -quiet]] } {
|
||||
delete_hw_axi_txn [get_hw_axi_txns -quiet]
|
||||
}
|
||||
|
||||
|
||||
# Test all lite slaves.
|
||||
set wdata_1 abcd1234
|
||||
|
||||
# Test: S00_AXI
|
||||
# Create a write transaction at s00_axi_addr address
|
||||
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
|
||||
# Create a read transaction at s00_axi_addr address
|
||||
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
|
||||
# Initiate transactions
|
||||
run_hw_axi r_s00_axi_addr
|
||||
run_hw_axi w_s00_axi_addr
|
||||
run_hw_axi r_s00_axi_addr
|
||||
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
|
||||
# Compare read data
|
||||
if { $rdata_tmp == $wdata_1 } {
|
||||
puts "Data comparison test pass for - S00_AXI"
|
||||
} else {
|
||||
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
|
||||
inc ec
|
||||
}
|
||||
|
||||
# Check error flag
|
||||
if { $ec == 0 } {
|
||||
puts "PTGEN_TEST: PASSED!"
|
||||
} else {
|
||||
puts "PTGEN_TEST: FAILED!"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,240 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity qsfp_init_fsm is
|
||||
port(
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_aresetn_in : in std_logic;
|
||||
|
||||
mode_50g_40g_n_in : in std_logic;
|
||||
qsfp1_reset_n_in : in std_logic;
|
||||
qsfp4_reset_n_in : in std_logic;
|
||||
|
||||
cmd_strb_out : out std_logic;
|
||||
cmd_addr_out : out std_logic_vector(11 downto 0);
|
||||
cmd_write_out : out std_logic;
|
||||
cmd_sel_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_wdata_out : out std_logic_vector(31 downto 0);
|
||||
cmd_ready_in : in std_logic;
|
||||
fsm_running_out : out std_logic
|
||||
);
|
||||
end entity qsfp_init_fsm;
|
||||
|
||||
architecture imp of qsfp_init_fsm is
|
||||
|
||||
type fsm_state is (IDLE, QSFP1_INIT_WAIT, QSFP1_INIT, QSFP4_INIT_WAIT, QSFP4_INIT, DONE, ERROR);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
signal qsfp1_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp4_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp1_reset_r : std_logic := '0';
|
||||
|
||||
signal qsfp4_reset_r : std_logic := '0';
|
||||
|
||||
signal cmd_addr_r : std_logic_vector (11 downto 0) := (others => '0');
|
||||
signal cmd_sel_r : std_logic_vector ( 2 downto 0) := (others => '0');
|
||||
signal cmd_strb_r : std_logic := '0';
|
||||
signal cmd_wdata_r : std_logic_vector (31 downto 0) := (others => '0');
|
||||
signal cmd_write_r : std_logic := '0';
|
||||
|
||||
signal fsm_running_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
cmd_strb_out <= cmd_strb_r;
|
||||
cmd_addr_out <= cmd_addr_r;
|
||||
cmd_write_out <= cmd_write_r;
|
||||
cmd_sel_out <= cmd_sel_r;
|
||||
cmd_wdata_out <= cmd_wdata_r;
|
||||
fsm_running_out <= fsm_running_r;
|
||||
|
||||
--
|
||||
qsfp1_reset_n(0) <= qsfp1_reset_n_in;
|
||||
|
||||
i_cdc_qsfp1_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp1_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp1_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp1_reset_n_r <= qsfp1_reset_n_r(1 to 31) & qsfp1_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
qsfp4_reset_n(0) <= qsfp4_reset_n_in;
|
||||
|
||||
i_cdc_qsfp4_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp4_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp4_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp4_reset_n_r <= qsfp4_reset_n_r(1 to 31) & qsfp4_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (clk_125_aresetn_in = '0') then
|
||||
qsfp1_reset_r <= '0';
|
||||
qsfp4_reset_r <= '0';
|
||||
|
||||
cmd_sel_r <= (others => '0');
|
||||
cmd_addr_r <= (others => '0');
|
||||
cmd_wdata_r <= (others => '0');
|
||||
cmd_write_r <= '0';
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
state_cnt_r <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(clk_125_in)) then
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
if (qsfp1_reset_n_r(1) = '1' and qsfp1_reset_n_r(0) = '0') then
|
||||
qsfp1_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
if (qsfp4_reset_n_r(1) = '1' and qsfp4_reset_n_r(0) = '0') then
|
||||
qsfp4_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (qsfp1_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "000";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
elsif (qsfp4_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "001";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
else
|
||||
fsm_running_r <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP1_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP4_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when ERROR =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,933 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
--use ieee.numeric_std.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
entity qsfp_intfc_v1_0 is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0603_2024";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_reset_n_in : in std_logic;
|
||||
|
||||
clk_250_in : in std_logic;
|
||||
clk_250_reset_n_in : in std_logic;
|
||||
|
||||
rx_device_clk_in : in std_logic;
|
||||
tx_device_clk_in : in std_logic;
|
||||
|
||||
clkin8_in : in std_logic;
|
||||
-- sysref_in : in std_logic;
|
||||
ref_clk_div2_in : in std_logic;
|
||||
qsfp2_clk_in : in std_logic;
|
||||
qsfp3_clk_in : in std_logic;
|
||||
pl_clk3_0 : in std_logic;
|
||||
|
||||
QSFP1_SI570_CLOCK_P : in std_logic;
|
||||
QSFP1_SI570_CLOCK_N : in std_logic;
|
||||
QSFP1_TX1_P : out std_logic;
|
||||
QSFP1_TX1_N : out std_logic;
|
||||
QSFP1_RX1_P : in std_logic;
|
||||
QSFP1_RX1_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX2_P : out std_logic;
|
||||
QSFP1_TX2_N : out std_logic;
|
||||
QSFP1_RX2_P : in std_logic;
|
||||
QSFP1_RX2_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX3_P : out std_logic;
|
||||
QSFP1_TX3_N : out std_logic;
|
||||
QSFP1_RX3_P : in std_logic;
|
||||
QSFP1_RX3_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX4_P : out std_logic;
|
||||
QSFP1_TX4_N : out std_logic;
|
||||
QSFP1_RX4_P : in std_logic;
|
||||
QSFP1_RX4_N : in std_logic;
|
||||
|
||||
QSFP1_RESETL_LS : out std_logic;
|
||||
QSFP1_MODPRSL_LS : in std_logic;
|
||||
QSFP1_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP4_SI570_CLOCK_P : in std_logic;
|
||||
QSFP4_SI570_CLOCK_N : in std_logic;
|
||||
QSFP4_TX1_P : out std_logic;
|
||||
QSFP4_TX1_N : out std_logic;
|
||||
QSFP4_RX1_P : in std_logic;
|
||||
QSFP4_RX1_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX2_P : out std_logic;
|
||||
QSFP4_TX2_N : out std_logic;
|
||||
QSFP4_RX2_P : in std_logic;
|
||||
QSFP4_RX2_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX3_P : out std_logic;
|
||||
QSFP4_TX3_N : out std_logic;
|
||||
QSFP4_RX3_P : in std_logic;
|
||||
QSFP4_RX3_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX4_P : out std_logic;
|
||||
QSFP4_TX4_N : out std_logic;
|
||||
QSFP4_RX4_P : in std_logic;
|
||||
QSFP4_RX4_N : in std_logic;
|
||||
|
||||
QSFP4_RESETL_LS : out std_logic;
|
||||
QSFP4_MODPRSL_LS : in std_logic;
|
||||
QSFP4_INTL_LS : in std_logic;
|
||||
|
||||
qsfp1_capture_aclk_out : out std_logic;
|
||||
qsfp1_capture_aresetn_out : out std_logic;
|
||||
qsfp1_capture_tdata_240b_out : out std_logic_vector(239 downto 0);
|
||||
qsfp1_capture_tvalid_240b_out : out std_logic;
|
||||
qsfp1_capture_rx_data_ready_in : in std_logic;
|
||||
|
||||
qsfp4_playback_aclk_out : out std_logic;
|
||||
qsfp4_playback_aresetn_out : out std_logic;
|
||||
qsfp4_playback_tdata_240b_in : in std_logic_vector(239 downto 0);
|
||||
qsfp4_playback_tvalid_240b_in : in std_logic;
|
||||
qsfp4_playback_tready_240b_out : out std_logic;
|
||||
|
||||
qsfp1_capture_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_overflow_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_fifo_aempty_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0);
|
||||
tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
adc_rx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp4_playback_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cnt_reset_out : out std_logic;
|
||||
|
||||
slv_reg9_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg21_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg22_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg23_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg24_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg25_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg26_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg27_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg28_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg29_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg30_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg31_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg32_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg33_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg34_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg35_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg36_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg37_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg38_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg39_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg40_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg41_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg42_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg43_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg44_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg45_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg46_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg47_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg48_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg49_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg50_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg51_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg52_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Ports of Axi Slave Bus Interface S00_AXI
|
||||
sys_cpu_clk_in : in std_logic;
|
||||
s00_axi_aresetn : in std_logic;
|
||||
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_awprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_awvalid : in std_logic;
|
||||
s00_axi_awready : out std_logic;
|
||||
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
s00_axi_wvalid : in std_logic;
|
||||
s00_axi_wready : out std_logic;
|
||||
s00_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_bvalid : out std_logic;
|
||||
s00_axi_bready : in std_logic;
|
||||
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_arprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_arvalid : in std_logic;
|
||||
s00_axi_arready : out std_logic;
|
||||
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_rresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_rvalid : out std_logic;
|
||||
s00_axi_rready : in std_logic
|
||||
);
|
||||
end qsfp_intfc_v1_0;
|
||||
|
||||
architecture arch_imp of qsfp_intfc_v1_0 is
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal dig_iq_cmd_addr_i : std_logic_vector (11 downto 0);
|
||||
signal dig_iq_cmd_sel_i : std_logic_vector ( 2 downto 0);
|
||||
signal dig_iq_cmd_strb_i : std_logic;
|
||||
signal dig_iq_cmd_wdata_i : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_write_i : std_logic;
|
||||
|
||||
signal dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal dig_iq_cmd_rdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_ready : std_logic;
|
||||
signal dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal dig_iq_cmd_strb : std_logic;
|
||||
signal dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_write : std_logic;
|
||||
signal dig_iq_interface_ready : std_logic_vector ( 1 downto 0);
|
||||
signal dig_iq_interface_reset : std_logic_vector ( 1 downto 0);
|
||||
|
||||
signal vio_dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal vio_dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal vio_dig_iq_cmd_strb : std_logic;
|
||||
signal vio_dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal vio_dig_iq_cmd_write : std_logic;
|
||||
signal vio_enable : std_logic;
|
||||
|
||||
--
|
||||
signal qsfp1_axis_aclk : std_logic;
|
||||
signal qsfp1_axis_aresetn : std_logic;
|
||||
|
||||
signal qsfp1_rx_rxn : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_rx_rxp : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_tx_txn : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_tx_txp : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_reset_n : std_logic;
|
||||
signal vio_qsfp1_reset_n : std_logic;
|
||||
signal qsfp1_reset_n_i : std_logic;
|
||||
signal qsfp1_modprsl : std_logic;
|
||||
signal qsfp1_intl : std_logic;
|
||||
|
||||
signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0);
|
||||
signal qsfp1_m_axis_tvalid : std_logic;
|
||||
|
||||
signal qsfp1_axis_aresetn_i : std_logic;
|
||||
signal vio_qsfp1_axis_aresetn : std_logic;
|
||||
--
|
||||
signal qsfp4_axis_aclk : std_logic;
|
||||
signal qsfp4_axis_aresetn : std_logic;
|
||||
|
||||
signal qsfp4_rx_rxn : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_rx_rxp : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_tx_txn : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_tx_txp : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_reset_n : std_logic;
|
||||
signal vio_qsfp4_reset_n : std_logic;
|
||||
signal qsfp4_reset_n_i : std_logic;
|
||||
signal qsfp4_modprsl : std_logic;
|
||||
signal qsfp4_intl : std_logic;
|
||||
|
||||
signal qsfp4_s_axis_tready : std_logic;
|
||||
|
||||
signal qsfp4_axis_aresetn_i : std_logic;
|
||||
signal vio_qsfp4_axis_aresetn : std_logic;
|
||||
|
||||
--
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp1_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp1_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp1_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp4_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp4_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp4_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal rx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal rx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal rx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal tx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal tx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clkin8_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clkin8_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clkin8_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal sys_cpu_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal sys_cpu_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal sys_cpu_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal ref_clk_div2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal ref_clk_div2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal ref_clk_div2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp2_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg3 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg4 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg5 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg6 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg7 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg8 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal vio_cnt_reset : std_logic;
|
||||
signal cnt_rst : std_logic;
|
||||
|
||||
signal fsm_dig_iq_cmd_strb : std_logic;
|
||||
signal fsm_dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal fsm_dig_iq_cmd_write : std_logic;
|
||||
signal fsm_dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal fsm_dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_mode_50g_40g_n : std_logic;
|
||||
signal dig_iq_mode_50g_40g_n_i : std_logic;
|
||||
signal vio_dig_iq_mode_50g_40g_n : std_logic;
|
||||
|
||||
signal fsm_running : std_logic;
|
||||
|
||||
signal clk_50 : std_logic;
|
||||
signal clk_50_reset : std_logic_vector(0 to 15) := (others => '1');
|
||||
|
||||
signal pl_clk3_0_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal pl_clk3_0_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pl_clk3_0_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
cnt_reset_out <= vio_cnt_reset when vio_enable = '1' else cnt_rst;
|
||||
|
||||
i_bufgce_div : BUFGCE_DIV
|
||||
generic map (
|
||||
BUFGCE_DIVIDE => 2, -- 1-8
|
||||
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
IS_CE_INVERTED => '0', -- Optional inversion for CE
|
||||
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
|
||||
IS_I_INVERTED => '0', -- Optional inversion for I
|
||||
SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS
|
||||
)
|
||||
port map (
|
||||
O => clk_50, -- 1-bit output: Buffer
|
||||
CE => '1', -- 1-bit input: Buffer enable
|
||||
CLR => '0', -- 1-bit input: Asynchronous clear
|
||||
I => sys_cpu_clk_in -- 1-bit input: Buffer
|
||||
);
|
||||
|
||||
process(clk_50)
|
||||
begin
|
||||
if (rising_edge(clk_50)) then
|
||||
clk_50_reset <= clk_50_reset(1 to 15) & '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
|
||||
slv_reg0_in => slv_reg0, -- 0x44a0_0000
|
||||
slv_reg1_in => slv_reg1, -- 0x44a0_0004
|
||||
slv_reg2_in => slv_reg2, -- 0x44a0_0008
|
||||
slv_reg3_out => slv_reg3, -- 0x44a0_000C
|
||||
slv_reg4_out => slv_reg4, -- 0x44a0_0010
|
||||
slv_reg5_out => slv_reg5, -- 0x44a0_0014
|
||||
slv_reg6_out => slv_reg6, -- 0x44a0_0018
|
||||
slv_reg7_out => slv_reg7, -- 0x44a0_001C
|
||||
slv_reg8_out => slv_reg8, -- 0x44a0_0020
|
||||
|
||||
slv_reg9_out => slv_reg9_out, -- 0x44a0_0024
|
||||
slv_reg10_out => slv_reg10_out, -- 0x44a0_0028
|
||||
|
||||
slv_reg11_in => qsfp1_s_axis_aclk_freq_r, -- 0x44a0_002C
|
||||
slv_reg12_in => qsfp1_s_axis_aclk_cnt_r, -- 0x44a0_0030
|
||||
slv_reg13_in => qsfp4_s_axis_aclk_freq_r, -- 0x44a0_0034
|
||||
slv_reg14_in => qsfp4_s_axis_aclk_cnt_r, -- 0x44a0_0038
|
||||
slv_reg15_in => rx_device_clk_freq_r, -- 0x44a0_003C
|
||||
slv_reg16_in => tx_device_clk_freq_r, -- 0x44a0_0040
|
||||
slv_reg17_in => clk_125_freq_r, -- 0x44a0_0044
|
||||
slv_reg18_in => clk_125_cnt_r, -- 0x44a0_0048
|
||||
slv_reg19_in => clk_250_freq_r, -- 0x44a0_004C
|
||||
slv_reg20_in => clk_250_cnt_r, -- 0x44a0_0050
|
||||
|
||||
slv_reg21_out => slv_reg21_out, -- 0x44a0_0054
|
||||
slv_reg22_out => slv_reg22_out, -- 0x44a0_0058
|
||||
slv_reg23_out => slv_reg23_out, -- 0x44a0_005C *
|
||||
slv_reg24_out => slv_reg24_out, -- 0x44a0_0060
|
||||
slv_reg25_out => slv_reg25_out, -- 0x44a0_0064 *
|
||||
slv_reg26_out => slv_reg26_out, -- 0x44a0_0068 *
|
||||
slv_reg27_out => slv_reg27_out, -- 0x44a0_006C
|
||||
slv_reg28_out => slv_reg28_out, -- 0x44a0_0070
|
||||
|
||||
slv_reg29_out => slv_reg29_out, -- 0x44a0_0074
|
||||
slv_reg30_out => slv_reg30_out, -- 0x44a0_0078
|
||||
slv_reg31_out => slv_reg31_out, -- 0x44a0_007C *
|
||||
slv_reg32_out => slv_reg32_out, -- 0x44a0_0080
|
||||
slv_reg33_out => slv_reg33_out, -- 0x44a0_0084 *
|
||||
slv_reg34_out => slv_reg34_out, -- 0x44a0_0088 *
|
||||
slv_reg35_out => slv_reg35_out, -- 0x44a0_008C
|
||||
slv_reg36_out => slv_reg36_out, -- 0x44a0_0090
|
||||
|
||||
slv_reg37_out => slv_reg37_out, -- 0x44a0_0094
|
||||
slv_reg38_out => slv_reg38_out, -- 0x44a0_0098
|
||||
slv_reg39_out => slv_reg39_out, -- 0x44a0_009C *
|
||||
slv_reg40_out => slv_reg40_out, -- 0x44a0_00A0
|
||||
slv_reg41_out => slv_reg41_out, -- 0x44a0_00A4 *
|
||||
slv_reg42_out => slv_reg42_out, -- 0x44a0_00A8 *
|
||||
slv_reg43_out => slv_reg43_out, -- 0x44a0_00AC
|
||||
slv_reg44_out => slv_reg44_out, -- 0x44a0_00B0
|
||||
|
||||
slv_reg45_out => slv_reg45_out, -- 0x44a0_00B4
|
||||
slv_reg46_out => slv_reg46_out, -- 0x44a0_00B8
|
||||
slv_reg47_out => slv_reg47_out, -- 0x44a0_00BC *
|
||||
slv_reg48_out => slv_reg48_out, -- 0x44a0_00C0
|
||||
slv_reg49_out => slv_reg49_out, -- 0x44a0_00C4 *
|
||||
slv_reg50_out => slv_reg50_out, -- 0x44a0_00C8 *
|
||||
slv_reg51_out => slv_reg51_out, -- 0x44a0_00CC
|
||||
slv_reg52_out => slv_reg52_out, -- 0x44a0_00D0
|
||||
|
||||
slv_reg53_in => qsfp4_playback_tvalid_240b_cnt_in, -- 0x44a0_00D4
|
||||
slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x44a0_00D8
|
||||
|
||||
slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x44a0_00DC
|
||||
slv_reg56_in => tx_tvalid_128b_cnt_in, -- 0x44a0_00E0
|
||||
slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x44a0_00E4
|
||||
slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x44a0_00E8
|
||||
slv_reg59_in => (others => '0'), -- 0x44a0_00EC
|
||||
slv_reg60_in => dac_tx_tvalid_128b_cnt_in, -- 0x44a0_00F0
|
||||
slv_reg61_in => qsfp1_capture_tvalid_240b_cnt_in, -- 0x44a0_00F4
|
||||
slv_reg62_in => qsfp1_capture_fifo_aempty_512b_cnt_in, -- 0x44a0_00F8
|
||||
slv_reg63_in => qsfp1_capture_rx_data_ready_cnt_in, -- 0x44a0_00FC
|
||||
|
||||
S_AXI_ACLK => sys_cpu_clk_in,
|
||||
S_AXI_ARESETN => s00_axi_aresetn,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
--
|
||||
slv_reg0 <= fpga_revision_date_r; -- 0x44a0_0000
|
||||
--
|
||||
slv_reg1(31 downto 24) <= minor_rev_r; -- 0x44a0_0004
|
||||
slv_reg1(23 downto 9) <= (others => '0');
|
||||
slv_reg1(8) <= dig_iq_cmd_ready;
|
||||
slv_reg1( 7 downto 2) <= (others => '0');
|
||||
slv_reg1( 1 downto 0) <= dig_iq_interface_ready;
|
||||
--
|
||||
slv_reg2 <= dig_iq_cmd_rdata; -- 0x44a0_0008
|
||||
--
|
||||
dig_iq_cmd_addr_i <= slv_reg3(11 downto 0); -- 0x44a0_000C
|
||||
dig_iq_cmd_sel_i <= slv_reg4( 2 downto 0); -- 0x44a0_0010
|
||||
--
|
||||
dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x44a0_0014
|
||||
qsfp1_reset_n_i <= slv_reg5(16);
|
||||
qsfp4_reset_n_i <= slv_reg5(24);
|
||||
--
|
||||
dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x44a0_0018
|
||||
--
|
||||
dig_iq_cmd_write_i <= slv_reg7(0); -- 0x44a0_001C
|
||||
--
|
||||
dig_iq_mode_50g_40g_n_i <= slv_reg8(0); -- 0x44a0_0020
|
||||
-- <= slv_reg8(24);
|
||||
-- <= slv_reg8(28);
|
||||
cnt_rst <= slv_reg8(31);
|
||||
|
||||
-- Add user logic here
|
||||
QSFP1_TX1_P <= qsfp1_tx_txp(0);
|
||||
QSFP1_TX1_N <= qsfp1_tx_txn(0);
|
||||
qsfp1_rx_rxp(0) <= QSFP1_RX1_P;
|
||||
qsfp1_rx_rxn(0) <= QSFP1_RX1_N;
|
||||
|
||||
QSFP1_TX2_P <= qsfp1_tx_txp(1);
|
||||
QSFP1_TX2_N <= qsfp1_tx_txn(1);
|
||||
qsfp1_rx_rxp(1) <= QSFP1_RX2_P;
|
||||
qsfp1_rx_rxn(1) <= QSFP1_RX2_N;
|
||||
|
||||
QSFP1_TX3_P <= qsfp1_tx_txp(2);
|
||||
QSFP1_TX3_N <= qsfp1_tx_txn(2);
|
||||
qsfp1_rx_rxp(2) <= QSFP1_RX3_P;
|
||||
qsfp1_rx_rxn(2) <= QSFP1_RX3_N;
|
||||
|
||||
QSFP1_TX4_P <= qsfp1_tx_txp(3);
|
||||
QSFP1_TX4_N <= qsfp1_tx_txn(3);
|
||||
qsfp1_rx_rxp(3) <= QSFP1_RX4_P;
|
||||
qsfp1_rx_rxn(3) <= QSFP1_RX4_N;
|
||||
|
||||
QSFP1_RESETL_LS <= qsfp1_reset_n;
|
||||
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
|
||||
qsfp1_intl <= QSFP1_INTL_LS;
|
||||
-------
|
||||
QSFP4_TX1_P <= qsfp4_tx_txp(0);
|
||||
QSFP4_TX1_N <= qsfp4_tx_txn(0);
|
||||
qsfp4_rx_rxp(0) <= QSFP4_RX1_P;
|
||||
qsfp4_rx_rxn(0) <= QSFP4_RX1_N;
|
||||
|
||||
QSFP4_TX2_P <= qsfp4_tx_txp(1);
|
||||
QSFP4_TX2_N <= qsfp4_tx_txn(1);
|
||||
qsfp4_rx_rxp(1) <= QSFP4_RX2_P;
|
||||
qsfp4_rx_rxn(1) <= QSFP4_RX2_N;
|
||||
|
||||
QSFP4_TX3_P <= qsfp4_tx_txp(2);
|
||||
QSFP4_TX3_N <= qsfp4_tx_txn(2);
|
||||
qsfp4_rx_rxp(2) <= QSFP4_RX3_P;
|
||||
qsfp4_rx_rxn(2) <= QSFP4_RX3_N;
|
||||
|
||||
QSFP4_TX4_P <= qsfp4_tx_txp(3);
|
||||
QSFP4_TX4_N <= qsfp4_tx_txn(3);
|
||||
qsfp4_rx_rxp(3) <= QSFP4_RX4_P;
|
||||
qsfp4_rx_rxn(3) <= QSFP4_RX4_N;
|
||||
|
||||
QSFP4_RESETL_LS <= qsfp4_reset_n;
|
||||
qsfp4_modprsl <= QSFP4_MODPRSL_LS;
|
||||
qsfp4_intl <= QSFP4_INTL_LS;
|
||||
|
||||
i_vio_2 : entity work.vio_2_1
|
||||
port map (
|
||||
clk => clk_50,
|
||||
probe_in0(0) => dig_iq_cmd_ready, -- 1
|
||||
probe_in1 => dig_iq_cmd_rdata, -- 32
|
||||
probe_in2 => dig_iq_interface_ready, -- 2
|
||||
|
||||
probe_in3(0) => qsfp1_modprsl, -- 1
|
||||
probe_in4(0) => qsfp1_intl, -- 1
|
||||
probe_in5(0) => qsfp4_modprsl, -- 1
|
||||
probe_in6(0) => qsfp4_intl, -- 1
|
||||
probe_in7 => qsfp1_capture_tvalid_240b_cnt_in, -- 32
|
||||
probe_in8 => qsfp1_capture_rx_data_ready_cnt_in, -- 32
|
||||
probe_in9 => qsfp1_capture_fifo_aempty_512b_cnt_in, -- 32
|
||||
|
||||
probe_in10 => tx_tvalid_128b_cnt_in, -- 32
|
||||
probe_in11 => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 32
|
||||
probe_in12 => dac_tx_tvalid_128b_cnt_in, -- 32
|
||||
probe_in13 => qsfp1_capture_rx_data_ready_in, -- 1
|
||||
|
||||
probe_in14 => qsfp1_capture_overflow_240b_cnt_in, -- 32
|
||||
probe_in15 => qsfp4_playback_tvalid_128b_cnt_in, -- 32
|
||||
probe_in16 => qsfp4_playback_tvalid_240b_cnt_in, -- 32
|
||||
probe_in17 => adc_rx_tvalid_128b_cnt_in, -- 32
|
||||
|
||||
probe_out0(0) => vio_dig_iq_cmd_strb, -- 1
|
||||
probe_out1 => vio_dig_iq_cmd_addr, -- 12
|
||||
probe_out2(0) => vio_dig_iq_cmd_write, -- 1
|
||||
probe_out3 => vio_dig_iq_cmd_sel, -- 3
|
||||
probe_out4 => vio_dig_iq_cmd_wdata, -- 32
|
||||
probe_out5 => vio_dig_iq_mode_50g_40g_n, -- 1
|
||||
probe_out6(0) => vio_enable, -- 1
|
||||
|
||||
probe_out7(0) => vio_qsfp1_reset_n, -- 1
|
||||
probe_out8(0) => vio_qsfp4_reset_n, -- 1
|
||||
probe_out9(0) => vio_qsfp1_axis_aresetn, -- 1
|
||||
probe_out10(0) => vio_qsfp4_axis_aresetn, -- 1
|
||||
probe_out11(0) => vio_cnt_reset -- 1
|
||||
);
|
||||
|
||||
dig_iq_cmd_strb <= fsm_dig_iq_cmd_strb when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_strb when vio_enable = '1' else dig_iq_cmd_strb_i;
|
||||
dig_iq_cmd_addr <= fsm_dig_iq_cmd_addr when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_addr when vio_enable = '1' else dig_iq_cmd_addr_i;
|
||||
dig_iq_cmd_write <= fsm_dig_iq_cmd_write when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_write when vio_enable = '1' else dig_iq_cmd_write_i;
|
||||
dig_iq_cmd_sel <= fsm_dig_iq_cmd_sel when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_sel when vio_enable = '1' else dig_iq_cmd_sel_i;
|
||||
dig_iq_cmd_wdata <= fsm_dig_iq_cmd_wdata when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_wdata when vio_enable = '1' else dig_iq_cmd_wdata_i;
|
||||
dig_iq_mode_50g_40g_n <= vio_dig_iq_mode_50g_40g_n when vio_enable = '1' else dig_iq_mode_50g_40g_n_i;
|
||||
|
||||
qsfp1_reset_n <= vio_qsfp1_reset_n when vio_enable = '1' else qsfp1_reset_n_i;
|
||||
dig_iq_interface_reset(0) <= not qsfp1_reset_n;
|
||||
qsfp4_reset_n <= vio_qsfp4_reset_n when vio_enable = '1' else qsfp4_reset_n_i;
|
||||
dig_iq_interface_reset(1) <= not qsfp4_reset_n;
|
||||
|
||||
i_qsfp_int_fsm : entity work.qsfp_init_fsm
|
||||
port map (
|
||||
clk_125_in => clk_125_in,
|
||||
clk_125_aresetn_in => clk_125_reset_n_in,
|
||||
|
||||
mode_50g_40g_n_in => dig_iq_mode_50g_40g_n,
|
||||
qsfp1_reset_n_in => qsfp1_reset_n,
|
||||
qsfp4_reset_n_in => qsfp4_reset_n,
|
||||
|
||||
cmd_strb_out => fsm_dig_iq_cmd_strb,
|
||||
cmd_addr_out => fsm_dig_iq_cmd_addr,
|
||||
cmd_write_out => fsm_dig_iq_cmd_write,
|
||||
cmd_sel_out => fsm_dig_iq_cmd_sel,
|
||||
cmd_wdata_out => fsm_dig_iq_cmd_wdata,
|
||||
cmd_ready_in => dig_iq_cmd_ready,
|
||||
fsm_running_out => fsm_running
|
||||
);
|
||||
|
||||
------------------------------------------------------
|
||||
i_dig_iq_x2 : entity work.dig_iq_x2
|
||||
port map(
|
||||
--
|
||||
clk_125_resetn_in => clk_125_reset_n_in,
|
||||
clk_125_in => clk_125_in,
|
||||
--
|
||||
aclk_in => clk_250_in,
|
||||
aresetn_in => clk_250_reset_n_in,
|
||||
cmd_strb_in => dig_iq_cmd_strb,
|
||||
cmd_addr_in => dig_iq_cmd_addr,
|
||||
cmd_write_in => dig_iq_cmd_write,
|
||||
cmd_sel_in => dig_iq_cmd_sel,
|
||||
cmd_wdata_in => dig_iq_cmd_wdata,
|
||||
cmd_ready_out => dig_iq_cmd_ready,
|
||||
cmd_rdata_out => dig_iq_cmd_rdata,
|
||||
dig_iq_interface_reset_in => dig_iq_interface_reset,
|
||||
--
|
||||
dig_iq_interface_ready_out => dig_iq_interface_ready,
|
||||
--
|
||||
rx_data_ready_in => qsfp1_capture_rx_data_ready_in,
|
||||
|
||||
axis_0_aclk_out => qsfp1_axis_aclk,
|
||||
axis_0_aresetn_out => qsfp1_axis_aresetn,
|
||||
m0_axis_tdata_out => qsfp1_m_axis_tdata,
|
||||
m0_axis_tvalid_out => qsfp1_m_axis_tvalid,
|
||||
s0_axis_tdata_in => (others =>'0'),
|
||||
s0_axis_tvalid_in => '0',
|
||||
s0_axis_tready_out => open,
|
||||
--
|
||||
axis_1_aclk_out => qsfp4_axis_aclk,
|
||||
axis_1_aresetn_out => qsfp4_axis_aresetn,
|
||||
m1_axis_tdata_out => open,
|
||||
m1_axis_tvalid_out => open,
|
||||
s1_axis_tdata_in => qsfp4_playback_tdata_240b_in,
|
||||
s1_axis_tvalid_in => qsfp4_playback_tvalid_240b_in,
|
||||
s1_axis_tready_out => qsfp4_s_axis_tready,
|
||||
|
||||
tx_data_channel_reset_in => '0',
|
||||
tx_data_clear_in => '0',
|
||||
|
||||
--
|
||||
qsfp0_ref_clk_p_in => QSFP1_SI570_CLOCK_P,
|
||||
qsfp0_ref_clk_n_in => QSFP1_SI570_CLOCK_N,
|
||||
qsfp0_rx_rxp_in => qsfp1_rx_rxp,
|
||||
qsfp0_rx_rxn_in => qsfp1_rx_rxn,
|
||||
qsfp0_tx_txp_out => qsfp1_tx_txp,
|
||||
qsfp0_tx_txn_out => qsfp1_tx_txn,
|
||||
--
|
||||
qsfp1_ref_clk_p_in => QSFP4_SI570_CLOCK_P,
|
||||
qsfp1_ref_clk_n_in => QSFP4_SI570_CLOCK_N,
|
||||
qsfp1_rx_rxp_in => qsfp4_rx_rxp,
|
||||
qsfp1_rx_rxn_in => qsfp4_rx_rxn,
|
||||
qsfp1_tx_txp_out => qsfp4_tx_txp,
|
||||
qsfp1_tx_txn_out => qsfp4_tx_txn
|
||||
);
|
||||
|
||||
qsfp1_axis_aresetn_i <= qsfp1_axis_aresetn and vio_qsfp1_axis_aresetn;
|
||||
qsfp1_capture_aclk_out <= qsfp1_axis_aclk;
|
||||
qsfp1_capture_aresetn_out <= qsfp1_axis_aresetn_i;
|
||||
qsfp1_capture_tdata_240b_out <= qsfp1_m_axis_tdata;
|
||||
qsfp1_capture_tvalid_240b_out <= qsfp1_m_axis_tvalid;
|
||||
|
||||
-- i_ila_3_qsfp1 : entity work.ila_3
|
||||
-- port map (
|
||||
-- clk => qsfp1_axis_aclk,
|
||||
-- probe0(0) => qsfp1_m_axis_tvalid, --1
|
||||
-- probe1(0) => '0', --1
|
||||
-- probe2 => qsfp1_m_axis_tdata(31 downto 0), --32
|
||||
-- probe3 => qsfp1_m_axis_tdata(63 downto 32), --32
|
||||
-- probe4 => qsfp1_m_axis_tdata(95 downto 64), --32
|
||||
-- probe5 => qsfp1_m_axis_tdata(127 downto 96), --32
|
||||
-- probe6 => qsfp1_m_axis_tdata(159 downto 128), --32
|
||||
-- probe7 => qsfp1_m_axis_tdata(191 downto 160), --32
|
||||
-- probe8 => qsfp1_m_axis_tdata(223 downto 192), --32
|
||||
-- probe9 => qsfp1_m_axis_tdata(239 downto 224) --16
|
||||
-- );
|
||||
|
||||
--------------------------------------------------------------------------------------------
|
||||
qsfp4_axis_aresetn_i <= qsfp4_axis_aresetn and vio_qsfp4_axis_aresetn;
|
||||
qsfp4_playback_aclk_out <= qsfp4_axis_aclk;
|
||||
qsfp4_playback_tready_240b_out <= qsfp4_s_axis_tready;
|
||||
qsfp4_playback_aresetn_out <= qsfp4_axis_aresetn_i;
|
||||
|
||||
-- i_ila_3_qsfp4 : entity work.ila_3
|
||||
-- port map (
|
||||
-- clk => qsfp4_axis_aclk,
|
||||
-- probe0(0) => qsfp4_playback_tvalid_240b_in, --1
|
||||
-- probe1(0) => qsfp4_s_axis_tready, --1
|
||||
-- probe2 => qsfp4_playback_tdata_240b_in(31 downto 0), --32
|
||||
-- probe3 => qsfp4_playback_tdata_240b_in(63 downto 32), --32
|
||||
-- probe4 => qsfp4_playback_tdata_240b_in(95 downto 64), --32
|
||||
-- probe5 => qsfp4_playback_tdata_240b_in(127 downto 96), --32
|
||||
-- probe6 => qsfp4_playback_tdata_240b_in(159 downto 128), --32
|
||||
-- probe7 => qsfp4_playback_tdata_240b_in(191 downto 160), --32
|
||||
-- probe8 => qsfp4_playback_tdata_240b_in(223 downto 192), --32
|
||||
-- probe9 => qsfp4_playback_tdata_240b_in(239 downto 224) --16
|
||||
-- );
|
||||
|
||||
------------------------------------------------
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 50
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_50,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_50_reset(0)
|
||||
);
|
||||
|
||||
process(clk_50)
|
||||
begin
|
||||
if (rising_edge(clk_50)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_vio_0 : entity work.vio_0_1
|
||||
port map (
|
||||
clk => clk_50,
|
||||
probe_in0 => fpga_revision_date_r, -- 32
|
||||
probe_in1 => minor_rev_r, -- 8
|
||||
probe_in2 => clk_125_freq_r, -- 32
|
||||
probe_in3 => clk_125_cnt_r, -- 32
|
||||
probe_in4 => clk_250_freq_r, -- 32
|
||||
probe_in5 => clk_250_cnt_r, -- 32
|
||||
probe_in6 => qsfp1_s_axis_aclk_freq_r, -- 32
|
||||
probe_in7 => qsfp1_s_axis_aclk_cnt_r, -- 32
|
||||
probe_in8 => qsfp4_s_axis_aclk_freq_r, -- 32
|
||||
probe_in9 => qsfp4_s_axis_aclk_cnt_r, -- 32
|
||||
probe_in10 => rx_device_clk_freq_r, -- 32
|
||||
probe_in11 => rx_device_clk_cnt_r, -- 32
|
||||
probe_in12 => tx_device_clk_freq_r, -- 32
|
||||
probe_in13 => tx_device_clk_cnt_r, -- 32
|
||||
probe_in14 => clkin8_freq_r, -- 32
|
||||
probe_in15 => clkin8_cnt_r, -- 32
|
||||
probe_in16 => sys_cpu_clk_freq_r, -- 32
|
||||
probe_in17 => sys_cpu_clk_cnt_r, -- 32
|
||||
probe_in18 => ref_clk_div2_freq_r, -- 32
|
||||
probe_in19 => ref_clk_div2_cnt_r, -- 32
|
||||
probe_in20 => qsfp2_clk_freq_r, -- 32
|
||||
probe_in21 => qsfp2_clk_cnt_r, -- 32
|
||||
probe_in22 => qsfp3_clk_freq_r, -- 32
|
||||
probe_in23 => qsfp3_clk_cnt_r, -- 32
|
||||
probe_in24 => pl_clk3_0_freq_r -- 32
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_125_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_125_freq_r <= clk_125_cnt_r;
|
||||
clk_125_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_125_cnt_r <= clk_125_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_250_in)
|
||||
begin
|
||||
if (rising_edge(clk_250_in)) then
|
||||
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_250_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_250_freq_r <= clk_250_cnt_r;
|
||||
clk_250_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_250_cnt_r <= clk_250_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp1_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(qsfp1_axis_aclk)) then
|
||||
qsfp1_s_axis_aclk_tick_1ms_r <= qsfp1_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp1_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp1_s_axis_aclk_freq_r <= qsfp1_s_axis_aclk_cnt_r;
|
||||
qsfp1_s_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp1_s_axis_aclk_cnt_r <= qsfp1_s_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp4_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(qsfp4_axis_aclk)) then
|
||||
qsfp4_s_axis_aclk_tick_1ms_r <= qsfp4_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp4_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp4_s_axis_aclk_freq_r <= qsfp4_s_axis_aclk_cnt_r;
|
||||
qsfp4_s_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp4_s_axis_aclk_cnt_r <= qsfp4_s_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(rx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(rx_device_clk_in)) then
|
||||
rx_device_clk_tick_1ms_r <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
rx_device_clk_freq_r <= rx_device_clk_cnt_r;
|
||||
rx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
rx_device_clk_cnt_r <= rx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(tx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(tx_device_clk_in)) then
|
||||
tx_device_clk_tick_1ms_r <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
tx_device_clk_freq_r <= tx_device_clk_cnt_r;
|
||||
tx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
tx_device_clk_cnt_r <= tx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clkin8_in)
|
||||
begin
|
||||
if (rising_edge(clkin8_in)) then
|
||||
clkin8_tick_1ms_r <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clkin8_tick_1ms_r(0 to 1) = "01") then
|
||||
clkin8_freq_r <= clkin8_cnt_r;
|
||||
clkin8_cnt_r <= (others => '0');
|
||||
else
|
||||
clkin8_cnt_r <= clkin8_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(sys_cpu_clk_in)
|
||||
begin
|
||||
if (rising_edge(sys_cpu_clk_in)) then
|
||||
sys_cpu_clk_tick_1ms_r <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
sys_cpu_clk_freq_r <= sys_cpu_clk_cnt_r;
|
||||
sys_cpu_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
sys_cpu_clk_cnt_r <= sys_cpu_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(ref_clk_div2_in)
|
||||
begin
|
||||
if (rising_edge(ref_clk_div2_in)) then
|
||||
ref_clk_div2_tick_1ms_r <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then
|
||||
ref_clk_div2_freq_r <= ref_clk_div2_cnt_r;
|
||||
ref_clk_div2_cnt_r <= (others => '0');
|
||||
else
|
||||
ref_clk_div2_cnt_r <= ref_clk_div2_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp2_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp2_clk_in)) then
|
||||
qsfp2_clk_tick_1ms_r <= qsfp2_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp2_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp2_clk_freq_r <= qsfp2_clk_cnt_r;
|
||||
qsfp2_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp2_clk_cnt_r <= qsfp2_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp3_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp3_clk_in)) then
|
||||
qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp3_clk_freq_r <= qsfp3_clk_cnt_r;
|
||||
qsfp3_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(pl_clk3_0)
|
||||
begin
|
||||
if (rising_edge(pl_clk3_0)) then
|
||||
pl_clk3_0_tick_1ms_r <= pl_clk3_0_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (pl_clk3_0_tick_1ms_r(0 to 1) = "01") then
|
||||
pl_clk3_0_freq_r <= pl_clk3_0_cnt_r;
|
||||
pl_clk3_0_cnt_r <= (others => '0');
|
||||
else
|
||||
pl_clk3_0_cnt_r <= pl_clk3_0_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_1kx240_1",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "2048", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_1kx240_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"prog_full": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,337 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/08/2023
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_p_intfc
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
--
|
||||
--p_enable_in_0 : out std_logic;
|
||||
--p_enable_in_1 : out std_logic;
|
||||
--p_enable_in_2 : out std_logic;
|
||||
--p_enable_in_3 : out std_logic;
|
||||
--p_enable_out_0 : out std_logic;
|
||||
--p_enable_out_1 : out std_logic;
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
--
|
||||
--p_ready_in_0 : in std_logic;
|
||||
--p_ready_in_1 : in std_logic;
|
||||
--p_ready_in_2 : in std_logic;
|
||||
--p_ready_in_3 : in std_logic;
|
||||
--p_ready_out_0 : in std_logic;
|
||||
--p_ready_out_1 : in std_logic;
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
--
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end dig_iq_p_intfc;
|
||||
|
||||
architecture arch_imp of dig_iq_p_intfc is
|
||||
|
||||
--signal p_ready : std_logic_vector(7 downto 0);
|
||||
signal strb_in_r : std_logic := '0';
|
||||
signal strb_int : std_logic;
|
||||
signal addr_int : std_logic_vector(11 downto 0);
|
||||
signal sel_int : std_logic_vector(2 downto 0);
|
||||
signal write_int : std_logic;
|
||||
signal wdata_int : std_logic_vector(31 downto 0);
|
||||
signal p_addr_r : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal p_write_r : std_logic := '0';
|
||||
signal p_wdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal p_enable_r : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_enable_r1 : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_strb_r : std_logic := '0';
|
||||
signal p_ready_r : std_logic := '0';
|
||||
signal p_rdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
SAME_CLKS_FALSE_GEN :
|
||||
if SAME_CLKS = 0 generate
|
||||
begin
|
||||
|
||||
i_cdc_pulse_strb : xpm_cdc_pulse
|
||||
generic map (
|
||||
DEST_SYNC_FF => 7, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
REG_OUTPUT => 1, -- DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
RST_USED => 0, -- DECIMAL; 0=no reset, 1=implement reset
|
||||
SIM_ASSERT_CHK => 0 -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
)
|
||||
port map (
|
||||
dest_rst => '0',
|
||||
dest_pulse => strb_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => reg_clk,
|
||||
src_pulse => strb_in,
|
||||
src_rst => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_addr : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 12 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => addr_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => addr_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_sel : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 3 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => sel_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => sel_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_wdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => wdata_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => wdata_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_single_write : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => write_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => '0',
|
||||
src_in => write_in
|
||||
);
|
||||
|
||||
i_cdc_single_ready : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => ready_out,
|
||||
dest_clk => reg_clk,
|
||||
src_clk => '0',
|
||||
src_in => p_ready_r
|
||||
);
|
||||
|
||||
i_cdc_array_rdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => rdata_out,
|
||||
dest_clk => reg_clk,
|
||||
src_in => p_rdata_r,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
SAME_CLKS_TRUE_GEN :
|
||||
if SAME_CLKS = 1 generate
|
||||
begin
|
||||
|
||||
strb_int <= not(strb_in_r) and strb_in;
|
||||
addr_int <= addr_in;
|
||||
sel_int <= sel_in;
|
||||
wdata_int <= wdata_in;
|
||||
write_int <= write_in;
|
||||
ready_out <= p_ready_r;
|
||||
rdata_out <= p_rdata_r;
|
||||
|
||||
end generate;
|
||||
---------------------------------------
|
||||
|
||||
|
||||
|
||||
-- APB Interface Ports
|
||||
p_addr <= p_addr_r;
|
||||
p_write <= p_write_r;
|
||||
p_wdata <= p_wdata_r;
|
||||
|
||||
p_enable <= p_enable_r1;
|
||||
--p_enable_in_0 <= p_enable_r1(0);
|
||||
--p_enable_in_1 <= p_enable_r1(1);
|
||||
--p_enable_in_2 <= p_enable_r1(2);
|
||||
--p_enable_in_3 <= p_enable_r1(3);
|
||||
--p_enable_out_0 <= p_enable_r1(4);
|
||||
--p_enable_out_1 <= p_enable_r1(5);
|
||||
|
||||
--p_ready(0) <= p_ready_in_0;
|
||||
--p_ready(1) <= p_ready_in_1;
|
||||
--p_ready(2) <= p_ready_in_2;
|
||||
--p_ready(3) <= p_ready_in_3;
|
||||
--p_ready(4) <= p_ready_out_0;
|
||||
--p_ready(5) <= p_ready_out_1;
|
||||
|
||||
|
||||
process(clk_125)
|
||||
begin
|
||||
if(rising_edge(clk_125))then
|
||||
if(clk_125_resetn = '0')then
|
||||
strb_in_r <= '0';
|
||||
p_addr_r <= (others => '0');
|
||||
p_write_r <= '0';
|
||||
p_wdata_r <= (others => '0');
|
||||
p_enable_r <= (others => '0');
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_strb_r <= '0';
|
||||
p_ready_r <= '0';
|
||||
p_rdata_r <= (others => '0');
|
||||
else
|
||||
strb_in_r <= strb_in;
|
||||
|
||||
p_strb_r <= strb_int;
|
||||
|
||||
if(strb_int = '1')then
|
||||
p_addr_r <= addr_int;
|
||||
p_write_r <= write_int;
|
||||
p_wdata_r <= wdata_int;
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_enable_r <= "00000001";
|
||||
when "001" =>
|
||||
p_enable_r <= "00000010";
|
||||
when "010" =>
|
||||
p_enable_r <= "00000100";
|
||||
when "011" =>
|
||||
p_enable_r <= "00001000";
|
||||
when "100" =>
|
||||
p_enable_r <= "00010000";
|
||||
when "101" =>
|
||||
p_enable_r <= "00100000";
|
||||
when "110" =>
|
||||
p_enable_r <= "01000000";
|
||||
when "111" =>
|
||||
p_enable_r <= "10000000";
|
||||
when others =>
|
||||
p_enable_r <= "00000000";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
if(p_strb_r = '1')then
|
||||
|
||||
p_enable_r1 <= p_enable_r;
|
||||
if(p_enable_r /= "00000000")then
|
||||
p_ready_r <= '0';
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
if(p_ready = "11111111")then
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_ready_r <= '1';
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_rdata_r <= p_rdata_0;
|
||||
when "001" =>
|
||||
p_rdata_r <= p_rdata_1;
|
||||
when "010" =>
|
||||
p_rdata_r <= p_rdata_2;
|
||||
when "011" =>
|
||||
p_rdata_r <= p_rdata_3;
|
||||
when "100" =>
|
||||
p_rdata_r <= p_rdata_4;
|
||||
when "101" =>
|
||||
p_rdata_r <= p_rdata_5;
|
||||
when "110" =>
|
||||
p_rdata_r <= p_rdata_6;
|
||||
when "111" =>
|
||||
p_rdata_r <= p_rdata_7;
|
||||
when others =>
|
||||
p_rdata_r <= x"DEADBEEF";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,596 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/02/2023 02:07:25 PM
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_x2 - structural
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_x2 is
|
||||
port (
|
||||
clk_125_resetn_in : in std_logic;
|
||||
clk_125_in : in std_logic;
|
||||
|
||||
aclk_in : in std_logic;
|
||||
aresetn_in : in std_logic;
|
||||
cmd_strb_in : in std_logic;
|
||||
cmd_addr_in : in std_logic_vector(11 downto 0);
|
||||
cmd_write_in : in std_logic;
|
||||
cmd_sel_in : in std_logic_vector(2 downto 0);
|
||||
cmd_wdata_in : in std_logic_vector(31 downto 0);
|
||||
cmd_ready_out : out std_logic;
|
||||
cmd_rdata_out : out std_logic_vector(31 downto 0);
|
||||
dig_iq_interface_reset_in : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_resetn : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_rx_enable : in std_logic_vector(1 downto 0);
|
||||
--
|
||||
dig_iq_interface_ready_out : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_cc_overflow : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_tx_overflow : out std_logic_vector(PORT_CNT-1 downto 0);
|
||||
rx_data_ready_in : in std_logic;
|
||||
|
||||
axis_0_aclk_out : out std_logic;
|
||||
axis_0_aresetn_out : out std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
s0_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s0_axis_tvalid_in : in std_logic;
|
||||
s0_axis_tready_out : out std_logic;
|
||||
|
||||
axis_1_aclk_out : out std_logic;
|
||||
axis_1_aresetn_out : out std_logic;
|
||||
m1_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
s1_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s1_axis_tvalid_in : in std_logic;
|
||||
s1_axis_tready_out : out std_logic;
|
||||
|
||||
tx_data_channel_reset_in : in std_logic;
|
||||
tx_data_clear_in : in std_logic;
|
||||
|
||||
qsfp0_ref_clk_n_in : in std_logic;
|
||||
qsfp0_ref_clk_p_in : in std_logic;
|
||||
qsfp0_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txp_out : out std_logic_vector(3 downto 0);
|
||||
|
||||
qsfp1_ref_clk_n_in : in std_logic;
|
||||
qsfp1_ref_clk_p_in : in std_logic;
|
||||
qsfp1_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txp_out : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end dig_iq_x2;
|
||||
|
||||
architecture structural of dig_iq_x2 is
|
||||
|
||||
component DIG_IQ_HS_CUSTOM1X is
|
||||
port(
|
||||
INIT_CLK : in std_logic := '0';
|
||||
INTERFACE_RESET : in std_logic := '1';
|
||||
IntL : in std_logic := '1';
|
||||
MGTREFCLK_N : in std_logic := '1';
|
||||
MGTREFCLK_P : in std_logic := '0';
|
||||
ModPrsL : in std_logic := '1';
|
||||
PADDR : in std_logic_vector (11 downto 0) := (others => '0');
|
||||
PCLK : in std_logic := '0';
|
||||
PENABLE : in std_logic := '0';
|
||||
PRESETn : in std_logic := '0';
|
||||
PSEL : in std_logic := '0';
|
||||
PWDATA : in std_logic_vector (31 downto 0) := (others => '0');
|
||||
PWRITE : in std_logic := '0';
|
||||
RXN : in std_logic_vector (3 downto 0) := (others => '1');
|
||||
RXP : in std_logic_vector (3 downto 0) := (others => '0');
|
||||
RX_DATA_READY : in std_logic := '1';
|
||||
SCL_I : in std_logic := '0';
|
||||
SDA_I : in std_logic := '0';
|
||||
TX_DATA_CLEAR : in std_logic := '0';
|
||||
TX_DATA_DAT : in std_logic_vector (239 downto 0) := (others => '0');
|
||||
TX_DATA_EN : in std_logic := '0';
|
||||
TX_DATA_CHANNEL_RESET : in std_logic := '0';
|
||||
RX_DATA_CHANNEL_RESET : out std_logic;
|
||||
DATA_CLK : out std_logic ;
|
||||
INTERFACE_READY : out std_logic ;
|
||||
ModselL : out std_logic ;
|
||||
PRDATA : out std_logic_vector (31 downto 0);
|
||||
PREADY : out std_logic ;
|
||||
RX_DATA_DAT : out std_logic_vector (239 downto 0);
|
||||
RX_DATA_EN : out std_logic ;
|
||||
SCL_O : out std_logic ;
|
||||
SCL_OE : out std_logic ;
|
||||
SDA_O : out std_logic ;
|
||||
SDA_OE : out std_logic ;
|
||||
TXN : out std_logic_vector (3 downto 0);
|
||||
TXP : out std_logic_vector (3 downto 0);
|
||||
TX_DATA_READY : out std_logic
|
||||
);
|
||||
end component DIG_IQ_HS_CUSTOM1X;
|
||||
|
||||
component dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
--
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component dig_iq_p_intfc;
|
||||
|
||||
component axis_clock_converter_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
m_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component axis_data_fifo_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal p_addr : std_logic_vector(11 downto 0);
|
||||
signal p_write : std_logic;
|
||||
signal p_wdata : std_logic_vector(31 downto 0);
|
||||
signal p_enable : std_logic_vector(7 downto 0);
|
||||
signal p_ready : std_logic_vector(7 downto 0);
|
||||
|
||||
type SLV_32_ARRAY is array (integer range 0 to 1) of std_logic_vector(31 downto 0);
|
||||
signal p_rdata : SLV_32_ARRAY;
|
||||
|
||||
type SLV_4_ARRAY is array (integer range 0 to 1) of std_logic_vector(3 downto 0);
|
||||
signal qsfp_rx_rxn : SLV_4_ARRAY;
|
||||
signal qsfp_rx_rxp : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txn : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txp : SLV_4_ARRAY;
|
||||
|
||||
type SLV_240_ARRAY is array (integer range 0 to 1) of std_logic_vector(239 downto 0);
|
||||
--signal tx_data_r : SLV_240_ARRAY;
|
||||
--signal rx_data_r : SLV_240_ARRAY;
|
||||
signal rx_data : SLV_240_ARRAY;
|
||||
signal s_axis_tdata : SLV_240_ARRAY;
|
||||
--signal m_axis_tdata_int : SLV_240_ARRAY;
|
||||
--signal tx_fifo_m_tdata : SLV_240_ARRAY;
|
||||
|
||||
signal clk : std_logic_vector(1 downto 0);
|
||||
--signal resetn : std_logic_vector(1 downto 0);
|
||||
--signal rx_enable : std_logic_vector(1 downto 0);
|
||||
signal interface_reset : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_n : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_p : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal rx_data_en : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal tx_data_ready : std_logic_vector(1 downto 0);
|
||||
signal s_axis_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal m_axis_tvalid_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_tready : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_r : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
--signal tx_fifo_m_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal s_axis_tready_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_fifo_overflow_int : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
|
||||
signal dig_iq_interface_ready : std_logic_vector(1 downto 0);
|
||||
signal axis_0_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
signal axis_1_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
|
||||
type array_32b_type is array (0 to 1) of std_logic_vector(0 to 31);
|
||||
signal tx_data_channel_reset_r : array_32b_type := (others => (others => '0'));
|
||||
signal tx_data_clear_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
signal rx_data_ready : std_logic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
rx_data_ready <= '1' & rx_data_ready_in;
|
||||
|
||||
p_ready(7 downto 2) <= (others => '1');
|
||||
|
||||
i_dig_iq_p_intfc : dig_iq_p_intfc
|
||||
generic map(
|
||||
SAME_CLKS => 1
|
||||
)
|
||||
port map(
|
||||
reg_clk => clk_125_in,
|
||||
reg_resetn => clk_125_resetn_in,
|
||||
--
|
||||
strb_in => cmd_strb_in,
|
||||
addr_in => cmd_addr_in,
|
||||
write_in => cmd_write_in,
|
||||
sel_in => cmd_sel_in,
|
||||
wdata_in => cmd_wdata_in,
|
||||
ready_out => cmd_ready_out,
|
||||
rdata_out => cmd_rdata_out,
|
||||
--
|
||||
clk_125 => clk_125_in,
|
||||
clk_125_resetn => clk_125_resetn_in,
|
||||
--
|
||||
p_addr => p_addr,
|
||||
p_write => p_write,
|
||||
p_wdata => p_wdata,
|
||||
p_enable => p_enable,
|
||||
p_ready => p_ready,
|
||||
p_rdata_0 => p_rdata(0),
|
||||
p_rdata_1 => p_rdata(1),
|
||||
p_rdata_2 => (others => '0'),
|
||||
p_rdata_3 => (others => '0'),
|
||||
p_rdata_4 => (others => '0'),
|
||||
p_rdata_5 => (others => '0'),
|
||||
p_rdata_6 => (others => '0'),
|
||||
p_rdata_7 => (others => '0')
|
||||
);
|
||||
|
||||
i_cdc_0 : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 2 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => interface_reset,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => dig_iq_interface_reset_in
|
||||
);
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
dig_iq_interface_ready_out <= dig_iq_interface_ready;
|
||||
|
||||
axis_0_aclk_out <= clk(0);
|
||||
axis_0_aresetn_out <= axis_0_aresetn_r(0);
|
||||
s_axis_tdata(0) <= s0_axis_tdata_in;
|
||||
s_axis_tvalid(0) <= s0_axis_tvalid_in;
|
||||
s0_axis_tready_out <= tx_data_ready(0);--s_axis_tready_int(0);
|
||||
m0_axis_tdata_out <= rx_data(0);--m_axis_tdata_int(0);
|
||||
m0_axis_tvalid_out <= rx_data_en(0);--m_axis_tvalid_int(0);
|
||||
|
||||
axis_1_aclk_out <= clk(1);
|
||||
axis_1_aresetn_out <= axis_1_aresetn_r(0);
|
||||
s_axis_tdata(1) <= s1_axis_tdata_in;
|
||||
s_axis_tvalid(1) <= s1_axis_tvalid_in;
|
||||
s1_axis_tready_out <= tx_data_ready(1);--s_axis_tready_int(1);
|
||||
m1_axis_tdata_out <= rx_data(1);--m_axis_tdata_int(1);
|
||||
m1_axis_tvalid_out <= rx_data_en(1);--m_axis_tvalid_int(1);
|
||||
|
||||
qsfp_ref_clk_n(0) <= qsfp0_ref_clk_n_in;
|
||||
qsfp_ref_clk_n(1) <= qsfp1_ref_clk_n_in;
|
||||
|
||||
qsfp_ref_clk_p(0) <= qsfp0_ref_clk_p_in;
|
||||
qsfp_ref_clk_p(1) <= qsfp1_ref_clk_p_in;
|
||||
|
||||
qsfp_rx_rxn(0) <= qsfp0_rx_rxn_in;
|
||||
qsfp_rx_rxn(1) <= qsfp1_rx_rxn_in;
|
||||
|
||||
qsfp_rx_rxp(0) <= qsfp0_rx_rxp_in;
|
||||
qsfp_rx_rxp(1) <= qsfp1_rx_rxp_in;
|
||||
|
||||
qsfp0_tx_txn_out <= qsfp_tx_txn(0);
|
||||
qsfp1_tx_txn_out <= qsfp_tx_txn(1);
|
||||
|
||||
qsfp0_tx_txp_out <= qsfp_tx_txp(0);
|
||||
qsfp1_tx_txp_out <= qsfp_tx_txp(1);
|
||||
|
||||
|
||||
process(clk(0))
|
||||
begin
|
||||
if (rising_edge(clk(0))) then
|
||||
if (dig_iq_interface_ready(0) = '1') then
|
||||
axis_0_aresetn_r <= axis_0_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_0_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk(1))
|
||||
begin
|
||||
if (rising_edge(clk(1))) then
|
||||
if (dig_iq_interface_ready(1) = '1') then
|
||||
axis_1_aresetn_r <= axis_1_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_1_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
GEN_0:
|
||||
for i in 0 to 1 generate
|
||||
begin
|
||||
|
||||
|
||||
-- i_cdc_resetn : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => resetn(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_resetn(i)
|
||||
-- );
|
||||
|
||||
-- i_cdc_rx_enable : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => rx_enable(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_rx_enable(i)
|
||||
-- );
|
||||
|
||||
|
||||
process(clk(i))
|
||||
begin
|
||||
if (rising_edge(clk(i))) then
|
||||
tx_data_clear_r(i) <= tx_data_clear_in;
|
||||
tx_data_channel_reset_r(i) <= tx_data_channel_reset_r(i)(1 to 31) & '0';
|
||||
|
||||
if (tx_data_channel_reset_in = '1') then
|
||||
tx_data_channel_reset_r(i) <= (others => '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
i_dig_iq : DIG_IQ_HS_CUSTOM1X
|
||||
port map(
|
||||
INIT_CLK => clk_125_in,
|
||||
INTERFACE_RESET => interface_reset(i),
|
||||
IntL => '1',
|
||||
MGTREFCLK_N => qsfp_ref_clk_n(i),
|
||||
MGTREFCLK_P => qsfp_ref_clk_p(i),
|
||||
ModPrsL => '0',
|
||||
PADDR => p_addr,
|
||||
PCLK => clk_125_in,
|
||||
PENABLE => p_enable(i),
|
||||
PRESETn => clk_125_resetn_in,
|
||||
PSEL => '1',
|
||||
PWDATA => p_wdata,
|
||||
PWRITE => p_write,
|
||||
RXN => qsfp_rx_rxn(i),
|
||||
RXP => qsfp_rx_rxp(i),
|
||||
RX_DATA_READY => rx_data_ready(i),
|
||||
SCL_I => '0',
|
||||
SDA_I => '0',
|
||||
TX_DATA_CHANNEL_RESET => tx_data_channel_reset_r(i)(0),
|
||||
TX_DATA_CLEAR => tx_data_clear_r(i),
|
||||
TX_DATA_DAT => s_axis_tdata(i),--tx_data_r(i),
|
||||
TX_DATA_EN => s_axis_tvalid(i),--tx_data_en_r(i),
|
||||
DATA_CLK => clk(i),
|
||||
INTERFACE_READY => dig_iq_interface_ready(i),
|
||||
ModselL => open,
|
||||
PRDATA => p_rdata(i),
|
||||
PREADY => p_ready(i),
|
||||
RX_DATA_CHANNEL_RESET => open,
|
||||
RX_DATA_DAT => rx_data(i),
|
||||
RX_DATA_EN => rx_data_en(i),
|
||||
SCL_O => open,
|
||||
SCL_OE => open,
|
||||
SDA_O => open,
|
||||
SDA_OE => open,
|
||||
TXN => qsfp_tx_txn(i),
|
||||
TXP => qsfp_tx_txp(i),
|
||||
TX_DATA_READY => tx_data_ready(i)
|
||||
);
|
||||
|
||||
-- GEN_1:
|
||||
-- for j in 0 to 239 generate
|
||||
-- begin
|
||||
|
||||
-- i_FD_rx_data : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
-- end generate;
|
||||
|
||||
-- rx_data_en_int(i) <= rx_data_en(i) and rx_enable(i);
|
||||
|
||||
-- i_FD_rx_data_en : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- i_clock_converter : axis_clock_converter_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => resetn(i),
|
||||
-- m_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => clk(i),
|
||||
-- s_axis_tvalid => rx_data_en_r(i),
|
||||
-- s_axis_tready => cc_overflow_tready(i),
|
||||
-- s_axis_tdata => rx_data_r(i),
|
||||
-- m_axis_aclk => aclk_in,
|
||||
-- m_axis_tvalid => m_axis_tvalid_int(i),
|
||||
-- m_axis_tready => m_axis_tvalid_int(i),
|
||||
-- m_axis_tdata => m_axis_tdata_int(i)
|
||||
-- );
|
||||
|
||||
-- cc_overflow_int(i) <= not(cc_overflow_tready(i)) and rx_data_en_r(i);
|
||||
|
||||
-- i_FDRE_cc_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_cc_overflow(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- CE => cc_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => resetn(i) -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- R&S Documentation states:
|
||||
--
|
||||
-- TX_DATA_READY signal -- TX channel is receptive. After the deactivation of this signal,
|
||||
-- up to five more enabled data samples are allowed on the TX_DATA_DAT
|
||||
-- bus.
|
||||
-- Thus, we can pipeline the tx_data between the output of the FIFO and the R&S core.
|
||||
--
|
||||
-- ** PIPELINING IS CURRENTLY COMMENTED OUT **
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
-- i_tx_fifo : axis_data_fifo_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => aclk_in,
|
||||
-- s_axis_tvalid => s_axis_tvalid(i),
|
||||
-- s_axis_tready => s_axis_tready_int(i),
|
||||
-- s_axis_tdata => s_axis_tdata(i),
|
||||
-- m_axis_aclk => clk(i),
|
||||
-- m_axis_tvalid => tx_fifo_m_tvalid(i),
|
||||
-- m_axis_tready => tx_data_ready(i),
|
||||
-- m_axis_tdata => tx_fifo_m_tdata(i)
|
||||
-- );
|
||||
|
||||
--tx_fifo_overflow_int(i) <= not(s_axis_tready_int(i)) and s_axis_tvalid(i);
|
||||
|
||||
-- i_FDRE_tx_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_tx_overflow(i), -- 1-bit output: Data
|
||||
-- C => aclk_in, -- 1-bit input: Clock
|
||||
-- CE => tx_fifo_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => aresetn_in -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_int(i) <= tx_fifo_m_tvalid(i) and tx_data_ready(i);
|
||||
|
||||
--i_FD_tx_data_en : FD --RE
|
||||
--generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
--port map (
|
||||
-- Q => tx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_r(i) <= tx_data_en_int(i);
|
||||
|
||||
--GEN_2:
|
||||
--for j in 0 to 239 generate
|
||||
-- begin
|
||||
--
|
||||
-- i_FD_tx_data : FD --RE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => tx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_fifo_m_tdata(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
--
|
||||
-- end generate;
|
||||
|
||||
-- tx_data_r(i) <= tx_fifo_m_tdata(i);
|
||||
|
||||
end generate;
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
end structural;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,90 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
ipgui::add_param $IPINST -name "MINOR_REV"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to validate MINOR_REV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,512 @@
|
||||
00000002
|
||||
00000010
|
||||
000001d0
|
||||
000001d8
|
||||
000001e0
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
63000000
|
||||
6e69616d
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
37656439
|
||||
30303939
|
||||
36643732
|
||||
38613839
|
||||
63653239
|
||||
62393030
|
||||
61333163
|
||||
34333835
|
||||
31326132
|
||||
39336363
|
||||
00000000
|
||||
00000074
|
||||
6a646176
|
||||
34313731
|
||||
31343537
|
||||
00003139
|
||||
00000000
|
||||
d0000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
30396461
|
||||
665f3138
|
||||
5f61636d
|
||||
007a6265
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
3175637a
|
||||
00003230
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user