4093 lines
225 KiB
Tcl
4093 lines
225 KiB
Tcl
#*****************************************************************************************
|
|
# Vivado (TM) v2023.2 (64-bit)
|
|
#
|
|
# create_proj.tcl: Tcl script for re-creating project 'alinx_ad9081_1gsps'
|
|
#
|
|
# Generated by Vivado on Tue Jul 15 20:12:30 EDT 2025
|
|
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
|
#
|
|
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
|
# when this script was generated. In order to re-create the project, please source this
|
|
# file in the Vivado Tcl Shell.
|
|
#
|
|
# * Note that the runs in the created project will be configured the same way as the
|
|
# original project, however they will not be launched automatically. To regenerate the
|
|
# run results please launch the synthesis/implementation runs as needed.
|
|
#
|
|
#*****************************************************************************************
|
|
# NOTE: In order to use this script for source control purposes, please make sure that the
|
|
# following files are added to the source control system:-
|
|
#
|
|
# 1. This project restoration tcl script (create_proj.tcl) that was generated.
|
|
#
|
|
# 2. The following source(s) files that were local or imported into the original project.
|
|
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
|
|
#
|
|
# <none>
|
|
#
|
|
# 3. The following remote source files that were added to the original project:-
|
|
#
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/vio_3/vio_3.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_register_slice_512b/axis_register_slice_512b.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_data_fifo_32kx256/axis_data_fifo_32kx256.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/src/vio_0_1/vio_0_1.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/src/vio_2_1/vio_2_1.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/vio_0/vio_0.xci"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/ad_3w_spi.v"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/ad_iobuf.v"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/global_types.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/i2c.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/i2c_st.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/qsfp1_capture_intfc.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/qsfp4_playback_intfc.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/tick_gen.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/ip_repo/Si5332/src/si5332_wrapper.vhd"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/source/system_top.v"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/constraints/system_constr.xdc"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/constraints/qsfp_constr.xdc"
|
|
# "/home/nsantana/proj_alinxz19/ALINX_Z19/alinx_z19_ad9081_1gsps/constraints/timing_constr.xdc"
|
|
#
|
|
#*****************************************************************************************
|
|
|
|
# Check file required for this script exists
|
|
proc checkRequiredFiles { origin_dir} {
|
|
set status true
|
|
set files [list \
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/vio_3/vio_3.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_register_slice_512b/axis_register_slice_512b.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_data_fifo_32kx256/axis_data_fifo_32kx256.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/vio_0_1/vio_0_1.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/vio_2_1/vio_2_1.xci"]"\
|
|
"[file normalize "$origin_dir/ip_repo/vio_0/vio_0.xci"]"\
|
|
"[file normalize "$origin_dir/source/ad_3w_spi.v"]"\
|
|
"[file normalize "$origin_dir/source/ad_iobuf.v"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/global_types.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/i2c.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/i2c_st.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd"]"\
|
|
"[file normalize "$origin_dir/source/qsfp1_capture_intfc.vhd"]"\
|
|
"[file normalize "$origin_dir/source/qsfp4_playback_intfc.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"]"\
|
|
"[file normalize "$origin_dir/source/tick_gen.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_clk_configurator.vhd"]"\
|
|
"[file normalize "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"]"\
|
|
"[file normalize "$origin_dir/source/system_top.v"]"\
|
|
"[file normalize "$origin_dir/constraints/system_constr.xdc"]"\
|
|
"[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"\
|
|
"[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\
|
|
]
|
|
foreach ifile $files {
|
|
if { ![file isfile $ifile] } {
|
|
puts " Could not find remote file $ifile "
|
|
set status false
|
|
}
|
|
}
|
|
|
|
set paths [list \
|
|
"[file normalize "$origin_dir/[file normalize "$origin_dir/../../../adi/hdl/library"]"]"\
|
|
"[file normalize "$origin_dir/[file normalize "$origin_dir/ip_repo"]"]"\
|
|
]
|
|
foreach ipath $paths {
|
|
if { ![file isdirectory $ipath] } {
|
|
puts " Could not access $ipath "
|
|
set status false
|
|
}
|
|
}
|
|
|
|
return $status
|
|
}
|
|
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
|
set origin_dir "."
|
|
|
|
# Use origin directory path location variable, if specified in the tcl shell
|
|
if { [info exists ::origin_dir_loc] } {
|
|
set origin_dir $::origin_dir_loc
|
|
}
|
|
|
|
# Set the project name
|
|
set _xil_proj_name_ "alinx_ad9081_1gsps"
|
|
|
|
# Use project name variable, if specified in the tcl shell
|
|
if { [info exists ::user_project_name] } {
|
|
set _xil_proj_name_ $::user_project_name
|
|
}
|
|
|
|
variable script_file
|
|
set script_file "create_proj.tcl"
|
|
|
|
# Help information for this script
|
|
proc print_help {} {
|
|
variable script_file
|
|
puts "\nDescription:"
|
|
puts "Recreate a Vivado project from this script. The created project will be"
|
|
puts "functionally equivalent to the original project for which this script was"
|
|
puts "generated. The script contains commands for creating a project, filesets,"
|
|
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
|
puts "Syntax:"
|
|
puts "$script_file"
|
|
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
|
puts "$script_file -tclargs \[--project_name <name>\]"
|
|
puts "$script_file -tclargs \[--help\]\n"
|
|
puts "Usage:"
|
|
puts "Name Description"
|
|
puts "-------------------------------------------------------------------------"
|
|
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
|
puts " origin_dir path value is \".\", otherwise, the value"
|
|
puts " that was set with the \"-paths_relative_to\" switch"
|
|
puts " when this script was generated.\n"
|
|
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
|
puts " name is the name of the project from where this"
|
|
puts " script was generated.\n"
|
|
puts "\[--help\] Print help information for this script"
|
|
puts "-------------------------------------------------------------------------\n"
|
|
exit 0
|
|
}
|
|
|
|
if { $::argc > 0 } {
|
|
for {set i 0} {$i < $::argc} {incr i} {
|
|
set option [string trim [lindex $::argv $i]]
|
|
switch -regexp -- $option {
|
|
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
|
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
|
"--help" { print_help }
|
|
default {
|
|
if { [regexp {^-} $option] } {
|
|
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
|
return 1
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
# Set the directory path for the original project from where this script was exported
|
|
set orig_proj_dir "[file normalize "$origin_dir/alinx_ad9081_1gsps"]"
|
|
|
|
# Check for paths and files needed for project creation
|
|
set validate_required 0
|
|
if { $validate_required } {
|
|
if { [checkRequiredFiles $origin_dir] } {
|
|
puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
|
|
} else {
|
|
puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
|
|
return
|
|
}
|
|
}
|
|
|
|
# Create project
|
|
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu19eg-ffvc1760-2-i
|
|
|
|
# Set the directory path for the new project
|
|
set proj_dir [get_property directory [current_project]]
|
|
|
|
# Reconstruct message rules
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {1} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {10} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {11} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {12} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {13} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {14} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {15} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {16} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {17} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {18} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {19} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {2} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {20} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {21} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {22} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {23} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {24} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {25} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {26} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {27} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {28} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {3} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {4} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {5} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {6} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {7} -source 2
|
|
set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2
|
|
set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2
|
|
|
|
|
|
# Set project properties
|
|
set obj [current_project]
|
|
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
|
set_property -name "enable_resource_estimation" -value "0" -objects $obj
|
|
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
|
set_property -name "feature_set" -value "FeatureSet_Classic" -objects $obj
|
|
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
|
set_property -name "ip_output_repo" -value "/home/nsantana/adi/hdl/ipcache" -objects $obj
|
|
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
|
set_property -name "revised_directory_structure" -value "1" -objects $obj
|
|
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
|
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
|
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
|
set_property -name "sim_compile_state" -value "1" -objects $obj
|
|
set_property -name "webtalk.activehdl_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.modelsim_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.questa_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.riviera_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.vcs_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.xcelium_export_sim" -value "9" -objects $obj
|
|
set_property -name "webtalk.xsim_export_sim" -value "9" -objects $obj
|
|
set_property -name "xpm_libraries" -value "XPM_CDC XPM_COMP_DECL XPM_FIFO XPM_MEMORY" -objects $obj
|
|
|
|
# Create 'sources_1' fileset (if not found)
|
|
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
|
create_fileset -srcset sources_1
|
|
}
|
|
|
|
# Set IP repository paths
|
|
set obj [get_filesets sources_1]
|
|
if { $obj != {} } {
|
|
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../adi/hdl/library"] [file normalize "$origin_dir/ip_repo"]" $obj
|
|
|
|
# Rebuild user ip_repo's index before adding any source files
|
|
update_ip_catalog -rebuild
|
|
}
|
|
|
|
# Set 'sources_1' fileset object
|
|
set obj [get_filesets sources_1]
|
|
set files [list \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/vio_3/vio_3.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_register_slice_512b/axis_register_slice_512b.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_data_fifo_32kx256/axis_data_fifo_32kx256.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/vio_0_1/vio_0_1.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/vio_2_1/vio_2_1.xci"] \
|
|
[file normalize "${origin_dir}/ip_repo/vio_0/vio_0.xci"] \
|
|
[file normalize "${origin_dir}/source/ad_3w_spi.v"] \
|
|
[file normalize "${origin_dir}/source/ad_iobuf.v"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/global_types.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_gen_cfg.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/i2c.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/i2c_st.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd"] \
|
|
[file normalize "${origin_dir}/source/qsfp1_capture_intfc.vhd"] \
|
|
[file normalize "${origin_dir}/source/qsfp4_playback_intfc.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"] \
|
|
[file normalize "${origin_dir}/source/tick_gen.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_clk_configurator.vhd"] \
|
|
[file normalize "${origin_dir}/ip_repo/Si5332/src/si5332_wrapper.vhd"] \
|
|
[file normalize "${origin_dir}/source/system_top.v"] \
|
|
]
|
|
add_files -norecurse -fileset $obj $files
|
|
|
|
# Set 'sources_1' fileset file properties for remote files
|
|
set file "$origin_dir/ip_repo/Si5332/src/vio_3/vio_3.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_register_slice_512b/axis_register_slice_512b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_256b_to_512b/axis_dwidth_converter_256b_to_512b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_register_slice_256b/axis_register_slice_256b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_data_fifo_32kx256/axis_data_fifo_32kx256.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_256b/axis_dwidth_converter_512b_to_256b.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
|
}
|
|
|
|
set file "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/src/vio_0_1/vio_0_1.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "netlist_only" -value "0" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/src/vio_2_1/vio_2_1.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/vio_0/vio_0.xci"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
|
if { ![get_property "is_locked" $file_obj] } {
|
|
set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj
|
|
}
|
|
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/global_types.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/clk_gen_cfg_2.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/i2c.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/i2c_st.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/source/qsfp1_capture_intfc.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/source/qsfp4_playback_intfc.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/source/tick_gen.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5341_clk_configurator.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
set file "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
|
|
|
|
|
# Set 'sources_1' fileset file properties for local files
|
|
# None
|
|
|
|
# Set 'sources_1' fileset properties
|
|
set obj [get_filesets sources_1]
|
|
set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
|
|
set_property -name "generic" -value "JESD_MODE=64B66B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj
|
|
set_property -name "top" -value "system_top" -objects $obj
|
|
set_property -name "top_auto_set" -value "0" -objects $obj
|
|
set_property -name "vhdl_generic" -value "JESD_MODE=64B66B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj
|
|
|
|
# Create 'constrs_1' fileset (if not found)
|
|
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
|
create_fileset -constrset constrs_1
|
|
}
|
|
|
|
# Set 'constrs_1' fileset object
|
|
set obj [get_filesets constrs_1]
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/system_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/system_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/qsfp_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Add/Import constrs file and set constrs file properties
|
|
set file "[file normalize "$origin_dir/constraints/timing_constr.xdc"]"
|
|
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
set file "$origin_dir/constraints/timing_constr.xdc"
|
|
set file [file normalize $file]
|
|
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
|
|
# Set 'constrs_1' fileset properties
|
|
set obj [get_filesets constrs_1]
|
|
|
|
# Create 'sim_1' fileset (if not found)
|
|
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
|
create_fileset -simset sim_1
|
|
}
|
|
|
|
# Set 'sim_1' fileset object
|
|
set obj [get_filesets sim_1]
|
|
# Empty (no sources present)
|
|
|
|
# Set 'sim_1' fileset properties
|
|
set obj [get_filesets sim_1]
|
|
set_property -name "top" -value "system_top" -objects $obj
|
|
set_property -name "top_auto_set" -value "0" -objects $obj
|
|
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
|
|
|
# Set 'utils_1' fileset object
|
|
set obj [get_filesets utils_1]
|
|
# Empty (no sources present)
|
|
|
|
# Set 'utils_1' fileset properties
|
|
set obj [get_filesets utils_1]
|
|
|
|
|
|
# Adding sources referenced in BDs, if not already added
|
|
|
|
|
|
# Proc to create BD iq_240b_to_512b
|
|
proc cr_bd_iq_240b_to_512b { parentCell } {
|
|
|
|
# CHANGE DESIGN NAME HERE
|
|
set design_name iq_240b_to_512b
|
|
|
|
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
|
|
create_bd_design $design_name
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:axis_data_fifo:2.0\
|
|
xilinx.com:user:axis_demux:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
xilinx.com:user:dig_iq_decoder:1.0\
|
|
xilinx.com:user:axis_mux:1.0\
|
|
xilinx.com:ip:axis_register_slice:1.1\
|
|
xilinx.com:ip:axis_dwidth_converter:1.1\
|
|
xilinx.com:ip:axis_subset_converter:1.1\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
set s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {195312500} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.LAYERED_METADATA {undef} \
|
|
CONFIG.TDATA_NUM_BYTES {30} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $s_axis
|
|
|
|
set m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.FREQ_HZ {195312500} \
|
|
] $m_axis
|
|
|
|
|
|
# Create ports
|
|
set aclk [ create_bd_port -dir I -type clk -freq_hz 195312500 aclk ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {s_axis:m_axis} \
|
|
CONFIG.ASSOCIATED_RESET {aresetn} \
|
|
] $aclk
|
|
set aresetn [ create_bd_port -dir I -type rst aresetn ]
|
|
set overflow [ create_bd_port -dir O overflow ]
|
|
set sel_12b_16bn [ create_bd_port -dir I sel_12b_16bn ]
|
|
set prog_full [ create_bd_port -dir O prog_full ]
|
|
set almost_empty [ create_bd_port -dir O almost_empty ]
|
|
set almost_full [ create_bd_port -dir O almost_full ]
|
|
|
|
# Create instance: fifo_0, and set properties
|
|
set fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 fifo_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.FIFO_DEPTH {64} \
|
|
CONFIG.HAS_AEMPTY {1} \
|
|
CONFIG.HAS_AFULL {1} \
|
|
CONFIG.HAS_PROG_FULL {1} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.PROG_FULL_THRESH {48} \
|
|
CONFIG.TDATA_NUM_BYTES {40} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $fifo_0
|
|
|
|
|
|
# Create instance: demux_16b_12b, and set properties
|
|
set demux_16b_12b [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_demux:1.0 demux_16b_12b ]
|
|
set_property CONFIG.DWIDTH {320} $demux_16b_12b
|
|
|
|
|
|
# Create instance: xlslice_0, and set properties
|
|
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {223} \
|
|
CONFIG.DIN_WIDTH {320} \
|
|
CONFIG.DOUT_WIDTH {224} \
|
|
] $xlslice_0
|
|
|
|
|
|
# Create instance: decoder_12b_16b, and set properties
|
|
set decoder_12b_16b [ create_bd_cell -type ip -vlnv xilinx.com:user:dig_iq_decoder:1.0 decoder_12b_16b ]
|
|
|
|
# Create instance: mux_16b_12b, and set properties
|
|
set mux_16b_12b [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_mux:1.0 mux_16b_12b ]
|
|
|
|
# Create instance: reg_28B, and set properties
|
|
set reg_28B [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 reg_28B ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {8} \
|
|
CONFIG.TDATA_NUM_BYTES {28} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $reg_28B
|
|
|
|
|
|
# Create instance: dwc_40B_to_64B, and set properties
|
|
set dwc_40B_to_64B [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 dwc_40B_to_64B ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_MI_TKEEP {1} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDATA_NUM_BYTES {40} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_BITS_PER_BYTE {0} \
|
|
] $dwc_40B_to_64B
|
|
|
|
|
|
# Create instance: ovf_detect, and set properties
|
|
set ovf_detect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 ovf_detect ]
|
|
set_property -dict [list \
|
|
CONFIG.M_HAS_TKEEP {0} \
|
|
CONFIG.M_HAS_TLAST {0} \
|
|
CONFIG.M_HAS_TREADY {1} \
|
|
CONFIG.M_HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {40} \
|
|
CONFIG.M_TDEST_WIDTH {0} \
|
|
CONFIG.M_TID_WIDTH {0} \
|
|
CONFIG.M_TUSER_WIDTH {0} \
|
|
CONFIG.S_HAS_TKEEP {0} \
|
|
CONFIG.S_HAS_TLAST {0} \
|
|
CONFIG.S_HAS_TREADY {0} \
|
|
CONFIG.S_HAS_TSTRB {0} \
|
|
CONFIG.S_TDATA_NUM_BYTES {40} \
|
|
CONFIG.S_TDEST_WIDTH {0} \
|
|
CONFIG.S_TID_WIDTH {0} \
|
|
CONFIG.S_TUSER_WIDTH {0} \
|
|
CONFIG.TDATA_REMAP {tdata[319:0]} \
|
|
] $ovf_detect
|
|
|
|
|
|
# Create instance: reg_40B, and set properties
|
|
set reg_40B [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 reg_40B ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {8} \
|
|
CONFIG.TDATA_NUM_BYTES {40} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $reg_40B
|
|
|
|
|
|
# Create instance: dwc_28B_to_64B, and set properties
|
|
set dwc_28B_to_64B [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 dwc_28B_to_64B ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_MI_TKEEP {1} \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.M_TDATA_NUM_BYTES {64} \
|
|
CONFIG.S_TDATA_NUM_BYTES {28} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_BITS_PER_BYTE {0} \
|
|
] $dwc_28B_to_64B
|
|
|
|
|
|
# Create instance: reg_64B, and set properties
|
|
set reg_64B [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 reg_64B ]
|
|
set_property -dict [list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.REG_CONFIG {8} \
|
|
CONFIG.TDATA_NUM_BYTES {64} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $reg_64B
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins fifo_0/M_AXIS] [get_bd_intf_pins demux_16b_12b/s_axis]
|
|
connect_bd_intf_net -intf_net axis_demux_0_m1_axis [get_bd_intf_pins demux_16b_12b/m1_axis] [get_bd_intf_pins reg_40B/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_dwidth_conv_40B_to_64B_M_AXIS [get_bd_intf_pins dwc_40B_to_64B/M_AXIS] [get_bd_intf_pins mux_16b_12b/s1_axis]
|
|
connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins dwc_28B_to_64B/M_AXIS] [get_bd_intf_pins mux_16b_12b/s0_axis]
|
|
connect_bd_intf_net -intf_net axis_mux_0_m_axis [get_bd_intf_pins mux_16b_12b/m_axis] [get_bd_intf_pins reg_64B/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins reg_28B/M_AXIS] [get_bd_intf_pins dwc_28B_to_64B/S_AXIS]
|
|
connect_bd_intf_net -intf_net axis_register_slice_40B_M_AXIS [get_bd_intf_pins reg_40B/M_AXIS] [get_bd_intf_pins dwc_40B_to_64B/S_AXIS]
|
|
connect_bd_intf_net -intf_net dig_iq_decoder_0_m_axis [get_bd_intf_pins decoder_12b_16b/m_axis] [get_bd_intf_pins ovf_detect/S_AXIS]
|
|
connect_bd_intf_net -intf_net iq_240b_to_512b_m_axis [get_bd_intf_pins reg_64B/M_AXIS] [get_bd_intf_ports m_axis]
|
|
connect_bd_intf_net -intf_net overflow_detect_M_AXIS [get_bd_intf_pins ovf_detect/M_AXIS] [get_bd_intf_pins fifo_0/S_AXIS]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins decoder_12b_16b/s_axis] [get_bd_intf_ports s_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins decoder_12b_16b/aclk] [get_bd_pins demux_16b_12b/aclk] [get_bd_pins dwc_28B_to_64B/aclk] [get_bd_pins dwc_40B_to_64B/aclk] [get_bd_pins fifo_0/s_axis_aclk] [get_bd_pins mux_16b_12b/aclk] [get_bd_pins ovf_detect/aclk] [get_bd_pins reg_28B/aclk] [get_bd_pins reg_40B/aclk] [get_bd_pins reg_64B/aclk]
|
|
connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins decoder_12b_16b/aresetn] [get_bd_pins demux_16b_12b/aresetn] [get_bd_pins dwc_28B_to_64B/aresetn] [get_bd_pins dwc_40B_to_64B/aresetn] [get_bd_pins fifo_0/s_axis_aresetn] [get_bd_pins mux_16b_12b/aresetn] [get_bd_pins ovf_detect/aresetn] [get_bd_pins reg_28B/aresetn] [get_bd_pins reg_40B/aresetn] [get_bd_pins reg_64B/aresetn]
|
|
connect_bd_net -net axis_demux_0_m0_axis_tdata [get_bd_pins demux_16b_12b/m0_axis_tdata] [get_bd_pins xlslice_0/Din]
|
|
connect_bd_net -net axis_demux_0_m0_axis_tvalid [get_bd_pins demux_16b_12b/m0_axis_tvalid] [get_bd_pins reg_28B/s_axis_tvalid]
|
|
connect_bd_net -net axis_register_slice_0_s_axis_tready [get_bd_pins reg_28B/s_axis_tready] [get_bd_pins demux_16b_12b/m0_axis_tready]
|
|
connect_bd_net -net const_1b0_dout [get_bd_ports sel_12b_16bn] [get_bd_pins decoder_12b_16b/select_12b] [get_bd_pins demux_16b_12b/aselect] [get_bd_pins mux_16b_12b/aselect]
|
|
connect_bd_net -net fifo_0_almost_empty [get_bd_pins fifo_0/almost_empty] [get_bd_ports almost_empty]
|
|
connect_bd_net -net fifo_0_almost_full [get_bd_pins fifo_0/almost_full] [get_bd_ports almost_full]
|
|
connect_bd_net -net fifo_0_prog_full [get_bd_pins fifo_0/prog_full] [get_bd_ports prog_full]
|
|
connect_bd_net -net iq_240b_to_512b_overflow [get_bd_pins ovf_detect/transfer_dropped] [get_bd_ports overflow]
|
|
connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins reg_28B/s_axis_tdata]
|
|
|
|
# Create address segments
|
|
|
|
# Perform GUI Layout
|
|
regenerate_bd_layout -layout_string {
|
|
"ActiveEmotionalView":"Default View",
|
|
"Default View_ScaleFactor":"0.702439",
|
|
"Default View_TopLeft":"-753,-30",
|
|
"ExpandedHierarchyInLayout":"",
|
|
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
|
# -string -flagsOSRD
|
|
preplace port s_axis -pg 1 -lvl 0 -x -120 -y 80 -defaultsOSRD
|
|
preplace port m_axis -pg 1 -lvl 3 -x 890 -y 20 -defaultsOSRD
|
|
preplace port port-id_aclk -pg 1 -lvl 0 -x -120 -y 20 -defaultsOSRD
|
|
preplace port port-id_aresetn -pg 1 -lvl 0 -x -120 -y 40 -defaultsOSRD
|
|
preplace port port-id_overflow -pg 1 -lvl 3 -x 890 -y 80 -defaultsOSRD
|
|
preplace port port-id_sel_12b_16bn -pg 1 -lvl 0 -x -120 -y 60 -defaultsOSRD
|
|
preplace port port-id_prog_full -pg 1 -lvl 3 -x 890 -y 100 -defaultsOSRD
|
|
preplace port port-id_almost_empty -pg 1 -lvl 3 -x 890 -y 40 -defaultsOSRD
|
|
preplace port port-id_almost_full -pg 1 -lvl 3 -x 890 -y 60 -defaultsOSRD
|
|
preplace inst fifo_0 -pg 1 -lvl 2 -x 570 -y 710 -defaultsOSRD
|
|
preplace inst demux_16b_12b -pg 1 -lvl 2 -x 570 -y 260 -defaultsOSRD
|
|
preplace inst xlslice_0 -pg 1 -lvl 1 -x 140 -y 510 -defaultsOSRD
|
|
preplace inst decoder_12b_16b -pg 1 -lvl 2 -x 570 -y 90 -defaultsOSRD
|
|
preplace inst mux_16b_12b -pg 1 -lvl 2 -x 570 -y 880 -defaultsOSRD
|
|
preplace inst reg_28B -pg 1 -lvl 1 -x 140 -y 80 -defaultsOSRD
|
|
preplace inst dwc_40B_to_64B -pg 1 -lvl 2 -x 570 -y 560 -defaultsOSRD
|
|
preplace inst ovf_detect -pg 1 -lvl 2 -x 570 -y 1040 -defaultsOSRD
|
|
preplace inst reg_40B -pg 1 -lvl 1 -x 140 -y 250 -defaultsOSRD
|
|
preplace inst dwc_28B_to_64B -pg 1 -lvl 2 -x 570 -y 420 -defaultsOSRD
|
|
preplace inst reg_64B -pg 1 -lvl 1 -x 140 -y 390 -defaultsOSRD
|
|
preplace netloc aclk_1 1 0 2 -70 590 330
|
|
preplace netloc aresetn_1 1 0 2 -80 600 340
|
|
preplace netloc axis_demux_0_m0_axis_tdata 1 0 3 -30 1160 NJ 1160 830
|
|
preplace netloc axis_demux_0_m0_axis_tvalid 1 0 3 -40 1170 NJ 1170 810
|
|
preplace netloc axis_register_slice_0_s_axis_tready 1 0 3 -20 1150 290J 1200 820
|
|
preplace netloc const_1b0_dout 1 0 2 -100 610 350
|
|
preplace netloc fifo_0_almost_empty 1 2 1 840 40n
|
|
preplace netloc fifo_0_almost_full 1 2 1 850 60n
|
|
preplace netloc fifo_0_prog_full 1 2 1 870 100n
|
|
preplace netloc iq_240b_to_512b_overflow 1 2 1 860 80n
|
|
preplace netloc xlslice_0_Dout 1 0 2 -10 580 290
|
|
preplace netloc axis_data_fifo_0_M_AXIS 1 1 2 390 -10 760
|
|
preplace netloc axis_demux_0_m1_axis 1 0 3 -50 1180 NJ 1180 800
|
|
preplace netloc axis_dwidth_conv_40B_to_64B_M_AXIS 1 1 2 390 1120 750
|
|
preplace netloc axis_dwidth_converter_0_M_AXIS 1 1 2 380 1130 780
|
|
preplace netloc axis_mux_0_m_axis 1 0 3 -60 1190 NJ 1190 790
|
|
preplace netloc axis_register_slice_0_M_AXIS 1 1 1 320 80n
|
|
preplace netloc axis_register_slice_40B_M_AXIS 1 1 1 310 250n
|
|
preplace netloc dig_iq_decoder_0_m_axis 1 1 2 370 1140 770
|
|
preplace netloc iq_240b_to_512b_m_axis 1 1 2 290J 0 870
|
|
preplace netloc overflow_detect_M_AXIS 1 1 2 360 1150 760
|
|
preplace netloc s_axis_1 1 0 2 -90J 570 300
|
|
levelinfo -pg 1 -120 140 570 890
|
|
pagesize -pg 1 -db -bbox -sgen -270 -30 1050 1210
|
|
"
|
|
}
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_iq_240b_to_512b()
|
|
|
|
cr_bd_iq_240b_to_512b ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files iq_240b_to_512b.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files iq_240b_to_512b.bd ]
|
|
|
|
|
|
|
|
# Proc to create BD system
|
|
proc cr_bd_system { parentCell } {
|
|
|
|
# CHANGE DESIGN NAME HERE
|
|
set design_name system
|
|
|
|
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
|
|
create_bd_design $design_name
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:zynq_ultra_ps_e:3.5\
|
|
xilinx.com:ip:proc_sys_reset:5.0\
|
|
xilinx.com:ip:xlconcat:2.1\
|
|
xilinx.com:ip:xlconstant:1.1\
|
|
analog.com:user:axi_sysid:1.0\
|
|
analog.com:user:sysid_rom:1.0\
|
|
xilinx.com:ip:smartconnect:1.0\
|
|
analog.com:user:util_adxcvr:1.0\
|
|
analog.com:user:axi_adxcvr:1.0\
|
|
analog.com:user:util_cpack2:1.0\
|
|
analog.com:user:axi_dmac:1.0\
|
|
analog.com:user:util_upack2:1.0\
|
|
xilinx.com:ip:util_vector_logic:2.0\
|
|
xilinx.com:ip:util_reduced_logic:2.0\
|
|
analog.com:user:axi_jesd204_rx:1.0\
|
|
analog.com:user:jesd204_rx:1.0\
|
|
analog.com:user:ad_ip_jesd204_tpl_adc:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
analog.com:user:data_offload:1.0\
|
|
analog.com:user:util_do_ram:1.0\
|
|
analog.com:user:axi_jesd204_tx:1.0\
|
|
analog.com:user:jesd204_tx:1.0\
|
|
analog.com:user:ad_ip_jesd204_tpl_dac:1.0\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
|
|
# Hierarchical cell: mxfe_tx_data_offload
|
|
proc create_hier_cell_mxfe_tx_data_offload { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_tx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_CYCLIC_EN {true} \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.MEM_SIZE_LOG2 {19} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {1} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.LENGTH_WIDTH {19} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: tx_mxfe_tpl_core
|
|
proc create_hier_cell_tx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_tx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 link
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I dac_dunf
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_0
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_1
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_2
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 dac_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 dac_valid_3
|
|
create_bd_pin -dir I -from 63 -to 0 dac_data_3
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O dac_sync_manual_req_out
|
|
create_bd_pin -dir I dac_sync_manual_req_in
|
|
create_bd_pin -dir O dac_rst
|
|
|
|
# Create instance: dac_tpl_core, and set properties
|
|
set dac_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_dac:1.0 dac_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.IQCORRECTION_DISABLE {0} \
|
|
CONFIG.NUM_CHANNELS {4} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.OCTETS_PER_BEAT {8} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $dac_tpl_core
|
|
|
|
|
|
# Create instance: data_concat0, and set properties
|
|
set data_concat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_concat0 ]
|
|
set_property CONFIG.NUM_PORTS {4} $data_concat0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net dac_tpl_core_link [get_bd_intf_pins dac_tpl_core/link] [get_bd_intf_pins link]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins dac_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net dac_data_0_1 [get_bd_pins dac_data_0] [get_bd_pins data_concat0/In0]
|
|
connect_bd_net -net dac_data_1_1 [get_bd_pins dac_data_1] [get_bd_pins data_concat0/In1]
|
|
connect_bd_net -net dac_data_2_1 [get_bd_pins dac_data_2] [get_bd_pins data_concat0/In2]
|
|
connect_bd_net -net dac_data_3_1 [get_bd_pins dac_data_3] [get_bd_pins data_concat0/In3]
|
|
connect_bd_net -net dac_dunf_1 [get_bd_pins dac_dunf] [get_bd_pins dac_tpl_core/dac_dunf]
|
|
connect_bd_net -net dac_sync_manual_req_in_1 [get_bd_pins dac_sync_manual_req_in] [get_bd_pins dac_tpl_core/dac_sync_manual_req_in]
|
|
connect_bd_net -net dac_tpl_core_dac_rst [get_bd_pins dac_tpl_core/dac_rst] [get_bd_pins dac_rst]
|
|
connect_bd_net -net dac_tpl_core_dac_sync_manual_req_out [get_bd_pins dac_tpl_core/dac_sync_manual_req_out] [get_bd_pins dac_sync_manual_req_out]
|
|
connect_bd_net -net dac_tpl_core_dac_valid [get_bd_pins dac_tpl_core/dac_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din]
|
|
connect_bd_net -net dac_tpl_core_enable [get_bd_pins dac_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din]
|
|
connect_bd_net -net data_concat0_dout [get_bd_pins data_concat0/dout] [get_bd_pins dac_tpl_core/dac_ddata]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins dac_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins dac_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins dac_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins dac_enable_3]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins dac_tpl_core/dac_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins dac_tpl_core/link_clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins dac_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins dac_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins dac_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins dac_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins dac_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins dac_valid_3]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_tx_jesd
|
|
proc create_hier_cell_axi_mxfe_tx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_tx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 tx_data
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy0
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy1
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy2
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 tx_phy3
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir I sysref
|
|
|
|
# Create instance: tx_axi, and set properties
|
|
set tx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_tx:1.0 tx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $tx_axi
|
|
|
|
|
|
# Create instance: tx, and set properties
|
|
set tx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_tx:1.0 tx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {8} \
|
|
] $tx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins tx_axi/s_axi]
|
|
connect_bd_intf_net -intf_net tx_axi_tx_cfg [get_bd_intf_pins tx_axi/tx_cfg] [get_bd_intf_pins tx/tx_cfg]
|
|
connect_bd_intf_net -intf_net tx_data_1 [get_bd_intf_pins tx_data] [get_bd_intf_pins tx/tx_data]
|
|
connect_bd_intf_net -intf_net tx_tx_event [get_bd_intf_pins tx/tx_event] [get_bd_intf_pins tx_axi/tx_event]
|
|
connect_bd_intf_net -intf_net tx_tx_phy0 [get_bd_intf_pins tx/tx_phy0] [get_bd_intf_pins tx_phy0]
|
|
connect_bd_intf_net -intf_net tx_tx_phy1 [get_bd_intf_pins tx/tx_phy1] [get_bd_intf_pins tx_phy1]
|
|
connect_bd_intf_net -intf_net tx_tx_phy2 [get_bd_intf_pins tx/tx_phy2] [get_bd_intf_pins tx_phy2]
|
|
connect_bd_intf_net -intf_net tx_tx_phy3 [get_bd_intf_pins tx/tx_phy3] [get_bd_intf_pins tx_phy3]
|
|
connect_bd_intf_net -intf_net tx_tx_status [get_bd_intf_pins tx/tx_status] [get_bd_intf_pins tx_axi/tx_status]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins tx/device_clk] [get_bd_pins tx_axi/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins tx/clk] [get_bd_pins tx_axi/core_clk]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins tx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins tx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins tx/sysref]
|
|
connect_bd_net -net tx_axi_core_reset [get_bd_pins tx_axi/core_reset] [get_bd_pins tx/reset]
|
|
connect_bd_net -net tx_axi_device_reset [get_bd_pins tx_axi/device_reset] [get_bd_pins tx/device_reset]
|
|
connect_bd_net -net tx_axi_irq [get_bd_pins tx_axi/irq] [get_bd_pins irq]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: mxfe_rx_data_offload
|
|
proc create_hier_cell_mxfe_rx_data_offload { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_mxfe_rx_data_offload() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk s_axis_aclk
|
|
create_bd_pin -dir I -type rst s_axis_aresetn
|
|
create_bd_pin -dir I -type clk m_axis_aclk
|
|
create_bd_pin -dir I -type rst m_axis_aresetn
|
|
create_bd_pin -dir I init_req
|
|
create_bd_pin -dir I sync_ext
|
|
|
|
# Create instance: i_data_offload, and set properties
|
|
set i_data_offload [ create_bd_cell -type ip -vlnv analog.com:user:data_offload:1.0 i_data_offload ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.MEM_SIZE_LOG2 {19} \
|
|
CONFIG.MEM_TYPE {0} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
CONFIG.SYNC_EXT_ADD_INTERNAL_CDC {true} \
|
|
CONFIG.TX_OR_RXN_PATH {0} \
|
|
] $i_data_offload
|
|
|
|
|
|
# Create instance: storage_unit, and set properties
|
|
set storage_unit [ create_bd_cell -type ip -vlnv analog.com:user:util_do_ram:1.0 storage_unit ]
|
|
set_property -dict [list \
|
|
CONFIG.DST_DATA_WIDTH {256} \
|
|
CONFIG.LENGTH_WIDTH {19} \
|
|
CONFIG.SRC_DATA_WIDTH {256} \
|
|
] $storage_unit
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net i_data_offload_m_axis [get_bd_intf_pins m_axis] [get_bd_intf_pins i_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_m_storage_axis [get_bd_intf_pins storage_unit/s_axis] [get_bd_intf_pins i_data_offload/m_storage_axis]
|
|
connect_bd_intf_net -intf_net i_data_offload_rd_ctrl [get_bd_intf_pins storage_unit/rd_ctrl] [get_bd_intf_pins i_data_offload/rd_ctrl]
|
|
connect_bd_intf_net -intf_net i_data_offload_wr_ctrl [get_bd_intf_pins storage_unit/wr_ctrl] [get_bd_intf_pins i_data_offload/wr_ctrl]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins i_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins i_data_offload/s_axis]
|
|
connect_bd_intf_net -intf_net storage_unit_m_axis [get_bd_intf_pins storage_unit/m_axis] [get_bd_intf_pins i_data_offload/s_storage_axis]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net init_req_1 [get_bd_pins init_req] [get_bd_pins i_data_offload/init_req]
|
|
connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins i_data_offload/m_axis_aclk] [get_bd_pins storage_unit/m_axis_aclk]
|
|
connect_bd_net -net m_axis_aresetn_1 [get_bd_pins m_axis_aresetn] [get_bd_pins i_data_offload/m_axis_aresetn] [get_bd_pins storage_unit/m_axis_aresetn]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins i_data_offload/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins i_data_offload/s_axi_aresetn]
|
|
connect_bd_net -net s_axis_aclk_1 [get_bd_pins s_axis_aclk] [get_bd_pins i_data_offload/s_axis_aclk] [get_bd_pins storage_unit/s_axis_aclk]
|
|
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins s_axis_aresetn] [get_bd_pins i_data_offload/s_axis_aresetn] [get_bd_pins storage_unit/s_axis_aresetn]
|
|
connect_bd_net -net sync_ext_1 [get_bd_pins sync_ext] [get_bd_pins i_data_offload/sync_ext]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: rx_mxfe_tpl_core
|
|
proc create_hier_cell_rx_mxfe_tpl_core { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rx_mxfe_tpl_core() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -from 7 -to 0 link_sof
|
|
create_bd_pin -dir I link_valid
|
|
create_bd_pin -dir I -from 255 -to 0 link_data
|
|
create_bd_pin -dir I adc_dovf
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_0
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_0
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_1
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_1
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_2
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_2
|
|
create_bd_pin -dir O -from 0 -to 0 adc_enable_3
|
|
create_bd_pin -dir O -from 0 -to 0 adc_valid_3
|
|
create_bd_pin -dir O -from 63 -to 0 adc_data_3
|
|
create_bd_pin -dir I ext_sync_in
|
|
create_bd_pin -dir O adc_sync_manual_req_out
|
|
create_bd_pin -dir I adc_sync_manual_req_in
|
|
create_bd_pin -dir O adc_rst
|
|
|
|
# Create instance: adc_tpl_core, and set properties
|
|
set adc_tpl_core [ create_bd_cell -type ip -vlnv analog.com:user:ad_ip_jesd204_tpl_adc:1.0 adc_tpl_core ]
|
|
set_property -dict [list \
|
|
CONFIG.BITS_PER_SAMPLE {16} \
|
|
CONFIG.CONVERTER_RESOLUTION {16} \
|
|
CONFIG.DMA_BITS_PER_SAMPLE {16} \
|
|
CONFIG.EXT_SYNC {1} \
|
|
CONFIG.NUM_CHANNELS {4} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.OCTETS_PER_BEAT {8} \
|
|
CONFIG.SAMPLES_PER_FRAME {1} \
|
|
] $adc_tpl_core
|
|
|
|
|
|
# Create instance: data_slice_0, and set properties
|
|
set data_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {63} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_0
|
|
|
|
|
|
# Create instance: enable_slice_0, and set properties
|
|
set enable_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_0
|
|
|
|
|
|
# Create instance: valid_slice_0, and set properties
|
|
set valid_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {0} \
|
|
CONFIG.DIN_TO {0} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_0
|
|
|
|
|
|
# Create instance: data_slice_1, and set properties
|
|
set data_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {127} \
|
|
CONFIG.DIN_TO {64} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_1
|
|
|
|
|
|
# Create instance: enable_slice_1, and set properties
|
|
set enable_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_1
|
|
|
|
|
|
# Create instance: valid_slice_1, and set properties
|
|
set valid_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {1} \
|
|
CONFIG.DIN_TO {1} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_1
|
|
|
|
|
|
# Create instance: data_slice_2, and set properties
|
|
set data_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {191} \
|
|
CONFIG.DIN_TO {128} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_2
|
|
|
|
|
|
# Create instance: enable_slice_2, and set properties
|
|
set enable_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_2
|
|
|
|
|
|
# Create instance: valid_slice_2, and set properties
|
|
set valid_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {2} \
|
|
CONFIG.DIN_TO {2} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_2
|
|
|
|
|
|
# Create instance: data_slice_3, and set properties
|
|
set data_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {255} \
|
|
CONFIG.DIN_TO {192} \
|
|
CONFIG.DIN_WIDTH {256} \
|
|
CONFIG.DOUT_WIDTH {64} \
|
|
] $data_slice_3
|
|
|
|
|
|
# Create instance: enable_slice_3, and set properties
|
|
set enable_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 enable_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $enable_slice_3
|
|
|
|
|
|
# Create instance: valid_slice_3, and set properties
|
|
set valid_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 valid_slice_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {3} \
|
|
CONFIG.DIN_TO {3} \
|
|
CONFIG.DIN_WIDTH {4} \
|
|
] $valid_slice_3
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins adc_tpl_core/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net adc_dovf_1 [get_bd_pins adc_dovf] [get_bd_pins adc_tpl_core/adc_dovf]
|
|
connect_bd_net -net adc_sync_manual_req_in_1 [get_bd_pins adc_sync_manual_req_in] [get_bd_pins adc_tpl_core/adc_sync_manual_req_in]
|
|
connect_bd_net -net adc_tpl_core_adc_data [get_bd_pins adc_tpl_core/adc_data] [get_bd_pins data_slice_0/Din] [get_bd_pins data_slice_1/Din] [get_bd_pins data_slice_2/Din] [get_bd_pins data_slice_3/Din]
|
|
connect_bd_net -net adc_tpl_core_adc_rst [get_bd_pins adc_tpl_core/adc_rst] [get_bd_pins adc_rst]
|
|
connect_bd_net -net adc_tpl_core_adc_sync_manual_req_out [get_bd_pins adc_tpl_core/adc_sync_manual_req_out] [get_bd_pins adc_sync_manual_req_out]
|
|
connect_bd_net -net adc_tpl_core_adc_valid [get_bd_pins adc_tpl_core/adc_valid] [get_bd_pins valid_slice_0/Din] [get_bd_pins valid_slice_1/Din] [get_bd_pins valid_slice_2/Din] [get_bd_pins valid_slice_3/Din]
|
|
connect_bd_net -net adc_tpl_core_enable [get_bd_pins adc_tpl_core/enable] [get_bd_pins enable_slice_0/Din] [get_bd_pins enable_slice_1/Din] [get_bd_pins enable_slice_2/Din] [get_bd_pins enable_slice_3/Din]
|
|
connect_bd_net -net data_slice_0_Dout [get_bd_pins data_slice_0/Dout] [get_bd_pins adc_data_0]
|
|
connect_bd_net -net data_slice_1_Dout [get_bd_pins data_slice_1/Dout] [get_bd_pins adc_data_1]
|
|
connect_bd_net -net data_slice_2_Dout [get_bd_pins data_slice_2/Dout] [get_bd_pins adc_data_2]
|
|
connect_bd_net -net data_slice_3_Dout [get_bd_pins data_slice_3/Dout] [get_bd_pins adc_data_3]
|
|
connect_bd_net -net enable_slice_0_Dout [get_bd_pins enable_slice_0/Dout] [get_bd_pins adc_enable_0]
|
|
connect_bd_net -net enable_slice_1_Dout [get_bd_pins enable_slice_1/Dout] [get_bd_pins adc_enable_1]
|
|
connect_bd_net -net enable_slice_2_Dout [get_bd_pins enable_slice_2/Dout] [get_bd_pins adc_enable_2]
|
|
connect_bd_net -net enable_slice_3_Dout [get_bd_pins enable_slice_3/Dout] [get_bd_pins adc_enable_3]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_pins ext_sync_in] [get_bd_pins adc_tpl_core/adc_sync_in]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins adc_tpl_core/link_clk]
|
|
connect_bd_net -net link_data_1 [get_bd_pins link_data] [get_bd_pins adc_tpl_core/link_data]
|
|
connect_bd_net -net link_sof_1 [get_bd_pins link_sof] [get_bd_pins adc_tpl_core/link_sof]
|
|
connect_bd_net -net link_valid_1 [get_bd_pins link_valid] [get_bd_pins adc_tpl_core/link_valid]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins adc_tpl_core/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins adc_tpl_core/s_axi_aresetn]
|
|
connect_bd_net -net valid_slice_0_Dout [get_bd_pins valid_slice_0/Dout] [get_bd_pins adc_valid_0]
|
|
connect_bd_net -net valid_slice_1_Dout [get_bd_pins valid_slice_1/Dout] [get_bd_pins adc_valid_1]
|
|
connect_bd_net -net valid_slice_2_Dout [get_bd_pins valid_slice_2/Dout] [get_bd_pins adc_valid_2]
|
|
connect_bd_net -net valid_slice_3_Dout [get_bd_pins valid_slice_3/Dout] [get_bd_pins adc_valid_3]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: axi_mxfe_rx_jesd
|
|
proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_mxfe_rx_jesd() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy0
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy1
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy2
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 rx_phy3
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir I -type clk s_axi_aclk
|
|
create_bd_pin -dir I -type rst s_axi_aresetn
|
|
create_bd_pin -dir O -type intr irq
|
|
create_bd_pin -dir I -type clk link_clk
|
|
create_bd_pin -dir I -type clk device_clk
|
|
create_bd_pin -dir I sysref
|
|
create_bd_pin -dir O -from 7 -to 0 rx_eof
|
|
create_bd_pin -dir O -from 7 -to 0 rx_sof
|
|
create_bd_pin -dir O rx_data_tvalid
|
|
create_bd_pin -dir O -from 255 -to 0 rx_data_tdata
|
|
|
|
# Create instance: rx_axi, and set properties
|
|
set rx_axi [ create_bd_cell -type ip -vlnv analog.com:user:axi_jesd204_rx:1.0 rx_axi ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
] $rx_axi
|
|
|
|
|
|
# Create instance: rx, and set properties
|
|
set rx [ create_bd_cell -type ip -vlnv analog.com:user:jesd204_rx:1.0 rx ]
|
|
set_property -dict [list \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.NUM_INPUT_PIPELINE {1} \
|
|
CONFIG.NUM_LANES {4} \
|
|
CONFIG.NUM_LINKS {1} \
|
|
CONFIG.SYSREF_IOB {false} \
|
|
CONFIG.TPL_DATA_PATH_WIDTH {8} \
|
|
] $rx
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net rx_axi_rx_cfg [get_bd_intf_pins rx_axi/rx_cfg] [get_bd_intf_pins rx/rx_cfg]
|
|
connect_bd_intf_net -intf_net rx_phy0_1 [get_bd_intf_pins rx/rx_phy0] [get_bd_intf_pins rx_phy0]
|
|
connect_bd_intf_net -intf_net rx_phy1_1 [get_bd_intf_pins rx/rx_phy1] [get_bd_intf_pins rx_phy1]
|
|
connect_bd_intf_net -intf_net rx_phy2_1 [get_bd_intf_pins rx/rx_phy2] [get_bd_intf_pins rx_phy2]
|
|
connect_bd_intf_net -intf_net rx_phy3_1 [get_bd_intf_pins rx/rx_phy3] [get_bd_intf_pins rx_phy3]
|
|
connect_bd_intf_net -intf_net rx_rx_event [get_bd_intf_pins rx/rx_event] [get_bd_intf_pins rx_axi/rx_event]
|
|
connect_bd_intf_net -intf_net rx_rx_status [get_bd_intf_pins rx/rx_status] [get_bd_intf_pins rx_axi/rx_status]
|
|
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins rx_axi/s_axi]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net device_clk_1 [get_bd_pins device_clk] [get_bd_pins rx/device_clk] [get_bd_pins rx_axi/device_clk]
|
|
connect_bd_net -net link_clk_1 [get_bd_pins link_clk] [get_bd_pins rx/clk] [get_bd_pins rx_axi/core_clk]
|
|
connect_bd_net -net rx_axi_core_reset [get_bd_pins rx_axi/core_reset] [get_bd_pins rx/reset]
|
|
connect_bd_net -net rx_axi_device_reset [get_bd_pins rx_axi/device_reset] [get_bd_pins rx/device_reset]
|
|
connect_bd_net -net rx_axi_irq [get_bd_pins rx_axi/irq] [get_bd_pins irq]
|
|
connect_bd_net -net rx_rx_data [get_bd_pins rx/rx_data] [get_bd_pins rx_data_tdata]
|
|
connect_bd_net -net rx_rx_eof [get_bd_pins rx/rx_eof] [get_bd_pins rx_eof]
|
|
connect_bd_net -net rx_rx_sof [get_bd_pins rx/rx_sof] [get_bd_pins rx_sof]
|
|
connect_bd_net -net rx_rx_valid [get_bd_pins rx/rx_valid] [get_bd_pins rx_data_tvalid]
|
|
connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins rx_axi/s_axi_aclk]
|
|
connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins rx_axi/s_axi_aresetn]
|
|
connect_bd_net -net sysref_1 [get_bd_pins sysref] [get_bd_pins rx/sysref]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" } {
|
|
set parentCell [get_bd_cells /]
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
|
|
# Create interface ports
|
|
set M11_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M11_AXI_0 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ADDR_WIDTH {32} \
|
|
CONFIG.DATA_WIDTH {32} \
|
|
CONFIG.PROTOCOL {AXI4} \
|
|
] $M11_AXI_0
|
|
|
|
set mxfe_tx_data_offload_m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 mxfe_tx_data_offload_m_axis ]
|
|
|
|
set util_mxfe_upack_s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 util_mxfe_upack_s_axis ]
|
|
set_property -dict [ list \
|
|
CONFIG.HAS_TKEEP {0} \
|
|
CONFIG.HAS_TLAST {0} \
|
|
CONFIG.HAS_TREADY {1} \
|
|
CONFIG.HAS_TSTRB {0} \
|
|
CONFIG.LAYERED_METADATA {undef} \
|
|
CONFIG.TDATA_NUM_BYTES {32} \
|
|
CONFIG.TDEST_WIDTH {0} \
|
|
CONFIG.TID_WIDTH {0} \
|
|
CONFIG.TUSER_WIDTH {0} \
|
|
] $util_mxfe_upack_s_axis
|
|
|
|
|
|
# Create ports
|
|
set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ]
|
|
set spi0_sclk [ create_bd_port -dir O spi0_sclk ]
|
|
set spi0_mosi [ create_bd_port -dir O spi0_mosi ]
|
|
set spi0_miso [ create_bd_port -dir I spi0_miso ]
|
|
set spi1_csn [ create_bd_port -dir O -from 2 -to 0 spi1_csn ]
|
|
set spi1_sclk [ create_bd_port -dir O spi1_sclk ]
|
|
set spi1_mosi [ create_bd_port -dir O spi1_mosi ]
|
|
set spi1_miso [ create_bd_port -dir I spi1_miso ]
|
|
set gpio_i [ create_bd_port -dir I -from 94 -to 0 gpio_i ]
|
|
set gpio_o [ create_bd_port -dir O -from 94 -to 0 gpio_o ]
|
|
set gpio_t [ create_bd_port -dir O -from 94 -to 0 gpio_t ]
|
|
set rx_device_clk [ create_bd_port -dir I rx_device_clk ]
|
|
set tx_device_clk [ create_bd_port -dir I tx_device_clk ]
|
|
set ref_clk_q0 [ create_bd_port -dir I ref_clk_q0 ]
|
|
set ref_clk_q1 [ create_bd_port -dir I ref_clk_q1 ]
|
|
set rx_sysref_0 [ create_bd_port -dir I rx_sysref_0 ]
|
|
set rx_sync_0 [ create_bd_port -dir O -from 0 -to 0 rx_sync_0 ]
|
|
set rx_data_0_p [ create_bd_port -dir I rx_data_0_p ]
|
|
set rx_data_0_n [ create_bd_port -dir I rx_data_0_n ]
|
|
set rx_data_1_p [ create_bd_port -dir I rx_data_1_p ]
|
|
set rx_data_1_n [ create_bd_port -dir I rx_data_1_n ]
|
|
set rx_data_2_p [ create_bd_port -dir I rx_data_2_p ]
|
|
set rx_data_2_n [ create_bd_port -dir I rx_data_2_n ]
|
|
set rx_data_3_p [ create_bd_port -dir I rx_data_3_p ]
|
|
set rx_data_3_n [ create_bd_port -dir I rx_data_3_n ]
|
|
set tx_sysref_0 [ create_bd_port -dir I tx_sysref_0 ]
|
|
set tx_sync_0 [ create_bd_port -dir I -from 0 -to 0 tx_sync_0 ]
|
|
set tx_data_0_p [ create_bd_port -dir O tx_data_0_p ]
|
|
set tx_data_0_n [ create_bd_port -dir O tx_data_0_n ]
|
|
set tx_data_1_p [ create_bd_port -dir O tx_data_1_p ]
|
|
set tx_data_1_n [ create_bd_port -dir O tx_data_1_n ]
|
|
set tx_data_2_p [ create_bd_port -dir O tx_data_2_p ]
|
|
set tx_data_2_n [ create_bd_port -dir O tx_data_2_n ]
|
|
set tx_data_3_p [ create_bd_port -dir O tx_data_3_p ]
|
|
set tx_data_3_n [ create_bd_port -dir O tx_data_3_n ]
|
|
set rx_data_4_n [ create_bd_port -dir I rx_data_4_n ]
|
|
set rx_data_4_p [ create_bd_port -dir I rx_data_4_p ]
|
|
set rx_data_5_n [ create_bd_port -dir I rx_data_5_n ]
|
|
set rx_data_5_p [ create_bd_port -dir I rx_data_5_p ]
|
|
set rx_data_6_n [ create_bd_port -dir I rx_data_6_n ]
|
|
set rx_data_6_p [ create_bd_port -dir I rx_data_6_p ]
|
|
set rx_data_7_n [ create_bd_port -dir I rx_data_7_n ]
|
|
set rx_data_7_p [ create_bd_port -dir I rx_data_7_p ]
|
|
set tx_data_4_n [ create_bd_port -dir O tx_data_4_n ]
|
|
set tx_data_4_p [ create_bd_port -dir O tx_data_4_p ]
|
|
set tx_data_5_n [ create_bd_port -dir O tx_data_5_n ]
|
|
set tx_data_5_p [ create_bd_port -dir O tx_data_5_p ]
|
|
set tx_data_6_n [ create_bd_port -dir O tx_data_6_n ]
|
|
set tx_data_6_p [ create_bd_port -dir O tx_data_6_p ]
|
|
set tx_data_7_n [ create_bd_port -dir O tx_data_7_n ]
|
|
set tx_data_7_p [ create_bd_port -dir O tx_data_7_p ]
|
|
set ext_sync_in [ create_bd_port -dir I ext_sync_in ]
|
|
set pl_clk3_0 [ create_bd_port -dir O -type clk pl_clk3_0 ]
|
|
set pl_clk2_clk125 [ create_bd_port -dir O -type clk pl_clk2_clk125 ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_RESET {pl_clk2_clk125_aresetn_out} \
|
|
] $pl_clk2_clk125
|
|
set pl_clk2_clk125_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst pl_clk2_clk125_aresetn_out ]
|
|
set clk_250_out [ create_bd_port -dir O -type clk clk_250_out ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_RESET {clk_250_aresetn_out} \
|
|
] $clk_250_out
|
|
set clk_250_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst clk_250_aresetn_out ]
|
|
set tx_device_clk_out [ create_bd_port -dir O -type clk tx_device_clk_out ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {util_mxfe_upack_s_axis:mxfe_tx_data_offload_m_axis} \
|
|
] $tx_device_clk_out
|
|
set tx_device_clk_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst tx_device_clk_aresetn_out ]
|
|
set rx_device_clk_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst rx_device_clk_aresetn_out ]
|
|
set rx_device_clk_out [ create_bd_port -dir O -type clk rx_device_clk_out ]
|
|
set sys_cpu_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst sys_cpu_aresetn_out ]
|
|
set sys_cpu_clk_out [ create_bd_port -dir O -type clk sys_cpu_clk_out ]
|
|
set_property -dict [ list \
|
|
CONFIG.ASSOCIATED_BUSIF {M11_AXI_0} \
|
|
] $sys_cpu_clk_out
|
|
set packed_fifo_wr_en_out [ create_bd_port -dir O -type data packed_fifo_wr_en_out ]
|
|
set packed_fifo_wr_data_out [ create_bd_port -dir O -from 255 -to 0 -type data packed_fifo_wr_data_out ]
|
|
set packed_fifo_wr_overflow_out [ create_bd_port -dir O -type data packed_fifo_wr_overflow_out ]
|
|
|
|
# Create instance: sys_ps8, and set properties
|
|
set sys_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 sys_ps8 ]
|
|
set_property -dict [list \
|
|
CONFIG.CAN0_BOARD_INTERFACE {custom} \
|
|
CONFIG.CAN1_BOARD_INTERFACE {custom} \
|
|
CONFIG.CSU_BOARD_INTERFACE {custom} \
|
|
CONFIG.DP_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM0_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM1_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM2_BOARD_INTERFACE {custom} \
|
|
CONFIG.GEM3_BOARD_INTERFACE {custom} \
|
|
CONFIG.GPIO_BOARD_INTERFACE {custom} \
|
|
CONFIG.IIC0_BOARD_INTERFACE {custom} \
|
|
CONFIG.IIC1_BOARD_INTERFACE {custom} \
|
|
CONFIG.NAND_BOARD_INTERFACE {custom} \
|
|
CONFIG.PCIE_BOARD_INTERFACE {custom} \
|
|
CONFIG.PJTAG_BOARD_INTERFACE {custom} \
|
|
CONFIG.PMU_BOARD_INTERFACE {custom} \
|
|
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
|
|
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
|
|
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
|
|
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \
|
|
CONFIG.PSU_IMPORT_BOARD_PRESET {} \
|
|
CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_0_SLEW {fast} \
|
|
CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_10_SLEW {fast} \
|
|
CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_11_SLEW {fast} \
|
|
CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_12_SLEW {fast} \
|
|
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_13_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_13_SLEW {fast} \
|
|
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_14_SLEW {fast} \
|
|
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_15_SLEW {fast} \
|
|
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_16_SLEW {fast} \
|
|
CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_17_SLEW {fast} \
|
|
CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_19_SLEW {fast} \
|
|
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_1_SLEW {fast} \
|
|
CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_20_SLEW {fast} \
|
|
CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_22_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_22_SLEW {fast} \
|
|
CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_23_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_23_SLEW {fast} \
|
|
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_24_SLEW {fast} \
|
|
CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_26_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_26_SLEW {fast} \
|
|
CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_27_SLEW {fast} \
|
|
CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_29_SLEW {fast} \
|
|
CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_2_SLEW {fast} \
|
|
CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_31_SLEW {fast} \
|
|
CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_32_SLEW {fast} \
|
|
CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_33_SLEW {fast} \
|
|
CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_34_SLEW {fast} \
|
|
CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_35_SLEW {fast} \
|
|
CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_36_SLEW {fast} \
|
|
CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_37_SLEW {fast} \
|
|
CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_38_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_38_SLEW {fast} \
|
|
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_39_SLEW {fast} \
|
|
CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_3_SLEW {fast} \
|
|
CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_40_SLEW {fast} \
|
|
CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_41_SLEW {fast} \
|
|
CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_42_SLEW {fast} \
|
|
CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_43_POLARITY {Default} \
|
|
CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_43_SLEW {fast} \
|
|
CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_46_SLEW {fast} \
|
|
CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_47_SLEW {fast} \
|
|
CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_48_SLEW {fast} \
|
|
CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_49_SLEW {fast} \
|
|
CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_4_SLEW {fast} \
|
|
CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_50_SLEW {fast} \
|
|
CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_51_SLEW {fast} \
|
|
CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_54_SLEW {fast} \
|
|
CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_56_SLEW {fast} \
|
|
CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_57_SLEW {fast} \
|
|
CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_58_SLEW {fast} \
|
|
CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_59_SLEW {fast} \
|
|
CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_5_SLEW {fast} \
|
|
CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_60_SLEW {fast} \
|
|
CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_61_SLEW {fast} \
|
|
CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_62_SLEW {fast} \
|
|
CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_63_SLEW {fast} \
|
|
CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_64_SLEW {fast} \
|
|
CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_65_SLEW {fast} \
|
|
CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_66_SLEW {fast} \
|
|
CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_67_SLEW {fast} \
|
|
CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_68_SLEW {fast} \
|
|
CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_69_SLEW {fast} \
|
|
CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_6_SLEW {fast} \
|
|
CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_76_SLEW {fast} \
|
|
CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_77_SLEW {fast} \
|
|
CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_7_SLEW {fast} \
|
|
CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_8_SLEW {fast} \
|
|
CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
|
|
CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
|
|
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
|
|
CONFIG.PSU_MIO_9_SLEW {fast} \
|
|
CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
|
|
SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#PCIE#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU\
|
|
GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
|
|
3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
|
|
CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#reset_n#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
|
|
\
|
|
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
|
|
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
|
|
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
|
|
CONFIG.PSU_SMC_CYCLE_T0 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T1 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T2 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T3 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T4 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T5 {NA} \
|
|
CONFIG.PSU_SMC_CYCLE_T6 {NA} \
|
|
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
|
|
CONFIG.PSU_VALUE_SILVERSION {3} \
|
|
CONFIG.PSU__ACPU0__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU1__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU2__POWER__ON {1} \
|
|
CONFIG.PSU__ACPU3__POWER__ON {1} \
|
|
CONFIG.PSU__ACTUAL__IP {1} \
|
|
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
|
|
CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
|
|
CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
|
|
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
|
|
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
|
|
CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
|
|
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666666} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
|
|
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
|
|
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
|
|
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
|
|
CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
|
|
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
|
|
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
|
|
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
|
|
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
|
|
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
|
|
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
|
|
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {75.000000} \
|
|
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {75} \
|
|
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
|
|
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
|
|
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
|
|
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
|
|
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
|
|
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
|
|
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
|
|
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
|
|
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
|
|
CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
|
|
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__DDRC__AL {0} \
|
|
CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
|
|
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
|
|
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
|
|
CONFIG.PSU__DDRC__CL {15} \
|
|
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
|
|
CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
|
|
CONFIG.PSU__DDRC__CWL {14} \
|
|
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
|
|
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
|
|
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
|
|
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
|
|
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
|
|
CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
|
|
CONFIG.PSU__DDRC__ECC {Disabled} \
|
|
CONFIG.PSU__DDRC__ECC_SCRUB {0} \
|
|
CONFIG.PSU__DDRC__ENABLE {1} \
|
|
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
|
|
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
|
|
CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
|
|
CONFIG.PSU__DDRC__FGRM {1X} \
|
|
CONFIG.PSU__DDRC__FREQ_MHZ {1} \
|
|
CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
|
|
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
|
|
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
|
|
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
|
|
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
|
|
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
|
|
CONFIG.PSU__DDRC__PLL_BYPASS {0} \
|
|
CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
|
|
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
|
|
CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
|
|
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
|
|
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
|
|
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
|
|
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
|
|
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
|
|
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
|
|
CONFIG.PSU__DDRC__T_FAW {30.0} \
|
|
CONFIG.PSU__DDRC__T_RAS_MIN {33} \
|
|
CONFIG.PSU__DDRC__T_RC {47.06} \
|
|
CONFIG.PSU__DDRC__T_RCD {15} \
|
|
CONFIG.PSU__DDRC__T_RP {15} \
|
|
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
|
|
CONFIG.PSU__DDRC__VREF {1} \
|
|
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
|
|
CONFIG.PSU__DDR_QOS_ENABLE {0} \
|
|
CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
|
|
CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
|
|
CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
|
|
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
|
|
CONFIG.PSU__DEVICE_TYPE {EG} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
|
|
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \
|
|
CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__DLL__ISUSED {1} \
|
|
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
|
|
CONFIG.PSU__DP__LANE_SEL {Single Lower} \
|
|
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
|
|
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
|
|
CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
|
|
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
|
|
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
|
|
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
|
|
CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
|
|
CONFIG.PSU__EN_EMIO_TRACE {0} \
|
|
CONFIG.PSU__EP__IP {0} \
|
|
CONFIG.PSU__EXPAND__CORESIGHT {0} \
|
|
CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
|
|
CONFIG.PSU__EXPAND__GIC {0} \
|
|
CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
|
|
CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
|
|
CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
|
|
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL2_ENABLE {1} \
|
|
CONFIG.PSU__FPGA_PL3_ENABLE {1} \
|
|
CONFIG.PSU__FP__POWER__ON {1} \
|
|
CONFIG.PSU__FTM__CTI_IN_0 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_1 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_2 {0} \
|
|
CONFIG.PSU__FTM__CTI_IN_3 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_0 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_1 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_2 {0} \
|
|
CONFIG.PSU__FTM__CTI_OUT_3 {0} \
|
|
CONFIG.PSU__FTM__GPI {0} \
|
|
CONFIG.PSU__FTM__GPO {0} \
|
|
CONFIG.PSU__GEM3_COHERENCY {0} \
|
|
CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__GEM__TSU__ENABLE {0} \
|
|
CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
|
|
CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
|
|
CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
|
|
CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
|
|
CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
|
|
CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
|
|
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
|
|
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
|
|
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \
|
|
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
|
|
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
|
|
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
|
|
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__GT__LINK_SPEED {HBR} \
|
|
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
|
|
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
|
|
CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
|
|
CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
|
|
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
|
|
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
|
|
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
|
|
CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
|
|
CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
|
|
CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
|
|
CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
|
|
CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
|
|
CONFIG.PSU__L2_BANK0__POWER__ON {1} \
|
|
CONFIG.PSU__LPDMA0_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA1_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA2_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA3_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA4_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA5_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA6_COHERENCY {0} \
|
|
CONFIG.PSU__LPDMA7_COHERENCY {0} \
|
|
CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
|
|
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
|
|
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
|
|
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
|
|
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
|
|
CONFIG.PSU__NUM_FABRIC_RESETS {1} \
|
|
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
|
|
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
|
|
CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
|
|
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
|
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
|
|
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
|
|
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__BAR0_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__BAR1_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR2_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR3_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR4_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__BAR5_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
|
|
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {0x60400} \
|
|
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
|
|
CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
|
|
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
|
|
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__EROM_VAL {0x0} \
|
|
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
|
|
CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
|
|
CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
|
|
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
|
|
CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
|
|
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
|
|
CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {256 bytes} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {1} \
|
|
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
|
|
CONFIG.PSU__PCIE__REF_CLK_FREQ {100} \
|
|
CONFIG.PSU__PCIE__REF_CLK_SEL {Ref Clk0} \
|
|
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__PCIE__REVISION_ID {0x0} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \
|
|
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \
|
|
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK1_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK2_BUF {TRUE} \
|
|
CONFIG.PSU__PL_CLK3_BUF {TRUE} \
|
|
CONFIG.PSU__PL__POWER__ON {1} \
|
|
CONFIG.PSU__PMU_COHERENCY {0} \
|
|
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
|
|
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
|
|
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
|
|
CONFIG.PSU__PMU__GPO0__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
|
|
CONFIG.PSU__PMU__GPO1__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
|
|
CONFIG.PSU__PMU__GPO2__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
|
|
CONFIG.PSU__PMU__GPO2__POLARITY {high} \
|
|
CONFIG.PSU__PMU__GPO3__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO3__IO {MIO 35} \
|
|
CONFIG.PSU__PMU__GPO3__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO4__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO4__IO {MIO 36} \
|
|
CONFIG.PSU__PMU__GPO4__POLARITY {low} \
|
|
CONFIG.PSU__PMU__GPO5__ENABLE {1} \
|
|
CONFIG.PSU__PMU__GPO5__IO {MIO 37} \
|
|
CONFIG.PSU__PMU__GPO5__POLARITY {low} \
|
|
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
|
|
CONFIG.PSU__PRESET_APPLIED {1} \
|
|
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
|
|
CONFIG.PSU__PROTECTION__ENABLE {0} \
|
|
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
|
|
subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
|
|
Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
|
|
| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
|
|
| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
|
|
subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
|
|
Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
|
|
SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\
|
|
; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\
|
|
; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
|
|
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;1|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
|
|
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
|
|
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;1|FPD;PCIE_LOW;E0000000;EFFFFFFF;1|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;1|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;1|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;1|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;1|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
|
|
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
|
|
\
|
|
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
|
|
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
|
|
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333333} \
|
|
CONFIG.PSU__QSPI_COHERENCY {0} \
|
|
CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
|
|
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
|
|
CONFIG.PSU__REPORT__DBGLOG {0} \
|
|
CONFIG.PSU__RPU_COHERENCY {0} \
|
|
CONFIG.PSU__RPU__POWER__ON {1} \
|
|
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
|
|
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
|
|
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
|
|
CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
|
|
CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
|
|
CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x00} \
|
|
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__SD0__RESET__ENABLE {0} \
|
|
CONFIG.PSU__SD1_COHERENCY {0} \
|
|
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
|
|
CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \
|
|
CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x3} \
|
|
CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x3D} \
|
|
CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x4} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
|
|
CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
|
|
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \
|
|
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
|
|
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
|
|
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
|
|
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
|
|
CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \
|
|
CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \
|
|
CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
|
|
CONFIG.PSU__SPI0__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS0__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS1__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__GRP_SS2__IO {EMIO} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
|
|
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
|
|
CONFIG.PSU__TCM0A__POWER__ON {1} \
|
|
CONFIG.PSU__TCM0B__POWER__ON {1} \
|
|
CONFIG.PSU__TCM1A__POWER__ON {1} \
|
|
CONFIG.PSU__TCM1B__POWER__ON {1} \
|
|
CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
|
|
CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__TRISTATE__INVERTED {1} \
|
|
CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
|
|
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
|
|
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
|
|
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
|
|
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
|
|
CONFIG.PSU__UART0__BAUD_RATE {115200} \
|
|
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
|
|
CONFIG.PSU__UART1__BAUD_RATE {115200} \
|
|
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
|
|
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
|
|
CONFIG.PSU__USB0_COHERENCY {0} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
|
|
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
|
|
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
|
|
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
|
|
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
|
|
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
|
|
CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
|
|
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
|
|
CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
|
|
CONFIG.PSU__USE__ADMA {0} \
|
|
CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
|
|
CONFIG.PSU__USE__AUDIO {0} \
|
|
CONFIG.PSU__USE__CLK {0} \
|
|
CONFIG.PSU__USE__CLK0 {0} \
|
|
CONFIG.PSU__USE__CLK1 {0} \
|
|
CONFIG.PSU__USE__CLK2 {0} \
|
|
CONFIG.PSU__USE__CLK3 {0} \
|
|
CONFIG.PSU__USE__CROSS_TRIGGER {0} \
|
|
CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
|
|
CONFIG.PSU__USE__DEBUG__TEST {0} \
|
|
CONFIG.PSU__USE__EVENT_RPU {0} \
|
|
CONFIG.PSU__USE__FABRIC__RST {1} \
|
|
CONFIG.PSU__USE__FTM {0} \
|
|
CONFIG.PSU__USE__GDMA {0} \
|
|
CONFIG.PSU__USE__IRQ {0} \
|
|
CONFIG.PSU__USE__IRQ0 {1} \
|
|
CONFIG.PSU__USE__IRQ1 {1} \
|
|
CONFIG.PSU__USE__M_AXI_GP0 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP1 {0} \
|
|
CONFIG.PSU__USE__M_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
|
|
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
|
|
CONFIG.PSU__USE__RST0 {0} \
|
|
CONFIG.PSU__USE__RST1 {0} \
|
|
CONFIG.PSU__USE__RST2 {0} \
|
|
CONFIG.PSU__USE__RST3 {0} \
|
|
CONFIG.PSU__USE__RTC {0} \
|
|
CONFIG.PSU__USE__STM {0} \
|
|
CONFIG.PSU__USE__S_AXI_ACE {0} \
|
|
CONFIG.PSU__USE__S_AXI_ACP {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP0 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP1 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP2 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP3 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP4 {1} \
|
|
CONFIG.PSU__USE__S_AXI_GP5 {0} \
|
|
CONFIG.PSU__USE__S_AXI_GP6 {0} \
|
|
CONFIG.PSU__USE__USB3_0_HUB {0} \
|
|
CONFIG.PSU__USE__USB3_1_HUB {0} \
|
|
CONFIG.PSU__USE__VIDEO {0} \
|
|
CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
|
|
CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
|
|
CONFIG.QSPI_BOARD_INTERFACE {custom} \
|
|
CONFIG.SATA_BOARD_INTERFACE {custom} \
|
|
CONFIG.SD0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SD1_BOARD_INTERFACE {custom} \
|
|
CONFIG.SPI0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SPI1_BOARD_INTERFACE {custom} \
|
|
CONFIG.SUBPRESET1 {Custom} \
|
|
CONFIG.SUBPRESET2 {Custom} \
|
|
CONFIG.SWDT0_BOARD_INTERFACE {custom} \
|
|
CONFIG.SWDT1_BOARD_INTERFACE {custom} \
|
|
CONFIG.TRACE_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC0_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC1_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC2_BOARD_INTERFACE {custom} \
|
|
CONFIG.TTC3_BOARD_INTERFACE {custom} \
|
|
CONFIG.UART0_BOARD_INTERFACE {custom} \
|
|
CONFIG.UART1_BOARD_INTERFACE {custom} \
|
|
CONFIG.USB0_BOARD_INTERFACE {custom} \
|
|
CONFIG.USB1_BOARD_INTERFACE {custom} \
|
|
] $sys_ps8
|
|
|
|
|
|
# Create instance: sys_rstgen, and set properties
|
|
set sys_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_rstgen
|
|
|
|
|
|
# Create instance: sys_250m_rstgen, and set properties
|
|
set sys_250m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_250m_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_250m_rstgen
|
|
|
|
|
|
# Create instance: sys_500m_rstgen, and set properties
|
|
set sys_500m_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_500m_rstgen ]
|
|
set_property CONFIG.C_EXT_RST_WIDTH {1} $sys_500m_rstgen
|
|
|
|
|
|
# Create instance: spi0_csn_concat, and set properties
|
|
set spi0_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi0_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi0_csn_concat
|
|
|
|
|
|
# Create instance: VCC_1, and set properties
|
|
set VCC_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 VCC_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {1} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $VCC_1
|
|
|
|
|
|
# Create instance: GND_1, and set properties
|
|
set GND_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 GND_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {1} \
|
|
] $GND_1
|
|
|
|
|
|
# Create instance: spi1_csn_concat, and set properties
|
|
set spi1_csn_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 spi1_csn_concat ]
|
|
set_property CONFIG.NUM_PORTS {3} $spi1_csn_concat
|
|
|
|
|
|
# Create instance: axi_sysid_0, and set properties
|
|
set axi_sysid_0 [ create_bd_cell -type ip -vlnv analog.com:user:axi_sysid:1.0 axi_sysid_0 ]
|
|
set_property CONFIG.ROM_ADDR_BITS {10} $axi_sysid_0
|
|
|
|
|
|
# Create instance: rom_sys_0, and set properties
|
|
set rom_sys_0 [ create_bd_cell -type ip -vlnv analog.com:user:sysid_rom:1.0 rom_sys_0 ]
|
|
set_property CONFIG.ROM_ADDR_BITS {10} $rom_sys_0
|
|
|
|
|
|
# Create instance: axi_cpu_interconnect, and set properties
|
|
set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {12} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_cpu_interconnect
|
|
|
|
|
|
# Create instance: sys_concat_intc_0, and set properties
|
|
set sys_concat_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_0
|
|
|
|
|
|
# Create instance: sys_concat_intc_1, and set properties
|
|
set sys_concat_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1 ]
|
|
set_property CONFIG.NUM_PORTS {8} $sys_concat_intc_1
|
|
|
|
|
|
# Create instance: axi_hp0_interconnect, and set properties
|
|
set axi_hp0_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp0_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp0_interconnect
|
|
|
|
|
|
# Create instance: util_mxfe_xcvr, and set properties
|
|
set util_mxfe_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_mxfe_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.A_TXDIFFCTRL {0x0C} \
|
|
CONFIG.CH_HSPMUX {0x6868} \
|
|
CONFIG.CPLL_CFG0 {0x01FA} \
|
|
CONFIG.CPLL_CFG1 {0x0023} \
|
|
CONFIG.CPLL_CFG2 {0x0002} \
|
|
CONFIG.CPLL_FBDIV {2} \
|
|
CONFIG.CPLL_FBDIV_4_5 {5} \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.POR_CFG {0x0000} \
|
|
CONFIG.PPF0_CFG {0x0F00} \
|
|
CONFIG.PREIQ_FREQ_BST {1} \
|
|
CONFIG.QPLL_CFG0 {0x333c} \
|
|
CONFIG.QPLL_CFG4 {0x0045} \
|
|
CONFIG.QPLL_CP {0x0FF} \
|
|
CONFIG.QPLL_CP_G3 {0x00F} \
|
|
CONFIG.QPLL_FBDIV {"0000010100"} \
|
|
CONFIG.QPLL_LPF {0x2FF} \
|
|
CONFIG.QPLL_REFCLK_DIV {1} \
|
|
CONFIG.RTX_BUF_CML_CTRL {000} \
|
|
CONFIG.RXCDR_CFG0 {0x0003} \
|
|
CONFIG.RXCDR_CFG2_GEN2 {0x265} \
|
|
CONFIG.RXCDR_CFG2_GEN4 {0x0164} \
|
|
CONFIG.RXCDR_CFG3 {0x0012} \
|
|
CONFIG.RXCDR_CFG3_GEN2 {0x12} \
|
|
CONFIG.RXCDR_CFG3_GEN3 {0x0012} \
|
|
CONFIG.RXCDR_CFG3_GEN4 {0x0012} \
|
|
CONFIG.RXPI_CFG0 {0x0200} \
|
|
CONFIG.RXPI_CFG1 {0x00FD} \
|
|
CONFIG.RX_CLK25_DIV {31} \
|
|
CONFIG.RX_LANE_RATE {10} \
|
|
CONFIG.RX_NUM_OF_LANES {4} \
|
|
CONFIG.RX_OUT_DIV {1} \
|
|
CONFIG.RX_WIDEMODE_CDR {0x0} \
|
|
CONFIG.TXPI_CFG {0x0000} \
|
|
CONFIG.TX_CLK25_DIV {31} \
|
|
CONFIG.TX_LANE_RATE {10} \
|
|
CONFIG.TX_NUM_OF_LANES {4} \
|
|
CONFIG.TX_PI_BIASSET {3} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $util_mxfe_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_xcvr, and set properties
|
|
set axi_mxfe_rx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_rx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.FPGA_VOLTAGE {850} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.LPM_OR_DFE_N {1} \
|
|
CONFIG.NUM_OF_LANES {4} \
|
|
CONFIG.QPLL_ENABLE {0} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {0} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $axi_mxfe_rx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_rx_jesd
|
|
create_hier_cell_axi_mxfe_rx_jesd [current_bd_instance .] axi_mxfe_rx_jesd
|
|
|
|
# Create instance: rx_mxfe_tpl_core
|
|
create_hier_cell_rx_mxfe_tpl_core [current_bd_instance .] rx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_cpack, and set properties
|
|
set util_mxfe_cpack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack2:1.0 util_mxfe_cpack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {4} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {4} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_cpack
|
|
|
|
|
|
# Create instance: mxfe_rx_data_offload
|
|
create_hier_cell_mxfe_rx_data_offload [current_bd_instance .] mxfe_rx_data_offload
|
|
|
|
# Create instance: axi_mxfe_rx_dma, and set properties
|
|
set axi_mxfe_rx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_rx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.ALLOW_ASYM_MEM {1} \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {false} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {256} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {256} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {0} \
|
|
CONFIG.DMA_TYPE_SRC {1} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
CONFIG.SYNC_TRANSFER_START {false} \
|
|
] $axi_mxfe_rx_dma
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_xcvr, and set properties
|
|
set axi_mxfe_tx_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_mxfe_tx_xcvr ]
|
|
set_property -dict [list \
|
|
CONFIG.FPGA_VOLTAGE {850} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.LINK_MODE {2} \
|
|
CONFIG.NUM_OF_LANES {4} \
|
|
CONFIG.QPLL_ENABLE {1} \
|
|
CONFIG.SYS_CLK_SEL {0x3} \
|
|
CONFIG.TX_OR_RX_N {1} \
|
|
CONFIG.XCVR_TYPE {8} \
|
|
] $axi_mxfe_tx_xcvr
|
|
|
|
|
|
# Create instance: axi_mxfe_tx_jesd
|
|
create_hier_cell_axi_mxfe_tx_jesd [current_bd_instance .] axi_mxfe_tx_jesd
|
|
|
|
# Create instance: tx_mxfe_tpl_core
|
|
create_hier_cell_tx_mxfe_tpl_core [current_bd_instance .] tx_mxfe_tpl_core
|
|
|
|
# Create instance: util_mxfe_upack, and set properties
|
|
set util_mxfe_upack [ create_bd_cell -type ip -vlnv analog.com:user:util_upack2:1.0 util_mxfe_upack ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_OF_CHANNELS {4} \
|
|
CONFIG.SAMPLES_PER_CHANNEL {4} \
|
|
CONFIG.SAMPLE_DATA_WIDTH {16} \
|
|
] $util_mxfe_upack
|
|
|
|
|
|
# Create instance: mxfe_tx_data_offload
|
|
create_hier_cell_mxfe_tx_data_offload [current_bd_instance .] mxfe_tx_data_offload
|
|
|
|
# Create instance: axi_mxfe_tx_dma, and set properties
|
|
set axi_mxfe_tx_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_mxfe_tx_dma ]
|
|
set_property -dict [list \
|
|
CONFIG.ALLOW_ASYM_MEM {1} \
|
|
CONFIG.AXI_SLICE_DEST {true} \
|
|
CONFIG.AXI_SLICE_SRC {true} \
|
|
CONFIG.CYCLIC {true} \
|
|
CONFIG.DMA_2D_TRANSFER {false} \
|
|
CONFIG.DMA_DATA_WIDTH_DEST {256} \
|
|
CONFIG.DMA_DATA_WIDTH_SRC {256} \
|
|
CONFIG.DMA_LENGTH_WIDTH {24} \
|
|
CONFIG.DMA_TYPE_DEST {1} \
|
|
CONFIG.DMA_TYPE_SRC {0} \
|
|
CONFIG.ID {0} \
|
|
CONFIG.MAX_BYTES_PER_BURST {4096} \
|
|
] $axi_mxfe_tx_dma
|
|
|
|
|
|
# Create instance: rx_device_clk_rstgen, and set properties
|
|
set rx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rx_device_clk_rstgen ]
|
|
|
|
# Create instance: tx_device_clk_rstgen, and set properties
|
|
set tx_device_clk_rstgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 tx_device_clk_rstgen ]
|
|
|
|
# Create instance: axi_hp1_interconnect, and set properties
|
|
set axi_hp1_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp1_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_CLKS {2} \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp1_interconnect
|
|
|
|
|
|
# Create instance: axi_hp2_interconnect, and set properties
|
|
set axi_hp2_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_hp2_interconnect ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {1} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $axi_hp2_interconnect
|
|
|
|
|
|
# Create instance: manual_sync_or, and set properties
|
|
set manual_sync_or [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 manual_sync_or ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $manual_sync_or
|
|
|
|
|
|
# Create instance: cpack_rst_logic, and set properties
|
|
set cpack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 cpack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {3} \
|
|
] $cpack_rst_logic
|
|
|
|
|
|
# Create instance: rx_do_rstout_logic, and set properties
|
|
set rx_do_rstout_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rx_do_rstout_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rx_do_rstout_logic
|
|
|
|
|
|
# Create instance: cpack_reset_sources, and set properties
|
|
set cpack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 cpack_reset_sources ]
|
|
set_property CONFIG.NUM_PORTS {3} $cpack_reset_sources
|
|
|
|
|
|
# Create instance: upack_rst_logic, and set properties
|
|
set upack_rst_logic [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 upack_rst_logic ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {or} \
|
|
CONFIG.C_SIZE {2} \
|
|
] $upack_rst_logic
|
|
|
|
|
|
# Create instance: upack_reset_sources, and set properties
|
|
set upack_reset_sources [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 upack_reset_sources ]
|
|
set_property CONFIG.NUM_PORTS {2} $upack_reset_sources
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M00_AXI [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_sysid_0/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M01_AXI [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M02_AXI [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins rx_mxfe_tpl_core/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M03_AXI [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_mxfe_rx_jesd/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M04_AXI [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M05_AXI [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins mxfe_rx_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M06_AXI [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_mxfe_tx_xcvr/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins tx_mxfe_tpl_core/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M08_AXI [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mxfe_tx_jesd/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M09_AXI [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi]
|
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_ports M11_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI]
|
|
connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD]
|
|
connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD]
|
|
connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_dma_m_dest_axi [get_bd_intf_pins axi_hp1_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_dma/m_dest_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_m_axi [get_bd_intf_pins axi_hp0_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_rx_xcvr/m_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_rx_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_rx_1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_rx_2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_rx_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_0 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_0] [get_bd_intf_pins util_mxfe_xcvr/up_es_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_1 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_1] [get_bd_intf_pins util_mxfe_xcvr/up_es_1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_2 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_2] [get_bd_intf_pins util_mxfe_xcvr/up_es_2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_rx_xcvr_up_es_3 [get_bd_intf_pins axi_mxfe_rx_xcvr/up_es_3] [get_bd_intf_pins util_mxfe_xcvr/up_es_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_dma_m_src_axi [get_bd_intf_pins axi_hp2_interconnect/S00_AXI] [get_bd_intf_pins axi_mxfe_tx_dma/m_src_axi]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy0 [get_bd_intf_pins util_mxfe_xcvr/tx_0] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy1 [get_bd_intf_pins util_mxfe_xcvr/tx_1] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy2 [get_bd_intf_pins util_mxfe_xcvr/tx_2] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_jesd_tx_phy3 [get_bd_intf_pins util_mxfe_xcvr/tx_3] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_phy3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_0] [get_bd_intf_pins util_mxfe_xcvr/up_tx_0]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_1 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_1] [get_bd_intf_pins util_mxfe_xcvr/up_tx_1]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_2 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_2] [get_bd_intf_pins util_mxfe_xcvr/up_tx_2]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_ch_3 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_ch_3] [get_bd_intf_pins util_mxfe_xcvr/up_tx_3]
|
|
connect_bd_intf_net -intf_net axi_mxfe_tx_xcvr_up_cm_0 [get_bd_intf_pins axi_mxfe_tx_xcvr/up_cm_0] [get_bd_intf_pins util_mxfe_xcvr/up_cm_0]
|
|
connect_bd_intf_net -intf_net mxfe_rx_data_offload_m_axis [get_bd_intf_pins mxfe_rx_data_offload/m_axis] [get_bd_intf_pins axi_mxfe_rx_dma/s_axis]
|
|
connect_bd_intf_net -intf_net mxfe_tx_data_offload_m_axis [get_bd_intf_ports mxfe_tx_data_offload_m_axis] [get_bd_intf_pins mxfe_tx_data_offload/m_axis]
|
|
connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins mxfe_tx_data_offload/s_axis] [get_bd_intf_pins axi_mxfe_tx_dma/m_axis]
|
|
connect_bd_intf_net -intf_net sys_ps8_M_AXI_HPM0_LPD [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_LPD]
|
|
connect_bd_intf_net -intf_net tx_mxfe_tpl_core_link [get_bd_intf_pins tx_mxfe_tpl_core/link] [get_bd_intf_pins axi_mxfe_tx_jesd/tx_data]
|
|
connect_bd_intf_net -intf_net util_mxfe_upack_s_axis [get_bd_intf_ports util_mxfe_upack_s_axis] [get_bd_intf_pins util_mxfe_upack/s_axis]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_0 [get_bd_intf_pins util_mxfe_xcvr/rx_0] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy0]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_1 [get_bd_intf_pins util_mxfe_xcvr/rx_1] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy1]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_2 [get_bd_intf_pins util_mxfe_xcvr/rx_2] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy2]
|
|
connect_bd_intf_net -intf_net util_mxfe_xcvr_rx_3 [get_bd_intf_pins util_mxfe_xcvr/rx_3] [get_bd_intf_pins axi_mxfe_rx_jesd/rx_phy3]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net GND_1_dout [get_bd_pins GND_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tlast] [get_bd_pins tx_mxfe_tpl_core/dac_dunf] [get_bd_pins mxfe_rx_data_offload/sync_ext] [get_bd_pins mxfe_tx_data_offload/sync_ext] [get_bd_pins sys_concat_intc_0/In0] [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins sys_concat_intc_1/In0] [get_bd_pins sys_concat_intc_1/In1] [get_bd_pins sys_concat_intc_1/In6] [get_bd_pins sys_concat_intc_1/In7] [get_bd_pins sys_ps8/emio_spi0_sclk_i] [get_bd_pins sys_ps8/emio_spi0_s_i] [get_bd_pins sys_ps8/emio_spi1_sclk_i] [get_bd_pins sys_ps8/emio_spi1_s_i]
|
|
connect_bd_net -net VCC_1_dout [get_bd_pins VCC_1/dout] [get_bd_pins mxfe_rx_data_offload/s_axis_tkeep] [get_bd_pins sys_ps8/emio_spi0_ss_i_n] [get_bd_pins sys_ps8/emio_spi1_ss_i_n]
|
|
connect_bd_net -net adc_dovf_1 [get_bd_pins util_mxfe_cpack/fifo_wr_overflow] [get_bd_pins rx_mxfe_tpl_core/adc_dovf] [get_bd_ports packed_fifo_wr_overflow_out]
|
|
connect_bd_net -net axi_mxfe_rx_dma_irq [get_bd_pins axi_mxfe_rx_dma/irq] [get_bd_pins sys_concat_intc_1/In5]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_irq [get_bd_pins axi_mxfe_rx_jesd/irq] [get_bd_pins sys_concat_intc_1/In3]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tdata [get_bd_pins axi_mxfe_rx_jesd/rx_data_tdata] [get_bd_pins rx_mxfe_tpl_core/link_data]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_rx_data_tvalid [get_bd_pins axi_mxfe_rx_jesd/rx_data_tvalid] [get_bd_pins rx_mxfe_tpl_core/link_valid]
|
|
connect_bd_net -net axi_mxfe_rx_jesd_rx_sof [get_bd_pins axi_mxfe_rx_jesd/rx_sof] [get_bd_pins rx_mxfe_tpl_core/link_sof]
|
|
connect_bd_net -net axi_mxfe_rx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_rx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_0] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_1] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_2] [get_bd_pins util_mxfe_xcvr/up_cpll_rst_3]
|
|
connect_bd_net -net axi_mxfe_tx_dma_irq [get_bd_pins axi_mxfe_tx_dma/irq] [get_bd_pins sys_concat_intc_1/In4]
|
|
connect_bd_net -net axi_mxfe_tx_jesd_irq [get_bd_pins axi_mxfe_tx_jesd/irq] [get_bd_pins sys_concat_intc_1/In2]
|
|
connect_bd_net -net axi_mxfe_tx_xcvr_up_pll_rst [get_bd_pins axi_mxfe_tx_xcvr/up_pll_rst] [get_bd_pins util_mxfe_xcvr/up_qpll_rst_0]
|
|
connect_bd_net -net axi_sysid_0_rom_addr [get_bd_pins axi_sysid_0/rom_addr] [get_bd_pins rom_sys_0/rom_addr]
|
|
connect_bd_net -net cpack_reset_sources_dout [get_bd_pins cpack_reset_sources/dout] [get_bd_pins cpack_rst_logic/Op1]
|
|
connect_bd_net -net cpack_rst_logic_Res [get_bd_pins cpack_rst_logic/Res] [get_bd_pins util_mxfe_cpack/reset]
|
|
connect_bd_net -net ext_sync_in_1 [get_bd_ports ext_sync_in] [get_bd_pins rx_mxfe_tpl_core/ext_sync_in] [get_bd_pins tx_mxfe_tpl_core/ext_sync_in]
|
|
connect_bd_net -net gpio_i_1 [get_bd_ports gpio_i] [get_bd_pins sys_ps8/emio_gpio_i]
|
|
connect_bd_net -net init_req_1 [get_bd_pins axi_mxfe_rx_dma/s_axis_xfer_req] [get_bd_pins mxfe_rx_data_offload/init_req]
|
|
connect_bd_net -net init_req_2 [get_bd_pins axi_mxfe_tx_dma/m_axis_xfer_req] [get_bd_pins mxfe_tx_data_offload/init_req]
|
|
connect_bd_net -net manual_sync_or_Res [get_bd_pins manual_sync_or/Res] [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_in] [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_in]
|
|
connect_bd_net -net mxfe_rx_data_offload_s_axis_tready [get_bd_pins mxfe_rx_data_offload/s_axis_tready] [get_bd_pins rx_do_rstout_logic/Op1]
|
|
connect_bd_net -net ref_clk_q0_1 [get_bd_ports ref_clk_q0] [get_bd_pins util_mxfe_xcvr/qpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_0] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_1] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_2] [get_bd_pins util_mxfe_xcvr/cpll_ref_clk_3]
|
|
connect_bd_net -net rom_sys_0_rom_data [get_bd_pins rom_sys_0/rom_data] [get_bd_pins axi_sysid_0/sys_rom_data]
|
|
connect_bd_net -net rx_data_0_n_1 [get_bd_ports rx_data_0_n] [get_bd_pins util_mxfe_xcvr/rx_0_n]
|
|
connect_bd_net -net rx_data_0_p_1 [get_bd_ports rx_data_0_p] [get_bd_pins util_mxfe_xcvr/rx_0_p]
|
|
connect_bd_net -net rx_data_1_n_1 [get_bd_ports rx_data_1_n] [get_bd_pins util_mxfe_xcvr/rx_1_n]
|
|
connect_bd_net -net rx_data_1_p_1 [get_bd_ports rx_data_1_p] [get_bd_pins util_mxfe_xcvr/rx_1_p]
|
|
connect_bd_net -net rx_data_2_n_1 [get_bd_ports rx_data_2_n] [get_bd_pins util_mxfe_xcvr/rx_2_n]
|
|
connect_bd_net -net rx_data_2_p_1 [get_bd_ports rx_data_2_p] [get_bd_pins util_mxfe_xcvr/rx_2_p]
|
|
connect_bd_net -net rx_data_3_n_1 [get_bd_ports rx_data_3_n] [get_bd_pins util_mxfe_xcvr/rx_3_n]
|
|
connect_bd_net -net rx_data_3_p_1 [get_bd_ports rx_data_3_p] [get_bd_pins util_mxfe_xcvr/rx_3_p]
|
|
connect_bd_net -net rx_device_clk_1 [get_bd_ports rx_device_clk] [get_bd_pins axi_mxfe_rx_jesd/device_clk] [get_bd_pins rx_mxfe_tpl_core/link_clk] [get_bd_pins mxfe_rx_data_offload/s_axis_aclk] [get_bd_ports rx_device_clk_out] [get_bd_pins rx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_cpack/clk]
|
|
connect_bd_net -net rx_device_clk_rstgen_peripheral_aresetn [get_bd_pins rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axis_aresetn] [get_bd_ports rx_device_clk_aresetn_out]
|
|
connect_bd_net -net rx_device_clk_rstgen_peripheral_reset [get_bd_pins rx_device_clk_rstgen/peripheral_reset] [get_bd_pins cpack_reset_sources/In0]
|
|
connect_bd_net -net rx_do_rstout_logic_Res [get_bd_pins rx_do_rstout_logic/Res] [get_bd_pins cpack_reset_sources/In2]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_data_0 [get_bd_pins rx_mxfe_tpl_core/adc_data_0] [get_bd_pins util_mxfe_cpack/fifo_wr_data_0]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_data_1 [get_bd_pins rx_mxfe_tpl_core/adc_data_1] [get_bd_pins util_mxfe_cpack/fifo_wr_data_1]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_data_2 [get_bd_pins rx_mxfe_tpl_core/adc_data_2] [get_bd_pins util_mxfe_cpack/fifo_wr_data_2]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_data_3 [get_bd_pins rx_mxfe_tpl_core/adc_data_3] [get_bd_pins util_mxfe_cpack/fifo_wr_data_3]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_enable_0 [get_bd_pins rx_mxfe_tpl_core/adc_enable_0] [get_bd_pins util_mxfe_cpack/enable_0]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_enable_1 [get_bd_pins rx_mxfe_tpl_core/adc_enable_1] [get_bd_pins util_mxfe_cpack/enable_1]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_enable_2 [get_bd_pins rx_mxfe_tpl_core/adc_enable_2] [get_bd_pins util_mxfe_cpack/enable_2]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_enable_3 [get_bd_pins rx_mxfe_tpl_core/adc_enable_3] [get_bd_pins util_mxfe_cpack/enable_3]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_rst [get_bd_pins rx_mxfe_tpl_core/adc_rst] [get_bd_pins cpack_reset_sources/In1]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_sync_manual_req_out [get_bd_pins rx_mxfe_tpl_core/adc_sync_manual_req_out] [get_bd_pins manual_sync_or/Op1]
|
|
connect_bd_net -net rx_mxfe_tpl_core_adc_valid_0 [get_bd_pins rx_mxfe_tpl_core/adc_valid_0] [get_bd_pins util_mxfe_cpack/fifo_wr_en]
|
|
connect_bd_net -net spi0_csn_concat_dout [get_bd_pins spi0_csn_concat/dout] [get_bd_ports spi0_csn]
|
|
connect_bd_net -net spi0_miso_1 [get_bd_ports spi0_miso] [get_bd_pins sys_ps8/emio_spi0_m_i]
|
|
connect_bd_net -net spi1_csn_concat_dout [get_bd_pins spi1_csn_concat/dout] [get_bd_ports spi1_csn]
|
|
connect_bd_net -net spi1_miso_1 [get_bd_ports spi1_miso] [get_bd_pins sys_ps8/emio_spi1_m_i]
|
|
connect_bd_net -net sys_250m_clk [get_bd_pins sys_ps8/pl_clk1] [get_bd_pins mxfe_rx_data_offload/m_axis_aclk] [get_bd_pins mxfe_tx_data_offload/s_axis_aclk] [get_bd_ports clk_250_out] [get_bd_pins axi_hp1_interconnect/aclk1] [get_bd_pins axi_hp2_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aclk] [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] [get_bd_pins sys_250m_rstgen/slowest_sync_clk] [get_bd_pins sys_ps8/saxihp2_fpd_aclk]
|
|
connect_bd_net -net sys_250m_reset [get_bd_pins sys_250m_rstgen/peripheral_reset]
|
|
connect_bd_net -net sys_250m_resetn [get_bd_pins sys_250m_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/m_axis_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axis_aresetn] [get_bd_ports clk_250_aresetn_out] [get_bd_pins axi_hp2_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/m_dest_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/m_src_axi_aresetn]
|
|
connect_bd_net -net sys_500m_rstgen_peripheral_aresetn [get_bd_pins sys_500m_rstgen/peripheral_aresetn] [get_bd_ports pl_clk2_clk125_aresetn_out]
|
|
connect_bd_net -net sys_concat_intc_0_dout [get_bd_pins sys_concat_intc_0/dout] [get_bd_pins sys_ps8/pl_ps_irq0]
|
|
connect_bd_net -net sys_concat_intc_1_dout [get_bd_pins sys_concat_intc_1/dout] [get_bd_pins sys_ps8/pl_ps_irq1]
|
|
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps8/pl_clk0] [get_bd_pins rx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aclk] [get_bd_pins mxfe_rx_data_offload/s_axi_aclk] [get_bd_pins tx_mxfe_tpl_core/s_axi_aclk] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aclk] [get_bd_pins mxfe_tx_data_offload/s_axi_aclk] [get_bd_ports sys_cpu_clk_out] [get_bd_pins axi_cpu_interconnect/aclk] [get_bd_pins axi_hp0_interconnect/aclk] [get_bd_pins axi_hp1_interconnect/aclk] [get_bd_pins axi_mxfe_rx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aclk] [get_bd_pins axi_mxfe_tx_dma/s_axi_aclk] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aclk] [get_bd_pins axi_sysid_0/s_axi_aclk] [get_bd_pins rom_sys_0/clk] [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/saxihp0_fpd_aclk] [get_bd_pins sys_ps8/saxihp1_fpd_aclk] [get_bd_pins sys_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_xcvr/up_clk]
|
|
connect_bd_net -net sys_cpu_reset [get_bd_pins sys_rstgen/peripheral_reset]
|
|
connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] [get_bd_pins mxfe_rx_data_offload/s_axi_aresetn] [get_bd_pins rx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_jesd/s_axi_aresetn] [get_bd_pins mxfe_tx_data_offload/s_axi_aresetn] [get_bd_pins tx_mxfe_tpl_core/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_jesd/s_axi_aresetn] [get_bd_ports sys_cpu_aresetn_out] [get_bd_pins axi_cpu_interconnect/aresetn] [get_bd_pins axi_hp0_interconnect/aresetn] [get_bd_pins axi_hp1_interconnect/aresetn] [get_bd_pins axi_mxfe_rx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_rx_xcvr/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_dma/s_axi_aresetn] [get_bd_pins axi_mxfe_tx_xcvr/s_axi_aresetn] [get_bd_pins axi_sysid_0/s_axi_aresetn] [get_bd_pins rx_device_clk_rstgen/ext_reset_in] [get_bd_pins tx_device_clk_rstgen/ext_reset_in] [get_bd_pins util_mxfe_xcvr/up_rstn]
|
|
connect_bd_net -net sys_ps8_emio_gpio_o [get_bd_pins sys_ps8/emio_gpio_o] [get_bd_ports gpio_o]
|
|
connect_bd_net -net sys_ps8_emio_gpio_t [get_bd_pins sys_ps8/emio_gpio_t] [get_bd_ports gpio_t]
|
|
connect_bd_net -net sys_ps8_emio_spi0_m_o [get_bd_pins sys_ps8/emio_spi0_m_o] [get_bd_ports spi0_mosi]
|
|
connect_bd_net -net sys_ps8_emio_spi0_sclk_o [get_bd_pins sys_ps8/emio_spi0_sclk_o] [get_bd_ports spi0_sclk]
|
|
connect_bd_net -net sys_ps8_emio_spi0_ss1_o_n [get_bd_pins sys_ps8/emio_spi0_ss1_o_n] [get_bd_pins spi0_csn_concat/In1]
|
|
connect_bd_net -net sys_ps8_emio_spi0_ss2_o_n [get_bd_pins sys_ps8/emio_spi0_ss2_o_n] [get_bd_pins spi0_csn_concat/In2]
|
|
connect_bd_net -net sys_ps8_emio_spi0_ss_o_n [get_bd_pins sys_ps8/emio_spi0_ss_o_n] [get_bd_pins spi0_csn_concat/In0]
|
|
connect_bd_net -net sys_ps8_emio_spi1_m_o [get_bd_pins sys_ps8/emio_spi1_m_o] [get_bd_ports spi1_mosi]
|
|
connect_bd_net -net sys_ps8_emio_spi1_sclk_o [get_bd_pins sys_ps8/emio_spi1_sclk_o] [get_bd_ports spi1_sclk]
|
|
connect_bd_net -net sys_ps8_emio_spi1_ss1_o_n [get_bd_pins sys_ps8/emio_spi1_ss1_o_n] [get_bd_pins spi1_csn_concat/In1]
|
|
connect_bd_net -net sys_ps8_emio_spi1_ss2_o_n [get_bd_pins sys_ps8/emio_spi1_ss2_o_n] [get_bd_pins spi1_csn_concat/In2]
|
|
connect_bd_net -net sys_ps8_emio_spi1_ss_o_n [get_bd_pins sys_ps8/emio_spi1_ss_o_n] [get_bd_pins spi1_csn_concat/In0]
|
|
connect_bd_net -net sys_ps8_pl_clk2 [get_bd_pins sys_ps8/pl_clk2] [get_bd_ports pl_clk2_clk125] [get_bd_pins sys_500m_rstgen/slowest_sync_clk]
|
|
connect_bd_net -net sys_ps8_pl_clk3 [get_bd_pins sys_ps8/pl_clk3] [get_bd_ports pl_clk3_0]
|
|
connect_bd_net -net sys_ps8_pl_resetn0 [get_bd_pins sys_ps8/pl_resetn0] [get_bd_pins sys_250m_rstgen/ext_reset_in] [get_bd_pins sys_500m_rstgen/ext_reset_in] [get_bd_pins sys_rstgen/ext_reset_in]
|
|
connect_bd_net -net sysref_1 [get_bd_ports rx_sysref_0] [get_bd_pins axi_mxfe_rx_jesd/sysref]
|
|
connect_bd_net -net sysref_2 [get_bd_ports tx_sysref_0] [get_bd_pins axi_mxfe_tx_jesd/sysref]
|
|
connect_bd_net -net tx_device_clk_1 [get_bd_ports tx_device_clk] [get_bd_pins axi_mxfe_tx_jesd/device_clk] [get_bd_pins tx_mxfe_tpl_core/link_clk] [get_bd_pins mxfe_tx_data_offload/m_axis_aclk] [get_bd_ports tx_device_clk_out] [get_bd_pins tx_device_clk_rstgen/slowest_sync_clk] [get_bd_pins util_mxfe_upack/clk]
|
|
connect_bd_net -net tx_device_clk_rstgen_peripheral_aresetn [get_bd_pins tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins mxfe_tx_data_offload/m_axis_aresetn] [get_bd_ports tx_device_clk_aresetn_out]
|
|
connect_bd_net -net tx_device_clk_rstgen_peripheral_reset [get_bd_pins tx_device_clk_rstgen/peripheral_reset] [get_bd_pins upack_reset_sources/In0]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_enable_0 [get_bd_pins tx_mxfe_tpl_core/dac_enable_0] [get_bd_pins util_mxfe_upack/enable_0]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_enable_1 [get_bd_pins tx_mxfe_tpl_core/dac_enable_1] [get_bd_pins util_mxfe_upack/enable_1]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_enable_2 [get_bd_pins tx_mxfe_tpl_core/dac_enable_2] [get_bd_pins util_mxfe_upack/enable_2]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_enable_3 [get_bd_pins tx_mxfe_tpl_core/dac_enable_3] [get_bd_pins util_mxfe_upack/enable_3]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_rst [get_bd_pins tx_mxfe_tpl_core/dac_rst] [get_bd_pins upack_reset_sources/In1]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_sync_manual_req_out [get_bd_pins tx_mxfe_tpl_core/dac_sync_manual_req_out] [get_bd_pins manual_sync_or/Op2]
|
|
connect_bd_net -net tx_mxfe_tpl_core_dac_valid_0 [get_bd_pins tx_mxfe_tpl_core/dac_valid_0] [get_bd_pins util_mxfe_upack/fifo_rd_en]
|
|
connect_bd_net -net upack_reset_sources_dout [get_bd_pins upack_reset_sources/dout] [get_bd_pins upack_rst_logic/Op1]
|
|
connect_bd_net -net upack_rst_logic_Res [get_bd_pins upack_rst_logic/Res] [get_bd_pins util_mxfe_upack/reset]
|
|
connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_data [get_bd_pins util_mxfe_cpack/packed_fifo_wr_data] [get_bd_pins mxfe_rx_data_offload/s_axis_tdata] [get_bd_ports packed_fifo_wr_data_out]
|
|
connect_bd_net -net util_mxfe_cpack_packed_fifo_wr_en [get_bd_pins util_mxfe_cpack/packed_fifo_wr_en] [get_bd_pins mxfe_rx_data_offload/s_axis_tvalid] [get_bd_ports packed_fifo_wr_en_out]
|
|
connect_bd_net -net util_mxfe_upack_fifo_rd_data_0 [get_bd_pins util_mxfe_upack/fifo_rd_data_0] [get_bd_pins tx_mxfe_tpl_core/dac_data_0]
|
|
connect_bd_net -net util_mxfe_upack_fifo_rd_data_1 [get_bd_pins util_mxfe_upack/fifo_rd_data_1] [get_bd_pins tx_mxfe_tpl_core/dac_data_1]
|
|
connect_bd_net -net util_mxfe_upack_fifo_rd_data_2 [get_bd_pins util_mxfe_upack/fifo_rd_data_2] [get_bd_pins tx_mxfe_tpl_core/dac_data_2]
|
|
connect_bd_net -net util_mxfe_upack_fifo_rd_data_3 [get_bd_pins util_mxfe_upack/fifo_rd_data_3] [get_bd_pins tx_mxfe_tpl_core/dac_data_3]
|
|
connect_bd_net -net util_mxfe_xcvr_rx_out_clk_0 [get_bd_pins util_mxfe_xcvr/rx_out_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_2x_0] [get_bd_pins util_mxfe_xcvr/rx_clk_2x_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2x_2] [get_bd_pins util_mxfe_xcvr/rx_clk_2x_3]
|
|
connect_bd_net -net util_mxfe_xcvr_rx_out_clk_div2_0 [get_bd_pins util_mxfe_xcvr/rx_out_clk_div2_0] [get_bd_pins axi_mxfe_rx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/rx_clk_0] [get_bd_pins util_mxfe_xcvr/rx_clk_1] [get_bd_pins util_mxfe_xcvr/rx_clk_2] [get_bd_pins util_mxfe_xcvr/rx_clk_3]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_0_n [get_bd_pins util_mxfe_xcvr/tx_0_n] [get_bd_ports tx_data_0_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_0_p [get_bd_pins util_mxfe_xcvr/tx_0_p] [get_bd_ports tx_data_0_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_1_n [get_bd_pins util_mxfe_xcvr/tx_1_n] [get_bd_ports tx_data_1_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_1_p [get_bd_pins util_mxfe_xcvr/tx_1_p] [get_bd_ports tx_data_1_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_2_n [get_bd_pins util_mxfe_xcvr/tx_2_n] [get_bd_ports tx_data_2_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_2_p [get_bd_pins util_mxfe_xcvr/tx_2_p] [get_bd_ports tx_data_2_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_3_n [get_bd_pins util_mxfe_xcvr/tx_3_n] [get_bd_ports tx_data_3_n]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_3_p [get_bd_pins util_mxfe_xcvr/tx_3_p] [get_bd_ports tx_data_3_p]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_out_clk_0 [get_bd_pins util_mxfe_xcvr/tx_out_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_2x_0] [get_bd_pins util_mxfe_xcvr/tx_clk_2x_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2x_2] [get_bd_pins util_mxfe_xcvr/tx_clk_2x_3]
|
|
connect_bd_net -net util_mxfe_xcvr_tx_out_clk_div2_0 [get_bd_pins util_mxfe_xcvr/tx_out_clk_div2_0] [get_bd_pins axi_mxfe_tx_jesd/link_clk] [get_bd_pins util_mxfe_xcvr/tx_clk_0] [get_bd_pins util_mxfe_xcvr/tx_clk_1] [get_bd_pins util_mxfe_xcvr/tx_clk_2] [get_bd_pins util_mxfe_xcvr/tx_clk_3]
|
|
|
|
# Create address segments
|
|
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M11_AXI_0/Reg] -force
|
|
assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C430000 -range 0x00001000 -with_name SEG_data_axi_mxfe_tx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_dma/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_tx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_jesd/tx_axi/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_tx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_tx_xcvr/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x85000000 -range 0x00010000 -with_name SEG_data_axi_sysid_0 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_sysid_0/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C450000 -range 0x00010000 -with_name SEG_data_mxfe_rx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_rx_data_offload/i_data_offload/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x9C440000 -range 0x00010000 -with_name SEG_data_mxfe_tx_data_offload -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs mxfe_tx_data_offload/i_data_offload/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84A10000 -range 0x00002000 -with_name SEG_data_rx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs rx_mxfe_tpl_core/adc_tpl_core/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x84B10000 -range 0x00002000 -with_name SEG_data_tx_mxfe_tpl_core -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs tx_mxfe_tpl_core/dac_tpl_core/s_axi/axi_lite] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_LOW] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] -force
|
|
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] -force
|
|
|
|
# Exclude Address Segments
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_HIGH]
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH]
|
|
exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH]
|
|
|
|
# Perform GUI Layout
|
|
regenerate_bd_layout -layout_string {
|
|
"ActiveEmotionalView":"Default View",
|
|
"Default View_ScaleFactor":"0.639506",
|
|
"Default View_TopLeft":"5476,600",
|
|
"ExpandedHierarchyInLayout":"",
|
|
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
|
# -string -flagsOSRD
|
|
preplace port M11_AXI_0 -pg 1 -lvl 15 -x 6740 -y 1660 -defaultsOSRD
|
|
preplace port mxfe_tx_data_offload_m_axis -pg 1 -lvl 15 -x 6740 -y 1720 -defaultsOSRD
|
|
preplace port util_mxfe_upack_s_axis -pg 1 -lvl 0 -x -10 -y 820 -defaultsOSRD
|
|
preplace port port-id_spi0_sclk -pg 1 -lvl 15 -x 6740 -y 3220 -defaultsOSRD
|
|
preplace port port-id_spi0_mosi -pg 1 -lvl 15 -x 6740 -y 3200 -defaultsOSRD
|
|
preplace port port-id_spi0_miso -pg 1 -lvl 0 -x -10 -y 2860 -defaultsOSRD
|
|
preplace port port-id_spi1_sclk -pg 1 -lvl 15 -x 6740 -y 1290 -defaultsOSRD
|
|
preplace port port-id_spi1_mosi -pg 1 -lvl 15 -x 6740 -y 1310 -defaultsOSRD
|
|
preplace port port-id_spi1_miso -pg 1 -lvl 0 -x -10 -y 2880 -defaultsOSRD
|
|
preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x -10 -y 1490 -defaultsOSRD
|
|
preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x -10 -y 2430 -defaultsOSRD
|
|
preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x -10 -y 2620 -defaultsOSRD
|
|
preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD
|
|
preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x -10 -y 2800 -defaultsOSRD
|
|
preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x -10 -y 2390 -defaultsOSRD
|
|
preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x -10 -y 2410 -defaultsOSRD
|
|
preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x -10 -y 2640 -defaultsOSRD
|
|
preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x -10 -y 2660 -defaultsOSRD
|
|
preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x -10 -y 2820 -defaultsOSRD
|
|
preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x -10 -y 2840 -defaultsOSRD
|
|
preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x -10 -y 3000 -defaultsOSRD
|
|
preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x -10 -y 2980 -defaultsOSRD
|
|
preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x -10 -y 3020 -defaultsOSRD
|
|
preplace port port-id_tx_data_0_p -pg 1 -lvl 15 -x 6740 -y 2410 -defaultsOSRD
|
|
preplace port port-id_tx_data_0_n -pg 1 -lvl 15 -x 6740 -y 2430 -defaultsOSRD
|
|
preplace port port-id_tx_data_1_p -pg 1 -lvl 15 -x 6740 -y 2530 -defaultsOSRD
|
|
preplace port port-id_tx_data_1_n -pg 1 -lvl 15 -x 6740 -y 2550 -defaultsOSRD
|
|
preplace port port-id_tx_data_2_p -pg 1 -lvl 15 -x 6740 -y 2650 -defaultsOSRD
|
|
preplace port port-id_tx_data_2_n -pg 1 -lvl 15 -x 6740 -y 2670 -defaultsOSRD
|
|
preplace port port-id_tx_data_3_p -pg 1 -lvl 15 -x 6740 -y 2770 -defaultsOSRD
|
|
preplace port port-id_tx_data_3_n -pg 1 -lvl 15 -x 6740 -y 2790 -defaultsOSRD
|
|
preplace port port-id_rx_data_4_n -pg 1 -lvl 0 -x -10 -y 40 -defaultsOSRD
|
|
preplace port port-id_rx_data_4_p -pg 1 -lvl 0 -x -10 -y 60 -defaultsOSRD
|
|
preplace port port-id_rx_data_5_n -pg 1 -lvl 0 -x -10 -y 80 -defaultsOSRD
|
|
preplace port port-id_rx_data_5_p -pg 1 -lvl 0 -x -10 -y 100 -defaultsOSRD
|
|
preplace port port-id_rx_data_6_n -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD
|
|
preplace port port-id_rx_data_6_p -pg 1 -lvl 0 -x -10 -y 140 -defaultsOSRD
|
|
preplace port port-id_rx_data_7_n -pg 1 -lvl 0 -x -10 -y 160 -defaultsOSRD
|
|
preplace port port-id_rx_data_7_p -pg 1 -lvl 0 -x -10 -y 180 -defaultsOSRD
|
|
preplace port port-id_tx_data_4_n -pg 1 -lvl 15 -x 6740 -y 20 -defaultsOSRD
|
|
preplace port port-id_tx_data_4_p -pg 1 -lvl 15 -x 6740 -y 40 -defaultsOSRD
|
|
preplace port port-id_tx_data_5_n -pg 1 -lvl 15 -x 6740 -y 60 -defaultsOSRD
|
|
preplace port port-id_tx_data_5_p -pg 1 -lvl 15 -x 6740 -y 80 -defaultsOSRD
|
|
preplace port port-id_tx_data_6_n -pg 1 -lvl 15 -x 6740 -y 100 -defaultsOSRD
|
|
preplace port port-id_tx_data_6_p -pg 1 -lvl 15 -x 6740 -y 120 -defaultsOSRD
|
|
preplace port port-id_tx_data_7_n -pg 1 -lvl 15 -x 6740 -y 140 -defaultsOSRD
|
|
preplace port port-id_tx_data_7_p -pg 1 -lvl 15 -x 6740 -y 160 -defaultsOSRD
|
|
preplace port port-id_ext_sync_in -pg 1 -lvl 0 -x -10 -y 560 -defaultsOSRD
|
|
preplace port port-id_pl_clk3_0 -pg 1 -lvl 15 -x 6740 -y 1270 -defaultsOSRD
|
|
preplace port port-id_pl_clk2_clk125 -pg 1 -lvl 15 -x 6740 -y 1460 -defaultsOSRD
|
|
preplace port port-id_clk_250_out -pg 1 -lvl 15 -x 6740 -y 1640 -defaultsOSRD
|
|
preplace port port-id_tx_device_clk_out -pg 1 -lvl 15 -x 6740 -y 1760 -defaultsOSRD
|
|
preplace port port-id_rx_device_clk_out -pg 1 -lvl 15 -x 6740 -y 2000 -defaultsOSRD
|
|
preplace port port-id_sys_cpu_clk_out -pg 1 -lvl 15 -x 6740 -y 2110 -defaultsOSRD
|
|
preplace port port-id_packed_fifo_wr_en_out -pg 1 -lvl 15 -x 6740 -y 430 -defaultsOSRD
|
|
preplace port port-id_packed_fifo_wr_overflow_out -pg 1 -lvl 15 -x 6740 -y 670 -defaultsOSRD
|
|
preplace portBus spi0_csn -pg 1 -lvl 15 -x 6740 -y 1090 -defaultsOSRD
|
|
preplace portBus spi1_csn -pg 1 -lvl 15 -x 6740 -y 1550 -defaultsOSRD
|
|
preplace portBus gpio_i -pg 1 -lvl 0 -x -10 -y 2330 -defaultsOSRD
|
|
preplace portBus gpio_o -pg 1 -lvl 15 -x 6740 -y 3160 -defaultsOSRD
|
|
preplace portBus gpio_t -pg 1 -lvl 15 -x 6740 -y 3180 -defaultsOSRD
|
|
preplace portBus rx_sync_0 -pg 1 -lvl 15 -x 6740 -y 180 -defaultsOSRD
|
|
preplace portBus tx_sync_0 -pg 1 -lvl 0 -x -10 -y 200 -defaultsOSRD
|
|
preplace portBus pl_clk2_clk125_aresetn_out -pg 1 -lvl 15 -x 6740 -y 1500 -defaultsOSRD
|
|
preplace portBus clk_250_aresetn_out -pg 1 -lvl 15 -x 6740 -y 1860 -defaultsOSRD
|
|
preplace portBus tx_device_clk_aresetn_out -pg 1 -lvl 15 -x 6740 -y 1680 -defaultsOSRD
|
|
preplace portBus rx_device_clk_aresetn_out -pg 1 -lvl 15 -x 6740 -y 1950 -defaultsOSRD
|
|
preplace portBus sys_cpu_aresetn_out -pg 1 -lvl 15 -x 6740 -y 2040 -defaultsOSRD
|
|
preplace portBus packed_fifo_wr_data_out -pg 1 -lvl 15 -x 6740 -y 580 -defaultsOSRD
|
|
preplace inst sys_ps8 -pg 1 -lvl 9 -x 3450 -y 980 -defaultsOSRD
|
|
preplace inst sys_rstgen -pg 1 -lvl 1 -x 210 -y 1880 -defaultsOSRD
|
|
preplace inst sys_250m_rstgen -pg 1 -lvl 5 -x 1570 -y 1680 -defaultsOSRD
|
|
preplace inst sys_500m_rstgen -pg 1 -lvl 11 -x 4960 -y 1460 -defaultsOSRD
|
|
preplace inst spi0_csn_concat -pg 1 -lvl 14 -x 6430 -y 1090 -defaultsOSRD
|
|
preplace inst VCC_1 -pg 1 -lvl 5 -x 1570 -y 1920 -defaultsOSRD
|
|
preplace inst GND_1 -pg 1 -lvl 5 -x 1570 -y 1820 -defaultsOSRD
|
|
preplace inst spi1_csn_concat -pg 1 -lvl 14 -x 6430 -y 1550 -defaultsOSRD
|
|
preplace inst axi_sysid_0 -pg 1 -lvl 11 -x 4960 -y 1190 -defaultsOSRD
|
|
preplace inst rom_sys_0 -pg 1 -lvl 10 -x 4190 -y 1190 -defaultsOSRD
|
|
preplace inst axi_cpu_interconnect -pg 1 -lvl 10 -x 4190 -y 1550 -defaultsOSRD
|
|
preplace inst sys_concat_intc_0 -pg 1 -lvl 8 -x 2870 -y 2200 -defaultsOSRD
|
|
preplace inst sys_concat_intc_1 -pg 1 -lvl 8 -x 2870 -y 1750 -defaultsOSRD
|
|
preplace inst axi_hp0_interconnect -pg 1 -lvl 8 -x 2870 -y 1250 -defaultsOSRD
|
|
preplace inst util_mxfe_xcvr -pg 1 -lvl 13 -x 6030 -y 2560 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_xcvr -pg 1 -lvl 7 -x 2410 -y 1390 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_jesd -pg 1 -lvl 14 -x 6430 -y 2270 -defaultsOSRD
|
|
preplace inst rx_mxfe_tpl_core -pg 1 -lvl 11 -x 4960 -y 370 -defaultsOSRD
|
|
preplace inst util_mxfe_cpack -pg 1 -lvl 5 -x 1570 -y 390 -defaultsOSRD
|
|
preplace inst mxfe_rx_data_offload -pg 1 -lvl 6 -x 2030 -y 1800 -defaultsOSRD
|
|
preplace inst axi_mxfe_rx_dma -pg 1 -lvl 7 -x 2410 -y 1740 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_xcvr -pg 1 -lvl 12 -x 5530 -y 2160 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_jesd -pg 1 -lvl 12 -x 5530 -y 1950 -defaultsOSRD
|
|
preplace inst tx_mxfe_tpl_core -pg 1 -lvl 11 -x 4960 -y 750 -defaultsOSRD
|
|
preplace inst util_mxfe_upack -pg 1 -lvl 12 -x 5530 -y 890 -defaultsOSRD
|
|
preplace inst mxfe_tx_data_offload -pg 1 -lvl 11 -x 4960 -y 1720 -defaultsOSRD
|
|
preplace inst axi_mxfe_tx_dma -pg 1 -lvl 7 -x 2410 -y 1990 -defaultsOSRD
|
|
preplace inst rx_device_clk_rstgen -pg 1 -lvl 2 -x 580 -y 1530 -defaultsOSRD
|
|
preplace inst tx_device_clk_rstgen -pg 1 -lvl 9 -x 3450 -y 2510 -defaultsOSRD
|
|
preplace inst axi_hp1_interconnect -pg 1 -lvl 8 -x 2870 -y 1460 -defaultsOSRD
|
|
preplace inst axi_hp2_interconnect -pg 1 -lvl 8 -x 2870 -y 1980 -defaultsOSRD
|
|
preplace inst manual_sync_or -pg 1 -lvl 10 -x 4190 -y 130 -defaultsOSRD
|
|
preplace inst cpack_rst_logic -pg 1 -lvl 4 -x 1130 -y 310 -defaultsOSRD
|
|
preplace inst rx_do_rstout_logic -pg 1 -lvl 2 -x 580 -y 660 -defaultsOSRD
|
|
preplace inst cpack_reset_sources -pg 1 -lvl 3 -x 880 -y 640 -defaultsOSRD
|
|
preplace inst upack_rst_logic -pg 1 -lvl 11 -x 4960 -y 960 -defaultsOSRD
|
|
preplace inst upack_reset_sources -pg 1 -lvl 10 -x 4190 -y 1000 -defaultsOSRD
|
|
preplace netloc GND_1_dout 1 5 6 1850 2100 NJ 2100 2710 1580 NJ 1580 3820 860 4700
|
|
preplace netloc VCC_1_dout 1 5 5 1800 1160 NJ 1160 NJ 1160 3080J 1390 3760
|
|
preplace netloc adc_dovf_1 1 5 10 NJ 420 NJ 420 NJ 420 NJ 420 NJ 420 4700 560 N 560 N 560 N 560 6720
|
|
preplace netloc axi_mxfe_rx_dma_irq 1 7 1 2600 1740n
|
|
preplace netloc axi_mxfe_rx_jesd_irq 1 7 8 2730 1890 NJ 1890 NJ 1890 4440J 1950 5310J 1740 NJ 1740 NJ 1740 6620
|
|
preplace netloc axi_mxfe_rx_jesd_rx_data_tdata 1 10 5 4730 1900 5280J 1750 NJ 1750 NJ 1750 6610
|
|
preplace netloc axi_mxfe_rx_jesd_rx_data_tvalid 1 10 5 4740 1880 5290J 1760 NJ 1760 NJ 1760 6600
|
|
preplace netloc axi_mxfe_rx_jesd_rx_sof 1 10 5 4720 1920 5320J 1780 NJ 1780 NJ 1780 6590
|
|
preplace netloc axi_mxfe_rx_xcvr_up_pll_rst 1 7 6 2570 1590 NJ 1590 4040J 1340 4530J 1360 NJ 1360 5720
|
|
preplace netloc axi_mxfe_tx_dma_irq 1 7 1 2590 1760n
|
|
preplace netloc axi_mxfe_tx_jesd_irq 1 7 6 2720 1900 3010J 1970 NJ 1970 NJ 1970 5340J 1800 5670
|
|
preplace netloc axi_mxfe_tx_xcvr_up_pll_rst 1 12 1 5700 2220n
|
|
preplace netloc axi_sysid_0_rom_addr 1 9 3 4040 1260 4590J 1310 5160
|
|
preplace netloc cpack_reset_sources_dout 1 3 1 990 310n
|
|
preplace netloc cpack_rst_logic_Res 1 4 1 NJ 310
|
|
preplace netloc ext_sync_in_1 1 0 11 NJ 560 NJ 560 NJ 560 NJ 560 NJ 560 1860J 580 NJ 580 NJ 580 NJ 580 NJ 580 4480
|
|
preplace netloc gpio_i_1 1 0 10 NJ 2330 NJ 2330 NJ 2330 NJ 2330 NJ 2330 NJ 2330 NJ 2330 2570J 2340 NJ 2340 3780
|
|
preplace netloc init_req_1 1 5 3 1880 2000 2220J 1860 2570
|
|
preplace netloc init_req_2 1 7 4 2580J 2060 3120J 1870 NJ 1870 4420
|
|
preplace netloc manual_sync_or_Res 1 10 1 4410 130n
|
|
preplace netloc mxfe_rx_data_offload_s_axis_tready 1 1 5 400 1980 NJ 1980 NJ 1980 NJ 1980 1820J
|
|
preplace netloc ref_clk_q0_1 1 0 13 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 NJ 2620 5670
|
|
preplace netloc rom_sys_0_rom_data 1 10 1 4370 1190n
|
|
preplace netloc rx_data_0_n_1 1 0 13 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 NJ 2410 5680J
|
|
preplace netloc rx_data_0_p_1 1 0 13 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 NJ 2390 5690J
|
|
preplace netloc rx_data_1_n_1 1 0 13 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ 2660 NJ
|
|
preplace netloc rx_data_1_p_1 1 0 13 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ 2640 NJ
|
|
preplace netloc rx_data_2_n_1 1 0 13 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ 2840 NJ
|
|
preplace netloc rx_data_2_p_1 1 0 13 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ 2820 NJ
|
|
preplace netloc rx_data_3_n_1 1 0 13 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 NJ 2980 5680J
|
|
preplace netloc rx_data_3_p_1 1 0 13 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ 3000 NJ
|
|
preplace netloc rx_device_clk_1 1 0 15 NJ 1490 390 1430 NJ 1430 NJ 1430 1270 1430 1830 1600 NJ 1600 NJ 1600 NJ 1600 4030J 1330 4400 1930 5330J 1790 NJ 1790 6220J 2000 N
|
|
preplace netloc rx_device_clk_rstgen_peripheral_aresetn 1 2 13 NJ 1570 NJ 1570 NJ 1570 1790 2110 N 2110 2730 2070 N 2070 N 2070 4750 1980 5350 1810 N 1810 N 1810 6630
|
|
preplace netloc rx_device_clk_rstgen_peripheral_reset 1 2 1 760 620n
|
|
preplace netloc rx_do_rstout_logic_Res 1 2 1 NJ 660
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_0 1 4 8 1280 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 5370
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_1 1 4 8 1290 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 5310
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_2 1 4 8 1300 30 NJ 30 NJ 30 NJ 30 NJ 30 NJ 30 NJ 30 5270
|
|
preplace netloc rx_mxfe_tpl_core_adc_data_3 1 4 8 1310 40 NJ 40 NJ 40 NJ 40 NJ 40 NJ 40 NJ 40 5260
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_0 1 4 8 1340 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 4430J 160 5200
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_1 1 4 8 1350 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 4450J 170 5180
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_2 1 4 8 1360 230 NJ 230 NJ 230 NJ 230 NJ 230 3780J 240 4420J 130 5240
|
|
preplace netloc rx_mxfe_tpl_core_adc_enable_3 1 4 8 1330 50 NJ 50 NJ 50 NJ 50 NJ 50 NJ 50 NJ 50 5250
|
|
preplace netloc rx_mxfe_tpl_core_adc_rst 1 2 10 770 60 NJ 60 NJ 60 NJ 60 NJ 60 NJ 60 NJ 60 NJ 60 NJ 60 5220
|
|
preplace netloc rx_mxfe_tpl_core_adc_sync_manual_req_out 1 9 3 3940 250 4440J 140 5160
|
|
preplace netloc rx_mxfe_tpl_core_adc_valid_0 1 4 8 1320 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 4390J 150 5230
|
|
preplace netloc spi0_csn_concat_dout 1 14 1 NJ 1090
|
|
preplace netloc spi0_miso_1 1 0 10 NJ 2860 NJ 2860 NJ 2860 NJ 2860 NJ 2860 NJ 2860 NJ 2860 NJ 2860 NJ 2860 3790
|
|
preplace netloc spi1_csn_concat_dout 1 14 1 NJ 1550
|
|
preplace netloc spi1_miso_1 1 0 10 NJ 2880 NJ 2880 NJ 2880 NJ 2880 NJ 2880 NJ 2880 NJ 2880 NJ 2880 NJ 2880 3770
|
|
preplace netloc sys_250m_clk 1 4 11 1360 2000 1870 2030 2230 1870 2700 1170 3140 1410 3800 1300 4520 1910 5200 1640 N 1640 N 1640 N
|
|
preplace netloc sys_250m_reset 1 5 1 N 1680
|
|
preplace netloc sys_250m_resetn 1 5 10 1810 2020 2240 1880 2670 1880 NJ 1880 NJ 1880 4710 1940 5260 1690 N 1690 N 1690 6660
|
|
preplace netloc sys_concat_intc_0_dout 1 8 1 3110 1040n
|
|
preplace netloc sys_concat_intc_1_dout 1 8 1 3070 1060n
|
|
preplace netloc sys_cpu_clk 1 0 15 30 2010 NJ 2010 NJ 2010 NJ 2010 NJ 2010 1840 2010 2210 1230 2670 1140 3120 1420 3990 890 4650 2010 5360 1820 5800 1930 6200J 2110 N
|
|
preplace netloc sys_cpu_reset 1 1 1 N 1880
|
|
preplace netloc sys_cpu_resetn 1 1 14 390 1970 NJ 1970 NJ 1970 1270J 1990 1860 1990 2190 1550 2720 1610 3060 1610 4020 1310 4390 2000 5370 1830 5780 1920 6210J 2040 N
|
|
preplace netloc sys_ps8_emio_gpio_o 1 9 6 3820J 650 4530J 580 NJ 580 NJ 580 NJ 580 6690J
|
|
preplace netloc sys_ps8_emio_gpio_t 1 9 6 3790J 640 4540J 590 NJ 590 NJ 590 NJ 590 6670J
|
|
preplace netloc sys_ps8_emio_spi0_m_o 1 9 6 NJ 870 4630J 1350 NJ 1350 NJ 1350 NJ 1350 6640J
|
|
preplace netloc sys_ps8_emio_spi0_sclk_o 1 9 6 NJ 830 4470J 70 NJ 70 NJ 70 NJ 70 6700J
|
|
preplace netloc sys_ps8_emio_spi0_ss1_o_n 1 9 5 3870 920 4670J 1090 NJ 1090 NJ 1090 NJ
|
|
preplace netloc sys_ps8_emio_spi0_ss2_o_n 1 9 5 3880 930 4680J 1060 NJ 1060 NJ 1060 6200J
|
|
preplace netloc sys_ps8_emio_spi0_ss_o_n 1 9 5 3840 910 4690J 1080 NJ 1080 NJ 1080 6180J
|
|
preplace netloc sys_ps8_emio_spi1_m_o 1 9 6 3920J 1110 4610J 1320 5220J 1310 NJ 1310 NJ 1310 NJ
|
|
preplace netloc sys_ps8_emio_spi1_sclk_o 1 9 6 3930J 1120 4620J 1290 NJ 1290 NJ 1290 NJ 1290 NJ
|
|
preplace netloc sys_ps8_emio_spi1_ss1_o_n 1 9 5 3860J 840 4500J 90 NJ 90 NJ 90 6230
|
|
preplace netloc sys_ps8_emio_spi1_ss2_o_n 1 9 5 3850J 820 4490J 100 NJ 100 NJ 100 6190
|
|
preplace netloc sys_ps8_emio_spi1_ss_o_n 1 9 5 3830J 810 4460J 80 NJ 80 NJ 80 6270
|
|
preplace netloc sys_ps8_pl_resetn0 1 0 11 20 1660 NJ 1660 NJ 1660 NJ 1660 1300 1150 NJ 1150 NJ 1150 NJ 1150 3090J 1400 3810 1320 4540
|
|
preplace netloc sysref_1 1 0 14 10J 2340 NJ 2340 NJ 2340 NJ 2340 NJ 2340 NJ 2340 NJ 2340 2670J 2330 3140J 1960 NJ 1960 NJ 1960 5300J 1720 NJ 1720 6230J
|
|
preplace netloc sysref_2 1 0 12 20J 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 NJ 2400 5380J
|
|
preplace netloc tx_device_clk_1 1 0 15 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 NJ 2430 3130 1750 NJ 1750 4660 1570 5270 1700 N 1700 N 1700 6650
|
|
preplace netloc tx_device_clk_rstgen_peripheral_aresetn 1 9 6 4040J 2380 4680 1990 5170 1710 N 1710 N 1710 6680
|
|
preplace netloc tx_device_clk_rstgen_peripheral_reset 1 9 1 4000 990n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_0 1 11 1 5370 670n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_1 1 11 1 5260 710n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_2 1 11 1 5230 750n
|
|
preplace netloc tx_mxfe_tpl_core_dac_enable_3 1 11 1 5220 790n
|
|
preplace netloc tx_mxfe_tpl_core_dac_rst 1 9 3 4030 1290 4580J 1300 5190
|
|
preplace netloc tx_mxfe_tpl_core_dac_sync_manual_req_out 1 9 3 4040 230 4480J 180 5170
|
|
preplace netloc tx_mxfe_tpl_core_dac_valid_0 1 11 1 5240 690n
|
|
preplace netloc upack_reset_sources_dout 1 10 1 4590 960n
|
|
preplace netloc upack_rst_logic_Res 1 11 1 5210J 860n
|
|
preplace netloc util_mxfe_cpack_packed_fifo_wr_data 1 5 10 1850 590 N 590 N 590 N 590 N 590 4520 570 N 570 N 570 N 570 6710
|
|
preplace netloc util_mxfe_cpack_packed_fifo_wr_en 1 5 10 1870 600 N 600 N 600 N 600 N 600 4510 550 5370 430 N 430 N 430 N
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_0 1 10 3 4760 1040 NJ 1040 5670
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_1 1 10 3 4690 110 NJ 110 5710
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_2 1 10 3 4750 120 NJ 120 5860
|
|
preplace netloc util_mxfe_upack_fifo_rd_data_3 1 10 3 4750 1340 NJ 1340 5710
|
|
preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 12 2 5880 3180 6180
|
|
preplace netloc util_mxfe_xcvr_rx_out_clk_div2_0 1 12 2 5890 1940 6190
|
|
preplace netloc util_mxfe_xcvr_tx_0_n 1 13 2 NJ 2430 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_0_p 1 13 2 NJ 2410 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_1_n 1 13 2 NJ 2550 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_1_p 1 13 2 NJ 2530 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_2_n 1 13 2 NJ 2670 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_2_p 1 13 2 NJ 2650 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_3_n 1 13 2 NJ 2790 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_3_p 1 13 2 NJ 2770 NJ
|
|
preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 12 2 5870 3200 6230
|
|
preplace netloc util_mxfe_xcvr_tx_out_clk_div2_0 1 11 3 5390 2560 5840 3190 6170
|
|
preplace netloc sys_ps8_pl_clk3 1 9 6 NJ 1270 4570J 1330 5200J 1270 NJ 1270 NJ 1270 NJ
|
|
preplace netloc sys_ps8_pl_clk2 1 9 6 3900J 1280 4560J 1560 5170J 1460 NJ 1460 NJ 1460 NJ
|
|
preplace netloc sys_500m_rstgen_peripheral_aresetn 1 11 4 5200J 1470 NJ 1470 NJ 1470 6720J
|
|
preplace netloc axi_cpu_interconnect_M00_AXI 1 10 1 4380 1150n
|
|
preplace netloc axi_cpu_interconnect_M01_AXI 1 6 5 2230 610 NJ 610 NJ 610 NJ 610 4340
|
|
preplace netloc axi_cpu_interconnect_M02_AXI 1 10 1 4550 280n
|
|
preplace netloc axi_cpu_interconnect_M03_AXI 1 10 4 4510 1860 5220J 1730 NJ 1730 6270J
|
|
preplace netloc axi_cpu_interconnect_M04_AXI 1 6 5 2240 620 NJ 620 NJ 620 NJ 620 4360
|
|
preplace netloc axi_cpu_interconnect_M05_AXI 1 5 6 1880 570 NJ 570 NJ 570 NJ 570 NJ 570 4420
|
|
preplace netloc axi_cpu_interconnect_M06_AXI 1 10 2 4450 2140 NJ
|
|
preplace netloc axi_cpu_interconnect_M07_AXI 1 10 1 4600 650n
|
|
preplace netloc axi_cpu_interconnect_M08_AXI 1 10 2 4500 1890 NJ
|
|
preplace netloc axi_cpu_interconnect_M09_AXI 1 6 5 2250 630 NJ 630 NJ 630 NJ 630 4350
|
|
preplace netloc axi_cpu_interconnect_M10_AXI 1 10 1 4690 1630n
|
|
preplace netloc axi_hp0_interconnect_M00_AXI 1 8 1 3010 900n
|
|
preplace netloc axi_hp1_interconnect_M00_AXI 1 8 1 3020 920n
|
|
preplace netloc axi_hp2_interconnect_M00_AXI 1 8 1 3030 940n
|
|
preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 7 1 2590 1430n
|
|
preplace netloc axi_mxfe_rx_xcvr_m_axi 1 7 1 2680 1230n
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 7 6 NJ 1330 3100J 1350 NJ 1350 4480J 2290 NJ 2290 5750
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 7 6 2680J 1360 NJ 1360 NJ 1360 4470J 2280 NJ 2280 5760
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 7 6 2730J 1550 NJ 1550 3980J 1370 4460J 2300 NJ 2300 5670
|
|
preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 7 6 2600 1560 NJ 1560 4010J 1380 4430J 2310 NJ 2310 5850J
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 7 6 2730J 1340 NJ 1340 3910J 1080 4590J 1020 NJ 1020 5860
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 7 6 NJ 1350 3040J 1380 3950J 1090 4620J 1030 NJ 1030 5850
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 7 6 2690 1370 NJ 1370 3960J 1100 4640J 1050 NJ 1050 5840J
|
|
preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 7 6 2580 1570 NJ 1570 3970J 1070 NJ 1070 NJ 1070 5820J
|
|
preplace netloc axi_mxfe_tx_dma_m_src_axi 1 7 1 N 1960
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 12 1 5830 1910n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 12 1 5790 1930n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 12 1 5810 1950n
|
|
preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 12 1 5730 1970n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 12 1 5740 2060n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 12 1 N 2140
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 12 1 5770 2160n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 12 1 5710 2180n
|
|
preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 12 1 5710 2000n
|
|
preplace netloc mxfe_rx_data_offload_m_axis 1 6 1 2200 1700n
|
|
preplace netloc s_axis_1 1 7 4 2680J 1620 NJ 1620 3860J 1720 4690
|
|
preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 9 1 3940 690n
|
|
preplace netloc tx_mxfe_tpl_core_link 1 11 1 5250 650n
|
|
preplace netloc util_mxfe_xcvr_rx_0 1 13 1 6240 2200n
|
|
preplace netloc util_mxfe_xcvr_rx_1 1 13 1 6250 2220n
|
|
preplace netloc util_mxfe_xcvr_rx_2 1 13 1 6260 2240n
|
|
preplace netloc util_mxfe_xcvr_rx_3 1 13 1 6270 2260n
|
|
preplace netloc axi_cpu_interconnect_M11_AXI 1 10 5 4490J 1870 5180J 1660 NJ 1660 NJ 1660 NJ
|
|
preplace netloc mxfe_tx_data_offload_m_axis 1 11 4 5190J 1770 NJ 1770 NJ 1770 6720J
|
|
preplace netloc util_mxfe_upack_s_axis 1 0 12 NJ 820 NJ 820 NJ 820 NJ 820 NJ 820 NJ 820 NJ 820 NJ 820 3130J 1330 3890J 900 NJ 900 5200
|
|
levelinfo -pg 1 -10 210 580 880 1130 1570 2030 2410 2870 3450 4190 4960 5530 6030 6430 6740
|
|
pagesize -pg 1 -db -bbox -sgen -230 0 7020 3240
|
|
"
|
|
}
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
validate_bd_design
|
|
save_bd_design
|
|
close_bd_design $design_name
|
|
}
|
|
# End of cr_bd_system()
|
|
|
|
cr_bd_system ""
|
|
set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ]
|
|
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ]
|
|
|
|
set idrFlowPropertiesConstraints ""
|
|
catch {
|
|
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
|
|
set_param runs.disableIDRFlowPropertyConstraints 1
|
|
}
|
|
|
|
# Create 'synth_1' run (if not found)
|
|
if {[string equal [get_runs -quiet synth_1] ""]} {
|
|
create_run -name synth_1 -part xczu19eg-ffvc1760-2-i -flow {Vivado Synthesis 2023} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
|
} else {
|
|
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
|
set_property flow "Vivado Synthesis 2023" [get_runs synth_1]
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
|
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
set obj [get_runs synth_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
|
|
|
# set the current synth run
|
|
current_run -synthesis [get_runs synth_1]
|
|
|
|
# Create 'impl_1' run (if not found)
|
|
if {[string equal [get_runs -quiet impl_1] ""]} {
|
|
create_run -name impl_1 -part xczu19eg-ffvc1760-2-i -flow {Vivado Implementation 2023} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
|
} else {
|
|
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
|
set_property flow "Vivado Implementation 2023" [get_runs impl_1]
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property set_report_strategy_name 1 $obj
|
|
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
|
set_property set_report_strategy_name 0 $obj
|
|
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_io_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.verbose" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "is_enabled" -value "0" -objects $obj
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_drc_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_power_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
|
if { $obj != "" } {
|
|
|
|
}
|
|
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
|
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
|
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
|
}
|
|
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
|
if { $obj != "" } {
|
|
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
|
|
}
|
|
set obj [get_runs impl_1]
|
|
set_property -name "needs_refresh" -value "1" -objects $obj
|
|
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
|
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
|
|
|
# set the current impl run
|
|
current_run -implementation [get_runs impl_1]
|
|
catch {
|
|
if { $idrFlowPropertiesConstraints != {} } {
|
|
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
|
|
}
|
|
}
|
|
|
|
puts "INFO: Project created:${_xil_proj_name_}"
|
|
# Create 'drc_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {drc_1} -type drc
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
|
|
|
# Create 'methodology_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {methodology_1} -type methodology
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
|
|
|
# Create 'power_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {power_1} -type power
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
|
|
|
# Create 'timing_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {timing_1} -type timing
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
|
|
|
# Create 'utilization_1' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_1} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
|
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
|
set_property -name "run.step" -value "synth_design" -objects $obj
|
|
set_property -name "run.type" -value "synthesis" -objects $obj
|
|
|
|
# Create 'utilization_2' gadget (if not found)
|
|
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
|
create_dashboard_gadget -name {utilization_2} -type utilization
|
|
}
|
|
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
|
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
|
|
|
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
|
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
|
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
|
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
|
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
|
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|