116 lines
4.3 KiB
VHDL
116 lines
4.3 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 05/18/2021 11:43:02 AM
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-- Design Name:
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-- Module Name: axis_mux - imp
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity axis_mux is
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generic(
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DWIDTH : integer := 512
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);
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port (
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aclk : in STD_LOGIC;
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aresetn : in std_logic;
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aselect : in std_logic;
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s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
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s0_axis_tvalid : in std_logic;
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s0_axis_tready : out std_logic;
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s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
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s1_axis_tvalid : in std_logic;
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s1_axis_tready : out std_logic;
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m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
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m_axis_tvalid : out std_logic;
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m_axis_tready : in std_logic
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);
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end axis_mux;
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architecture imp of axis_mux is
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-- ATTRIBUTE X_INTERFACE_INFO : STRING;
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-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
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-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
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-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
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-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
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-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
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-- -- Use the port name for ASSOCIATED_RESET.
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-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
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-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
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-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
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-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
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-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
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-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
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-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
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-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
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-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
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-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
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-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
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-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
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-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
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signal aselect_int : std_logic;
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begin
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-- i_xpm_cdc_single_0 : xpm_cdc_single
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-- generic map(
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-- DEST_SYNC_FF => 4,
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-- INIT_SYNC_FF => 0,
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-- SIM_ASSERT_CHK => 0,
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-- SRC_INPUT_REG => 0
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-- )
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-- port map(
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-- dest_out => aselect_int,
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-- dest_clk => aclk,
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-- src_clk => '0',
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-- src_in => aselect
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-- );
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aselect_int <= aselect;
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m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
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m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
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s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
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s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
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end imp;
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