Erisys/zcu102_ad9081_dds_x4
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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-05-29 13:44:57 -07:00
commit 059f1cf45b
81 changed files with 122333 additions and 0 deletions
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ip_repo/dds_pulse_intfc_1_0/bd/bd.tcl
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}
ip_repo/dds_pulse_intfc_1_0/component.xml
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ip_repo/dds_pulse_intfc_1_0/hdl/dds_pulse_intfc_v1_0.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dds_pulse_intfc_v1_0 is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"00";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
m_axis_aclk : in std_logic;
reset : in std_logic;
m_axis_tdata : out std_logic_vector(127 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
s00_axis_tdata : in std_logic_vector(127 downto 0);
s00_axis_tvalid : in std_logic;
s00_axis_tready : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end dds_pulse_intfc_v1_0;
architecture arch_imp of dds_pulse_intfc_v1_0 is
-- -- component declaration
-- component dds_pulse_intfc_v1_0_S00_AXI is
-- generic (
-- FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
-- MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- C_S_AXI_DATA_WIDTH : integer := 32;
-- C_S_AXI_ADDR_WIDTH : integer := 6
-- );
-- port (
-- cmd_idx_out : out std_logic_vector( 2 downto 0);
-- cmd_send_out : out std_logic;
--
-- mode_out : out std_logic;
-- scale_out : out std_logic_vector(15 downto 0);
-- dac_holdoff_out : out std_logic;
--
-- reserv1_out : out std_logic_vector(31 downto 0);
-- dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
-- dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
-- idle_samples_out : out std_logic_vector(31 downto 0);
-- dds_samples_out : out std_logic_vector(31 downto 0);
-- phase_inc_out : out std_logic_vector(31 downto 0);
-- phase_off_out : out std_logic_vector(31 downto 0);
-- swap_sf_out : out std_logic_vector(31 downto 0);
--
-- cmd_send_cnt_in : in std_logic_vector(31 downto 0);
-- pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
-- m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
-- dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
--
--
-- S_AXI_ACLK : in std_logic;
-- S_AXI_ARESETN : in std_logic;
-- S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- S_AXI_AWVALID : in std_logic;
-- S_AXI_AWREADY : out std_logic;
-- S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- S_AXI_WVALID : in std_logic;
-- S_AXI_WREADY : out std_logic;
-- S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- S_AXI_BVALID : out std_logic;
-- S_AXI_BREADY : in std_logic;
-- S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- S_AXI_ARVALID : in std_logic;
-- S_AXI_ARREADY : out std_logic;
-- S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- S_AXI_RVALID : out std_logic;
-- S_AXI_RREADY : in std_logic
-- );
-- end component dds_pulse_intfc_v1_0_S00_AXI;
signal cmd_idx : std_logic_vector( 2 downto 0);
signal cmd_send : std_logic;
signal mode : std_logic;
signal scale : std_logic_vector(15 downto 0);
signal dac_holdoff : std_logic;
signal reserv1 : std_logic_vector(31 downto 0);
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
signal idle_samples : std_logic_vector(31 downto 0);
signal dds_samples : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_off : std_logic_vector(31 downto 0);
signal swap_sf : std_logic_vector(31 downto 0);
signal cmd_send_cnt : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rden_cnt : std_logic_vector(31 downto 0);
signal m_axis_tvalid_cnt : std_logic_vector(31 downto 0);
signal dds_pulse_data_cnt : std_logic_vector(31 downto 0);
signal dac_data_src_sel : std_logic;
signal m_axis_tdata_i : std_logic_vector(127 downto 0);
signal m_axis_tvalid_i : std_logic;
signal m_axis_tready_i : std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
generic map (
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
MINOR_REV => MINOR_REV,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
cmd_idx_out => cmd_idx,
cmd_send_out => cmd_send,
mode_out => mode,
scale_out => scale,
dac_holdoff_out => dac_holdoff,
reserv1_out => reserv1,
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time,
dds_phase_inc_step_size_out => dds_phase_inc_step_size,
idle_samples_out => idle_samples,
dds_samples_out => dds_samples,
phase_inc_out => phase_inc,
phase_off_out => phase_off,
swap_sf_out => swap_sf,
dac_data_src_sel_out => dac_data_src_sel,
cmd_send_cnt_in => cmd_send_cnt,
pipe_in_ch1_fifo_rden_cnt_in => pipe_in_ch1_fifo_rden_cnt,
m_axis_tvalid_cnt_in => m_axis_tvalid_cnt,
dds_pulse_data_cnt_in => dds_pulse_data_cnt,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
i_dds_pulse_wrapper : entity work.dds_pulse_wrapper
generic map (
SIM_ENABLED => FALSE,
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
MINOR_REV => MINOR_REV
)
port map (
s_axi_aclk_in => s00_axi_aclk,
s_axi_aresetn_in => s00_axi_aresetn,
cmd_idx_in => cmd_idx,
cmd_send_in => cmd_send,
mode_in => mode,
scale_in => scale,
dac_holdoff_in => dac_holdoff,
reserv1_in => reserv1,
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
idle_samples_in => idle_samples,
dds_samples_in => dds_samples,
phase_inc_in => phase_inc,
phase_off_in => phase_off,
swap_sf_in => swap_sf,
m_axis_aclk_in => m_axis_aclk,
m_axis_tdata_out => m_axis_tdata_i,
m_axis_tvalid_out => m_axis_tvalid_i,
m_axis_tready_in => m_axis_tready_i,
cmd_send_cnt_out => cmd_send_cnt,
pipe_in_ch1_fifo_rden_cnt_out => pipe_in_ch1_fifo_rden_cnt,
m_axis_tvalid_cnt_out => m_axis_tvalid_cnt,
dds_pulse_data_cnt_out => dds_pulse_data_cnt,
reset_in => reset
);
m_axis_tdata <= m_axis_tdata_i when dac_data_src_sel = '1' else s00_axis_tdata;
m_axis_tvalid <= m_axis_tvalid_i when dac_data_src_sel = '1' else s00_axis_tvalid;
m_axis_tready_i <= m_axis_tready when dac_data_src_sel = '1' else '0';
s00_axis_tready <= m_axis_tready when dac_data_src_sel = '0' else '0';
-- User logic ends
end arch_imp;
ip_repo/dds_pulse_intfc_1_0/hdl/dds_pulse_intfc_v1_0_S00_AXI.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dds_pulse_intfc_v1_0_S00_AXI is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
cmd_idx_out : out std_logic_vector( 2 downto 0);
cmd_send_out : out std_logic;
mode_out : out std_logic;
scale_out : out std_logic_vector(15 downto 0);
dac_holdoff_out : out std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
dac_data_src_sel_out : out std_logic;
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end dds_pulse_intfc_v1_0_S00_AXI;
architecture arch_imp of dds_pulse_intfc_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 16
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
else
slv_reg0(0) <= '0'; -- self clear bit 0
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= dds_pulse_data_cnt_in; --slv_reg0;
when b"0001" =>
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= slv_reg5;
when b"0110" =>
reg_data_out <= slv_reg6;
when b"0111" =>
reg_data_out <= slv_reg7;
when b"1000" =>
reg_data_out <= slv_reg8;
when b"1001" =>
reg_data_out <= slv_reg9;
when b"1010" =>
reg_data_out <= slv_reg10;
when b"1011" =>
reg_data_out <= slv_reg11;
when b"1100" =>
reg_data_out <= slv_reg12;
when b"1101" =>
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in(15 downto 0) & cmd_send_cnt_in(15 downto 0); -- slv_reg13;
when b"1110" =>
reg_data_out <= m_axis_tvalid_cnt_in; --slv_reg14
when b"1111" =>
reg_data_out <= FPGA_REVISION_DATE; --slv_reg15;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (slv_reg0(0) = '1') then
cmd_send_r <= "111";
else
cmd_send_r <= cmd_send_r(1 to 2) & '0';
end if;
end if;
end process;
cmd_send_out <= cmd_send_r(0);
dac_holdoff_out <= slv_reg1(0);
cmd_idx_out <= slv_reg2(2 downto 0);
scale_out <= slv_reg3(15 downto 0);
mode_out <= slv_reg4(0);
dac_data_src_sel_out <= slv_reg4(31);
reserv1_out <= slv_reg5;
dds_phase_inc_dwell_time_out <= slv_reg6;
dds_phase_inc_step_size_out <= slv_reg7;
idle_samples_out <= slv_reg8;
dds_samples_out <= slv_reg9;
phase_inc_out <= slv_reg10;
phase_off_out <= slv_reg11;
swap_sf_out <= slv_reg12;
-- User logic ends
end arch_imp;
ip_repo/dds_pulse_intfc_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci
+228
View File
@@ -0,0 +1,228 @@
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ip_repo/dds_pulse_intfc_1_0/src/addsub/addsub.xci
+216
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@@ -0,0 +1,216 @@
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ip_repo/dds_pulse_intfc_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci
+486
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@@ -0,0 +1,486 @@
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}
ip_repo/dds_pulse_intfc_1_0/src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci
+176
View File
@@ -0,0 +1,176 @@
{
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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}
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"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
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"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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}
}
ip_repo/dds_pulse_intfc_1_0/src/dds_cmd_gen.vhd
+219
View File
@@ -0,0 +1,219 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dds_cmd_gen is
generic (
SIM_ENABLED : boolean := FALSE
);
port(
clk_in : in std_logic;
cmd_idx_in : in std_logic_vector( 2 downto 0);
cmd_send_in : in std_logic;
vio_reserv1_in : in std_logic_vector(31 downto 0);
vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
vio_idle_samples_in : in std_logic_vector(31 downto 0);
vio_dds_samples_in : in std_logic_vector(31 downto 0);
vio_phase_inc_in : in std_logic_vector(31 downto 0);
vio_phase_off_in : in std_logic_vector(31 downto 0);
vio_swap_sf_in : in std_logic_vector(31 downto 0);
fifo_rd_clk_in : in std_logic;
fifo_rd_data_out : out std_logic_vector(31 downto 0);
fifo_rd_dval_out : out std_logic;
fifo_rd_rd_en_in : in std_logic;
fifo_rd_empty_out : out std_logic;
rst_in : in std_logic
);
end entity dds_cmd_gen;
architecture imp of dds_cmd_gen is
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_wr_en_r : std_logic := '0';
signal cmd_idx_r : integer range 0 to 4 := 0;
signal cmd_send_r : std_logic := '0';
type fsm_state is (IDLE, SEND, DONE);
signal state_r : fsm_state := IDLE;
signal state_cnt_r : integer := 0;
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
type dds_command_list is array (integer range <>) of array_32b_type;
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
--
-- Phase Inc Start = 2^32 * (1/250) = 17179869
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
--
signal dds_command_set : dds_command_list(0 to 4) :=
(
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
0 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
),
-- WFM 1
-- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
1 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
),
-- WFM 2
-- CW TONE
2 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
-- x"000FFFFF", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
),
-- WFM 3
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
3 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
x"000000FF", --IDLE_SAMPLES
x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
),
-- WFM 4
-- ??????
4 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
x"00000000", --IDLE_SAMPLES
x"00000000", --DDS_SAMPLES (~5 us)
x"00000000", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
)
);
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
begin
dds_command_set(4)(0) <= vio_reserv1_in;
dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in;
dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in;
dds_command_set(4)(3) <= vio_idle_samples_in;
dds_command_set(4)(4) <= vio_dds_samples_in;
dds_command_set(4)(5) <= vio_phase_inc_in;
dds_command_set(4)(6) <= vio_phase_off_in;
dds_command_set(4)(7) <= vio_swap_sf_in;
process(clk_in)
begin
if (rising_edge(clk_in)) then
-- if (rst_in = '1') then
-- cmd_idx_r <= 0;
-- cmd_send_r <= '0';
-- fifo_wr_en_r <= '0';
-- state_cnt_r <= 0;
-- state_r <= IDLE;
-- else
cmd_send_r <= cmd_send_in;
fifo_wr_en_r <= '0';
case (state_r) is
when IDLE =>
if (cmd_send_in = '1' and cmd_send_r = '0') then
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
state_cnt_r <= 0;
state_r <= SEND;
else
state_r <= IDLE;
end if;
when SEND =>
if (state_cnt_r = 8) then
state_r <= DONE;
else
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
fifo_wr_en_r <= '1';
state_cnt_r <= state_cnt_r + 1;
state_r <= SEND;
end if;
when DONE =>
state_r <= IDLE;
when others =>
state_r <= IDLE;
end case;
-- end if;
end if;
end process;
test_state_r <= "00" when state_r = IDLE else
"01" when state_r = SEND else
"10" when state_r = DONE else
"11";
sim_false : if (SIM_ENABLED = FALSE) generate
i_ila_1 : entity work.ila_2
port map (
clk => clk_in,
probe0 => test_state_r, -- 2
probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
probe2 => fifo_wr_data_r, -- 32
probe3(0) => fifo_wr_en_r, -- 1
probe4(0) => cmd_send_in, -- 1
probe5(0) => cmd_send_r -- 1
);
end generate sim_false;
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
port map(
wr_clk => clk_in,
din => fifo_wr_data_r,
wr_en => fifo_wr_en_r,
full => open,
overflow => open,
rd_clk => fifo_rd_clk_in,
dout => fifo_rd_data_out,
valid => fifo_rd_dval_out,
rd_en => fifo_rd_rd_en_in,
empty => fifo_rd_empty_out,
underflow => open,
prog_full => open,
wr_rst_busy => open,
rd_rst_busy => open,
srst => rst_in
);
end architecture imp;
ip_repo/dds_pulse_intfc_1_0/src/dds_latency10/dds_latency10.xci
+366
View File
@@ -0,0 +1,366 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "dds_latency10",
"cell_name": "i_dds_pulse_wrapper/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds",
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
"ip_revision": "22",
"gen_directory": "../../../../../../aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/dds_latency10",
"parameters": {
"component_parameters": {
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"DDS_Clock_Rate": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
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"boundary": {
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}
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"mode": "master",
"parameters": {
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"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
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"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
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}
},
"event_s_config_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
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"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
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"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"S_AXIS_PHASE": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
},
"port_maps": {
"CE": [ { "physical_name": "aclken" } ]
}
},
"M_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
}
}
}
}
}
}
ip_repo/dds_pulse_intfc_1_0/src/dds_pulse_2x_top.vhd
+419
View File
@@ -0,0 +1,419 @@
-------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M. Blevins
--
-- Create Date: 19:38:12 11/10/2016
-- Design Name:
-- Module Name: dds_pulse_2x_top - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- * All information is proprietary/confidential *
--
-- Supports single channel mode or dual channel (summed) mode.
-- When using dual channel mode, the module hangs after the shortest of the
-- two pulse streams completes. Ideally, both streams will be equal length.
--
-- For each channel:
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
-- The control word contains all information needed to create a pulse
--
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library UNIMACRO;
--use UNIMACRO.vcomponents.all;
USE IEEE.NUMERIC_STD.ALL;
entity dds_pulse_2x_top is
port(
clk_in : in std_logic;
rst_in : in std_logic;
mode_in : in std_logic; -- 0=single, 1=dual
scale_in : in std_logic_vector(15 downto 0);
fifo1_data_in : in std_logic_vector(31 downto 0);
fifo1_dval_in : in std_logic;
fifo1_empty_in : in std_logic;
fifo1_rden_out : out std_logic;
fifo2_data_in : in std_logic_vector(31 downto 0);
fifo2_dval_in : in std_logic;
fifo2_empty_in : in std_logic;
fifo2_rden_out : out std_logic;
holdoff_in : in std_logic;
overflow_out : out std_logic_vector(1 downto 0);
underflow_out : out std_logic_vector(1 downto 0);
i_max_abs_out : out std_logic_vector(15 downto 0);
q_max_abs_out : out std_logic_vector(15 downto 0);
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic
);
end entity;
architecture mixed of dds_pulse_2x_top is
component mult_16signed_x_16unsigned_latency3
port(
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
ce : in std_logic;
sclr : in std_logic;
p : out std_logic_vector(15 downto 0)
);
end component;
component dds_pulse_gen is
port(
clk_in : in std_logic;
rst_in : in std_logic;
fifo_data_in : in std_logic_vector(31 downto 0);
fifo_dval_in : in std_logic;
fifo_empty_in : in std_logic;
fifo_rden_out : out std_logic;
holdoff_in : in std_logic;
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic
);
end component;
component sfifo_32b_1024_pf992_latency1
port(
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
overflow : out std_logic;
empty : out std_logic;
underflow : out std_logic;
prog_full : out std_logic
);
end component;
component adder_16signed_16signed_latency2
port(
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
clk : in std_logic;
ce : in std_logic;
bypass : in std_logic;
s : out std_logic_vector(16 downto 0)
);
end component;
signal rst_r : std_logic := '1';
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
signal pulse_adder_dval_r : std_logic := '0';
signal pulse_adder_ce : std_logic;
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
signal pulse_dval_r : std_logic := '0';
signal adder_dval_r : std_logic := '0';
signal holdoff_r : std_logic;
signal pulse1_mult_dval_r : std_logic := '0';
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal pulse1_mult_ce : std_logic;
signal pulse1_data : std_logic_vector(31 downto 0);
signal pulse1_dval : std_logic;
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
signal pulse1_fifo_overflow : std_logic;
signal pulse1_fifo_empty : std_logic;
signal pulse1_fifo_underflow : std_logic;
signal pulse1_fifo_progfull : std_logic;
signal pulse1_fifo_rden : std_logic;
signal pulse1_fifo_rden_r : std_logic := '0';
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
signal adder1_s : std_logic_vector(16 downto 0);
signal adder1_s_r : std_logic_vector(16 downto 0);
signal adder1_s_r1 : std_logic_vector(15 downto 0);
signal i_abs_max_r : unsigned(15 downto 0);
signal fifo1_underflow_r : std_logic := '0';
signal fifo1_overflow_r : std_logic := '0';
signal pulse2_mult_dval_r : std_logic := '0';
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal pulse2_mult_ce : std_logic;
signal pulse2_data : std_logic_vector(31 downto 0);
signal pulse2_dval : std_logic;
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
signal pulse2_fifo_overflow : std_logic;
signal pulse2_fifo_empty : std_logic;
signal pulse2_fifo_underflow : std_logic;
signal pulse2_fifo_progfull : std_logic;
signal pulse2_fifo_rden : std_logic;
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
signal adder2_s : std_logic_vector(16 downto 0);
signal adder2_s_r : std_logic_vector(16 downto 0);
signal adder2_s_r1 : std_logic_vector(15 downto 0);
signal q_abs_max_r : unsigned(15 downto 0);
signal fifo2_underflow_r : std_logic := '0';
signal fifo2_overflow_r : std_logic := '0';
begin
data_out <= pulse_data_r;
dval_out <= pulse_dval_r;
i_max_abs_out <= std_logic_vector(i_abs_max_r);
q_max_abs_out <= std_logic_vector(q_abs_max_r);
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
process(clk_in)
begin
if(rising_edge(clk_in))then
rst_r <= rst_in;
scale_r <= scale_in;
mode_n_r <= not(mode_in);
holdoff_r <= holdoff_in;
end if;
end process;
process(clk_in)
begin
if(rising_edge(clk_in))then
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
pulse1_fifo_rden_r <= pulse1_fifo_rden;
pulse1_fifo_dout_r <= pulse1_fifo_dout;
pulse2_fifo_dout_r <= pulse2_fifo_dout;
end if;
end process;
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
not(pulse1_fifo_empty) and not(holdoff_r);
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
'0';
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
i_dds_pulse1_gen : dds_pulse_gen
port map(
clk_in => clk_in,
rst_in => rst_r,
fifo_data_in => fifo1_data_in,
fifo_dval_in => fifo1_dval_in,
fifo_empty_in => fifo1_empty_in,
fifo_rden_out => fifo1_rden_out,
holdoff_in => pulse1_fifo_progfull,
data_out => pulse1_data,
dval_out => pulse1_dval
);
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse1_data(15 downto 0),
b => scale_r,
ce => pulse1_mult_ce,
sclr => '0',
p => pulse1_data_scaled(15 downto 0)
);
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse1_data(31 downto 16),
b => scale_r,
ce => pulse1_mult_ce,
sclr => '0',
p => pulse1_data_scaled(31 downto 16)
);
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
port map(
clk => clk_in,
srst => rst_r,
din => pulse1_data_scaled,
wr_en => pulse1_mult_dval_r,
rd_en => pulse1_fifo_rden,
dout => pulse1_fifo_dout,
full => open,
overflow => pulse1_fifo_overflow,
empty => pulse1_fifo_empty,
underflow => pulse1_fifo_underflow,
prog_full => pulse1_fifo_progfull
);
i_dds_pulse2_gen : dds_pulse_gen
port map(
clk_in => clk_in,
rst_in => rst_r,
fifo_data_in => fifo2_data_in,
fifo_dval_in => fifo2_dval_in,
fifo_empty_in => fifo2_empty_in,
fifo_rden_out => fifo2_rden_out,
holdoff_in => pulse2_fifo_progfull,
data_out => pulse2_data,
dval_out => pulse2_dval
);
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse2_data(15 downto 0),
b => scale_r,
ce => pulse2_mult_ce,
sclr => '0',
p => pulse2_data_scaled(15 downto 0)
);
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse2_data(31 downto 16),
b => scale_r,
ce => pulse2_mult_ce,
sclr => '0',
p => pulse2_data_scaled(31 downto 16)
);
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
port map(
clk => clk_in,
srst => rst_r,
din => pulse2_data_scaled,
wr_en => pulse2_mult_dval_r,
rd_en => pulse2_fifo_rden,
dout => pulse2_fifo_dout,
full => open,
overflow => pulse2_fifo_overflow,
empty => pulse2_fifo_empty,
underflow => pulse2_fifo_underflow,
prog_full => pulse2_fifo_progfull
);
i_pulse_adder1 : adder_16signed_16signed_latency2
port map(
a => pulse2_fifo_dout_r(15 downto 0),
b => pulse1_fifo_dout_r(15 downto 0),
clk => clk_in,
ce => pulse_adder_ce,
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
s => adder1_s
);
i_pulse_adder2 : adder_16signed_16signed_latency2
port map(
a => pulse2_fifo_dout_r(31 downto 16),
b => pulse1_fifo_dout_r(31 downto 16),
clk => clk_in,
ce => pulse_adder_ce,
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
s => adder2_s
);
process(clk_in)
begin
if(rising_edge(clk_in))then
adder1_s_r <= adder1_s;
adder2_s_r <= adder2_s;
adder_dval_r <= pulse_adder_dval_r;
pulse_dval_r <= adder_dval_r;
if(adder_dval_r = '1')then
case adder1_s_r(16 downto 15) is
when "01" => --positive overflow
pulse_data_r(15 downto 0) <= x"7FFF";
when "10" => --negative overflow
pulse_data_r(15 downto 0) <= x"8000";
when others =>
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
end case;
case adder2_s_r(16 downto 15) is
when "01" => --positive overflow
pulse_data_r(31 downto 16) <= x"7FFF";
when "10" => --negative overflow
pulse_data_r(31 downto 16) <= x"8000";
when others =>
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
end case;
end if;
if(rst_r = '1')then
--adder_dval_r <= '0';
--pulse_dval_r <= '0';
i_abs_max_r <= (others => '0');
q_abs_max_r <= (others => '0');
fifo1_overflow_r <= '0';
fifo1_underflow_r <= '0';
fifo2_overflow_r <= '0';
fifo2_underflow_r <= '0';
else
--adder_dval_r <= pulse_adder_dval_r;
--pulse_dval_r <= adder_dval_r;
if(pulse1_fifo_overflow = '1')then
fifo1_overflow_r <= '1';
end if;
if(pulse1_fifo_underflow = '1')then
fifo1_underflow_r <= '1';
end if;
if(pulse2_fifo_overflow = '1')then
fifo2_overflow_r <= '1';
end if;
if(pulse2_fifo_underflow = '1')then
fifo2_underflow_r <= '1';
end if;
if(adder_dval_r = '1')then
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
-- i_abs_max_r <= abs(signed(adder1_s_r));
-- end if;
if(adder1_s_r(16) = '0')then
adder1_s_r1 <= adder1_s_r(15 downto 0);
else
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
end if;
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
-- q_abs_max_r <= abs(signed(adder2_s_r));
-- end if;
if(adder2_s_r(16) = '0')then
adder2_s_r1 <= adder2_s_r(15 downto 0);
else
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
end if;
end if;
if(pulse_dval_r = '1')then
if(unsigned(adder1_s_r1) > i_abs_max_r)then
i_abs_max_r <= unsigned(adder1_s_r1);
end if;
if(unsigned(adder2_s_r1) > q_abs_max_r)then
q_abs_max_r <= unsigned(adder2_s_r1);
end if;
end if;
end if;
end if;
end process;
end mixed;
ip_repo/dds_pulse_intfc_1_0/src/dds_pulse_gen.vhd
+415
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@@ -0,0 +1,415 @@
-------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M. Blevins
--
-- Create Date: 19:38:12 11/10/2016
-- Design Name:
-- Module Name: dds_pulse_gen - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
-- Additional Comments:
-- * All information is proprietary/confidential *
--
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
-- The control word contains all information needed to create a pulse
--
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library UNIMACRO;
--use UNIMACRO.vcomponents.all;
USE IEEE.NUMERIC_STD.ALL;
entity dds_pulse_gen is
port(
clk_in : in std_logic;
rst_in : in std_logic;
fifo_data_in : in std_logic_vector(31 downto 0);
fifo_dval_in : in std_logic;
fifo_empty_in : in std_logic;
fifo_rden_out : out std_logic;
holdoff_in : in std_logic;
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic
);
end entity;
architecture mixed of dds_pulse_gen is
component mult_16signed_x_16unsigned_latency3
port(
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
ce : in std_logic;
sclr : in std_logic;
p : out std_logic_vector(15 downto 0)
);
end component;
component dds_latency10
port(
-- ce : in std_logic;
-- clk : in std_logic;
-- sclr : in std_logic;
-- pinc_in : in std_logic_vector(31 downto 0);
-- poff_in : in std_logic_vector(31 downto 0);
-- rdy : out std_logic;
-- cosine : out std_logic_vector(15 downto 0);
-- sine : out std_logic_vector(15 downto 0)
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
component addsub
port (
a : in std_logic_vector(31 downto 0); -- unsigned
b : in std_logic_vector(23 downto 0); -- signed
--clk : in std_logic;
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
);
end component;
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
signal state : state_type;
signal state_r : state_type;
signal rst_r : std_logic := '1';
signal rstn_r : std_logic := '0';
signal cnt1_r : unsigned(3 downto 0) := "0000";
signal cnt1 : unsigned(3 downto 0);
signal cnt2_r : unsigned(2 downto 0) := "000";
signal cnt2 : unsigned(2 downto 0);
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
signal cnt3 : unsigned(31 downto 0);
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
signal cnt4 : unsigned(31 downto 0);
signal cnt5_r : unsigned(3 downto 0) := "0000";
signal cnt5 : unsigned(3 downto 0);
signal fifo_data_ce : std_logic;
signal fifo_data_r : std_logic_vector(255 downto 0);
signal fifo_rden : std_logic;
--signal fifo_rden_r : std_logic := '0';
signal dval_r : std_logic := '0';
signal dval : std_logic;
signal dds_data : std_logic_vector(31 downto 0);
signal data : std_logic_vector(31 downto 0);
signal data_r : std_logic_vector(31 downto 0);
signal idle_sample_cnt_r : unsigned(31 downto 0);
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
signal dds_sample_cnt_r : unsigned(31 downto 0);
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
signal phase_inc_init_r : std_logic_vector(31 downto 0);
signal phase_offset_r : std_logic_vector(31 downto 0);
signal swap_r : std_logic := '0';
signal scale_r : std_logic_vector(15 downto 0);
signal mult_dval_r : std_logic := '0';
signal data_swap_scaled : std_logic_vector(31 downto 0);
signal data_scaled : std_logic_vector(31 downto 0);
signal dds_ce : std_logic;
signal dds_rst : std_logic;
signal dds_rdy : std_logic;
signal mult_ce : std_logic;
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal holdoff_r : std_logic;
--signal phase_inc_mux_sel : std_logic;
signal phase_inc_update_en : std_logic;
--signal phase_inc_mux : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_inc_r : std_logic_vector(31 downto 0);
signal phase_inc_r1 : std_logic_vector(31 downto 0);
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
signal phase_inc_addsub : std_logic_vector(31 downto 0);
signal rstn : std_logic;
begin
i_addsub : addsub
port map(
a => phase_inc_r,
b => phase_inc_step_r,
--clk => clk_in,
s => phase_inc_addsub
);
fifo_rden_out <= fifo_rden;--fifo_rden_r;
data_out <= data_r;
dval_out <= dval_r;
process(clk_in)
begin
if(rising_edge(clk_in))then
if(rst_r = '1')then
state_r <= s0;
cnt1_r <= (others => '0');
cnt2_r <= (others => '0');
cnt3_r <= (others => '0');
cnt4_r <= (others => '0');
cnt5_r <= (others => '0');
phase_inc_dwell_cnt_r <= (others => '0');
else
state_r <= state;
cnt1_r <= cnt1;
cnt2_r <= cnt2;
cnt3_r <= cnt3;
cnt4_r <= cnt4;
cnt5_r <= cnt5;
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
end if;
if(fifo_data_ce = '1')then
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
end if;
rst_r <= rst_in;
rstn_r <= not(rst_in);
dval_r <= dval;
phase_offset_r <= fifo_data_r(223 downto 192);
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
dds_sample_cnt_r1 <= dds_sample_cnt_r;
swap_r <= fifo_data_r(240);
scale_r <= fifo_data_r(239 downto 224);
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
idle_sample_cnt_r1 <= idle_sample_cnt_r;
phase_inc_step_r <= fifo_data_r(87 downto 64);
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
data_r <= data;
holdoff_r <= holdoff_in;
phase_inc_r <= phase_inc;
if(phase_inc_update_en = '1')then
phase_inc_r1 <= phase_inc_r;
end if;
end if;
end process;
phase_inc_init_r <= fifo_data_r(191 downto 160);
-- FSM next-state & output process
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
begin
--defaults
fifo_rden <= '0';
cnt1 <= cnt1_r;
cnt2 <= cnt2_r;
cnt3 <= cnt3_r;
cnt4 <= cnt4_r;
cnt5 <= cnt5_r;
state <= state_r;
dds_ce <= '0';
dds_rst <= '1';
dval <= mult_dval_r;
data <= data_swap_scaled;
fifo_data_ce <= '0';
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
phase_inc <= phase_inc_r;
phase_inc_update_en <= '0';
case state_r is
when s0 =>
phase_inc_dwell_cnt <= (others => '0');
if(fifo_empty_in = '0' and cnt1_r < 8)then
fifo_rden <= '1';
cnt1 <= cnt1_r +1;
end if;
if(fifo_dval_in = '1')then
fifo_data_ce <= '1';
if(cnt2_r < 7)then
cnt2 <= cnt2_r +1;
else
cnt2 <= (others => '0');
cnt1 <= (others => '0');
state <= s0a;
end if;
end if;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
when s0a =>
state <= s0b;--s1;
phase_inc <= phase_inc_init_r;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
when s0b =>
state <= s1;
phase_inc_update_en <= '1';
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
-- when s0c =>
-- state <= s1;
-- phase_inc_update_en <= '1';
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
-- Insert midpoint (idle) samples that preceed the pulse.
when s1 =>
data <= MIDPOINT;
if(cnt3_r < idle_sample_cnt_r1)then
if(holdoff_r = '0')then
cnt3 <= cnt3_r +1;
dval <= '1';
end if;
else
cnt3 <= (others => '0');
if(dds_sample_cnt_r1 > 0)then
state <= s2;
else
state <= s0;
end if;
end if;
-- Turn on DDS for requested number of samples.
when s2 =>
dds_rst <= '0';
if(holdoff_r = '0')then
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
else
phase_inc_dwell_cnt <= (others => '0');
phase_inc_update_en <= '1';
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
end if;
end if;
if(holdoff_r = '0')then
dds_ce <= '1';
if(cnt4_r < dds_sample_cnt_r1)then
cnt4 <= cnt4_r +1;
else
cnt4 <= (others => '0');
state <= s3;
end if;
end if;
-- phase_inc_mux_sel <= '1';
-- --phase_inc_en <= not(holdoff_r);
-- dds_rst <= '0';
-- if(cnt4_r < dds_sample_cnt_r1)then
-- if(holdoff_r = '0')then
-- dds_ce <= '1';
-- cnt4 <= cnt4_r +1;
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
-- else
-- phase_inc_dwell_cnt <= x"00000";
-- phase_inc_en <= '1';
-- end if;
-- end if;
-- else
-- if(holdoff_r = '0')then
-- dds_ce <= '1';
-- cnt4 <= (others => '0');
-- state <= s3;
-- end if;
-- end if;
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
when s3 =>
dds_rst <= '0';
if(cnt5_r < 9)then
if(holdoff_r = '0')then
dds_ce <= '1';
cnt5 <= cnt5_r +1;
end if;
else
cnt5 <= (others => '0');
state <= s0;
end if;
when others =>
end case;
end process;
process(clk_in)
begin
if(rising_edge(clk_in))then
mult_dval_r <= mult_ce_pipe_r(1);
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
end if;
end process;
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
i_dds : dds_latency10
port map(
-- ce => dds_ce,
-- clk => clk_in,
-- sclr => dds_rst,
-- pinc_in => phase_inc_r1,
-- poff_in => phase_offset_r,
-- rdy => dds_rdy,
-- cosine => dds_data(15 downto 0),
-- sine => dds_data(31 downto 16)
aclk => clk_in,
aclken => dds_ce,
aresetn => rstn_r,
s_axis_phase_tvalid => dds_ce,
s_axis_phase_tdata => phase_inc_r1,
m_axis_data_tvalid => dds_rdy,
m_axis_data_tdata => dds_data(31 downto 0)
);
i_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => dds_data(15 downto 0),
b => scale_r,
ce => mult_ce,
sclr => '0',
p => data_scaled(15 downto 0)
);
i_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => dds_data(31 downto 16),
b => scale_r,
ce => mult_ce,
sclr => '0',
p => data_scaled(31 downto 16)
);
end mixed;
ip_repo/dds_pulse_intfc_1_0/src/dds_pulse_wrapper.vhd
+606
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@@ -0,0 +1,606 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
entity dds_pulse_wrapper is
generic (
SIM_ENABLED : boolean := FALSE;
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
);
port(
s_axi_aclk_in : in std_logic;
s_axi_aresetn_in : in std_logic;
cmd_idx_in : in std_logic_vector( 2 downto 0);
cmd_send_in : in std_logic;
mode_in : in std_logic;
scale_in : in std_logic_vector(15 downto 0);
dac_holdoff_in : in std_logic;
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
m_axis_aclk_in : in std_logic;
m_axis_tdata_out : out std_logic_vector(127 downto 0);
m_axis_tvalid_out : out std_logic;
m_axis_tready_in : in std_logic;
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
reset_in : in std_logic
);
end entity dds_pulse_wrapper;
architecture imp of dds_pulse_wrapper is
constant ok_clk_in_period : time := 10 ns;
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
attribute keep of minor_rev_r : signal is "true";
signal reset_n : std_logic;
signal s_axi_areset : std_logic;
signal s_axis_tready : std_logic;
signal cmd_idx : std_logic_vector( 2 downto 0);
signal cmd_send : std_logic;
signal mode : std_logic;
signal scale : std_logic_vector(15 downto 0);
signal dac_holdoff : std_logic;
signal reserv1 : std_logic_vector(31 downto 0);
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
signal idle_samples : std_logic_vector(31 downto 0);
signal dds_samples : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_off : std_logic_vector(31 downto 0);
signal swap_sf : std_logic_vector(31 downto 0);
signal dds_pulse_dval : std_logic;
signal dds_pulse_data : std_logic_vector(31 downto 0);
signal pulse_i : std_logic_vector(15 downto 0);
signal pulse_q : std_logic_vector(15 downto 0);
signal pipe_in_ch1_fifo_rden : std_logic;
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rd_dval : std_logic;
signal pipe_in_ch1_fifo_empty : std_logic;
signal pipe_in_ch2_fifo_rden : std_logic;
signal m_axis_tdata : std_logic_vector(63 downto 0);
signal m_axis_tvalid : std_logic;
signal pulse_data_word_r : std_logic_vector(63 downto 0) := (others => '0');
signal pulse_data_word_dval_r : std_logic := '0';
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
signal vio_cmd_send : std_logic;
signal vio_mode : std_logic;
signal vio_scale : std_logic_vector(15 downto 0);
signal vio_dac_holdoff : std_logic;
signal vio_reserv1 : std_logic_vector(31 downto 0);
attribute keep of vio_reserv1 : signal is "true";
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
signal vio_idle_samples : std_logic_vector(31 downto 0);
attribute keep of vio_idle_samples : signal is "true";
signal vio_dds_samples : std_logic_vector(31 downto 0);
attribute keep of vio_dds_samples : signal is "true";
signal vio_phase_inc : std_logic_vector(31 downto 0);
attribute keep of vio_phase_inc : signal is "true";
signal vio_phase_off : std_logic_vector(31 downto 0);
attribute keep of vio_phase_off : signal is "true";
signal vio_swap_sf : std_logic_vector(31 downto 0);
attribute keep of vio_swap_sf : signal is "true";
signal vio_enable : std_logic;
signal vio_cnt_rst : std_logic;
signal cmd_send_r : std_logic := '0';
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_tvalid_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tick_1ms : std_logic;
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
-- file DataFile : text;
signal read_toggle_r : std_logic := '0';
signal dds_m_axis_tready : std_logic;
begin
cmd_send_cnt_out <= cmd_send_cnt_r;
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
m_axis_tvalid_cnt_out <= m_axis_tvalid_cnt_r;
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
reset_n <= not reset_in; -- synchronous with m_axis_aclk_in
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
fpga_revision_date_r <= FPGA_REVISION_DATE;
minor_rev_r <= MINOR_REV;
end if;
end process;
sim_false : if (SIM_ENABLED = FALSE) generate
i_vio_0 : entity work.vio_0
port map (
clk => s_axi_aclk_in,
probe_in0 => fpga_revision_date_r, -- 32
probe_in1 => minor_rev_r, -- 8
probe_in2 => m_axis_aclk_freq_r, -- 32
probe_in3 => m_axis_aclk_cnt_r , -- 32
probe_in4 => s_axi_aclk_freq_r, -- 32
probe_in5 => s_axi_aclk_cnt_r , -- 32
probe_in6 => dds_pulse_data_overflow_cnt_r,
probe_out0(0) => vio_mode, -- 1
probe_out1 => vio_scale, -- 16
probe_out2 => vio_cmd_idx, -- 3
probe_out3(0) => vio_cmd_send, -- 1
probe_out4(0) => vio_dac_holdoff, -- 1
probe_out5 => vio_reserv1, -- 32
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
probe_out7 => vio_dds_phase_inc_step_size, -- 32
probe_out8 => vio_idle_samples, -- 32
probe_out9 => vio_dds_samples, -- 32
probe_out10 => vio_phase_inc, -- 32
probe_out11 => vio_phase_off, -- 32
probe_out12 => vio_swap_sf, -- 32
probe_out13 => vio_enable, -- 1
probe_out14 => vio_cnt_rst -- 1
);
end generate sim_false;
mode <= vio_mode when vio_enable = '1' else mode_in;
scale <= vio_scale when vio_enable = '1' else scale_in;
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
-- mode <= vio_mode;
-- scale <= vio_scale;
-- dac_holdoff <= vio_dac_holdoff;
-- cmd_idx <= vio_cmd_idx;
-- cmd_send <= vio_cmd_send;
--
-- reserv1 <= vio_reserv1;
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
-- idle_samples <= vio_idle_samples;
-- dds_samples <= vio_dds_samples;
-- phase_inc <= vio_phase_inc;
-- phase_off <= vio_phase_off;
-- swap_sf <= vio_swap_sf;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
cmd_send_r <= cmd_send;
if (cmd_send = '1' and cmd_send_r = '0') then
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
end if;
end if;
end process;
i_dds_cmd_gen : entity work.dds_cmd_gen
generic map (
SIM_ENABLED => SIM_ENABLED
)
port map (
clk_in => s_axi_aclk_in,
cmd_idx_in => cmd_idx,
cmd_send_in => cmd_send,
vio_reserv1_in => reserv1,
vio_dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
vio_dds_phase_inc_step_size_in => dds_phase_inc_step_size,
vio_idle_samples_in => idle_samples,
vio_dds_samples_in => dds_samples,
vio_phase_inc_in => phase_inc,
vio_phase_off_in => phase_off,
vio_swap_sf_in => swap_sf,
fifo_rd_clk_in => m_axis_aclk_in,
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
rst_in => s_axi_areset
);
sim_false1 : if (SIM_ENABLED = FALSE) generate
i_ila_4 : entity work.ila_4
port map (
clk => m_axis_aclk_in,
probe0 => pipe_in_ch1_fifo_rd_data, --32
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
probe2(0) => pipe_in_ch1_fifo_rden, --1
probe3(0) => pipe_in_ch1_fifo_empty --1
);
end generate sim_false1;
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
port map(
clk_in => m_axis_aclk_in,
rst_in => reset_in,
mode_in => mode, -- 0=single, 1=dual
scale_in => scale,
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
fifo1_empty_in => pipe_in_ch1_fifo_empty,
fifo1_rden_out => pipe_in_ch1_fifo_rden,
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
fifo2_rden_out => pipe_in_ch2_fifo_rden,
holdoff_in => dac_holdoff,
overflow_out => open,
underflow_out => open,
i_max_abs_out => open,
q_max_abs_out => open,
data_out => dds_pulse_data,
dval_out => dds_pulse_dval
);
pulse_i <= dds_pulse_data(15 downto 0);
pulse_q <= dds_pulse_data(31 downto 16);
-- process(m_axis_aclk_in)
-- variable LineOut : line;
-- begin
-- if (rising_edge(m_axis_aclk_in)) then
-- if (dds_pulse_dval = '1') then
-- hwrite(LineOut, dds_pulse_data);
-- writeline(DataFile, LineOut);
-- end if;
-- end if;
-- end process;
process(m_axis_aclk_in, vio_cnt_rst)
begin
if(vio_cnt_rst = '1') then
dds_pulse_data_cnt_r <= (others => '0');
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
m_axis_tvalid_cnt_r <= (others => '0');
dds_pulse_data_overflow_cnt_r <= (others => '0');
elsif (rising_edge(m_axis_aclk_in)) then
if (pulse_data_word_dval_r = '1' and s_axis_tready = '1') then
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
end if;
if (pulse_data_word_dval_r = '1' and s_axis_tready = '0') then
dds_pulse_data_overflow_cnt_r <= dds_pulse_data_overflow_cnt_r + 1;
end if;
if (pipe_in_ch1_fifo_rden = '1') then
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
end if;
if (m_axis_tvalid = '1' and m_axis_tready_in = '1') then
m_axis_tvalid_cnt_r <= m_axis_tvalid_cnt_r + 1;
end if;
end if;
end process;
sim_false2 : if (SIM_ENABLED = FALSE) generate
i_ila_3 : entity work.ila_3
port map (
clk => m_axis_aclk_in,
probe0 => dds_pulse_data(15 downto 0),
probe1 => dds_pulse_data(31 downto 16),
probe2(0) => dds_pulse_dval,
probe3(0) => s_axis_tready
);
end generate sim_false2;
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
pulse_data_word_dval_r <= '0';
if (dds_pulse_dval = '1') then
read_toggle_r <= not read_toggle_r;
if (read_toggle_r = '0') then
pulse_data_word_r(31 downto 0) <= dds_pulse_data;
else
pulse_data_word_r(63 downto 32) <= dds_pulse_data;
pulse_data_word_dval_r <= '1';
end if;
end if;
end if;
end process;
-- this FIFO is actually 32K by 64
i_fifo : entity work.axis_data_fifo_512x128
port map (
s_axis_aclk => m_axis_aclk_in,
s_axis_aresetn => reset_n,
s_axis_tdata => pulse_data_word_r, ---dds_pulse_data,
s_axis_tvalid => pulse_data_word_dval_r, --dds_pulse_dval,
s_axis_tready => s_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready_in
);
m_axis_tdata_out <= m_axis_tdata & m_axis_tdata;--- & m_axis_tdata & m_axis_tdata;
m_axis_tvalid_out <= m_axis_tvalid;
-- dds_m_axis_tready <= '1' when read_toggle_r = '0' and m_axis_tready_in = '1' else '0';
--
-- process(m_axis_aclk_in)
-- begin
-- if (rising_edge(m_axis_aclk_in)) then
-- if (m_axis_tready_in = '1') then
-- read_toggle_r <= not read_toggle_r;
-- end if;
-- end if;
-- end process;
sim_false3 : if (SIM_ENABLED = FALSE) generate
i_ila_2 : entity work.ila_0
port map (
clk => m_axis_aclk_in,
probe0 => m_axis_tdata(15 downto 0), -- 16
probe1 => m_axis_tdata(31 downto 16), -- 16
probe2 => m_axis_tdata(47 downto 32), -- 16
probe3 => m_axis_tdata(63 downto 48), -- 16
-- probe4 => m_axis_tdata(79 downto 64), -- 16
-- probe5 => m_axis_tdata(95 downto 80), -- 16
-- probe6 => m_axis_tdata(111 downto 96), -- 16
-- probe7 => m_axis_tdata(127 downto 112), -- 16
probe4(0) => m_axis_tvalid, -- 1
probe5(0) => m_axis_tready_in -- 1
);
end generate sim_false3;
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 100
)
port map (
clk_in => s_axi_aclk_in,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000",
prog_us_tick_out => open,
reset_in => reset_in
);
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
m_axis_aclk_cnt_r <= (others => '0');
else
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
end if;
end if;
end process;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
s_axi_aclk_cnt_r <= (others => '0');
else
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
end if;
end if;
end process;
sim_true : if (SIM_ENABLED = TRUE) generate
-- Stimulus process
stim_proc: process
begin
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
wait until rising_edge(s_axi_aclk_in);
wait for 1 ns;
vio_mode <= '0';
vio_scale <= x"8000";
vio_cmd_idx <= "000";
vio_cmd_send <= '0';
vio_dac_holdoff <= '1';
vio_reserv1 <= x"00000000"; --RESERVED1
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
vio_phase_off <= x"00000000"; --PHASE_OFF
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
vio_enable <= '1';
vio_cnt_rst <= '0';
wait for ok_clk_in_period*10;
wait until rising_edge(s_axi_aclk_in);
wait for 200 ns;
wait for 200 ns;
wait for 200 ns;
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "000";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 3
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "011";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
--
-- -- WFM 1
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "001";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
-- -- WFM 0
-- -- FREQUENCY SWEEP (UP-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "000";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
-- -- WFM 1
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "001";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
--
-- -- WFM 2
-- -- CW TONE
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "010";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
wait for ok_clk_in_period*10;
wait until rising_edge(s_axi_aclk_in);
vio_dac_holdoff <= '0';
-- -- WFM 3
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "011";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
-- wait for 100 ns;
-- CW TONE
-- vio_reserv1 <= x"00000000"; --RESERVED1
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
-- vio_phase_off <= x"00000000"; --PHASE_OFF
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "100";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
wait for 5 us;
wait;
end process;
end generate sim_true;
end architecture imp;
ip_repo/dds_pulse_intfc_1_0/src/ila_0/ila_0.xci
+6306
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ip_repo/dds_pulse_intfc_1_0/src/ila_2/ila_2.xci
+6306
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ip_repo/dds_pulse_intfc_1_0/src/ila_3/ila_3.xci
+6304
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ip_repo/dds_pulse_intfc_1_0/src/ila_4/ila_4.xci
+6304
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ip_repo/dds_pulse_intfc_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci
+169
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@@ -0,0 +1,169 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
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ip_repo/dds_pulse_intfc_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci
+468
View File
@@ -0,0 +1,468 @@
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},
"project_parameters": {
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"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
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"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
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}
},
"boundary": {
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"srst": [ { "direction": "in", "driver_value": "0" } ],
"din": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"full": [ { "direction": "out", "driver_value": "0x0" } ],
"overflow": [ { "direction": "out", "driver_value": "0x0" } ],
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
"underflow": [ { "direction": "out", "driver_value": "0x0" } ],
"prog_full": [ { "direction": "out", "driver_value": "0x0" } ],
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"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
},
"interfaces": {
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"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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},
"port_maps": {
"CLK": [ { "physical_name": "clk" } ]
}
},
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"vlnv": "xilinx.com:interface:fifo_write:1.0",
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
"mode": "slave",
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"WR_DATA": [ { "physical_name": "din" } ],
"WR_EN": [ { "physical_name": "wr_en" } ]
}
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"FIFO_READ": {
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"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
"mode": "slave",
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"RD_DATA": [ { "physical_name": "dout" } ],
"RD_EN": [ { "physical_name": "rd_en" } ]
}
}
}
}
}
}
ip_repo/dds_pulse_intfc_1_0/src/tick_gen.vhd
+121
View File
@@ -0,0 +1,121 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tick_gen is
generic(
CLOCK_SPEED_MHZ : integer := 100
);
port(
clk_in : in std_logic;
tick_1us_out : out std_logic;
tick_1ms_out : out std_logic;
tick_500ms_out : out std_logic;
tick_750ms_out : out std_logic;
tick_1s_out : out std_logic;
prog_us_tick_rate_in : in std_logic_vector(15 downto 0);
prog_us_tick_out : out std_logic;
reset_in : in std_logic
);
end entity tick_gen;
architecture imp of tick_gen is
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
signal usec_cnt_r : integer range 0 to 999;
signal msec_cnt_r : integer range 0 to 499;
signal msec_cnt1_r : integer range 0 to 999;
signal tick_1us_r : std_logic;
signal tick_1ms_r : std_logic;
signal tick_500ms_r : std_logic;
signal tick_750ms_r : std_logic;
signal tick_1s_r : std_logic;
signal prog_usec_cnt_r : std_logic_vector(15 downto 0);
signal prog_us_tick_r : std_logic;
begin
tick_1us_out <= tick_1us_r;
tick_1ms_out <= tick_1ms_r;
tick_500ms_out <= tick_500ms_r;
tick_750ms_out <= tick_750ms_r;
tick_1s_out <= tick_1s_r;
prog_us_tick_out <= prog_us_tick_r;
process(clk_in, reset_in)
begin
if(reset_in = '1') then
sysclk_cnt_r <= 0;
usec_cnt_r <= 0;
msec_cnt_r <= 0;
msec_cnt1_r <= 0;
tick_1us_r <= '1';
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '0';
elsif rising_edge(clk_in) then
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_us_tick_r <= '0';
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
sysclk_cnt_r <= 0;
tick_1us_r <= '1';
else
sysclk_cnt_r <= sysclk_cnt_r + 1;
tick_1us_r <= '0';
end if;
if(tick_1us_r = '1') then
if(usec_cnt_r = 999) then -- 1000us
usec_cnt_r <= 0;
tick_1ms_r <= '1';
else
usec_cnt_r <= usec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt_r = 499) then -- 500ms
msec_cnt_r <= 0;
tick_500ms_r <= '1';
else
msec_cnt_r <= msec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt1_r = 749) then -- 750ms
tick_750ms_r <= '1';
end if;
if(msec_cnt1_r = 999) then -- 1s
msec_cnt1_r <= 0;
tick_1s_r <= '1';
else
msec_cnt1_r <= msec_cnt1_r + 1;
end if;
end if;
if(tick_1us_r = '1') then
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '1';
else
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
end if;
end if;
end if;
end process;
end architecture imp;
ip_repo/dds_pulse_intfc_1_0/src/vio_0/vio_0.xci
+1651
View File
File diff suppressed because it is too large Load Diff
ip_repo/dds_pulse_intfc_1_0/xgui/dds_pulse_intfc_v1_0.tcl
+90
View File
@@ -0,0 +1,90 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
ipgui::add_param $IPINST -name "MINOR_REV"
}
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to validate FPGA_REVISION_DATE
return true
}
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to validate MINOR_REV
return true
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
}
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
}
ip_repo/pdw_generator_1_0/bd/bd.tcl
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}
ip_repo/pdw_generator_1_0/component.xml
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ip_repo/pdw_generator_1_0/hdl/pdw_generator_v1_0.vhd
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ip_repo/pdw_generator_1_0/hdl/pdw_generator_v1_0_S00_AXI.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdw_generator_v1_0_S00_AXI is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
cmd_idx_out : out std_logic_vector( 2 downto 0);
cmd_send_out : out std_logic;
mode_out : out std_logic;
scale_out : out std_logic_vector(15 downto 0);
dac_holdoff_out : out std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
latch_en_out : out std_logic;
loop_mode_en_out : out std_logic_vector( 7 downto 0);
trigger_mode_out : out std_logic_vector( 1 downto 0);
prog_us_tick_out : out std_logic_vector(31 downto 0);
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
dds_done_in : in std_logic;
fpga_reboot_out : out std_logic;
dac_data_src_sel_out : out std_logic;
d_frmt_out : out std_logic_vector(1 downto 0);
slv_reg19_in : in std_logic_vector(31 downto 0);
slv_reg20_in : in std_logic_vector(31 downto 0);
slv_reg21_in : in std_logic_vector(31 downto 0);
slv_reg22_in : in std_logic_vector(31 downto 0);
dds_reset_out : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end pdw_generator_v1_0_S00_AXI;
architecture arch_imp of pdw_generator_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 24
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
signal dds_reset_r : std_logic_vector(0 to 15) := (others => '0');
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
else
slv_reg0(0) <= '0'; -- self clear bit 0
slv_reg4(16) <= '0'; -- self clear bit 16
slv_reg3(31) <= '0'; -- self clear bit 31
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
when b"00101" =>
reg_data_out <= reserv1_in; -- slv_reg5;
when b"00110" =>
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
when b"00111" =>
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
when b"01000" =>
reg_data_out <= idle_samples_in; -- slv_reg8;
when b"01001" =>
reg_data_out <= dds_samples_in; -- slv_reg9;
when b"01010" =>
reg_data_out <= phase_inc_in; -- slv_reg10;
when b"01011" =>
reg_data_out <= phase_off_in; -- slv_reg11;
when b"01100" =>
reg_data_out <= swap_sf_in; -- slv_reg12;
when b"01101" =>
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
when b"01110" =>
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
when b"01111" =>
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
when b"10000" =>
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
when b"10001" =>
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19_in;
when b"10100" =>
reg_data_out <= slv_reg20_in;
when b"10101" =>
reg_data_out <= slv_reg21_in;
when b"10110" =>
reg_data_out <= slv_reg22_in;
when b"10111" =>
reg_data_out <= slv_reg23;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (slv_reg0(0) = '1') then -- self clear bit 0
cmd_send_r <= "111";
else
cmd_send_r <= cmd_send_r(1 to 2) & '0';
end if;
if (slv_reg3(31) = '1') then -- self clear bit 0
dds_reset_r <= (others => '1');
else
dds_reset_r <= dds_reset_r(1 to 15) & '0';
end if;
end if;
end process;
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
-- <= slv_reg0(30 downto 1);
fpga_reboot_out <= slv_reg0(31);
dac_holdoff_out <= slv_reg1(0);
-- <= slv_reg1( 3 downto 1);
cmd_idx_out <= slv_reg1( 6 downto 4);
-- <= slv_reg1( 7);
loop_mode_en_out <= slv_reg1(15 downto 8);
d_frmt_out <= slv_reg1(17 downto 16);
-- <= slv_reg1(31 downto 18);
prog_us_tick_out <= slv_reg2;
scale_out <= slv_reg3(15 downto 0);
trigger_mode_out <= slv_reg3(17 downto 16);
-- <= slv_reg3(30 downto 18);
dds_reset_out <= dds_reset_r(0); -- self clear bit 0
mode_out <= slv_reg4(0);
-- <= slv_reg4(15 downto 1);
latch_en_out <= slv_reg4(16); -- self clear bit 0
-- <= slv_reg4(30 downto 17);
dac_data_src_sel_out <= slv_reg4(31);
reserv1_out <= slv_reg5;
dds_phase_inc_dwell_time_out <= slv_reg6;
dds_phase_inc_step_size_out <= slv_reg7;
idle_samples_out <= slv_reg8;
dds_samples_out <= slv_reg9;
phase_inc_out <= slv_reg10;
phase_off_out <= slv_reg11;
swap_sf_out <= slv_reg12;
duration_ms_cnt_out <= slv_reg18;
-- User logic ends
end arch_imp;
ip_repo/pdw_generator_1_0/hdl/pdw_generator_v1_0_S01_AXI.vhd
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@@ -0,0 +1,740 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdw_generator_v1_0_S01_AXI is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
cmd_idx_out : out std_logic_vector( 2 downto 0);
cmd_send_out : out std_logic;
mode_out : out std_logic;
scale_out : out std_logic_vector(15 downto 0);
dac_holdoff_out : out std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
latch_en_out : out std_logic;
loop_mode_en_out : out std_logic_vector( 7 downto 0);
trigger_mode_out : out std_logic_vector( 1 downto 0);
prog_us_tick_out : out std_logic_vector(31 downto 0);
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
dds_done_in : in std_logic;
slv_reg19_in : in std_logic_vector(31 downto 0);
slv_reg20_in : in std_logic_vector(31 downto 0);
slv_reg21_in : in std_logic_vector(31 downto 0);
slv_reg22_in : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end pdw_generator_v1_0_S01_AXI;
architecture arch_imp of pdw_generator_v1_0_S01_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 24
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
else
slv_reg0(0) <= '0'; -- self clear bit 0
slv_reg4(16) <= '0'; -- self clear bit 16
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
when b"00101" =>
reg_data_out <= reserv1_in; -- slv_reg5;
when b"00110" =>
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
when b"00111" =>
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
when b"01000" =>
reg_data_out <= idle_samples_in; -- slv_reg8;
when b"01001" =>
reg_data_out <= dds_samples_in; -- slv_reg9;
when b"01010" =>
reg_data_out <= phase_inc_in; -- slv_reg10;
when b"01011" =>
reg_data_out <= phase_off_in; -- slv_reg11;
when b"01100" =>
reg_data_out <= swap_sf_in; -- slv_reg12;
when b"01101" =>
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
when b"01110" =>
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
when b"01111" =>
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
when b"10000" =>
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
when b"10001" =>
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19_in;
when b"10100" =>
reg_data_out <= slv_reg20_in;
when b"10101" =>
reg_data_out <= slv_reg21_in;
when b"10110" =>
reg_data_out <= slv_reg22_in;
when b"10111" =>
reg_data_out <= slv_reg23;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (slv_reg0(0) = '1') then -- self clear bit 0
cmd_send_r <= "111";
else
cmd_send_r <= cmd_send_r(1 to 2) & '0';
end if;
end if;
end process;
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
-- <= slv_reg0(30 downto 1);
-- <= slv_reg0(31);
dac_holdoff_out <= slv_reg1(0);
-- <= slv_reg1( 3 downto 1);
cmd_idx_out <= slv_reg1( 6 downto 4);
-- <= slv_reg1( 7);
loop_mode_en_out <= slv_reg1(15 downto 8);
-- <= slv_reg1(31 downto 16);
prog_us_tick_out <= slv_reg2;
scale_out <= slv_reg3(15 downto 0);
trigger_mode_out <= slv_reg3(17 downto 16);
-- <= slv_reg3(31 downto 18);
mode_out <= slv_reg4(0);
-- <= slv_reg4(15 downto 1);
latch_en_out <= slv_reg4(16); -- self clear bit 0
-- <= slv_reg1(30 downto 17);
-- <= slv_reg4(31);
reserv1_out <= slv_reg5;
dds_phase_inc_dwell_time_out <= slv_reg6;
dds_phase_inc_step_size_out <= slv_reg7;
idle_samples_out <= slv_reg8;
dds_samples_out <= slv_reg9;
phase_inc_out <= slv_reg10;
phase_off_out <= slv_reg11;
swap_sf_out <= slv_reg12;
duration_ms_cnt_out <= slv_reg18;
-- User logic ends
end arch_imp;
ip_repo/pdw_generator_1_0/hdl/pdw_generator_v1_0_S02_AXI.vhd
+740
View File
@@ -0,0 +1,740 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdw_generator_v1_0_S02_AXI is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
cmd_idx_out : out std_logic_vector( 2 downto 0);
cmd_send_out : out std_logic;
mode_out : out std_logic;
scale_out : out std_logic_vector(15 downto 0);
dac_holdoff_out : out std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
latch_en_out : out std_logic;
loop_mode_en_out : out std_logic_vector( 7 downto 0);
trigger_mode_out : out std_logic_vector( 1 downto 0);
prog_us_tick_out : out std_logic_vector(31 downto 0);
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
dds_done_in : in std_logic;
slv_reg19_in : in std_logic_vector(31 downto 0);
slv_reg20_in : in std_logic_vector(31 downto 0);
slv_reg21_in : in std_logic_vector(31 downto 0);
slv_reg22_in : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end pdw_generator_v1_0_S02_AXI;
architecture arch_imp of pdw_generator_v1_0_S02_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 24
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
else
slv_reg0(0) <= '0'; -- self clear bit 0
slv_reg4(16) <= '0'; -- self clear bit 16
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
when b"00101" =>
reg_data_out <= reserv1_in; -- slv_reg5;
when b"00110" =>
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
when b"00111" =>
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
when b"01000" =>
reg_data_out <= idle_samples_in; -- slv_reg8;
when b"01001" =>
reg_data_out <= dds_samples_in; -- slv_reg9;
when b"01010" =>
reg_data_out <= phase_inc_in; -- slv_reg10;
when b"01011" =>
reg_data_out <= phase_off_in; -- slv_reg11;
when b"01100" =>
reg_data_out <= swap_sf_in; -- slv_reg12;
when b"01101" =>
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
when b"01110" =>
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
when b"01111" =>
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
when b"10000" =>
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
when b"10001" =>
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19_in;
when b"10100" =>
reg_data_out <= slv_reg20_in;
when b"10101" =>
reg_data_out <= slv_reg21_in;
when b"10110" =>
reg_data_out <= slv_reg22_in;
when b"10111" =>
reg_data_out <= slv_reg23;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (slv_reg0(0) = '1') then -- self clear bit 0
cmd_send_r <= "111";
else
cmd_send_r <= cmd_send_r(1 to 2) & '0';
end if;
end if;
end process;
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
-- <= slv_reg0(30 downto 1);
-- <= slv_reg0(31);
dac_holdoff_out <= slv_reg1(0);
-- <= slv_reg1( 3 downto 1);
cmd_idx_out <= slv_reg1( 6 downto 4);
-- <= slv_reg1( 7);
loop_mode_en_out <= slv_reg1(15 downto 8);
-- <= slv_reg1(31 downto 16);
prog_us_tick_out <= slv_reg2;
scale_out <= slv_reg3(15 downto 0);
trigger_mode_out <= slv_reg3(17 downto 16);
-- <= slv_reg3(31 downto 18);
mode_out <= slv_reg4(0);
-- <= slv_reg4(15 downto 1);
latch_en_out <= slv_reg4(16); -- self clear bit 0
-- <= slv_reg1(30 downto 17);
-- <= slv_reg4(31);
reserv1_out <= slv_reg5;
dds_phase_inc_dwell_time_out <= slv_reg6;
dds_phase_inc_step_size_out <= slv_reg7;
idle_samples_out <= slv_reg8;
dds_samples_out <= slv_reg9;
phase_inc_out <= slv_reg10;
phase_off_out <= slv_reg11;
swap_sf_out <= slv_reg12;
duration_ms_cnt_out <= slv_reg18;
-- User logic ends
end arch_imp;
ip_repo/pdw_generator_1_0/hdl/pdw_generator_v1_0_S03_AXI.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdw_generator_v1_0_S03_AXI is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"1024_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
cmd_idx_out : out std_logic_vector( 2 downto 0);
cmd_send_out : out std_logic;
mode_out : out std_logic;
scale_out : out std_logic_vector(15 downto 0);
dac_holdoff_out : out std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
latch_en_out : out std_logic;
loop_mode_en_out : out std_logic_vector( 7 downto 0);
trigger_mode_out : out std_logic_vector( 1 downto 0);
prog_us_tick_out : out std_logic_vector(31 downto 0);
duration_ms_cnt_out : out std_logic_vector(31 downto 0);
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
cmd_send_cnt_in : in std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_in : in std_logic_vector(31 downto 0);
m_axis_tvalid_cnt_in : in std_logic_vector(31 downto 0);
dds_pulse_data_cnt_in : in std_logic_vector(31 downto 0);
dds_done_in : in std_logic;
slv_reg19_in : in std_logic_vector(31 downto 0);
slv_reg20_in : in std_logic_vector(31 downto 0);
slv_reg21_in : in std_logic_vector(31 downto 0);
slv_reg22_in : in std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end pdw_generator_v1_0_S03_AXI;
architecture arch_imp of pdw_generator_v1_0_S03_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 24
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal aw_en : std_logic;
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
aw_en <= '0';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
else
slv_reg0(0) <= '0'; -- self clear bit 0
slv_reg4(16) <= '0'; -- self clear bit 16
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= MINOR_REV & slv_reg1(23 downto 0);
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= dds_done_in & slv_reg4(30 downto 0);
when b"00101" =>
reg_data_out <= reserv1_in; -- slv_reg5;
when b"00110" =>
reg_data_out <= dds_phase_inc_dwell_time_in; -- slv_reg6;
when b"00111" =>
reg_data_out <= dds_phase_inc_step_size_in; -- slv_reg7;
when b"01000" =>
reg_data_out <= idle_samples_in; -- slv_reg8;
when b"01001" =>
reg_data_out <= dds_samples_in; -- slv_reg9;
when b"01010" =>
reg_data_out <= phase_inc_in; -- slv_reg10;
when b"01011" =>
reg_data_out <= phase_off_in; -- slv_reg11;
when b"01100" =>
reg_data_out <= swap_sf_in; -- slv_reg12;
when b"01101" =>
reg_data_out <= pipe_in_ch1_fifo_rden_cnt_in; --slv_reg13;
when b"01110" =>
reg_data_out <= m_axis_tvalid_cnt_in; -- slv_reg14;
when b"01111" =>
reg_data_out <= FPGA_REVISION_DATE; -- slv_reg15;
when b"10000" =>
reg_data_out <= cmd_send_cnt_in; --slv_reg16;
when b"10001" =>
reg_data_out <= dds_pulse_data_cnt_in; -- slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19_in;
when b"10100" =>
reg_data_out <= slv_reg20_in;
when b"10101" =>
reg_data_out <= slv_reg21_in;
when b"10110" =>
reg_data_out <= slv_reg22_in;
when b"10111" =>
reg_data_out <= slv_reg23;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (slv_reg0(0) = '1') then -- self clear bit 0
cmd_send_r <= "111";
else
cmd_send_r <= cmd_send_r(1 to 2) & '0';
end if;
end if;
end process;
cmd_send_out <= cmd_send_r(0); -- self clear bit 0
-- <= slv_reg0(30 downto 1);
-- <= slv_reg0(31);
dac_holdoff_out <= slv_reg1(0);
-- <= slv_reg1( 3 downto 1);
cmd_idx_out <= slv_reg1( 6 downto 4);
-- <= slv_reg1( 7);
loop_mode_en_out <= slv_reg1(15 downto 8);
-- <= slv_reg1(31 downto 16);
prog_us_tick_out <= slv_reg2;
scale_out <= slv_reg3(15 downto 0);
trigger_mode_out <= slv_reg3(17 downto 16);
-- <= slv_reg3(31 downto 18);
mode_out <= slv_reg4(0);
-- <= slv_reg4(15 downto 1);
latch_en_out <= slv_reg4(16); -- self clear bit 0
-- <= slv_reg1(30 downto 17);
-- <= slv_reg4(31);
reserv1_out <= slv_reg5;
dds_phase_inc_dwell_time_out <= slv_reg6;
dds_phase_inc_step_size_out <= slv_reg7;
idle_samples_out <= slv_reg8;
dds_samples_out <= slv_reg9;
phase_inc_out <= slv_reg10;
phase_off_out <= slv_reg11;
swap_sf_out <= slv_reg12;
duration_ms_cnt_out <= slv_reg18;
-- User logic ends
end arch_imp;
ip_repo/pdw_generator_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci
+228
View File
@@ -0,0 +1,228 @@
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ip_repo/pdw_generator_1_0/src/addsub/addsub.xci
+216
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ip_repo/pdw_generator_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci
+486
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@@ -0,0 +1,486 @@
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ip_repo/pdw_generator_1_0/src/axis_data_fifo_32x32/axis_data_fifo_32x32.xci
+176
View File
@@ -0,0 +1,176 @@
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ip_repo/pdw_generator_1_0/src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci
+176
View File
@@ -0,0 +1,176 @@
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"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "axis_data_fifo_512x128", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "32768", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu9eg" } ],
"PACKAGE": [ { "value": "ffvb1156" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "9" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/axis_data_fifo_512x128" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}
ip_repo/pdw_generator_1_0/src/dds_cmd_gen.vhd
+286
View File
@@ -0,0 +1,286 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dds_cmd_gen is
generic (
SIM_ENABLED : boolean := FALSE
);
port(
clk_in : in std_logic;
cmd_idx_in : in std_logic_vector( 2 downto 0);
cmd_send_in : in std_logic;
busy_out : out std_logic;
latch_en_in : in std_logic;
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
fifo_rd_clk_in : in std_logic;
fifo_rd_data_out : out std_logic_vector(31 downto 0);
fifo_rd_dval_out : out std_logic;
fifo_rd_rd_en_in : in std_logic;
fifo_rd_empty_out : out std_logic;
rst_in : in std_logic
);
end entity dds_cmd_gen;
architecture imp of dds_cmd_gen is
signal latch_en_r : std_logic := '0';
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_wr_en_r : std_logic := '0';
signal cmd_idx_r : integer range 0 to 7 := 0;
signal cmd_send_r : std_logic := '0';
type fsm_state is (IDLE, SEND, DONE);
signal state_r : fsm_state := IDLE;
signal state_cnt_r : integer := 0;
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
type dds_command_list is array (integer range <>) of array_32b_type;
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
--
-- Phase Inc Start = 2^32 * (1/250) = 17179869
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
--
signal dds_command_set : dds_command_list(0 to 7) :=
(
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
0 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 1
-- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
1 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"FFFEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 2
-- CW TONE
2 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 3
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
3 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
x"000000FF", --IDLE_SAMPLES
x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 4
-- ??????
4 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 5
-- ??????
5 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 6
-- ??????
6 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
),
-- WFM 7
-- ??????
7 => (x"00000000", --RESERVED1
x"00000000", --DDS_PHASE_INC_DWELL_TIME
x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
x"00000000", --IDLE_SAMPLES
x"000004E2", --DDS_SAMPLES (~5 us)
x"0624DD2F", --PHASE_INC (~6 MHz)
x"00000000", --PHASE_OFF
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0, ==> bit 16 is iq_swap
)
);
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
signal busy_r : std_logic := '0';
begin
process(clk_in)
begin
if (rising_edge(clk_in)) then
latch_en_r <= latch_en_in;
if (latch_en_in = '1' and latch_en_r = '0') then
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(0) <= reserv1_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(1) <= dds_phase_inc_dwell_time_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(2) <= dds_phase_inc_step_size_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(3) <= idle_samples_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(4) <= dds_samples_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(5) <= phase_inc_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(6) <= phase_off_in;
dds_command_set(conv_integer(unsigned(cmd_idx_in)))(7) <= swap_sf_in;
end if;
end if;
end process;
reserv1_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(0);
dds_phase_inc_dwell_time_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(1);
dds_phase_inc_step_size_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(2);
idle_samples_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(3);
dds_samples_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(4);
phase_inc_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(5);
phase_off_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(6);
swap_sf_out <= dds_command_set(conv_integer(unsigned(cmd_idx_in)))(7);
busy_out <= busy_r;
process(clk_in)
begin
if (rising_edge(clk_in)) then
-- if (rst_in = '1') then
-- cmd_idx_r <= 0;
-- cmd_send_r <= '0';
-- fifo_wr_en_r <= '0';
-- state_cnt_r <= 0;
-- state_r <= IDLE;
-- else
cmd_send_r <= cmd_send_in;
fifo_wr_en_r <= '0';
case (state_r) is
when IDLE =>
if (cmd_send_in = '1' and cmd_send_r = '0') then
cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
state_cnt_r <= 0;
busy_r <= '1';
state_r <= SEND;
else
state_r <= IDLE;
end if;
when SEND =>
if (state_cnt_r = 8) then
state_r <= DONE;
else
fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
fifo_wr_en_r <= '1';
state_cnt_r <= state_cnt_r + 1;
state_r <= SEND;
end if;
when DONE =>
busy_r <= '0';
state_r <= IDLE;
when others =>
state_r <= IDLE;
end case;
-- end if;
end if;
end process;
test_state_r <= "00" when state_r = IDLE else
"01" when state_r = SEND else
"10" when state_r = DONE else
"11";
-- sim_false_ila_2 : if (SIM_ENABLED = FALSE) generate
-- i_ila_2 : entity work.ila_2
-- port map (
-- clk => clk_in,
-- probe0 => test_state_r, -- 2
-- probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
-- probe2 => fifo_wr_data_r, -- 32
-- probe3(0) => fifo_wr_en_r, -- 1
-- probe4(0) => cmd_send_in, -- 1
-- probe5(0) => cmd_send_r -- 1
-- );
-- end generate sim_false_ila_2;
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
port map(
wr_clk => clk_in,
din => fifo_wr_data_r,
wr_en => fifo_wr_en_r,
full => open,
overflow => open,
rd_clk => fifo_rd_clk_in,
dout => fifo_rd_data_out,
valid => fifo_rd_dval_out,
rd_en => fifo_rd_rd_en_in,
empty => fifo_rd_empty_out,
underflow => open,
prog_full => open,
wr_rst_busy => open,
rd_rst_busy => open,
srst => rst_in
);
end architecture imp;
ip_repo/pdw_generator_1_0/src/dds_latency10/dds_latency10.xci
+366
View File
@@ -0,0 +1,366 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "dds_latency10",
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds",
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
"ip_revision": "22",
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/dds_latency10",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"DDS_Clock_Rate": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles13": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF13": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles14": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF14": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles15": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF15": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Output_Frequency16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PINC16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"Phase_Offset_Angles16": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"POFF16": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"POR_mode": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"GUI_Behaviour": [ { "value": "Coregen", "resolve_type": "user", "usage": "all" } ],
"explicit_period": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"period": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ]
},
"model_parameters": {
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_MODE_OF_OPERATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MODULUS": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACCUMULATOR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_PHASE_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_PHASEGEN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SINCOS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LATENCY": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MEM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NEGATIVE_COSINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NEGATIVE_SINE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NOISE_SHAPING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUTS_REQUIRED": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_FORM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUTPUT_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_ANGLE_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_INCREMENT": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_INCREMENT_VALUE": [ { "value": "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
"C_RESYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_OFFSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PHASE_OFFSET_VALUE": [ { "value": "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", "resolve_type": "generated", "usage": "all" } ],
"C_OPTIMISE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_DSP48": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_POR_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AMPLITUDE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ACLKEN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_PHASE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_S_CONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_M_DATA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_M_PHASE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_PHASE_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CHAN_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu9eg" } ],
"PACKAGE": [ { "value": "ffvb1156" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "22" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/dds_latency10" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"aclken": [ { "direction": "in", "driver_value": "0x1" } ],
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_phase_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_phase_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
"m_axis_data_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"event_pinc_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_poff_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_phase_in_invalid_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_phase_chanid_incorrect_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_missing_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"event_s_config_tlast_unexpected_intf": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
}
},
"S_AXIS_PHASE": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
}
},
"aclk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"aresetn_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclken_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
},
"port_maps": {
"CE": [ { "physical_name": "aclken" } ]
}
},
"M_AXIS_DATA": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
}
}
}
}
}
}
ip_repo/pdw_generator_1_0/src/dds_pulse_2x_top.vhd
+432
View File
@@ -0,0 +1,432 @@
-------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M. Blevins
--
-- Create Date: 19:38:12 11/10/2016
-- Design Name:
-- Module Name: dds_pulse_2x_top - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- * All information is proprietary/confidential *
--
-- Supports single channel mode or dual channel (summed) mode.
-- When using dual channel mode, the module hangs after the shortest of the
-- two pulse streams completes. Ideally, both streams will be equal length.
--
-- For each channel:
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
-- The control word contains all information needed to create a pulse
--
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library UNIMACRO;
--use UNIMACRO.vcomponents.all;
USE IEEE.NUMERIC_STD.ALL;
entity dds_pulse_2x_top is
port(
clk_in : in std_logic;
rst_in : in std_logic;
mode_in : in std_logic; -- 0=single, 1=dual
scale_in : in std_logic_vector(15 downto 0);
fifo1_data_in : in std_logic_vector(31 downto 0);
fifo1_dval_in : in std_logic;
fifo1_empty_in : in std_logic;
fifo1_rden_out : out std_logic;
fifo2_data_in : in std_logic_vector(31 downto 0);
fifo2_dval_in : in std_logic;
fifo2_empty_in : in std_logic;
fifo2_rden_out : out std_logic;
holdoff_in : in std_logic;
overflow_out : out std_logic_vector(1 downto 0);
underflow_out : out std_logic_vector(1 downto 0);
i_max_abs_out : out std_logic_vector(15 downto 0);
q_max_abs_out : out std_logic_vector(15 downto 0);
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic;
done_out : out std_logic
);
end entity;
architecture mixed of dds_pulse_2x_top is
component mult_16signed_x_16unsigned_latency3
port(
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
ce : in std_logic;
sclr : in std_logic;
p : out std_logic_vector(15 downto 0)
);
end component;
component dds_pulse_gen is
port(
clk_in : in std_logic;
rst_in : in std_logic;
fifo_data_in : in std_logic_vector(31 downto 0);
fifo_dval_in : in std_logic;
fifo_empty_in : in std_logic;
fifo_rden_out : out std_logic;
holdoff_in : in std_logic;
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic
);
end component;
component sfifo_32b_1024_pf992_latency1
port(
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
overflow : out std_logic;
empty : out std_logic;
underflow : out std_logic;
prog_full : out std_logic
);
end component;
component adder_16signed_16signed_latency2
port(
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
clk : in std_logic;
ce : in std_logic;
bypass : in std_logic;
s : out std_logic_vector(16 downto 0)
);
end component;
signal rst_r : std_logic := '1';
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
signal pulse_adder_dval_r : std_logic := '0';
signal pulse_adder_ce : std_logic;
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
signal pulse_dval_r : std_logic := '0';
signal adder_dval_r : std_logic := '0';
signal holdoff_r : std_logic;
signal done_r : std_logic_vector(0 to 7) := (others => '0');
signal pulse1_mult_dval_r : std_logic := '0';
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal pulse1_mult_ce : std_logic;
signal pulse1_data : std_logic_vector(31 downto 0);
signal pulse1_dval : std_logic;
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
signal pulse1_fifo_overflow : std_logic;
signal pulse1_fifo_empty : std_logic;
signal pulse1_fifo_underflow : std_logic;
signal pulse1_fifo_progfull : std_logic;
signal pulse1_fifo_rden : std_logic;
signal pulse1_fifo_rden_r : std_logic := '0';
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
signal adder1_s : std_logic_vector(16 downto 0);
signal adder1_s_r : std_logic_vector(16 downto 0);
signal adder1_s_r1 : std_logic_vector(15 downto 0);
signal i_abs_max_r : unsigned(15 downto 0);
signal fifo1_underflow_r : std_logic := '0';
signal fifo1_overflow_r : std_logic := '0';
signal pulse2_mult_dval_r : std_logic := '0';
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal pulse2_mult_ce : std_logic;
signal pulse2_data : std_logic_vector(31 downto 0);
signal pulse2_dval : std_logic;
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
signal pulse2_fifo_overflow : std_logic;
signal pulse2_fifo_empty : std_logic;
signal pulse2_fifo_underflow : std_logic;
signal pulse2_fifo_progfull : std_logic;
signal pulse2_fifo_rden : std_logic;
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
signal adder2_s : std_logic_vector(16 downto 0);
signal adder2_s_r : std_logic_vector(16 downto 0);
signal adder2_s_r1 : std_logic_vector(15 downto 0);
signal q_abs_max_r : unsigned(15 downto 0);
signal fifo2_underflow_r : std_logic := '0';
signal fifo2_overflow_r : std_logic := '0';
signal pulse1_fifo_empty_r : std_logic := '0';
begin
data_out <= pulse_data_r;
dval_out <= pulse_dval_r;
i_max_abs_out <= std_logic_vector(i_abs_max_r);
q_max_abs_out <= std_logic_vector(q_abs_max_r);
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
done_out <= done_r(0);
process(clk_in)
begin
if(rising_edge(clk_in))then
rst_r <= rst_in;
scale_r <= scale_in;
mode_n_r <= not(mode_in);
-- holdoff_r <= holdoff_in;
pulse1_fifo_empty_r <= pulse1_fifo_empty;
done_r <= done_r(1 to 7) &'0';
if (holdoff_in = '0' and pulse1_fifo_empty = '0') then
holdoff_r <= '0';
elsif(pulse1_fifo_empty_r = '0' and pulse1_fifo_empty = '1') then -- rising_edge of pulse1_fifo_empty
holdoff_r <= '1';
done_r <= (others => '1');
end if;
end if;
end process;
process(clk_in)
begin
if(rising_edge(clk_in))then
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
pulse1_fifo_rden_r <= pulse1_fifo_rden;
pulse1_fifo_dout_r <= pulse1_fifo_dout;
pulse2_fifo_dout_r <= pulse2_fifo_dout;
end if;
end process;
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
not(pulse1_fifo_empty) and not(holdoff_r);
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
'0';
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
i_dds_pulse1_gen : dds_pulse_gen
port map(
clk_in => clk_in,
rst_in => rst_r,
fifo_data_in => fifo1_data_in,
fifo_dval_in => fifo1_dval_in,
fifo_empty_in => fifo1_empty_in,
fifo_rden_out => fifo1_rden_out,
holdoff_in => pulse1_fifo_progfull,
data_out => pulse1_data,
dval_out => pulse1_dval
);
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse1_data(15 downto 0),
b => scale_r,
ce => pulse1_mult_ce,
sclr => '0',
p => pulse1_data_scaled(15 downto 0)
);
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse1_data(31 downto 16),
b => scale_r,
ce => pulse1_mult_ce,
sclr => '0',
p => pulse1_data_scaled(31 downto 16)
);
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
port map(
clk => clk_in,
srst => rst_r,
din => pulse1_data_scaled,
wr_en => pulse1_mult_dval_r,
rd_en => pulse1_fifo_rden,
dout => pulse1_fifo_dout,
full => open,
overflow => pulse1_fifo_overflow,
empty => pulse1_fifo_empty,
underflow => pulse1_fifo_underflow,
prog_full => pulse1_fifo_progfull
);
i_dds_pulse2_gen : dds_pulse_gen
port map(
clk_in => clk_in,
rst_in => rst_r,
fifo_data_in => fifo2_data_in,
fifo_dval_in => fifo2_dval_in,
fifo_empty_in => fifo2_empty_in,
fifo_rden_out => fifo2_rden_out,
holdoff_in => pulse2_fifo_progfull,
data_out => pulse2_data,
dval_out => pulse2_dval
);
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse2_data(15 downto 0),
b => scale_r,
ce => pulse2_mult_ce,
sclr => '0',
p => pulse2_data_scaled(15 downto 0)
);
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => pulse2_data(31 downto 16),
b => scale_r,
ce => pulse2_mult_ce,
sclr => '0',
p => pulse2_data_scaled(31 downto 16)
);
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
port map(
clk => clk_in,
srst => rst_r,
din => pulse2_data_scaled,
wr_en => pulse2_mult_dval_r,
rd_en => pulse2_fifo_rden,
dout => pulse2_fifo_dout,
full => open,
overflow => pulse2_fifo_overflow,
empty => pulse2_fifo_empty,
underflow => pulse2_fifo_underflow,
prog_full => pulse2_fifo_progfull
);
i_pulse_adder1 : adder_16signed_16signed_latency2
port map(
a => pulse2_fifo_dout_r(15 downto 0),
b => pulse1_fifo_dout_r(15 downto 0),
clk => clk_in,
ce => pulse_adder_ce,
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
s => adder1_s
);
i_pulse_adder2 : adder_16signed_16signed_latency2
port map(
a => pulse2_fifo_dout_r(31 downto 16),
b => pulse1_fifo_dout_r(31 downto 16),
clk => clk_in,
ce => pulse_adder_ce,
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
s => adder2_s
);
process(clk_in)
begin
if(rising_edge(clk_in))then
adder1_s_r <= adder1_s;
adder2_s_r <= adder2_s;
adder_dval_r <= pulse_adder_dval_r;
pulse_dval_r <= adder_dval_r;
if(adder_dval_r = '1')then
case adder1_s_r(16 downto 15) is
when "01" => --positive overflow
pulse_data_r(15 downto 0) <= x"7FFF";
when "10" => --negative overflow
pulse_data_r(15 downto 0) <= x"8000";
when others =>
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
end case;
case adder2_s_r(16 downto 15) is
when "01" => --positive overflow
pulse_data_r(31 downto 16) <= x"7FFF";
when "10" => --negative overflow
pulse_data_r(31 downto 16) <= x"8000";
when others =>
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
end case;
end if;
if(rst_r = '1')then
--adder_dval_r <= '0';
--pulse_dval_r <= '0';
i_abs_max_r <= (others => '0');
q_abs_max_r <= (others => '0');
fifo1_overflow_r <= '0';
fifo1_underflow_r <= '0';
fifo2_overflow_r <= '0';
fifo2_underflow_r <= '0';
else
--adder_dval_r <= pulse_adder_dval_r;
--pulse_dval_r <= adder_dval_r;
if(pulse1_fifo_overflow = '1')then
fifo1_overflow_r <= '1';
end if;
if(pulse1_fifo_underflow = '1')then
fifo1_underflow_r <= '1';
end if;
if(pulse2_fifo_overflow = '1')then
fifo2_overflow_r <= '1';
end if;
if(pulse2_fifo_underflow = '1')then
fifo2_underflow_r <= '1';
end if;
if(adder_dval_r = '1')then
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
-- i_abs_max_r <= abs(signed(adder1_s_r));
-- end if;
if(adder1_s_r(16) = '0')then
adder1_s_r1 <= adder1_s_r(15 downto 0);
else
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
end if;
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
-- q_abs_max_r <= abs(signed(adder2_s_r));
-- end if;
if(adder2_s_r(16) = '0')then
adder2_s_r1 <= adder2_s_r(15 downto 0);
else
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
end if;
end if;
if(pulse_dval_r = '1')then
if(unsigned(adder1_s_r1) > i_abs_max_r)then
i_abs_max_r <= unsigned(adder1_s_r1);
end if;
if(unsigned(adder2_s_r1) > q_abs_max_r)then
q_abs_max_r <= unsigned(adder2_s_r1);
end if;
end if;
end if;
end if;
end process;
end mixed;
ip_repo/pdw_generator_1_0/src/dds_pulse_gen.vhd
+415
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@@ -0,0 +1,415 @@
-------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M. Blevins
--
-- Create Date: 19:38:12 11/10/2016
-- Design Name:
-- Module Name: dds_pulse_gen - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
-- Additional Comments:
-- * All information is proprietary/confidential *
--
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
-- The control word contains all information needed to create a pulse
--
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library UNIMACRO;
--use UNIMACRO.vcomponents.all;
USE IEEE.NUMERIC_STD.ALL;
entity dds_pulse_gen is
port(
clk_in : in std_logic;
rst_in : in std_logic;
fifo_data_in : in std_logic_vector(31 downto 0);
fifo_dval_in : in std_logic;
fifo_empty_in : in std_logic;
fifo_rden_out : out std_logic;
holdoff_in : in std_logic;
data_out : out std_logic_vector(31 downto 0);
dval_out : out std_logic
);
end entity;
architecture mixed of dds_pulse_gen is
component mult_16signed_x_16unsigned_latency3
port(
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
ce : in std_logic;
sclr : in std_logic;
p : out std_logic_vector(15 downto 0)
);
end component;
component dds_latency10
port(
-- ce : in std_logic;
-- clk : in std_logic;
-- sclr : in std_logic;
-- pinc_in : in std_logic_vector(31 downto 0);
-- poff_in : in std_logic_vector(31 downto 0);
-- rdy : out std_logic;
-- cosine : out std_logic_vector(15 downto 0);
-- sine : out std_logic_vector(15 downto 0)
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
component addsub
port (
a : in std_logic_vector(31 downto 0); -- unsigned
b : in std_logic_vector(23 downto 0); -- signed
--clk : in std_logic;
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
);
end component;
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
signal state : state_type;
signal state_r : state_type;
signal rst_r : std_logic := '1';
signal rstn_r : std_logic := '0';
signal cnt1_r : unsigned(3 downto 0) := "0000";
signal cnt1 : unsigned(3 downto 0);
signal cnt2_r : unsigned(2 downto 0) := "000";
signal cnt2 : unsigned(2 downto 0);
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
signal cnt3 : unsigned(31 downto 0);
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
signal cnt4 : unsigned(31 downto 0);
signal cnt5_r : unsigned(3 downto 0) := "0000";
signal cnt5 : unsigned(3 downto 0);
signal fifo_data_ce : std_logic;
signal fifo_data_r : std_logic_vector(255 downto 0);
signal fifo_rden : std_logic;
--signal fifo_rden_r : std_logic := '0';
signal dval_r : std_logic := '0';
signal dval : std_logic;
signal dds_data : std_logic_vector(31 downto 0);
signal data : std_logic_vector(31 downto 0);
signal data_r : std_logic_vector(31 downto 0);
signal idle_sample_cnt_r : unsigned(31 downto 0);
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
signal dds_sample_cnt_r : unsigned(31 downto 0);
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
signal phase_inc_init_r : std_logic_vector(31 downto 0);
signal phase_offset_r : std_logic_vector(31 downto 0);
signal swap_r : std_logic := '0';
signal scale_r : std_logic_vector(15 downto 0);
signal mult_dval_r : std_logic := '0';
signal data_swap_scaled : std_logic_vector(31 downto 0);
signal data_scaled : std_logic_vector(31 downto 0);
signal dds_ce : std_logic;
signal dds_rst : std_logic;
signal dds_rdy : std_logic;
signal mult_ce : std_logic;
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
signal holdoff_r : std_logic;
--signal phase_inc_mux_sel : std_logic;
signal phase_inc_update_en : std_logic;
--signal phase_inc_mux : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_inc_r : std_logic_vector(31 downto 0);
signal phase_inc_r1 : std_logic_vector(31 downto 0);
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
signal phase_inc_addsub : std_logic_vector(31 downto 0);
signal rstn : std_logic;
begin
i_addsub : addsub
port map(
a => phase_inc_r,
b => phase_inc_step_r,
--clk => clk_in,
s => phase_inc_addsub
);
fifo_rden_out <= fifo_rden;--fifo_rden_r;
data_out <= data_r;
dval_out <= dval_r;
process(clk_in)
begin
if(rising_edge(clk_in))then
if(rst_r = '1')then
state_r <= s0;
cnt1_r <= (others => '0');
cnt2_r <= (others => '0');
cnt3_r <= (others => '0');
cnt4_r <= (others => '0');
cnt5_r <= (others => '0');
phase_inc_dwell_cnt_r <= (others => '0');
else
state_r <= state;
cnt1_r <= cnt1;
cnt2_r <= cnt2;
cnt3_r <= cnt3;
cnt4_r <= cnt4;
cnt5_r <= cnt5;
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
end if;
if(fifo_data_ce = '1')then
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
end if;
rst_r <= rst_in;
rstn_r <= not(rst_in);
dval_r <= dval;
phase_offset_r <= fifo_data_r(223 downto 192);
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
dds_sample_cnt_r1 <= dds_sample_cnt_r;
swap_r <= fifo_data_r(240);
scale_r <= fifo_data_r(239 downto 224);
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
idle_sample_cnt_r1 <= idle_sample_cnt_r;
phase_inc_step_r <= fifo_data_r(87 downto 64);
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
data_r <= data;
holdoff_r <= holdoff_in;
phase_inc_r <= phase_inc;
if(phase_inc_update_en = '1')then
phase_inc_r1 <= phase_inc_r;
end if;
end if;
end process;
phase_inc_init_r <= fifo_data_r(191 downto 160);
-- FSM next-state & output process
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
begin
--defaults
fifo_rden <= '0';
cnt1 <= cnt1_r;
cnt2 <= cnt2_r;
cnt3 <= cnt3_r;
cnt4 <= cnt4_r;
cnt5 <= cnt5_r;
state <= state_r;
dds_ce <= '0';
dds_rst <= '1';
dval <= mult_dval_r;
data <= data_swap_scaled;
fifo_data_ce <= '0';
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
phase_inc <= phase_inc_r;
phase_inc_update_en <= '0';
case state_r is
when s0 =>
phase_inc_dwell_cnt <= (others => '0');
if(fifo_empty_in = '0' and cnt1_r < 8)then
fifo_rden <= '1';
cnt1 <= cnt1_r +1;
end if;
if(fifo_dval_in = '1')then
fifo_data_ce <= '1';
if(cnt2_r < 7)then
cnt2 <= cnt2_r +1;
else
cnt2 <= (others => '0');
cnt1 <= (others => '0');
state <= s0a;
end if;
end if;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
when s0a =>
state <= s0b;--s1;
phase_inc <= phase_inc_init_r;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
when s0b =>
state <= s1;
phase_inc_update_en <= '1';
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
-- This state is needed to clock the input shift reg data into next set of regs.
-- Possibly can be removed to decrease pulse param processing cycles.
-- when s0c =>
-- state <= s1;
-- phase_inc_update_en <= '1';
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
-- Insert midpoint (idle) samples that preceed the pulse.
when s1 =>
data <= MIDPOINT;
if(cnt3_r < idle_sample_cnt_r1)then
if(holdoff_r = '0')then
cnt3 <= cnt3_r +1;
dval <= '1';
end if;
else
cnt3 <= (others => '0');
if(dds_sample_cnt_r1 > 0)then
state <= s2;
else
state <= s0;
end if;
end if;
-- Turn on DDS for requested number of samples.
when s2 =>
dds_rst <= '0';
if(holdoff_r = '0')then
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
else
phase_inc_dwell_cnt <= (others => '0');
phase_inc_update_en <= '1';
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
end if;
end if;
if(holdoff_r = '0')then
dds_ce <= '1';
if(cnt4_r < dds_sample_cnt_r1)then
cnt4 <= cnt4_r +1;
else
cnt4 <= (others => '0');
state <= s3;
end if;
end if;
-- phase_inc_mux_sel <= '1';
-- --phase_inc_en <= not(holdoff_r);
-- dds_rst <= '0';
-- if(cnt4_r < dds_sample_cnt_r1)then
-- if(holdoff_r = '0')then
-- dds_ce <= '1';
-- cnt4 <= cnt4_r +1;
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
-- else
-- phase_inc_dwell_cnt <= x"00000";
-- phase_inc_en <= '1';
-- end if;
-- end if;
-- else
-- if(holdoff_r = '0')then
-- dds_ce <= '1';
-- cnt4 <= (others => '0');
-- state <= s3;
-- end if;
-- end if;
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
when s3 =>
dds_rst <= '0';
if(cnt5_r < 9)then
if(holdoff_r = '0')then
dds_ce <= '1';
cnt5 <= cnt5_r +1;
end if;
else
cnt5 <= (others => '0');
state <= s0;
end if;
when others =>
end case;
end process;
process(clk_in)
begin
if(rising_edge(clk_in))then
mult_dval_r <= mult_ce_pipe_r(1);
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
end if;
end process;
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
i_dds : dds_latency10
port map(
-- ce => dds_ce,
-- clk => clk_in,
-- sclr => dds_rst,
-- pinc_in => phase_inc_r1,
-- poff_in => phase_offset_r,
-- rdy => dds_rdy,
-- cosine => dds_data(15 downto 0),
-- sine => dds_data(31 downto 16)
aclk => clk_in,
aclken => dds_ce,
aresetn => rstn_r,
s_axis_phase_tvalid => dds_ce,
s_axis_phase_tdata => phase_inc_r1,
m_axis_data_tvalid => dds_rdy,
m_axis_data_tdata => dds_data(31 downto 0)
);
i_mult1 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => dds_data(15 downto 0),
b => scale_r,
ce => mult_ce,
sclr => '0',
p => data_scaled(15 downto 0)
);
i_mult2 : mult_16signed_x_16unsigned_latency3
port map(
clk => clk_in,
a => dds_data(31 downto 16),
b => scale_r,
ce => mult_ce,
sclr => '0',
p => data_scaled(31 downto 16)
);
end mixed;
ip_repo/pdw_generator_1_0/src/dds_pulse_wrapper_x4.vhd
+520
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@@ -0,0 +1,520 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
entity dds_pulse_wrapper_x4 is
generic (
SIM_ENABLED : boolean := FALSE;
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
);
port(
s_axi_aclk_in : in std_logic;
s_axi_aresetn_in : in std_logic;
cmd_idx_in : in std_logic_vector( 2 downto 0);
cmd_send_in : in std_logic;
mode_in : in std_logic;
scale_in : in std_logic_vector(15 downto 0);
dac_holdoff_in : in std_logic;
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
m_axis_aclk_in : in std_logic;
dds_pulse_data_out : out std_logic_vector(31 downto 0);
dds_pulse_dval_out : out std_logic;
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
reset_in : in std_logic
);
end entity dds_pulse_wrapper_x4;
architecture imp of dds_pulse_wrapper_x4 is
constant ok_clk_in_period : time := 10 ns;
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
attribute keep of minor_rev_r : signal is "true";
signal s_axi_areset : std_logic;
signal cmd_idx : std_logic_vector( 2 downto 0);
signal cmd_send : std_logic;
signal mode : std_logic;
signal scale : std_logic_vector(15 downto 0);
signal dac_holdoff : std_logic;
signal reserv1 : std_logic_vector(31 downto 0);
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
signal idle_samples : std_logic_vector(31 downto 0);
signal dds_samples : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_off : std_logic_vector(31 downto 0);
signal swap_sf : std_logic_vector(31 downto 0);
signal dds_pulse_dval : std_logic;
signal dds_pulse_data : std_logic_vector(31 downto 0);
signal pulse_i : std_logic_vector(15 downto 0);
signal pulse_q : std_logic_vector(15 downto 0);
signal pipe_in_ch1_fifo_rden : std_logic;
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rd_dval : std_logic;
signal pipe_in_ch1_fifo_empty : std_logic;
signal pipe_in_ch2_fifo_rden : std_logic;
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
signal vio_cmd_send : std_logic;
signal vio_mode : std_logic;
signal vio_scale : std_logic_vector(15 downto 0);
signal vio_dac_holdoff : std_logic;
signal vio_reserv1 : std_logic_vector(31 downto 0);
attribute keep of vio_reserv1 : signal is "true";
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
signal vio_idle_samples : std_logic_vector(31 downto 0);
attribute keep of vio_idle_samples : signal is "true";
signal vio_dds_samples : std_logic_vector(31 downto 0);
attribute keep of vio_dds_samples : signal is "true";
signal vio_phase_inc : std_logic_vector(31 downto 0);
attribute keep of vio_phase_inc : signal is "true";
signal vio_phase_off : std_logic_vector(31 downto 0);
attribute keep of vio_phase_off : signal is "true";
signal vio_swap_sf : std_logic_vector(31 downto 0);
attribute keep of vio_swap_sf : signal is "true";
signal vio_enable : std_logic;
signal vio_cnt_rst : std_logic;
signal cmd_send_r : std_logic := '0';
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tick_1ms : std_logic;
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
-- file DataFile : text;
signal dds_m_axis_tready : std_logic;
begin
cmd_send_cnt_out <= cmd_send_cnt_r;
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
fpga_revision_date_r <= FPGA_REVISION_DATE;
minor_rev_r <= MINOR_REV;
end if;
end process;
sim_false : if (SIM_ENABLED = FALSE) generate
i_vio_0 : entity work.vio_0
port map (
clk => s_axi_aclk_in,
probe_in0 => fpga_revision_date_r, -- 32
probe_in1 => minor_rev_r, -- 8
probe_in2 => m_axis_aclk_freq_r, -- 32
probe_in3 => m_axis_aclk_cnt_r , -- 32
probe_in4 => s_axi_aclk_freq_r, -- 32
probe_in5 => s_axi_aclk_cnt_r , -- 32
probe_in6 => dds_pulse_data_overflow_cnt_r,
probe_out0(0) => vio_mode, -- 1
probe_out1 => vio_scale, -- 16
probe_out2 => vio_cmd_idx, -- 3
probe_out3(0) => vio_cmd_send, -- 1
probe_out4(0) => vio_dac_holdoff, -- 1
probe_out5 => vio_reserv1, -- 32
probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
probe_out7 => vio_dds_phase_inc_step_size, -- 32
probe_out8 => vio_idle_samples, -- 32
probe_out9 => vio_dds_samples, -- 32
probe_out10 => vio_phase_inc, -- 32
probe_out11 => vio_phase_off, -- 32
probe_out12 => vio_swap_sf, -- 32
probe_out13 => vio_enable, -- 1
probe_out14 => vio_cnt_rst -- 1
);
end generate sim_false;
mode <= vio_mode when vio_enable = '1' else mode_in;
scale <= vio_scale when vio_enable = '1' else scale_in;
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
-- mode <= vio_mode;
-- scale <= vio_scale;
-- dac_holdoff <= vio_dac_holdoff;
-- cmd_idx <= vio_cmd_idx;
-- cmd_send <= vio_cmd_send;
--
-- reserv1 <= vio_reserv1;
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
-- idle_samples <= vio_idle_samples;
-- dds_samples <= vio_dds_samples;
-- phase_inc <= vio_phase_inc;
-- phase_off <= vio_phase_off;
-- swap_sf <= vio_swap_sf;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
cmd_send_r <= cmd_send;
if (cmd_send = '1' and cmd_send_r = '0') then
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
end if;
end if;
end process;
i_dds_cmd_gen : entity work.dds_cmd_gen
generic map (
SIM_ENABLED => SIM_ENABLED
)
port map (
clk_in => s_axi_aclk_in,
cmd_idx_in => cmd_idx,
cmd_send_in => cmd_send,
vio_reserv1_in => reserv1,
vio_dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
vio_dds_phase_inc_step_size_in => dds_phase_inc_step_size,
vio_idle_samples_in => idle_samples,
vio_dds_samples_in => dds_samples,
vio_phase_inc_in => phase_inc,
vio_phase_off_in => phase_off,
vio_swap_sf_in => swap_sf,
fifo_rd_clk_in => m_axis_aclk_in,
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
rst_in => s_axi_areset
);
sim_false1 : if (SIM_ENABLED = FALSE) generate
i_ila_4 : entity work.ila_4
port map (
clk => m_axis_aclk_in,
probe0 => pipe_in_ch1_fifo_rd_data, --32
probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
probe2(0) => pipe_in_ch1_fifo_rden, --1
probe3(0) => pipe_in_ch1_fifo_empty --1
);
end generate sim_false1;
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
port map(
clk_in => m_axis_aclk_in,
rst_in => reset_in,
mode_in => mode, -- 0=single, 1=dual
scale_in => scale,
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
fifo1_empty_in => pipe_in_ch1_fifo_empty,
fifo1_rden_out => pipe_in_ch1_fifo_rden,
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
fifo2_rden_out => pipe_in_ch2_fifo_rden,
holdoff_in => dac_holdoff,
overflow_out => open,
underflow_out => open,
i_max_abs_out => open,
q_max_abs_out => open,
data_out => dds_pulse_data,
dval_out => dds_pulse_dval
);
pulse_i <= dds_pulse_data(15 downto 0);
pulse_q <= dds_pulse_data(31 downto 16);
-- process(m_axis_aclk_in)
-- variable LineOut : line;
-- begin
-- if (rising_edge(m_axis_aclk_in)) then
-- if (dds_pulse_dval = '1') then
-- hwrite(LineOut, dds_pulse_data);
-- writeline(DataFile, LineOut);
-- end if;
-- end if;
-- end process;
process(m_axis_aclk_in, vio_cnt_rst)
begin
if(vio_cnt_rst = '1') then
dds_pulse_data_cnt_r <= (others => '0');
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
elsif (rising_edge(m_axis_aclk_in)) then
if (dds_pulse_dval = '1') then
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
end if;
if (pipe_in_ch1_fifo_rden = '1') then
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
end if;
end if;
end process;
sim_false2 : if (SIM_ENABLED = FALSE) generate
i_ila_3 : entity work.ila_3
port map (
clk => m_axis_aclk_in,
probe0 => dds_pulse_data(15 downto 0),
probe1 => dds_pulse_data(31 downto 16),
probe2(0) => dds_pulse_dval,
probe3(0) => '0'
);
end generate sim_false2;
dds_pulse_data_out <= dds_pulse_data;
dds_pulse_dval_out <= dds_pulse_dval;
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 100
)
port map (
clk_in => s_axi_aclk_in,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000",
prog_us_tick_out => open,
reset_in => reset_in
);
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
m_axis_aclk_cnt_r <= (others => '0');
else
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
end if;
end if;
end process;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
s_axi_aclk_cnt_r <= (others => '0');
else
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
end if;
end if;
end process;
sim_true : if (SIM_ENABLED = TRUE) generate
-- Stimulus process
stim_proc: process
begin
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
wait until rising_edge(s_axi_aclk_in);
wait for 1 ns;
vio_mode <= '0';
vio_scale <= x"8000";
vio_cmd_idx <= "000";
vio_cmd_send <= '0';
vio_dac_holdoff <= '1';
vio_reserv1 <= x"00000000"; --RESERVED1
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
vio_phase_off <= x"00000000"; --PHASE_OFF
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
vio_enable <= '1';
vio_cnt_rst <= '0';
wait for ok_clk_in_period*10;
wait until rising_edge(s_axi_aclk_in);
wait for 200 ns;
wait for 200 ns;
wait for 200 ns;
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "000";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 3
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "011";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
--
-- -- WFM 1
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "001";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
-- -- WFM 0
-- -- FREQUENCY SWEEP (UP-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "000";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
-- -- WFM 1
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "001";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
--
--
-- -- WFM 2
-- -- CW TONE
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_idx <= "010";
-- vio_cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- vio_cmd_send <= '0';
-- wait for 100 ns;
wait for ok_clk_in_period*10;
wait until rising_edge(s_axi_aclk_in);
vio_dac_holdoff <= '0';
-- -- WFM 3
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "011";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
-- wait for 100 ns;
-- CW TONE
-- vio_reserv1 <= x"00000000"; --RESERVED1
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
-- vio_phase_off <= x"00000000"; --PHASE_OFF
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "100";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
wait for 5 us;
wait;
end process;
end generate sim_true;
end architecture imp;
ip_repo/pdw_generator_1_0/src/dds_wrapper.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dds_wrapper is
generic (
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"00";
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
m_axis_aclk_in : in std_logic;
reset_in : in std_logic;
dds_pulse_data_out : out std_logic_vector(31 downto 0);
dds_pulse_dval_out : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end dds_wrapper;
architecture arch_imp of dds_wrapper is
signal cmd_idx : std_logic_vector( 2 downto 0);
signal cmd_send : std_logic;
signal mode : std_logic;
signal scale : std_logic_vector(15 downto 0);
signal dac_holdoff : std_logic;
signal reserv1 : std_logic_vector(31 downto 0);
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
signal idle_samples : std_logic_vector(31 downto 0);
signal dds_samples : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_off : std_logic_vector(31 downto 0);
signal swap_sf : std_logic_vector(31 downto 0);
signal cmd_send_cnt : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rden_cnt : std_logic_vector(31 downto 0);
signal m_axis_tvalid_cnt : std_logic_vector(31 downto 0);
signal dds_pulse_data_cnt : std_logic_vector(31 downto 0);
begin
-- Instantiation of Axi Bus Interface S00_AXI
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
generic map (
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
MINOR_REV => MINOR_REV,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
cmd_idx_out => cmd_idx,
cmd_send_out => cmd_send,
mode_out => mode,
scale_out => scale,
dac_holdoff_out => dac_holdoff,
reserv1_out => reserv1,
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time,
dds_phase_inc_step_size_out => dds_phase_inc_step_size,
idle_samples_out => idle_samples,
dds_samples_out => dds_samples,
phase_inc_out => phase_inc,
phase_off_out => phase_off,
swap_sf_out => swap_sf,
cmd_send_cnt_in => cmd_send_cnt,
pipe_in_ch1_fifo_rden_cnt_in => pipe_in_ch1_fifo_rden_cnt,
m_axis_tvalid_cnt_in => x"0000_0000",
dds_pulse_data_cnt_in => dds_pulse_data_cnt,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY
);
-- Add user logic here
i_dds_pulse_wrapper_x4 : entity work.dds_pulse_wrapper_x4
generic map (
SIM_ENABLED => FALSE,
FPGA_REVISION_DATE => FPGA_REVISION_DATE,
MINOR_REV => MINOR_REV
)
port map (
s_axi_aclk_in => S_AXI_ACLK,
s_axi_aresetn_in => S_AXI_ARESETN,
cmd_idx_in => cmd_idx,
cmd_send_in => cmd_send,
mode_in => mode,
scale_in => scale,
dac_holdoff_in => dac_holdoff,
reserv1_in => reserv1,
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
idle_samples_in => idle_samples,
dds_samples_in => dds_samples,
phase_inc_in => phase_inc,
phase_off_in => phase_off,
swap_sf_in => swap_sf,
m_axis_aclk_in => m_axis_aclk_in,
dds_pulse_data_out => dds_pulse_data_out,
dds_pulse_dval_out => dds_pulse_dval_out,
cmd_send_cnt_out => cmd_send_cnt,
pipe_in_ch1_fifo_rden_cnt_out => pipe_in_ch1_fifo_rden_cnt,
dds_pulse_data_cnt_out => dds_pulse_data_cnt,
reset_in => reset_in
);
end architecture arch_imp;
ip_repo/pdw_generator_1_0/src/ila_0/ila_0.xci
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ip_repo/pdw_generator_1_0/src/ila_3/ila_3.xci
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ip_repo/pdw_generator_1_0/src/ila_4/ila_4.xci
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ip_repo/pdw_generator_1_0/src/ila_5/ila_5.xci
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ip_repo/pdw_generator_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "mult_16signed_x_16unsigned_latency3",
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1",
"component_reference": "xilinx.com:ip:mult_gen:12.0",
"ip_revision": "18",
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
"parameters": {
"component_parameters": {
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
"PortAWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
"Use_Custom_Output_Width": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"OutputWidthHigh": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"OutputWidthLow": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PipeStages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ClockEnable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SyncClear": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_HAS_SCLR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_B_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUT_HIGH": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OUT_LOW": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu102:part0:3.4" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu9eg" } ],
"PACKAGE": [ { "value": "ffvb1156" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "18" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
"SCLR": [ { "direction": "in", "driver_value": "0x0" } ],
"P": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"a_intf": {
"vlnv": "xilinx.com:signal:data:1.0",
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
"mode": "slave",
"parameters": {
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"DATA": [ { "physical_name": "A" } ]
}
},
"clk_intf": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
},
"sclr_intf": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "SCLR" } ]
}
},
"ce_intf": {
"vlnv": "xilinx.com:signal:clockenable:1.0",
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
},
"port_maps": {
"CE": [ { "physical_name": "CE" } ]
}
},
"b_intf": {
"vlnv": "xilinx.com:signal:data:1.0",
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
"mode": "slave",
"parameters": {
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"DATA": [ { "physical_name": "B" } ]
}
},
"p_intf": {
"vlnv": "xilinx.com:signal:data:1.0",
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
"mode": "master",
"parameters": {
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"DATA": [ { "physical_name": "P" } ]
}
}
}
}
}
}
ip_repo/pdw_generator_1_0/src/pdw_wrapper.vhd
+813
View File
@@ -0,0 +1,813 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
entity pdw_wrapper is
generic (
SIM_ENABLED : boolean := FALSE;
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0911_2023";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
);
port(
s_axi_aclk_in : in std_logic;
s_axi_aresetn_in : in std_logic;
cmd_idx_in : in std_logic_vector( 2 downto 0);
cmd_send_in : in std_logic;
loop_mode_en_in : in std_logic_vector( 7 downto 0);
mode_in : in std_logic;
scale_in : in std_logic_vector(15 downto 0);
dac_holdoff_in : in std_logic;
reserv1_in : in std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
idle_samples_in : in std_logic_vector(31 downto 0);
dds_samples_in : in std_logic_vector(31 downto 0);
phase_inc_in : in std_logic_vector(31 downto 0);
phase_off_in : in std_logic_vector(31 downto 0);
swap_sf_in : in std_logic_vector(31 downto 0);
latch_en_in : in std_logic;
reserv1_out : out std_logic_vector(31 downto 0);
dds_phase_inc_dwell_time_out : out std_logic_vector(31 downto 0);
dds_phase_inc_step_size_out : out std_logic_vector(31 downto 0);
idle_samples_out : out std_logic_vector(31 downto 0);
dds_samples_out : out std_logic_vector(31 downto 0);
phase_inc_out : out std_logic_vector(31 downto 0);
phase_off_out : out std_logic_vector(31 downto 0);
swap_sf_out : out std_logic_vector(31 downto 0);
m_axis_aclk_in : in std_logic;
dds_pulse_data_out : out std_logic_vector(63 downto 0);
dds_pulse_dval_out : out std_logic;
cmd_send_cnt_out : out std_logic_vector(31 downto 0);
pipe_in_ch1_fifo_rden_cnt_out : out std_logic_vector(31 downto 0);
dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
dds_done_out : out std_logic;
trigger_mode_in : in std_logic_vector( 1 downto 0);
ext_trigger_in : in std_logic;
prog_us_tick_in : in std_logic_vector(31 downto 0);
duration_ms_cnt_in : in std_logic_vector(31 downto 0);
reset_in : in std_logic
);
end entity pdw_wrapper;
architecture imp of pdw_wrapper is
constant ok_clk_in_period : time := 10 ns;
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
attribute keep of minor_rev_r : signal is "true";
signal s_axi_areset : std_logic;
signal cmd_idx : std_logic_vector( 2 downto 0);
signal cmd_send : std_logic;
signal mode : std_logic;
signal scale : std_logic_vector(15 downto 0);
signal dac_holdoff : std_logic;
signal dac_holdoff_n_r : std_logic := '1';
signal reserv1 : std_logic_vector(31 downto 0);
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
signal idle_samples : std_logic_vector(31 downto 0);
signal dds_samples : std_logic_vector(31 downto 0);
signal phase_inc : std_logic_vector(31 downto 0);
signal phase_off : std_logic_vector(31 downto 0);
signal swap_sf : std_logic_vector(31 downto 0);
signal dds_pulse_dval : std_logic;
signal dds_pulse_data : std_logic_vector(31 downto 0);
signal pulse_i : std_logic_vector(15 downto 0);
signal pulse_q : std_logic_vector(15 downto 0);
signal pipe_in_ch1_fifo_rden : std_logic;
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
signal pipe_in_ch1_fifo_rd_dval : std_logic;
signal pipe_in_ch1_fifo_empty : std_logic;
signal pipe_in_ch2_fifo_rden : std_logic;
signal vio_cmd_idx : std_logic_vector( 2 downto 0);
signal vio_cmd_send : std_logic;
signal vio_mode : std_logic;
signal vio_scale : std_logic_vector(15 downto 0);
signal vio_dac_holdoff : std_logic;
signal vio_reserv1 : std_logic_vector(31 downto 0);
attribute keep of vio_reserv1 : signal is "true";
signal vio_dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_dwell_time : signal is "true";
signal vio_dds_phase_inc_step_size : std_logic_vector(31 downto 0);
attribute keep of vio_dds_phase_inc_step_size : signal is "true";
signal vio_idle_samples : std_logic_vector(31 downto 0);
attribute keep of vio_idle_samples : signal is "true";
signal vio_dds_samples : std_logic_vector(31 downto 0);
attribute keep of vio_dds_samples : signal is "true";
signal vio_phase_inc : std_logic_vector(31 downto 0);
attribute keep of vio_phase_inc : signal is "true";
signal vio_phase_off : std_logic_vector(31 downto 0);
attribute keep of vio_phase_off : signal is "true";
signal vio_swap_sf : std_logic_vector(31 downto 0);
attribute keep of vio_swap_sf : signal is "true";
signal vio_enable : std_logic := '0';
signal vio_cnt_rst : std_logic;
signal latch_en : std_logic;
signal vio_latch_en : std_logic;
signal cmd_send_r : std_logic := '0';
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tick_1ms : std_logic;
signal m_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal m_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
-- file DataFile : text;
signal dds_m_axis_tready : std_logic;
signal dac_holdoff_trig : std_logic;
signal dds_done : std_logic;
signal dds_done_r : std_logic_vector(0 to 3) := (others => '0');
attribute keep of dds_done_r : signal is "true";
signal loop_mode_en : std_logic_vector( 7 downto 0);
signal loop_mode_en_r : std_logic_vector( 7 downto 0) := (others => '0');
signal vio_loop_mode_en : std_logic_vector( 7 downto 0);
signal loop_mode_cmd_idx_r : std_logic_vector( 2 downto 0) := (others => '0');
signal loop_mode_cmd_send_r : std_logic := '0';
type fsm_state is (IDLE, SEND, WAIT1);
signal state_r : fsm_state := IDLE;
signal state_cnt_r : integer := 0;
signal cmd_idx_mux : std_logic_vector( 2 downto 0);
signal cmd_send_mux : std_logic;
signal cmd_gen_busy : std_logic;
signal trigger_mode : std_logic_vector( 1 downto 0);
signal vio_trigger_mode : std_logic_vector( 1 downto 0);
signal bit_idx_r : std_logic_vector( 2 downto 0) := (others => '0');
signal prog_tick : std_logic;
signal prog_tick_trig_n : std_logic;
signal prog_us_tick : std_logic_vector(31 downto 0);
signal vio_prog_us_tick : std_logic_vector(31 downto 0);
signal ext_trigger_n_r : std_logic := '1';
signal test_state : std_logic_vector(1 downto 0);
type fsm_state1 is (IDLE, DURATION_CNT);
signal state1_r : fsm_state1 := IDLE;
signal duration_ms_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal duration_en_r : std_logic := '0';
signal duration_done_r : std_logic := '0';
signal dds_done_done_r : std_logic := '0';
signal ext_trigger_r : std_logic_vector(0 to 2) := (others => '0');
signal pulse_data_word_r : std_logic_vector(63 downto 0) := (others => '0');
signal pulse_data_word_dval_r : std_logic := '0';
signal read_toggle_r : std_logic := '0';
begin
cmd_send_cnt_out <= cmd_send_cnt_r;
pipe_in_ch1_fifo_rden_cnt_out <= pipe_in_ch1_fifo_rden_cnt_r;
dds_pulse_data_cnt_out <= dds_pulse_data_cnt_r;
dds_done_out <= duration_done_r when trigger_mode = "11" else dds_done_done_r;
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
fpga_revision_date_r <= FPGA_REVISION_DATE;
minor_rev_r <= MINOR_REV;
end if;
end process;
-- sim_false_vio_0 : if (SIM_ENABLED = FALSE) generate
-- i_vio_0 : entity work.vio_0
-- port map (
-- clk => s_axi_aclk_in,
-- probe_in0 => fpga_revision_date_r, -- 32
-- probe_in1 => minor_rev_r, -- 8
-- probe_in2 => m_axis_aclk_freq_r, -- 32
-- probe_in3 => m_axis_aclk_cnt_r , -- 32
-- probe_in4 => s_axi_aclk_freq_r, -- 32
-- probe_in5 => s_axi_aclk_cnt_r , -- 32
-- probe_in6 => , --32
--
-- probe_out0(0) => vio_mode, -- 1
-- probe_out1 => vio_scale, -- 16
-- probe_out2 => vio_cmd_idx, -- 3
-- probe_out3(0) => vio_cmd_send, -- 1
-- probe_out4(0) => vio_dac_holdoff, -- 1
--
-- probe_out5 => vio_reserv1, -- 32
-- probe_out6 => vio_dds_phase_inc_dwell_time, -- 32
-- probe_out7 => vio_dds_phase_inc_step_size, -- 32
-- probe_out8 => vio_idle_samples, -- 32
-- probe_out9 => vio_dds_samples, -- 32
-- probe_out10 => vio_phase_inc, -- 32
-- probe_out11 => vio_phase_off, -- 32
-- probe_out12 => vio_swap_sf, -- 32
-- probe_out13 => vio_enable, -- 1
-- probe_out14 => vio_cnt_rst, -- 1
-- probe_out15 => vio_latch_en, -- 1
-- probe_out16 => vio_loop_mode_en, -- 8
-- probe_out17 => vio_trigger_mode, -- 2
-- probe_out18 => vio_prog_us_tick -- 32
-- );
-- end generate sim_false_vio_0;
mode <= vio_mode when vio_enable = '1' else mode_in;
scale <= vio_scale when vio_enable = '1' else scale_in;
dac_holdoff <= vio_dac_holdoff when vio_enable = '1' else dac_holdoff_in;
cmd_idx <= vio_cmd_idx when vio_enable = '1' else cmd_idx_in;
cmd_send <= vio_cmd_send when vio_enable = '1' else cmd_send_in;
loop_mode_en <= vio_loop_mode_en when vio_enable = '1' else loop_mode_en_in;
trigger_mode <= vio_trigger_mode when vio_enable = '1' else trigger_mode_in;
reserv1 <= vio_reserv1 when vio_enable = '1' else reserv1_in;
dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time when vio_enable = '1' else dds_phase_inc_dwell_time_in;
dds_phase_inc_step_size <= vio_dds_phase_inc_step_size when vio_enable = '1' else dds_phase_inc_step_size_in;
idle_samples <= vio_idle_samples when vio_enable = '1' else idle_samples_in;
dds_samples <= vio_dds_samples when vio_enable = '1' else dds_samples_in;
phase_inc <= vio_phase_inc when vio_enable = '1' else phase_inc_in;
phase_off <= vio_phase_off when vio_enable = '1' else phase_off_in;
swap_sf <= vio_swap_sf when vio_enable = '1' else swap_sf_in;
latch_en <= vio_latch_en when vio_enable = '1' else latch_en_in;
prog_us_tick <= vio_prog_us_tick when vio_enable = '1' else prog_us_tick_in;
cmd_idx_mux <= loop_mode_cmd_idx_r when loop_mode_en /= x"00" and dac_holdoff = '0' else cmd_idx;
cmd_send_mux <= loop_mode_cmd_send_r when loop_mode_en /= x"00" and dac_holdoff = '0' else cmd_send;
dac_holdoff_trig <= dac_holdoff when trigger_mode = "00" else
ext_trigger_n_r when trigger_mode = "01" and dac_holdoff = '0' else
prog_tick_trig_n when (trigger_mode = "10" or trigger_mode = "11") and dac_holdoff = '0' else '1';
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
if (dds_done = '1') then
dds_done_done_r <= '1';
elsif (cmd_send_mux = '1') then
dds_done_done_r <= '0';
end if;
ext_trigger_r <= ext_trigger_r(1 to 2) & ext_trigger_in;
if (ext_trigger_r(0) = '0' and ext_trigger_r(1) = '1') then -- detect rising_edge of trigger
ext_trigger_n_r <= '0';
else
ext_trigger_n_r <= '1';
end if;
end if;
end process;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
loop_mode_cmd_send_r <= '0';
dds_done_r <= dds_done_r(1 to 3) & dds_done;
case (state_r) is
when IDLE => --0
if (dds_done_r(0) = '1' and loop_mode_en /= x"00" and dac_holdoff = '0' and trigger_mode /= "00" ) then
loop_mode_en_r <= loop_mode_en;
bit_idx_r <= (others => '0');
state_r <= SEND;
else
state_r <= IDLE;
end if;
when SEND => --1
if (cmd_gen_busy = '0') then
bit_idx_r <= bit_idx_r + 1;
if (loop_mode_en_r(conv_integer(unsigned(bit_idx_r))) = '1') then
loop_mode_cmd_idx_r <= bit_idx_r;
loop_mode_cmd_send_r <= '1';
state_cnt_r <= 3;
else
state_cnt_r <= 0;
end if;
if (bit_idx_r = 7) then
state_r <= IDLE;
else
state_r <= WAIT1;
end if;
else
state_r <= SEND;
end if;
when WAIT1 => --2
if (state_cnt_r = 0) then
state_r <= SEND;
else
state_cnt_r <= state_cnt_r - 1;
state_r <= WAIT1;
end if;
end case;
end if;
end process;
test_state <= "00" when state_r = IDLE else
"01" when state_r = SEND else
"10" when state_r = WAIT1 else
"11";
-- sim_false_ila_1 : if (SIM_ENABLED = FALSE) generate
-- i_ila_1 : entity work.ila_1
-- port map (
-- clk => s_axi_aclk_in,
-- probe0 => test_state, -- 2
-- probe1(0) => dac_holdoff_trig, -- 1
-- probe2 => trigger_mode, -- 2
-- probe3(0) => dds_done_r(0), -- 1
-- probe4 => cmd_idx_mux, -- 3
-- probe5(0) => cmd_send_mux, -- 1
-- probe6(0) => cmd_gen_busy -- 1
-- );
-- end generate sim_false_ila_1;
-- mode <= vio_mode;
-- scale <= vio_scale;
-- dac_holdoff <= vio_dac_holdoff;
-- cmd_idx <= vio_cmd_idx;
-- cmd_send <= vio_cmd_send;
--
-- reserv1 <= vio_reserv1;
-- dds_phase_inc_dwell_time <= vio_dds_phase_inc_dwell_time;
-- dds_phase_inc_step_size <= vio_dds_phase_inc_step_size;
-- idle_samples <= vio_idle_samples;
-- dds_samples <= vio_dds_samples;
-- phase_inc <= vio_phase_inc;
-- phase_off <= vio_phase_off;
-- swap_sf <= vio_swap_sf;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
cmd_send_r <= cmd_send_mux;
if (reset_in = '1') then
cmd_send_cnt_r <= (others => '0');
else
if (cmd_send_mux = '1' and cmd_send_r = '0') then
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
end if;
end if;
end if;
end process;
i_dds_cmd_gen : entity work.dds_cmd_gen
generic map (
SIM_ENABLED => SIM_ENABLED
)
port map (
clk_in => s_axi_aclk_in,
cmd_idx_in => cmd_idx_mux, --cmd_idx,
cmd_send_in => cmd_send_mux, --cmd_send,
busy_out => cmd_gen_busy,
reserv1_in => reserv1,
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
idle_samples_in => idle_samples,
dds_samples_in => dds_samples,
phase_inc_in => phase_inc,
phase_off_in => phase_off,
swap_sf_in => swap_sf,
latch_en_in => latch_en,
reserv1_out => reserv1_out,
dds_phase_inc_dwell_time_out => dds_phase_inc_dwell_time_out,
dds_phase_inc_step_size_out => dds_phase_inc_step_size_out,
idle_samples_out => idle_samples_out,
dds_samples_out => dds_samples_out,
phase_inc_out => phase_inc_out,
phase_off_out => phase_off_out,
swap_sf_out => swap_sf_out,
fifo_rd_clk_in => m_axis_aclk_in,
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
rst_in => s_axi_areset
);
-- sim_false_ila_4 : if (SIM_ENABLED = FALSE) generate
-- i_ila_4 : entity work.ila_4
-- port map (
-- clk => m_axis_aclk_in,
-- probe0 => pipe_in_ch1_fifo_rd_data, --32
-- probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
-- probe2(0) => pipe_in_ch1_fifo_rden, --1
-- probe3(0) => pipe_in_ch1_fifo_empty --1
-- );
-- end generate sim_false_ila_4;
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
port map(
clk_in => m_axis_aclk_in,
rst_in => reset_in,
mode_in => mode, -- 0=single, 1=dual
scale_in => scale,
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
fifo1_empty_in => pipe_in_ch1_fifo_empty,
fifo1_rden_out => pipe_in_ch1_fifo_rden,
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
fifo2_rden_out => pipe_in_ch2_fifo_rden,
holdoff_in => dac_holdoff_trig, --dac_holdoff,
overflow_out => open,
underflow_out => open,
i_max_abs_out => open,
q_max_abs_out => open,
data_out => dds_pulse_data,
dval_out => dds_pulse_dval,
done_out => dds_done
);
pulse_i <= dds_pulse_data(15 downto 0);
pulse_q <= dds_pulse_data(31 downto 16);
-- process(m_axis_aclk_in)
-- variable LineOut : line;
-- begin
-- if (rising_edge(m_axis_aclk_in)) then
-- if (dds_pulse_dval = '1') then
-- hwrite(LineOut, dds_pulse_data);
-- writeline(DataFile, LineOut);
-- end if;
-- end if;
-- end process;
process(m_axis_aclk_in, vio_cnt_rst)
begin
if(vio_cnt_rst = '1') then
dds_pulse_data_cnt_r <= (others => '0');
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
elsif (rising_edge(m_axis_aclk_in)) then
if (reset_in = '1') then
dds_pulse_data_cnt_r <= (others => '0');
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
else
if (dds_pulse_dval = '1') then
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
end if;
if (pipe_in_ch1_fifo_rden = '1') then
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
end if;
end if;
end if;
end process;
-- sim_false_ila_3 : if (SIM_ENABLED = FALSE) generate
-- i_ila_3 : entity work.ila_3
-- port map (
-- clk => m_axis_aclk_in,
-- probe0 => dds_pulse_data(15 downto 0),
-- probe1 => dds_pulse_data(31 downto 16),
-- probe2(0) => dds_pulse_dval,
-- probe3(0) => s_axis_tready
-- );
-- end generate sim_false_ila_3;
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
pulse_data_word_dval_r <= '0';
if (dds_pulse_dval = '1') then
read_toggle_r <= not read_toggle_r;
if (read_toggle_r = '0') then
pulse_data_word_r(31 downto 0) <= dds_pulse_data;
else
pulse_data_word_r(63 downto 32) <= dds_pulse_data;
pulse_data_word_dval_r <= '1';
end if;
end if;
end if;
end process;
dds_pulse_data_out <= pulse_data_word_r;
dds_pulse_dval_out <= pulse_data_word_dval_r;
-- dds_pulse_data_out <= dds_pulse_data;
-- dds_pulse_dval_out <= dds_pulse_dval;
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 100
)
port map (
clk_in => s_axi_aclk_in,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => prog_us_tick,
prog_us_tick_out => prog_tick,
reset_in => reset_in
);
prog_tick_trig_n <= not prog_tick when trigger_mode = "11" and duration_en_r = '1' else
not prog_tick when trigger_mode = "10" else '1';
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
dac_holdoff_n_r <= dac_holdoff;
case (state1_r) is
when IDLE => --0
if (trigger_mode = "11" and dac_holdoff_n_r = '1' and dac_holdoff = '0') then
duration_ms_cnt_r <= (others => '0');
duration_en_r <= '1';
duration_done_r <= '0';
state1_r <= DURATION_CNT;
else
state1_r <= IDLE;
end if;
when DURATION_CNT => --1
if (tick_1ms = '1') then
if((duration_ms_cnt_r = duration_ms_cnt_in) or dac_holdoff = '1') then
duration_ms_cnt_r <= (others => '0');
duration_en_r <= '0';
duration_done_r <= '1';
state1_r <= IDLE;
else
duration_ms_cnt_r <= duration_ms_cnt_r + 1;
state1_r <= DURATION_CNT;
end if;
end if;
end case;
end if;
end process;
process(m_axis_aclk_in)
begin
if (rising_edge(m_axis_aclk_in)) then
m_axis_aclk_tick_1ms_r <= m_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (m_axis_aclk_tick_1ms_r(0 to 1) = "01") then
m_axis_aclk_freq_r <= m_axis_aclk_cnt_r;
m_axis_aclk_cnt_r <= (others => '0');
else
m_axis_aclk_cnt_r <= m_axis_aclk_cnt_r + 1;
end if;
end if;
end process;
process(s_axi_aclk_in)
begin
if (rising_edge(s_axi_aclk_in)) then
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
s_axi_aclk_cnt_r <= (others => '0');
else
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
end if;
end if;
end process;
sim_true : if (SIM_ENABLED = TRUE) generate
-- Stimulus process
stim_proc: process
begin
-- file_open(DataFile, "c:\temp\dds_data.txt", write_mode);
wait until rising_edge(s_axi_aclk_in);
wait for 1 ns;
vio_mode <= '0';
vio_scale <= x"8000";
vio_cmd_idx <= "000";
vio_cmd_send <= '0';
vio_loop_mode_en <= x"00";
vio_trigger_mode <= "00"; -- manual trigger
vio_prog_us_tick <= conv_std_logic_vector(100, 32);
vio_dac_holdoff <= '1';
vio_reserv1 <= x"00000000"; --RESERVED1
vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
vio_idle_samples <= x"00000000"; --IDLE_SAMPLES
vio_dds_samples <= x"00000000"; --DDS_SAMPLES (~5 us)
vio_phase_inc <= x"00000000"; --PHASE_INC (~1 MHz)
vio_phase_off <= x"00000000"; --PHASE_OFF
vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
vio_enable <= '1';
vio_cnt_rst <= '0';
wait for ok_clk_in_period*10;
wait until rising_edge(s_axi_aclk_in);
wait for 200 ns;
wait for 200 ns;
wait for 200 ns;
-- WFM 0
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "000";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 1
-- FREQUENCY SWEEP (DOWN-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "001";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 2
-- CW TONE
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "010";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 3
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "011";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 4
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "100";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 5
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "101";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 6
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "110";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
-- WFM 7
-- FREQUENCY SWEEP (UP-SWEEP)
wait until rising_edge(s_axi_aclk_in);
vio_cmd_idx <= "111";
vio_cmd_send <= '1';
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
wait until rising_edge(s_axi_aclk_in);
vio_cmd_send <= '0';
wait for 100 ns;
vio_loop_mode_en <= x"FF";
-- wait for ok_clk_in_period*10;
-- wait until rising_edge(s_axi_aclk_in);
-- vio_dac_holdoff <= '0';
-- wait for ok_clk_in_period*10;
-- wait until rising_edge(s_axi_aclk_in);
-- vio_dac_holdoff <= '1';
--
-- wait for 15 us;
-- wait for ok_clk_in_period*10;
-- wait until rising_edge(s_axi_aclk_in);
-- vio_dac_holdoff <= '0';
-- wait for ok_clk_in_period*10;
-- wait until rising_edge(s_axi_aclk_in);
-- vio_dac_holdoff <= '1';
-- vio_trigger_mode <= "01"; -- external trigger
vio_trigger_mode <= "10"; -- periodic trigger
wait for 200 ns;
wait until rising_edge(s_axi_aclk_in);
vio_dac_holdoff <= '0';
-- wait for 125 us;
-- vio_dac_holdoff <= '1';
-- -- WFM 3
-- -- FREQUENCY SWEEP (DOWN-SWEEP)
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "011";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
-- wait for 100 ns;
-- CW TONE
-- vio_reserv1 <= x"00000000"; --RESERVED1
-- vio_dds_phase_inc_dwell_time <= x"00000000"; --DDS_PHASE_INC_DWELL_TIME
-- vio_dds_phase_inc_step_size <= x"00000000"; --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
-- vio_idle_samples <= x"00000050"; --IDLE_SAMPLES
-- vio_dds_samples <= x"000FFFFF"; --DDS_SAMPLES (~5 us)
-- vio_phase_inc <= x"0624DD2F"; --PHASE_INC (~1 MHz)
-- vio_phase_off <= x"00000000"; --PHASE_OFF
-- vio_swap_sf <= x"00008000"; --RESERVED_SWAP_SF -- Scale Factor = 1.0
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_idx <= "100";
-- cmd_send <= '1';
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- wait until rising_edge(s_axi_aclk_in);
-- cmd_send <= '0';
-- wait for 100 ns;
wait for 5 us;
wait; -- wait here forever
end process;
end generate sim_true;
end architecture imp;
ip_repo/pdw_generator_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci
+468
View File
@@ -0,0 +1,468 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "sfifo_32b_1024_pf992_latency1",
"cell_name": "i_pdw_wrapper_0/i_dds_pulse_2x_top/i_pulse1_fifo",
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
"ip_revision": "7",
"gen_directory": "../../../../../../aa/pdw_generator_v1_0_project/pdw_generator_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
"Fifo_Implementation": [ { "value": "Common_Clock_Builtin_FIFO", "resolve_type": "user", "usage": "all" } ],
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
"asymmetric_port_width": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
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"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "clk" } ]
}
},
"FIFO_WRITE": {
"vlnv": "xilinx.com:interface:fifo_write:1.0",
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
"mode": "slave",
"port_maps": {
"FULL": [ { "physical_name": "full" } ],
"WR_DATA": [ { "physical_name": "din" } ],
"WR_EN": [ { "physical_name": "wr_en" } ]
}
},
"FIFO_READ": {
"vlnv": "xilinx.com:interface:fifo_read:1.0",
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
"mode": "slave",
"port_maps": {
"EMPTY": [ { "physical_name": "empty" } ],
"RD_DATA": [ { "physical_name": "dout" } ],
"RD_EN": [ { "physical_name": "rd_en" } ]
}
}
}
}
}
}
ip_repo/pdw_generator_1_0/src/tick_gen.vhd
+121
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@@ -0,0 +1,121 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tick_gen is
generic(
CLOCK_SPEED_MHZ : integer := 100
);
port(
clk_in : in std_logic;
tick_1us_out : out std_logic;
tick_1ms_out : out std_logic;
tick_500ms_out : out std_logic;
tick_750ms_out : out std_logic;
tick_1s_out : out std_logic;
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
prog_us_tick_out : out std_logic;
reset_in : in std_logic
);
end entity tick_gen;
architecture imp of tick_gen is
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
signal usec_cnt_r : integer range 0 to 999;
signal msec_cnt_r : integer range 0 to 499;
signal msec_cnt1_r : integer range 0 to 999;
signal tick_1us_r : std_logic;
signal tick_1ms_r : std_logic;
signal tick_500ms_r : std_logic;
signal tick_750ms_r : std_logic;
signal tick_1s_r : std_logic;
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
signal prog_us_tick_r : std_logic;
begin
tick_1us_out <= tick_1us_r;
tick_1ms_out <= tick_1ms_r;
tick_500ms_out <= tick_500ms_r;
tick_750ms_out <= tick_750ms_r;
tick_1s_out <= tick_1s_r;
prog_us_tick_out <= prog_us_tick_r;
process(clk_in, reset_in)
begin
if(reset_in = '1') then
sysclk_cnt_r <= 0;
usec_cnt_r <= 0;
msec_cnt_r <= 0;
msec_cnt1_r <= 0;
tick_1us_r <= '1';
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '0';
elsif rising_edge(clk_in) then
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_us_tick_r <= '0';
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
sysclk_cnt_r <= 0;
tick_1us_r <= '1';
else
sysclk_cnt_r <= sysclk_cnt_r + 1;
tick_1us_r <= '0';
end if;
if(tick_1us_r = '1') then
if(usec_cnt_r = 999) then -- 1000us
usec_cnt_r <= 0;
tick_1ms_r <= '1';
else
usec_cnt_r <= usec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt_r = 499) then -- 500ms
msec_cnt_r <= 0;
tick_500ms_r <= '1';
else
msec_cnt_r <= msec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt1_r = 749) then -- 750ms
tick_750ms_r <= '1';
end if;
if(msec_cnt1_r = 999) then -- 1s
msec_cnt1_r <= 0;
tick_1s_r <= '1';
else
msec_cnt1_r <= msec_cnt1_r + 1;
end if;
end if;
if(tick_1us_r = '1') then
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '1';
else
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
end if;
end if;
end if;
end process;
end architecture imp;
ip_repo/pdw_generator_1_0/src/vio_0/vio_0.xci
+1655
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File diff suppressed because it is too large Load Diff
ip_repo/pdw_generator_1_0/xgui/pdw_generator_v1_0.tcl
+240
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@@ -0,0 +1,240 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S01_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S01_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S01_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S01_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S03_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S03_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S03_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S03_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S02_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S02_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S02_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S02_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "MINOR_REV"
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
}
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to validate FPGA_REVISION_DATE
return true
}
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to validate MINOR_REV
return true
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_PARAM_VALUE.C_S01_AXI_DATA_WIDTH { PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
# Procedure called to update C_S01_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S01_AXI_DATA_WIDTH { PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
# Procedure called to validate C_S01_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S01_AXI_ADDR_WIDTH { PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
# Procedure called to update C_S01_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S01_AXI_ADDR_WIDTH { PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S01_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S01_AXI_BASEADDR { PARAM_VALUE.C_S01_AXI_BASEADDR } {
# Procedure called to update C_S01_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S01_AXI_BASEADDR { PARAM_VALUE.C_S01_AXI_BASEADDR } {
# Procedure called to validate C_S01_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S01_AXI_HIGHADDR { PARAM_VALUE.C_S01_AXI_HIGHADDR } {
# Procedure called to update C_S01_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S01_AXI_HIGHADDR { PARAM_VALUE.C_S01_AXI_HIGHADDR } {
# Procedure called to validate C_S01_AXI_HIGHADDR
return true
}
proc update_PARAM_VALUE.C_S03_AXI_DATA_WIDTH { PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
# Procedure called to update C_S03_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S03_AXI_DATA_WIDTH { PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
# Procedure called to validate C_S03_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S03_AXI_ADDR_WIDTH { PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
# Procedure called to update C_S03_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S03_AXI_ADDR_WIDTH { PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S03_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S03_AXI_BASEADDR { PARAM_VALUE.C_S03_AXI_BASEADDR } {
# Procedure called to update C_S03_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S03_AXI_BASEADDR { PARAM_VALUE.C_S03_AXI_BASEADDR } {
# Procedure called to validate C_S03_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S03_AXI_HIGHADDR { PARAM_VALUE.C_S03_AXI_HIGHADDR } {
# Procedure called to update C_S03_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S03_AXI_HIGHADDR { PARAM_VALUE.C_S03_AXI_HIGHADDR } {
# Procedure called to validate C_S03_AXI_HIGHADDR
return true
}
proc update_PARAM_VALUE.C_S02_AXI_DATA_WIDTH { PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
# Procedure called to update C_S02_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S02_AXI_DATA_WIDTH { PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
# Procedure called to validate C_S02_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S02_AXI_ADDR_WIDTH { PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
# Procedure called to update C_S02_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S02_AXI_ADDR_WIDTH { PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S02_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S02_AXI_BASEADDR { PARAM_VALUE.C_S02_AXI_BASEADDR } {
# Procedure called to update C_S02_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S02_AXI_BASEADDR { PARAM_VALUE.C_S02_AXI_BASEADDR } {
# Procedure called to validate C_S02_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S02_AXI_HIGHADDR { PARAM_VALUE.C_S02_AXI_HIGHADDR } {
# Procedure called to update C_S02_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S02_AXI_HIGHADDR { PARAM_VALUE.C_S02_AXI_HIGHADDR } {
# Procedure called to validate C_S02_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH PARAM_VALUE.C_S01_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S01_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH PARAM_VALUE.C_S01_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S01_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH PARAM_VALUE.C_S03_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S03_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S03_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH PARAM_VALUE.C_S03_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S03_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S03_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH PARAM_VALUE.C_S02_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S02_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S02_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH PARAM_VALUE.C_S02_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S02_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S02_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
}
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
}