415 lines
15 KiB
VHDL
415 lines
15 KiB
VHDL
-------------------------------------------------------------------------------
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-- Company:
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-- Engineer: Jason M. Blevins
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--
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-- Create Date: 19:38:12 11/10/2016
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-- Design Name:
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-- Module Name: dds_pulse_gen - behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - Added Sweep Functionality 10-17-2017
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-- Additional Comments:
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-- * All information is proprietary/confidential *
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--
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-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
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-- The control word contains all information needed to create a pulse
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--
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-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
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-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
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-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
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-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
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-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
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-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
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-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
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-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
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-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
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-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
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-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
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-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--Library UNIMACRO;
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--use UNIMACRO.vcomponents.all;
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USE IEEE.NUMERIC_STD.ALL;
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entity dds_pulse_gen is
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port(
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clk_in : in std_logic;
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rst_in : in std_logic;
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fifo_data_in : in std_logic_vector(31 downto 0);
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fifo_dval_in : in std_logic;
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fifo_empty_in : in std_logic;
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fifo_rden_out : out std_logic;
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holdoff_in : in std_logic;
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data_out : out std_logic_vector(31 downto 0);
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dval_out : out std_logic
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);
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end entity;
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architecture mixed of dds_pulse_gen is
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component mult_16signed_x_16unsigned_latency3
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port(
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clk : in std_logic;
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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ce : in std_logic;
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sclr : in std_logic;
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p : out std_logic_vector(15 downto 0)
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);
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end component;
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component dds_latency10
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port(
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-- ce : in std_logic;
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-- clk : in std_logic;
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-- sclr : in std_logic;
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-- pinc_in : in std_logic_vector(31 downto 0);
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-- poff_in : in std_logic_vector(31 downto 0);
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-- rdy : out std_logic;
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-- cosine : out std_logic_vector(15 downto 0);
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-- sine : out std_logic_vector(15 downto 0)
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aclk : IN STD_LOGIC;
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aclken : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_phase_tvalid : IN STD_LOGIC;
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s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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m_axis_data_tvalid : OUT STD_LOGIC;
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m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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end component;
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component addsub
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port (
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a : in std_logic_vector(31 downto 0); -- unsigned
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b : in std_logic_vector(23 downto 0); -- signed
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--clk : in std_logic;
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s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
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);
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end component;
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constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
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type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
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signal state : state_type;
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signal state_r : state_type;
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signal rst_r : std_logic := '1';
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signal rstn_r : std_logic := '0';
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signal cnt1_r : unsigned(3 downto 0) := "0000";
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signal cnt1 : unsigned(3 downto 0);
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signal cnt2_r : unsigned(2 downto 0) := "000";
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signal cnt2 : unsigned(2 downto 0);
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signal cnt3_r : unsigned(31 downto 0) := x"00000000";
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signal cnt3 : unsigned(31 downto 0);
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signal cnt4_r : unsigned(31 downto 0) := x"00000000";
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signal cnt4 : unsigned(31 downto 0);
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signal cnt5_r : unsigned(3 downto 0) := "0000";
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signal cnt5 : unsigned(3 downto 0);
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signal fifo_data_ce : std_logic;
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signal fifo_data_r : std_logic_vector(255 downto 0);
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signal fifo_rden : std_logic;
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--signal fifo_rden_r : std_logic := '0';
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signal dval_r : std_logic := '0';
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signal dval : std_logic;
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signal dds_data : std_logic_vector(31 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal data_r : std_logic_vector(31 downto 0);
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signal idle_sample_cnt_r : unsigned(31 downto 0);
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signal idle_sample_cnt_r1 : unsigned(31 downto 0);
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signal dds_sample_cnt_r : unsigned(31 downto 0);
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signal dds_sample_cnt_r1 : unsigned(31 downto 0);
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signal phase_inc_init_r : std_logic_vector(31 downto 0);
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signal phase_offset_r : std_logic_vector(31 downto 0);
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signal swap_r : std_logic := '0';
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signal scale_r : std_logic_vector(15 downto 0);
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signal mult_dval_r : std_logic := '0';
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signal data_swap_scaled : std_logic_vector(31 downto 0);
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signal data_scaled : std_logic_vector(31 downto 0);
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signal dds_ce : std_logic;
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signal dds_rst : std_logic;
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signal dds_rdy : std_logic;
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signal mult_ce : std_logic;
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signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
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signal holdoff_r : std_logic;
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--signal phase_inc_mux_sel : std_logic;
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signal phase_inc_update_en : std_logic;
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--signal phase_inc_mux : std_logic_vector(31 downto 0);
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signal phase_inc : std_logic_vector(31 downto 0);
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signal phase_inc_r : std_logic_vector(31 downto 0);
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signal phase_inc_r1 : std_logic_vector(31 downto 0);
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signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
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signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
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signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
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signal phase_inc_dwell_cnt : unsigned(15 downto 0);
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signal phase_inc_addsub : std_logic_vector(31 downto 0);
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signal rstn : std_logic;
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begin
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i_addsub : addsub
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port map(
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a => phase_inc_r,
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b => phase_inc_step_r,
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--clk => clk_in,
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s => phase_inc_addsub
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);
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fifo_rden_out <= fifo_rden;--fifo_rden_r;
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data_out <= data_r;
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dval_out <= dval_r;
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process(clk_in)
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begin
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if(rising_edge(clk_in))then
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if(rst_r = '1')then
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state_r <= s0;
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cnt1_r <= (others => '0');
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cnt2_r <= (others => '0');
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cnt3_r <= (others => '0');
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cnt4_r <= (others => '0');
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cnt5_r <= (others => '0');
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phase_inc_dwell_cnt_r <= (others => '0');
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else
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state_r <= state;
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cnt1_r <= cnt1;
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cnt2_r <= cnt2;
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cnt3_r <= cnt3;
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cnt4_r <= cnt4;
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cnt5_r <= cnt5;
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phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
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end if;
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if(fifo_data_ce = '1')then
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fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
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end if;
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rst_r <= rst_in;
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rstn_r <= not(rst_in);
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dval_r <= dval;
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phase_offset_r <= fifo_data_r(223 downto 192);
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-- phase_inc_init_r <= fifo_data_r(191 downto 160);
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dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
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dds_sample_cnt_r1 <= dds_sample_cnt_r;
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swap_r <= fifo_data_r(240);
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scale_r <= fifo_data_r(239 downto 224);
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idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
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idle_sample_cnt_r1 <= idle_sample_cnt_r;
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phase_inc_step_r <= fifo_data_r(87 downto 64);
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phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
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data_r <= data;
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holdoff_r <= holdoff_in;
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phase_inc_r <= phase_inc;
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if(phase_inc_update_en = '1')then
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phase_inc_r1 <= phase_inc_r;
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end if;
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end if;
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end process;
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phase_inc_init_r <= fifo_data_r(191 downto 160);
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-- FSM next-state & output process
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process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
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mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
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begin
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--defaults
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fifo_rden <= '0';
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cnt1 <= cnt1_r;
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cnt2 <= cnt2_r;
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cnt3 <= cnt3_r;
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cnt4 <= cnt4_r;
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cnt5 <= cnt5_r;
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state <= state_r;
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dds_ce <= '0';
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dds_rst <= '1';
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dval <= mult_dval_r;
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data <= data_swap_scaled;
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fifo_data_ce <= '0';
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phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
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phase_inc <= phase_inc_r;
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phase_inc_update_en <= '0';
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case state_r is
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when s0 =>
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phase_inc_dwell_cnt <= (others => '0');
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if(fifo_empty_in = '0' and cnt1_r < 8)then
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fifo_rden <= '1';
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cnt1 <= cnt1_r +1;
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end if;
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if(fifo_dval_in = '1')then
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fifo_data_ce <= '1';
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if(cnt2_r < 7)then
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cnt2 <= cnt2_r +1;
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else
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cnt2 <= (others => '0');
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cnt1 <= (others => '0');
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state <= s0a;
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end if;
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end if;
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-- This state is needed to clock the input shift reg data into next set of regs.
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-- Possibly can be removed to decrease pulse param processing cycles.
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when s0a =>
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state <= s0b;--s1;
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phase_inc <= phase_inc_init_r;
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-- This state is needed to clock the input shift reg data into next set of regs.
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-- Possibly can be removed to decrease pulse param processing cycles.
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when s0b =>
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state <= s1;
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phase_inc_update_en <= '1';
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phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
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-- This state is needed to clock the input shift reg data into next set of regs.
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-- Possibly can be removed to decrease pulse param processing cycles.
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-- when s0c =>
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-- state <= s1;
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-- phase_inc_update_en <= '1';
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-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
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-- Insert midpoint (idle) samples that preceed the pulse.
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when s1 =>
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data <= MIDPOINT;
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if(cnt3_r < idle_sample_cnt_r1)then
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if(holdoff_r = '0')then
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cnt3 <= cnt3_r +1;
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dval <= '1';
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end if;
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else
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cnt3 <= (others => '0');
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if(dds_sample_cnt_r1 > 0)then
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state <= s2;
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else
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state <= s0;
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end if;
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end if;
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-- Turn on DDS for requested number of samples.
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when s2 =>
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dds_rst <= '0';
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if(holdoff_r = '0')then
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if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
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phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
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else
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phase_inc_dwell_cnt <= (others => '0');
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phase_inc_update_en <= '1';
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phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
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end if;
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end if;
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if(holdoff_r = '0')then
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dds_ce <= '1';
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if(cnt4_r < dds_sample_cnt_r1)then
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cnt4 <= cnt4_r +1;
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else
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cnt4 <= (others => '0');
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state <= s3;
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end if;
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end if;
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-- phase_inc_mux_sel <= '1';
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-- --phase_inc_en <= not(holdoff_r);
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-- dds_rst <= '0';
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-- if(cnt4_r < dds_sample_cnt_r1)then
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-- if(holdoff_r = '0')then
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-- dds_ce <= '1';
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-- cnt4 <= cnt4_r +1;
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-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
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-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
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-- else
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-- phase_inc_dwell_cnt <= x"00000";
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-- phase_inc_en <= '1';
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-- end if;
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-- end if;
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-- else
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-- if(holdoff_r = '0')then
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-- dds_ce <= '1';
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-- cnt4 <= (others => '0');
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-- state <= s3;
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-- end if;
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-- end if;
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-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
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when s3 =>
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dds_rst <= '0';
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if(cnt5_r < 9)then
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if(holdoff_r = '0')then
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dds_ce <= '1';
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cnt5 <= cnt5_r +1;
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end if;
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else
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cnt5 <= (others => '0');
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state <= s0;
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end if;
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when others =>
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end case;
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end process;
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process(clk_in)
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begin
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if(rising_edge(clk_in))then
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mult_dval_r <= mult_ce_pipe_r(1);
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mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
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end if;
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end process;
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data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
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mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
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i_dds : dds_latency10
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port map(
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-- ce => dds_ce,
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-- clk => clk_in,
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-- sclr => dds_rst,
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-- pinc_in => phase_inc_r1,
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-- poff_in => phase_offset_r,
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-- rdy => dds_rdy,
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-- cosine => dds_data(15 downto 0),
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-- sine => dds_data(31 downto 16)
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aclk => clk_in,
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aclken => dds_ce,
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aresetn => rstn_r,
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s_axis_phase_tvalid => dds_ce,
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s_axis_phase_tdata => phase_inc_r1,
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m_axis_data_tvalid => dds_rdy,
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m_axis_data_tdata => dds_data(31 downto 0)
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);
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i_mult1 : mult_16signed_x_16unsigned_latency3
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port map(
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clk => clk_in,
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a => dds_data(15 downto 0),
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b => scale_r,
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ce => mult_ce,
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sclr => '0',
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p => data_scaled(15 downto 0)
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);
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i_mult2 : mult_16signed_x_16unsigned_latency3
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port map(
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clk => clk_in,
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a => dds_data(31 downto 16),
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b => scale_r,
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ce => mult_ce,
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sclr => '0',
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p => data_scaled(31 downto 16)
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);
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end mixed;
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