206 lines
7.7 KiB
VHDL
206 lines
7.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity dds_cmd_gen is
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generic (
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SIM_ENABLED : boolean := FALSE
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);
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port(
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clk_in : in std_logic;
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cmd_idx_in : in std_logic_vector( 2 downto 0);
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cmd_send_in : in std_logic;
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vio_reserv1_in : in std_logic_vector(31 downto 0);
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vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
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vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
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vio_idle_samples_in : in std_logic_vector(31 downto 0);
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vio_dds_samples_in : in std_logic_vector(31 downto 0);
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vio_phase_inc_in : in std_logic_vector(31 downto 0);
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vio_phase_off_in : in std_logic_vector(31 downto 0);
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vio_swap_sf_in : in std_logic_vector(31 downto 0);
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fifo_rd_clk_in : in std_logic;
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fifo_rd_data_out : out std_logic_vector(31 downto 0);
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fifo_rd_dval_out : out std_logic;
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fifo_rd_rd_en_in : in std_logic;
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fifo_rd_empty_out : out std_logic;
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rst_in : in std_logic
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);
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end entity dds_cmd_gen;
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architecture imp of dds_cmd_gen is
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signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
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signal fifo_wr_en_r : std_logic := '0';
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signal cmd_idx_r : integer range 0 to 4 := 0;
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signal cmd_send_r : std_logic := '0';
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type fsm_state is (IDLE, SEND, DONE);
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signal state_r : fsm_state := IDLE;
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signal state_cnt_r : integer := 0;
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type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
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type dds_command_list is array (integer range <>) of array_32b_type;
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signal dds_command_set : dds_command_list(0 to 4) :=
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(
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-- WFM 0
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-- FREQUENCY SWEEP (UP-SWEEP)
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0 => (x"00000000", --RESERVED1
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x"00000000", --DDS_PHASE_INC_DWELL_TIME
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x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) = 68719 = 0x00010C6F
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x"00000000", --IDLE_SAMPLES
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x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
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x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
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x"00000000", --PHASE_OFF
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x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
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),
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-- WFM 1
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-- FREQUENCY SWEEP (DOWN-SWEEP)
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1 => (x"00000000", --RESERVED1
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x"00000000", --DDS_PHASE_INC_DWELL_TIME
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x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
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x"00000000", --IDLE_SAMPLES
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x"000004E2", --DDS_SAMPLES (~5 us)
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x"0624DD2F", --PHASE_INC (~6 MHz)
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x"00000000", --PHASE_OFF
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x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
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),
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-- WFM 2
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-- CW TONE
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2 => (x"00000000", --RESERVED1
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x"00000000", --DDS_PHASE_INC_DWELL_TIME
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x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
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x"00000000", --IDLE_SAMPLES
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x"000004E2", --DDS_SAMPLES (~5 us)
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-- x"000FFFFF", --DDS_SAMPLES (~5 us)
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x"0624DD2F", --PHASE_INC (~6 MHz)
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x"00000000", --PHASE_OFF
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x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
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),
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-- WFM 3
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-- FREQUENCY SWEEP (DOWN-SWEEP)
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3 => (x"00000000", --RESERVED1
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x"00000000", --DDS_PHASE_INC_DWELL_TIME
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x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
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x"00000000", --IDLE_SAMPLES
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x"000004E2", --DDS_SAMPLES (~5 us)
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x"0624DD2F", --PHASE_INC (~6 MHz)
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x"00000000", --PHASE_OFF
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x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
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),
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-- WFM 4
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-- ??????
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4 => (x"00000000", --RESERVED1
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x"00000000", --DDS_PHASE_INC_DWELL_TIME
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x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
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x"00000000", --IDLE_SAMPLES
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x"00000000", --DDS_SAMPLES (~5 us)
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x"00000000", --PHASE_INC (~6 MHz)
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x"00000000", --PHASE_OFF
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x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
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)
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);
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signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
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begin
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dds_command_set(4)(0) <= vio_reserv1_in;
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dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in;
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dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in;
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dds_command_set(4)(3) <= vio_idle_samples_in;
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dds_command_set(4)(4) <= vio_dds_samples_in;
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dds_command_set(4)(5) <= vio_phase_inc_in;
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dds_command_set(4)(6) <= vio_phase_off_in;
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dds_command_set(4)(7) <= vio_swap_sf_in;
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process(clk_in)
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begin
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if (rising_edge(clk_in)) then
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if (rst_in = '1') then
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cmd_idx_r <= 0;
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cmd_send_r <= '0';
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fifo_wr_en_r <= '0';
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state_cnt_r <= 0;
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state_r <= IDLE;
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else
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cmd_send_r <= cmd_send_in;
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fifo_wr_en_r <= '0';
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case (state_r) is
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when IDLE =>
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if (cmd_send_in = '1' and cmd_send_r = '0') then
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cmd_idx_r <= conv_integer(unsigned(cmd_idx_in));
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state_cnt_r <= 0;
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state_r <= SEND;
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else
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state_r <= IDLE;
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end if;
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when SEND =>
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if (state_cnt_r = 8) then
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state_r <= DONE;
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else
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fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r);
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fifo_wr_en_r <= '1';
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state_cnt_r <= state_cnt_r + 1;
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state_r <= SEND;
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end if;
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when DONE =>
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state_r <= IDLE;
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when others =>
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state_r <= IDLE;
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end case;
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end if;
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end if;
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end process;
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test_state_r <= "00" when state_r = IDLE else
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"01" when state_r = SEND else
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"10" when state_r = DONE else
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"11";
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sim_false : if (SIM_ENABLED = FALSE) generate
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i_ila_1 : entity work.ila_2
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port map (
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clk => clk_in,
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probe0 => test_state_r, -- 2
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probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
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probe2 => fifo_wr_data_r, -- 32
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probe3(0) => fifo_wr_en_r, -- 1
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probe4(0) => cmd_send_in, -- 1
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probe5(0) => cmd_send_r -- 1
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);
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end generate sim_false;
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i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
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port map(
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wr_clk => clk_in,
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din => fifo_wr_data_r,
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wr_en => fifo_wr_en_r,
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full => open,
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overflow => open,
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rd_clk => fifo_rd_clk_in,
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dout => fifo_rd_data_out,
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valid => fifo_rd_dval_out,
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rd_en => fifo_rd_rd_en_in,
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empty => fifo_rd_empty_out,
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underflow => open,
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prog_full => open,
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wr_rst_busy => open,
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rd_rst_busy => open,
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srst => rst_in
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);
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end architecture imp;
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