Erisys/alinx_z19_ad9082
6
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

playback functions work now

Browse Source
This commit is contained in:
Nick Santana
2026-06-16 00:28:29 -04:00
parent 29c85ad83d
commit 79b8226260
10 changed files with 18757 additions and 5816 deletions
Download Patch File Download Diff File Expand all files Collapse all files
source/axis_mux_chan_sel.vhd
+55
View File
@@ -0,0 +1,55 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_mux_chan_sel is
port (
aselect_in : in std_logic_vector( 1 downto 0);
cmac_0_tdata_in : in std_logic_vector(127 downto 0);
cmac_0_tvalid_in : in std_logic;
cmac_0_tready_out : out std_logic;
cmac_4_tdata_in : in std_logic_vector(127 downto 0);
cmac_4_tvalid_in : in std_logic;
cmac_4_tready_out : out std_logic;
m_axis_tdata_out : out std_logic_vector(255 downto 0);
m_axis_tvalid_out : out std_logic;
m_axis_tready_in : in std_logic
);
end entity axis_mux_chan_sel;
architecture imp of axis_mux_chan_sel is
begin
-- adc_chan1_s3 adc_chan0_s3 adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
m_axis_tdata_out <= cmac_4_tdata_in(127 downto 96) & cmac_0_tdata_in(127 downto 96) & cmac_4_tdata_in(95 downto 64) & cmac_0_tdata_in(95 downto 64) & cmac_4_tdata_in(63 downto 32) & cmac_0_tdata_in(63 downto 32) & cmac_4_tdata_in(31 downto 0) & cmac_0_tdata_in(31 downto 0) when aselect_in = "00" else
x"FFFF_0000" & cmac_0_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_0_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_0_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_0_tdata_in(31 downto 0) when aselect_in = "01" else
cmac_4_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_4_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_4_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_4_tdata_in(31 downto 0) & x"FFFF_0000";
m_axis_tvalid_out <= cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
cmac_0_tvalid_in when aselect_in = "01" else
cmac_4_tvalid_in when aselect_in = "10" else
'0';
cmac_0_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
m_axis_tready_in and cmac_0_tvalid_in when aselect_in = "01" else '0';
cmac_4_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
m_axis_tready_in and cmac_4_tvalid_in when aselect_in = "10" else '0';
end imp;
source/system_raw_eth_top.v
+28 -12
View File
@@ -36,8 +36,8 @@
`timescale 1ns/100ps
module system_raw_eth_top #(
parameter FPGA_REVISION_DATE = 32'h05212026,
parameter MINOR_REV = 8'h02,
parameter FPGA_REVISION_DATE = 32'h06122026,
parameter MINOR_REV = 8'h01,
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
@@ -246,7 +246,8 @@ module system_raw_eth_top #(
wire [127:0] cmac_0_rx_tdata_128b;
wire cmac_0_rx_tvalid_128b;
wire cmac_0_rx_tready_128b;
////
wire [511:0] cmac_4_tx_tdata_512b;
wire cmac_4_tx_tvalid_512b;
@@ -264,12 +265,12 @@ module system_raw_eth_top #(
wire [127:0] cmac_4_rx_tdata_128b;
wire cmac_4_rx_tvalid_128b;
wire cmac_4_rx_tready_128b;
////
wire [255:0] cmac_rx_tdata_256b;
wire cmac_rx_tvalid_256b;
wire cmac_rx_tready_256b;
wire cmac_rx_tready_256b_i;
reg [31:0] cmac_rx_tvalid_256b_cnt_r = 32'h0;
////
@@ -398,6 +399,7 @@ module system_raw_eth_top #(
wire [127:0] adc_tdata_128b_chan0;
wire [127:0] adc_tdata_128b_chan1;
wire [1:0] cmac_2_dac_chan_sel;
////////////////////////////////////////////////////////////////
@@ -856,7 +858,8 @@ module system_raw_eth_top #(
assign chan1to4_mode_sel = slv_reg10[12];
//assign = slv_reg10[14:13];
//assign = slv_reg10[15];
//assign = slv_reg10[30:16];
assign cmac_2_dac_chan_sel = slv_reg10[17:16];
//assign = slv_reg10[30:18];
assign playback_path_data_enable_n = slv_reg10[31];
//ila_5 i_ila_rx (
@@ -878,7 +881,7 @@ module system_raw_eth_top #(
// .probe14 (cmac_rx_tdata_256b[239:224]), // 16
// .probe15 (cmac_rx_tdata_256b[255:240]), // 16
// .probe16 (cmac_rx_tvalid_256b), // 1
// .probe17 (cmac_rx_tready_256b_i) // 1
// .probe17 (cmac_rx_tready_256b) // 1
// );
///////////////////////////////////////////////////////////////
@@ -987,7 +990,7 @@ module system_raw_eth_top #(
.m_axis_tdata (cmac_0_rx_tdata_128b), // out
.m_axis_tvalid (cmac_0_rx_tvalid_128b), // out
.m_axis_tready (cmac_rx_tready_256b_i) // in
.m_axis_tready (cmac_0_rx_tready_128b) // in
);
@@ -1099,7 +1102,7 @@ module system_raw_eth_top #(
.m_axis_tdata (cmac_4_rx_tdata_128b), // out
.m_axis_tvalid (cmac_4_rx_tvalid_128b), // out
.m_axis_tready (cmac_rx_tready_256b_i) // in
.m_axis_tready (cmac_4_rx_tready_128b) // in
);
////////////////////////////////////////////////////////////////////////////
@@ -1107,11 +1110,24 @@ module system_raw_eth_top #(
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b, cmac_0_rx_tdata_128b};
// adc_chan1_s3 adc_chan0_s3 //adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b[127:96], cmac_0_rx_tdata_128b[127:96], cmac_4_rx_tdata_128b[95:64], cmac_0_rx_tdata_128b[95:64], cmac_4_rx_tdata_128b[63:32], cmac_0_rx_tdata_128b[63:32], cmac_4_rx_tdata_128b[31:0], cmac_0_rx_tdata_128b[31:0]};
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b[127:96], cmac_0_rx_tdata_128b[127:96], cmac_4_rx_tdata_128b[95:64], cmac_0_rx_tdata_128b[95:64], cmac_4_rx_tdata_128b[63:32], cmac_0_rx_tdata_128b[63:32], cmac_4_rx_tdata_128b[31:0], cmac_0_rx_tdata_128b[31:0]};
assign cmac_rx_tvalid_256b = cmac_4_rx_tvalid_128b & cmac_0_rx_tvalid_128b;
assign cmac_rx_tready_256b_i = cmac_rx_tvalid_256b & cmac_rx_tready_256b;
axis_mux_chan_sel i_axis_mux_chan_sel (
.aselect_in (cmac_2_dac_chan_sel),
.cmac_0_tdata_in (cmac_0_rx_tdata_128b), // in
.cmac_0_tvalid_in (cmac_0_rx_tvalid_128b), // in
.cmac_0_tready_out (cmac_0_rx_tready_128b), // out
.cmac_4_tdata_in (cmac_4_rx_tdata_128b), // in
.cmac_4_tvalid_in (cmac_4_rx_tvalid_128b), // in
.cmac_4_tready_out (cmac_4_rx_tready_128b), // out
.m_axis_tdata_out (cmac_rx_tdata_256b), // out
.m_axis_tvalid_out (cmac_rx_tvalid_256b), // out
.m_axis_tready_in (cmac_rx_tready_256b) // in
);
ila_5 i_ila_rx (
.clk (tx_device_clk_1),
.probe0 (cmac_rx_tdata_256b[15:0]), // 16
@@ -1186,7 +1202,7 @@ module system_raw_eth_top #(
begin
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
cmac_rx_tvalid_256b_cnt_r <= 32'h0;
else if (cmac_rx_tvalid_256b == 1'b1 && cmac_rx_tready_256b_i == 1'b1)
else if (cmac_rx_tvalid_256b == 1'b1 && (cmac_0_rx_tready_128b || cmac_4_rx_tready_128b) == 1'b1)
cmac_rx_tvalid_256b_cnt_r <= cmac_rx_tvalid_256b_cnt_r + 1;
end