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# ALINX_Z19_AD9081
# Block Diagram
![image](block_diagram/alinx_z19_qsfp_block_diagram.jpg)
# Board's Picture
![image3](misc_files/alinx_board_connections.jpg)
# Address Map
![image2](/misc_files/memory_map.jpg)
## QSFP Interface Registers Base Address: 0x8000_0000
| Address<br>Offset | Bit | Register Name | Bit(s) Name |Description | Read/Write |
| :--- | :----: | :-------: | :-------- | :-------- | :----: |
|0x00 | 31:0 | reg0 | fpga_revision_date | mmddyyyy (0x05142026 <= current version) | R |
| | | | | ||
|0x04 | | reg1 | | | R |
| | 31:24<br>23:9<br>8<br>7:2<br>1<br>0 | | minor_rev<br>reserved<br>dig_iq_cmd_ready<br>reserved<br>qsfp4_playback_interface_ready<br>qsfp1_capture_interface_ready | 0x02 <= (current value) <br><br> 0 = Not Ready, 1 = Ready<br> <br> 0 = Not Ready, 1 = Ready<br> 0 = Not Ready, 1 = Ready | | |
| | | | | |
0x08 | | reg2 | | | R/W |
| | 31:0 || dig_iq_cmd_rdata | | ||
| | | | | |
0x0c | | reg3 | | | R/W |
| | 31:12<br>11:0 | |reserved<br>dig_iq_cmd_addr | | ||
| | | | | ||
0x10 | | reg4 | | | R/W |
| | 31:3<br>2:0 || reserved<br>dig_iq_cmd_sel | <br>QSFP Interface Select 0 = QSFP1, 1 = QSFP4 |||
| | | | | |
0x14 | | reg5 || | R/W |
| | 31:25<br>24<br>23:17<br>16<br>15:1<br>0 || reserved<br>qsfp4_reset_n<br>reserved<br>qsfp1_reset_n<br>reserved<br>dig_iq_cmd_strb | <br>0 = Reset, 1 = Normal<br><br>0 = Reset, 1 = Normal<br><br>0 = Nomal, 1 = Asserted | ||
| | | | | ||
0x18 | | reg6 | | | R/W |
| | 31:0 || dig_iq_cmd_wdata | | ||
| | | | | ||
0x1c | | reg7 | | | R/W |
| | 31:1<br>0 || reserved<br>dig_iq_cmd_write | <br>0 = Read, 1 = Write | ||
| | | | | ||
0x20 | | reg8 | | | R/W |
| |31<br>30:1<br>0 || counters_rst<br>reserved<br>dig_iq_mode_50g_40g_n | 0 = Normal, 1 = Reset<br><br>0 = 40G mode, 1 = 50G mode | ||
| | | | | ||
0x24 | | reg9 | | | R/W |
| | 31:0 || reserved | ||
| | | | | ||
0x28 | | reg10 | | | R/W |
| |31<br>30:13<br>12<br>11:10<br>9:8<br>7:1<br>0 || rx_path_disable<br>reserved<br>tx_chan1to4_en<br>reserved<br>dac_src_data_sel<br>reserved<br>tx_fiber_src_data_sel | 0 = enabled, 1 = disabled<br><br>0 = disabled, 1 = enabled<br><br>0 = QuadSendRecv, 1 = Fiber, 2 = ADC_LOOPBACK, 3 = DDS<br> 0 = ADC, 1 = DDS | ||
|0x2C | 31:0 | reg11 | qsfp1_s_axis_aclk_freq | 40G mode: 161132 (in KHz)<br>50G mode: 195312 (in KHz) | R |
| | | | | ||
|0x30 | 31:0 | reg12 | qsfp1_s_axis_aclk_cnt | | R |
| | | | | ||
|0x34 | 31:0 | reg13 | qsfp4_s_axis_aclk_freq | 40G mode: 161132 (KHz)<br>50G mode: 195312 (KHz) | R |
| | | | | ||
|0x38 | 31:0 | reg14 | qsfp4_s_axis_aclk_cnt | | R |
| | | | | ||
|0x3C | 31:0 | reg15 | rx_device_clk_freq | (KHz) | R |
| | | | | ||
|0x40 | 31:0 | reg16 | tx_device_clk_freq | | R |
| | | | | ||
|0x44 | 31:0 | reg17 | clk_125_freq | (KHz) | R |
| | | | | ||
|0x48 | 31:0 | reg18 | clk_125_cnt | | R |
| | | | | ||
|0x4C | 31:0 | reg19 | clk_250_freq | (KHz) | R |
| | | | | ||
|0x50 | 31:0 | reg20 | clk_250_cnt | | R |
| | | | | ||
|0x54 | 31:0 | reg21 | reserved | | R/W |
| | | | | ||
|0x58 | 31:0 | reg22 | reserved | | R/W |
| | | | | ||
|0x5C | 31:0 | reg23 | reserved | | R/W |
| | | | | ||
|0x60 | 31:0 | reg24 | reserved | | R/W |
| | | | | ||
|0x64 | 31:0 | reg25 | reserved | | R/W |
| | | | | ||
|0x68 | 31:0 | reg26 | reserved | | R/W |
| | | | | ||
|0x6C | 31:0 | reg27 | reserved | | R/W |
| | | | | ||
|0x70 | 31:0 | reg28 | reserved | | R/W |
| | | | | ||
| | | | | ||
|0x74 | 31:0 | reg29 | reserved | | R/W |
| | | | | ||
|0x78 | 31:0 | reg30 | reserved | | R/W |
| | | | | ||
|0x7C | 31:0 | reg31 | reserved | | R/W |
| | | | | ||
|0x80 | 31:0 | reg32 | reserved | | R/W |
| | | | | ||
|0x84 | 31:0 | reg33 | reserved | | R/W |
| | | | | ||
|0x88 | 31:0 | reg34 | reserved | | R/W |
| | | | | ||
|0x8C | 31:0 | reg35 | reserved | | R/W |
| | | | | ||
|0x90 | 31:0 | reg36 | reserved | | R/W |
| | | | | ||
| | | | | ||
|0x94 | 31:0 | reg37 | reserved | | R/W |
| | | | | ||
|0x98 | 31:0 | reg38 | reserved | | R/W |
| | | | | ||
|0x9C | 31:0 | reg39 | reserved | | R/W |
| | | | | ||
|0xA0 | 31:0 | reg40 | reserved | | R/W |
| | | | | ||
|0xA4 | 31:0 | reg41 | reserved | | R/W |
| | | | | ||
|0xA8 | 31:0 | reg42 | reserved | | R/W |
| | | | | ||
|0xAC | 31:0 | reg43 | reserved | | R/W |
| | | | | ||
|0xB0 | 31:0 | reg44 | reserved | | R/W |
| | | | | ||
| | | | | ||
|0xB4 | 31:0 | reg45 | reserved | | R/W |
| | | | | ||
|0xB8 | 31:0 | reg46 | reserved | | R/W |
| | | | | ||
|0xBC | 31:0 | reg47 | reserved | | R/W |
| | | | | ||
|0xC0 | 31:0 | reg48 | reserved | | R/W |
| | | | | ||
|0xC4 | 31:0 | reg49 | reserved | | R/W |
| | | | | ||
|0xC8 | 31:0 | reg50 | reserved | | R/W |
| | | | | ||
|0xCC | 31:0 | reg51 | reserved | | R/W |
| | | | | ||
|0xD0 | 31:0 | reg52 | reserved | | R/W |
| | | | | ||
| | | | | ||
|0xD4 | 31:0 | reg53 | qsfp4_playback_tvalid_240b_cnt | | R |
| | | | | ||
|0xD8 | 31:0 | reg54 | qsfp1_capture_overflow_240b_cnt | | R |
| | | | | ||
|0xDC | 31:0 | reg55 | qsfp4_playback_tvalid_128b_cnt | | R |
| | | | | ||
|0xE0 | 31:0 | reg56 | tx_tvalid_128b_cnt | | R |
| | | | | ||
|0xE4 | 31:0 | reg57 | mem_xfer_tx_upload_tvalid_128b_cnt | | R |
| | | | | ||
|0xE8 | 31:0 | reg58 | adc_rx_tvalid_128b_cnt | | R |
| | | | | ||
|0xEC | 31:0 | reg59 | fiber_tx_tvalid_128b_cnt | | R |
| | | | | ||
|0xF0 | 31:0 | reg60 | dac_tx_tvalid_128b_cnt | | R |
| | | | | ||
|0xF4 | 31:0 | reg61 | qsfp1_capture_tvalid_240b_cnt | | R |
| | | | | ||
|0xF8 | 31:0 | reg62 | qsfp1_capture_fifo_aempty_512b_cnt | | R |
| | | | | ||
|0xFC | 31:0 | reg63 | qsfp1_capture_rx_data_ready_cnt | | R |
| | | | | ||
## DDS Interface Registers Base Address: 0x8300_0000
| Address<br>Offset | Bit | Register Name | Bit(s) Name |Description | Read/Write |
| :--- | :----: | :-------: | :-------- | :-------- | :----: |
|0x00 | 31:13<br>12<br>11:9<br>8<br>7:5<br>4<br>3:1<br>0 | reg0 | <br>chan4_dds_send<br><br>chan3_dds_send<br><br>chan2_dds_send<br><br>chan1_dds_send | 1 = Send to DDS <br> these bits are self clearing | R |
| | | | | ||
|0x04 | | reg1 | | | R |
| | 31:1<br>0 | | <br>dac_holdoff | <br> 0 = Disabled, 1 = Enabled | | |
| | | | | |
0x08 | | reg2 | | | R/W |
| | 31:0 || reserved | | ||
| | | | | |
0x0c | | reg3 | | | R/W |
| | 31<br>30:1<br>0<br> | |dds_enable<br><br>cnt_reset<br> | 0 = DDS_Reset, 1 = DDS_enabled<br><br>1 = Reset_counters<br> this bit is self-clearing | ||
| | | | | ||
| | | | | ||
|0x10 | 31:16<br>15:0| reg4 | <br>scale_1 | | R/W |
| | | | | |
|0x14 | 31:0 | reg5 | dds_phase_inc_dwell_time_1 | | R/W |
| | | | | ||
|0x18 | 31:0 | reg6 | dds_phase_inc_step_size_1 | | R/W |
| | | | | ||
|0x1c | 31:0 | reg7 | idle_samples_1 || R/W |
| | | | | ||
|0x20 | 31:0 | reg8 | dds_samples_1 | | R/W |
| | | | | ||
|0x24 | 31:0 | reg9 | phase_inc_1 | | R/W |
| | | | | ||
|0x28 | 31:0 | reg10 | phase_off_1 | | R/W |
| | | | | ||
|0x2C | 31:0 | reg11 | swap_sf_1 | | R/W |
| | | | | ||
| | | | | ||
|0x30 | 31:16<br>15:0| reg12| <br>scale_2 | | R/W |
| | | | | |
|0x34 | 31:0 | reg13 | dds_phase_inc_dwell_time_2 | | R/W |
| | | | | ||
|0x38 | 31:0 | reg14 | dds_phase_inc_step_size_2 | | R/W |
| | | | | ||
|0x3c | 31:0 | reg15 | idle_samples_2 || R/W |
| | | | | ||
|0x40 | 31:0 | reg16 | dds_samples_2 | | R/W |
| | | | | ||
|0x44 | 31:0 | reg17 | phase_inc_2 | | R/W |
| | | | | ||
|0x48 | 31:0 | reg18 | phase_off_2 | | R/W |
| | | | | ||
|0x4C | 31:0 | reg19 | swap_sf_2 | | R/W |
| | | | | ||
| | | | | ||
|0x50 | 31:16<br>15:0| reg20 | <br>scale_3 | | R/W |
| | | | | |
|0x54 | 31:0 | reg21 | dds_phase_inc_dwell_time_3 | | R/W |
| | | | | ||
|0x58 | 31:0 | reg22 | dds_phase_inc_step_size_3 | | R/W |
| | | | | ||
|0x5c | 31:0 | reg23 | idle_samples_3 || R/W |
| | | | | ||
|0x60 | 31:0 | reg24 | dds_samples_3 | | R/W |
| | | | | ||
|0x64 | 31:0 | reg25 | phase_inc_3 | | R/W |
| | | | | ||
|0x68 | 31:0 | reg26 | phase_off_3 | | R/W |
| | | | | ||
|0x6C | 31:0 | reg27 | swap_sf_3 | | R/W |
| | | | | ||
| | | | | ||
|0x70 | 31:16<br>15:0| reg28 | <br>scale_4 | | R/W |
| | | | | |
|0x74 | 31:0 | reg29 | dds_phase_inc_dwell_time_4 | | R/W |
| | | | | ||
|0x78 | 31:0 | reg30 | dds_phase_inc_step_size_4 | | R/W |
| | | | | ||
|0x7c | 31:0 | reg31 | idle_samples_4 || R/W |
| | | | | ||
|0x80 | 31:0 | reg32 | dds_samples_4 | | R/W |
| | | | | ||
|0x84 | 31:0 | reg33 | phase_inc_4 | | R/W |
| | | | | ||
|0x88 | 31:0 | reg34 | phase_off_4 | | R/W |
| | | | | ||
|0x8C | 31:0 | reg35 | swap_sf_4 | | R/W |
| | | | | ||
| | | | | ||
|0x90 | 31:0 | reg36 | m0_dds_pulse_data_cnt | | R |
| | | | | ||
|0x94 | 31:0 | reg37 | m0_axis_tvalid_cnt | | R |
| | | | | ||
|0x98 | 31:0 | reg38 | m1_dds_pulse_data_cnt | | R |
| | | | | ||
|0x9C | 31:0 | reg39 | m1_axis_tvalid_cnt | | R |
| | | | | ||
# How to re-create Project in Vivado
1. Clone the hdl repository from https://github.com/analogdevicesinc/hdl
2. Follow instructions to build all the libraries
3. check out this project into a project folder, for example /<home>/projects/ALINX_Z19
4. open Vivado and add the following user repository(s):<br>
/<home>/adi/hdl/library<br>
5. cd to /<home>/projects/ALINX_Z19/alinx_z19_ad9081
6. type source ./create_proj.tcl
7. After the project is re-created correctly, run "Create HDL Wrapper..." from the Sources tab for system.bd
8. Click on "Generate Bitstream"
# How to update project file after adding or removing project files
1. remove system_wrapper.vhd from Design Sources since this file is auto-generated.
2. remove system_top.dcp from Design Sources from Utility\utils_1\Design Checkpoint.
3. in the Tcl console, cd to /<home>/projects/ALINX_Z19/alinx_z19_ad9081
4. type write_project_tcl -force create_proj.tcl
5. Make sure to commit create_proj.tcl and all modified and added files to git
## How to read or write registers using devmem from Linux's command line
Usage: devmem ADDRESS [WIDTH [VALUE]]
Read/write from physical address
ADDRESS Address to act upon
WIDTH Width (8/16/...)
VALUE Data to be written
### Memory Read Example
To read the FPGA Revision Register type:
devmem 0x80000000
0x10212024 <-- response
### Memory Write Example
To write a32-bit register type:
devmem 0x80000028 32 0x12345678
### How to Build Atomic Rules Yocto ARDSoC Project for Alinx_AD9081
1) clone this repo https://github.com/AtomicRulesLLC/yocto-ardsoc#
2) cd proj_ar/yocto-ardsoc/
3) git checkout scarthgap_mt
4) sudo ./scripts/plnx-env-setup.sh
5) cd sources
6) git submodule update
7) cd ..
8) source setupsdk z19-9081 build_z19_9081
9) bitbake ardsoc-image-core --> if all builds successfully see see Output Artifacts below
### Notes on how to re-generate BOOT.BIN
1) replace the .xsa file with your latest at this location:
proj_ar/yocto-ardsoc/sources/meta-atomicrules/meta-atomicrules-ardsoc/meta-z19-9081/recipes-bsp/external-hdf/files/system.xsa --> for AD9081
3) cd proj_ar/yocto-ardsoc/build_z19_ad981
4) rm -rf tmp/
5) sudo ./scripts/plnx-env-setup.sh
6) source setupsdk z19-9081 build_z19_9081
7) bitbake ardsoc-image-core --> if all builds successfully see see Output Artifacts belowe
### Output Artifacts
1) Once you have a new build with your xsa the artifacts can be found here:
a) proj_ar/yocto-ardsoc/build_z19_9081/tmp/deploy/images/ardsoc-z19-zynqmp/boot.bin
b) proj_ar/yocto-ardsoc/build_z19_9081/tmp/deploy/images/ardsoc-z19-zynqmp/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs.wic.gz
to copy new boot.bin to board:
ex. scp boot.bin root@10.1.1.169:/boot
### Misc Stuff
dtc -I dtb -O dts system.dtb -o system.dts
dtc -I dts -O dtb system.dts -o system.dtb
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