moving repo from git to local repo
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#####################################
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#
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# VCU128 Rev1.0 XDC
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# Date: 01/24/2018
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#
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####################################
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###################################
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### J79
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set_property PACKAGE_PIN L33 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 CLK0_N
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set_property PACKAGE_PIN L32 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 CLK0_P
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set_property PACKAGE_PIN G42 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131
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set_property PACKAGE_PIN G41 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131
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set_property PACKAGE_PIN F40 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131
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set_property PACKAGE_PIN F39 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131
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set_property PACKAGE_PIN E42 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131
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set_property PACKAGE_PIN E41 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131
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set_property PACKAGE_PIN D40 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131
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set_property PACKAGE_PIN D39 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131
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set_property PACKAGE_PIN H35 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131
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set_property PACKAGE_PIN H34 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131
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set_property PACKAGE_PIN G37 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131
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set_property PACKAGE_PIN G36 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131
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set_property PACKAGE_PIN F35 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131
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set_property PACKAGE_PIN F34 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131
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set_property PACKAGE_PIN E37 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131
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set_property PACKAGE_PIN E36 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 } [get_ports "QSFP4_MODPRSL_LS"] ;#
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### J78
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set_property PACKAGE_PIN R33 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 - MGTREFCLK0N_130 CLK1_N
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set_property PACKAGE_PIN R32 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130 CLK1_P
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# set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130
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# set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130
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# set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
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# set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
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# set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
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# set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
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# set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
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# set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
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# set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
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# set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130
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# set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
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# set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
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# set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
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# set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
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# set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
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# set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
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# set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
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# set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130
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### J77
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set_property PACKAGE_PIN W33 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129 CLK3_N
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set_property PACKAGE_PIN W32 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129 CLK3_P
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# set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129
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# set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129
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# set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
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# set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
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# set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
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# set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
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# set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
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# set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
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# set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
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# set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129
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# set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
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# set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
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# set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
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# set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
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# set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
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# set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
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# set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
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# set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129
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# set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;
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# set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;
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# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;
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### J76
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set_property PACKAGE_PIN AB35 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 128 - MGTREFCLK0N_128 CLK2_N
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set_property PACKAGE_PIN AB34 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 128 - MGTREFCLK0P_128 CLK2_P
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set_property PACKAGE_PIN W42 [get_ports "QSFP1_RX1_N"] ;# Bank 128 - MGTYRXN0_128
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set_property PACKAGE_PIN W41 [get_ports "QSFP1_RX1_P"] ;# Bank 128 - MGTYRXP0_128
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set_property PACKAGE_PIN V40 [get_ports "QSFP1_RX2_N"] ;# Bank 128 - MGTYRXN1_128
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set_property PACKAGE_PIN V39 [get_ports "QSFP1_RX2_P"] ;# Bank 128 - MGTYRXP1_128
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set_property PACKAGE_PIN U42 [get_ports "QSFP1_RX3_N"] ;# Bank 128 - MGTYRXN2_128
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set_property PACKAGE_PIN U41 [get_ports "QSFP1_RX3_P"] ;# Bank 128 - MGTYRXP2_128
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set_property PACKAGE_PIN T40 [get_ports "QSFP1_RX4_N"] ;# Bank 128 - MGTYRXN3_128
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set_property PACKAGE_PIN T39 [get_ports "QSFP1_RX4_P"] ;# Bank 128 - MGTYRXP3_128
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set_property PACKAGE_PIN Y35 [get_ports "QSFP1_TX1_N"] ;# Bank 128 - MGTYTXN0_128
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set_property PACKAGE_PIN Y34 [get_ports "QSFP1_TX1_P"] ;# Bank 128 - MGTYTXP0_128
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set_property PACKAGE_PIN W37 [get_ports "QSFP1_TX2_N"] ;# Bank 128 - MGTYTXN1_128
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set_property PACKAGE_PIN W36 [get_ports "QSFP1_TX2_P"] ;# Bank 128 - MGTYTXP1_128
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set_property PACKAGE_PIN V35 [get_ports "QSFP1_TX3_N"] ;# Bank 128 - MGTYTXN2_128
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set_property PACKAGE_PIN V34 [get_ports "QSFP1_TX3_P"] ;# Bank 128 - MGTYTXP2_128
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set_property PACKAGE_PIN U37 [get_ports "QSFP1_TX4_N"] ;# Bank 128 - MGTYTXN3_128
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set_property PACKAGE_PIN U36 [get_ports "QSFP1_TX4_P"] ;# Bank 128 - MGTYTXP3_128
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set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_INTL_LS"] ;#
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set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_RESETL_LS"] ;#
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18 } [get_ports "QSFP1_MODPRSL_LS"] ;#
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# set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;#
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# set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;#
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# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;#
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@@ -0,0 +1,101 @@
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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#
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## mxfe
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#
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set_property -dict {PACKAGE_PIN AR24 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L14P_T2L_N2_GC_65 FMC2_LA17_CC_P D20
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set_property -dict {PACKAGE_PIN AR25 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L14N_T2L_N3_GC_65 FMC2_LA17_CC_N D21
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set_property -dict {PACKAGE_PIN AU25 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L11P_T1U_N8_GC_65 FMC2_LA18_CC_P C22
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set_property -dict {PACKAGE_PIN AU26 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L11N_T1U_N9_GC_65 FMC2_LA18_CC_N C23
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set_property -dict {PACKAGE_PIN AU28 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L10P_T1U_N6_QBC_AD4P_65 FMC2_LA20_P G21
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set_property -dict {PACKAGE_PIN AV28 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L10N_T1U_N7_QBC_AD4N_65 FMC2_LA20_N G22
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set_property -dict {PACKAGE_PIN BB24 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L2P_T0L_N2_65 FMC2_LA21_P H25
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set_property -dict {PACKAGE_PIN BB25 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L2N_T0L_N3_65 FMC2_LA21_N H26
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set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_n ] ; ## IO_L13N_T2L_N1_GC_QBC_65 FMC2_CLK1_M2C_N G3
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set_property -dict {PACKAGE_PIN AR27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin6_p ] ; ## IO_L13P_T2L_N0_GC_QBC_65 FMC2_CLK1_M2C_P G2
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set_property -dict {PACKAGE_PIN AK11 } [get_ports clkin8_n ] ; ## MGTREFCLK0N_224 FMC2_GBTCLK1_M2C_N B21
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set_property -dict {PACKAGE_PIN AK12 } [get_ports clkin8_p ] ; ## MGTREFCLK0P_224 FMC2_GBTCLK1_M2C_P B20
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set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_n ] ; ## IO_L11N_T1U_N9_GC_64 LA00_N_CC G7
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set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports clkin10_p ] ; ## IO_L11P_T1U_N8_GC_64 LA00_P_CC G6
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set_property -dict {PACKAGE_PIN AH11 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_225 FMC2_GBTCLK0_M2C_C_N D5
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set_property -dict {PACKAGE_PIN AH12 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_225 FMC2_GBTCLK0_M2C_C_P D4
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set_property -quiet -dict {PACKAGE_PIN AP3 } [get_ports rx_data_n[2] ] ; ## MGTHRXN2_225 FPGA_SERDIN_0_N FMC2_DP2_M2C_n A7
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set_property -quiet -dict {PACKAGE_PIN AP4 } [get_ports rx_data_p[2] ] ; ## MGTHRXP2_225 FPGA_SERDIN_0_P FMC2_DP2_M2C_P A6
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set_property -quiet -dict {PACKAGE_PIN AR1 } [get_ports rx_data_n[0] ] ; ## MGTHRXN1_225 FPGA_SERDIN_1_N FMC2_DP0_M2C_n C7
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set_property -quiet -dict {PACKAGE_PIN AR2 } [get_ports rx_data_p[0] ] ; ## MGTHRXP1_225 FPGA_SERDIN_1_P FMC2_DP0_M2C_P C6
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set_property -quiet -dict {PACKAGE_PIN AU1 } [get_ports rx_data_n[7] ] ; ## MGTHRXN3_224 FPGA_SERDIN_2_N FMC2_DP7_M2C_N B13
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set_property -quiet -dict {PACKAGE_PIN AU2 } [get_ports rx_data_p[7] ] ; ## MGTHRXP3_224 FPGA_SERDIN_2_P FMC2_DP7_M2C_P B12
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set_property -quiet -dict {PACKAGE_PIN AW1 } [get_ports rx_data_n[6] ] ; ## MGTHRXN1_224 FPGA_SERDIN_3_N FMC2_DP6_M2C_N B17
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set_property -quiet -dict {PACKAGE_PIN AW2 } [get_ports rx_data_p[6] ] ; ## MGTHRXP1_224 FPGA_SERDIN_3_P FMC2_DP6_M2C_P B16
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set_property -quiet -dict {PACKAGE_PIN BA1 } [get_ports rx_data_n[5] ] ; ## MGTHRXN0_224 FPGA_SERDIN_4_N FMC2_DP5_M2C_N A19
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set_property -quiet -dict {PACKAGE_PIN BA2 } [get_ports rx_data_p[5] ] ; ## MGTHRXP0_224 FPGA_SERDIN_4_P FMC2_DP5_M2C_P A18
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set_property -quiet -dict {PACKAGE_PIN AV3 } [get_ports rx_data_n[4] ] ; ## MGTHRXN2_224 FPGA_SERDIN_5_N FMC2_DP4_M2C_N A15
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set_property -quiet -dict {PACKAGE_PIN AV4 } [get_ports rx_data_p[4] ] ; ## MGTHRXP2_224 FPGA_SERDIN_5_P FMC2_DP4_M2C_P A14
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set_property -quiet -dict {PACKAGE_PIN AT3 } [get_ports rx_data_n[3] ] ; ## MGTHRXN0_225 FPGA_SERDIN_6_N FMC2_DP3_M2C_n A11
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set_property -quiet -dict {PACKAGE_PIN AT4 } [get_ports rx_data_p[3] ] ; ## MGTHRXP0_225 FPGA_SERDIN_6_P FMC2_DP3_M2C_P A10
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||||
set_property -quiet -dict {PACKAGE_PIN AN1 } [get_ports rx_data_n[1] ] ; ## MGTHRXN3_225 FPGA_SERDIN_7_N FMC2_DP1_M2C_n A3
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set_property -quiet -dict {PACKAGE_PIN AN2 } [get_ports rx_data_p[1] ] ; ## MGTHRXP3_225 FPGA_SERDIN_7_P FMC2_DP1_M2C_P A2
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set_property -quiet -dict {PACKAGE_PIN AP7 } [get_ports tx_data_n[0] ] ; ## MGTHTXN1_225 FPGA_SERDOUT_0_N FMC2_DP0_C2M_n C3
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set_property -quiet -dict {PACKAGE_PIN AP8 } [get_ports tx_data_p[0] ] ; ## MGTHTXP1_225 FPGA_SERDOUT_0_P FMC2_DP0_C2M_P C2
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||||
set_property -quiet -dict {PACKAGE_PIN AN5 } [get_ports tx_data_n[2] ] ; ## MGTHTXN2_225 FPGA_SERDOUT_1_N FMC2_DP2_C2M_n A27
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set_property -quiet -dict {PACKAGE_PIN AN6 } [get_ports tx_data_p[2] ] ; ## MGTHTXP2_225 FPGA_SERDOUT_1_P FMC2_DP2_C2M_P A26
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set_property -quiet -dict {PACKAGE_PIN AT7 } [get_ports tx_data_n[7] ] ; ## MGTHTXN3_224 FPGA_SERDOUT_2_N FMC2_DP7_C2M_N B33
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||||
set_property -quiet -dict {PACKAGE_PIN AT8 } [get_ports tx_data_p[7] ] ; ## MGTHTXP3_224 FPGA_SERDOUT_2_P FMC2_DP7_C2M_P B32
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||||
set_property -quiet -dict {PACKAGE_PIN AW5 } [get_ports tx_data_n[6] ] ; ## MGTHTXN1_224 FPGA_SERDOUT_3_N FMC2_DP6_C2M_N B37
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set_property -quiet -dict {PACKAGE_PIN AW6 } [get_ports tx_data_p[6] ] ; ## MGTHTXP1_224 FPGA_SERDOUT_3_P FMC2_DP6_C2M_P B36
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set_property -quiet -dict {PACKAGE_PIN AM7 } [get_ports tx_data_n[1] ] ; ## MGTHTXN3_225 FPGA_SERDOUT_4_N FMC2_DP1_C2M_n A23
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||||
set_property -quiet -dict {PACKAGE_PIN AM8 } [get_ports tx_data_p[1] ] ; ## MGTHTXP3_225 FPGA_SERDOUT_4_P FMC2_DP1_C2M_P A22
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||||
set_property -quiet -dict {PACKAGE_PIN AY3 } [get_ports tx_data_n[5] ] ; ## MGTHTXN0_224 FPGA_SERDOUT_5_N FMC2_DP5_C2M_N A39
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||||
set_property -quiet -dict {PACKAGE_PIN AY4 } [get_ports tx_data_p[5] ] ; ## MGTHTXP0_224 FPGA_SERDOUT_5_P FMC2_DP5_C2M_P A38
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||||
set_property -quiet -dict {PACKAGE_PIN AU5 } [get_ports tx_data_n[4] ] ; ## MGTHTXN2_224 FPGA_SERDOUT_6_N FMC2_DP4_C2M_N A35
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||||
set_property -quiet -dict {PACKAGE_PIN AU6 } [get_ports tx_data_p[4] ] ; ## MGTHTXP2_224 FPGA_SERDOUT_6_P FMC2_DP4_C2M_P A34
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||||
set_property -quiet -dict {PACKAGE_PIN AR5 } [get_ports tx_data_n[3] ] ; ## MGTHTXN0_225 FPGA_SERDOUT_7_N FMC2_DP3_C2M_n A31
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||||
set_property -quiet -dict {PACKAGE_PIN AR6 } [get_ports tx_data_p[3] ] ; ## MGTHTXP0_225 FPGA_SERDOUT_7_P FMC2_DP3_C2M_P A30
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||||
set_property -quiet -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## IO_L7N_T1L_N1_QBC_AD13N_64 FMC2_LA02_n H8
|
||||
set_property -quiet -dict {PACKAGE_PIN AU23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## IO_L7P_T1L_N0_QBC_AD13P_64 FMC2_LA02_P H7
|
||||
set_property -quiet -dict {PACKAGE_PIN AW19 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## IO_L9N_T1L_N5_AD12N_64 FMC2_LA03_n G10
|
||||
set_property -quiet -dict {PACKAGE_PIN AW20 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## IO_L9P_T1L_N4_AD12P_64 FMC2_LA03_P G9
|
||||
set_property -quiet -dict {PACKAGE_PIN AV19 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## IO_L12N_T1U_N11_GC_64 FMC2_LA01_CC_n D9
|
||||
set_property -quiet -dict {PACKAGE_PIN AU20 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## IO_L12P_T1U_N10_GC_64 FMC2_LA01_CC_P D8
|
||||
set_property -quiet -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## IO_L2N_T0L_N3_64 FMC2_LA06_n C11
|
||||
set_property -quiet -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## IO_L2P_T0L_N2_64 FMC2_LA06_P C10
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L20P_T3L_N2_AD1P_64 FMC2_LA15_P H19
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L20N_T3L_N3_AD1N_64 FMC2_LA15_N H20
|
||||
set_property -dict {PACKAGE_PIN AV27 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L9P_T1L_N4_AD12P_65 FMC2_LA19_P H22
|
||||
set_property -dict {PACKAGE_PIN AW27 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L9N_T1L_N5_AD12N_65 FMC2_LA19_N H23
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L23P_T3U_N8_64 FMC2_LA13_P D17
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L23N_T3U_N9_64 FMC2_LA13_N D18
|
||||
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_64 FMC2_LA14_P C18
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_64 FMC2_LA14_N C19
|
||||
set_property -dict {PACKAGE_PIN AL22 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L21P_T3L_N4_AD8P_64 FMC2_LA16_P G18
|
||||
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L21N_T3L_N5_AD8N_64 FMC2_LA16_N G19
|
||||
set_property -dict {PACKAGE_PIN BB26 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_65 FMC2_LA22_N G25
|
||||
set_property -dict {PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L22N_T3U_N7_DBC_AD0N_64 FMC2_LA11_N H17
|
||||
set_property -dict {PACKAGE_PIN BA21 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L3N_T0L_N5_AD15N_64 FMC2_LA07_N H14
|
||||
set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L5P_T0U_N8_AD14P_64 FMC2_LA08_P G12
|
||||
set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L5N_T0U_N9_AD14N_64 FMC2_LA08_N G13
|
||||
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L3P_T0L_N4_AD15P_64 FMC2_LA07_P H13
|
||||
set_property -dict {PACKAGE_PIN BA18 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L6P_T0U_N10_AD6P_64 FMC2_LA10_P C14
|
||||
set_property -dict {PACKAGE_PIN BB18 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L6N_T0U_N11_AD6N_64 FMC2_LA10_N C15
|
||||
set_property -dict {PACKAGE_PIN AY19 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L10P_T1U_N6_QBC_AD4P_64 FMC2_LA05_P D11
|
||||
set_property -dict {PACKAGE_PIN AY18 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L10N_T1U_N7_QBC_AD4N_64 FMC2_LA05_N D12
|
||||
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L16P_T2U_N6_QBC_AD3P_64 FMC2_LA04_P H10
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L16N_T2U_N7_QBC_AD3N_64 FMC2_LA04_N H11
|
||||
set_property -dict {PACKAGE_PIN BA23 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L1P_T0L_N0_DBC_64 FMC2_LA12_P G15
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L22P_T3U_N6_DBC_AD0P_64 FMC2_LA11_P H16
|
||||
set_property -dict {PACKAGE_PIN BB23 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L1N_T0L_N1_DBC_64 FMC2_LA12_N G16
|
||||
set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_64 FMC2_CLK0_M2C_n H5
|
||||
set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE } [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_64 FMC2_CLK0_M2C_P H4
|
||||
set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_64 FMC2_LA09_P D14
|
||||
set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_64 FMC2_LA09_N D15
|
||||
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports pll_scl ] ; ## IO_L12N_AD8N_91
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports pll_sda ] ; ## IO_L12N_AD8P_91
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# Primary clock definitions
|
||||
create_clock -name refclk -period 4.0 [get_ports fpga_refclk_in_p]
|
||||
|
||||
# device clock
|
||||
create_clock -name tx_device_clk -period 4.0 [get_ports clkin6_p]
|
||||
create_clock -name rx_device_clk -period 4.0 [get_ports clkin10_p]
|
||||
create_clock -name clkin8 -period 2.0 [get_ports clkin8_p]
|
||||
##create_clock -name sysref2 -period 4.0 [get_ports sysref2_p] # not a clock
|
||||
|
||||
create_clock -period 2.640 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
|
||||
create_clock -period 2.640 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
|
||||
create_clock -period 2.640 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
|
||||
create_clock -period 2.640 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
|
||||
|
||||
|
||||
# Constraint SYSREFs
|
||||
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||
[get_ports {sysref2_*}]
|
||||
|
||||
# For transceiver output clocks use reference clock divided by two
|
||||
# This will help autoderive the clocks correcly
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]
|
||||
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
|
||||
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
|
||||
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]
|
||||
|
||||
# Define SPI clock
|
||||
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]
|
||||
create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks refclk]
|
||||
set_false_path -from [get_clocks refclk] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks clkin8]
|
||||
set_false_path -from [get_clocks clkin8] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks rx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_1]
|
||||
set_false_path -from [get_clocks clk_pl_1] -to [get_clocks clk_pl_0]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks clk_pl_0]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
|
||||
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
|
||||
|
||||
set_false_path -from [get_clocks i_qsfp_intfc_v1_0/i_bufgce_div/O] -to [get_clocks -of_objects [get_pins QSFP2_SI570_CLOCK_P]]
|
||||
set_false_path -from [get_clocks i_qsfp_intfc_v1_0/i_bufgce_div/O] -to [get_clocks -of_objects [get_pins QSFP3_SI570_CLOCK_P]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
set_false_path -from [get_clocks clkin8] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks QSFP2_SI570_CLOCK_P]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks QSFP3_SI570_CLOCK_P]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks tx_device_clk]
|
||||
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins i_qsfp_intfc_v1_0/i_bufgce_div/O]] -to [get_clocks clkin8]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+5904
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
package global_types is
|
||||
type data_vc1_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type data_vc2_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type mask_vcx_type is array (127 downto 0) of std_logic_vector(7 downto 0);
|
||||
type addr_si5341_type is array (511 downto 0) of std_logic_vector(15 downto 0);
|
||||
type data_si5341_type is array (511 downto 0) of std_logic_vector(7 downto 0);
|
||||
end global_types;
|
||||
package body global_types is
|
||||
end global_types;
|
||||
@@ -0,0 +1,305 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c is
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coafficien (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end entity i2c;
|
||||
|
||||
architecture translated of i2c is
|
||||
|
||||
component IOBUF
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
IO : inout std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component OBUFT
|
||||
port
|
||||
(
|
||||
O : out std_ulogic;
|
||||
I : in std_ulogic;
|
||||
T : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component i2c_st
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end component;
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
function length_ct (int_length : integer) return positive is
|
||||
variable conv_length : std_logic_vector(9 downto 0);
|
||||
variable index : positive:= 1;
|
||||
begin
|
||||
conv_length := CONV_STD_LOGIC_VECTOR(int_length, 10);
|
||||
for i in 9 downto 1 loop
|
||||
index:= i;
|
||||
exit when conv_length(i) = '1';
|
||||
end loop;
|
||||
return index;
|
||||
end length_ct;
|
||||
|
||||
|
||||
|
||||
|
||||
signal cntr : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal cntr_length : std_logic_vector(length_ct(count_div) downto 0);
|
||||
signal scl_tick : std_logic;
|
||||
signal wrd_addr : std_logic_vector(7 downto 0);
|
||||
signal wrd_dat : std_logic_vector(7 downto 0);
|
||||
signal dev_addr_int : std_logic_vector(6 downto 0);
|
||||
signal ENAPH : std_logic;
|
||||
signal scl_cnt_en : std_logic;
|
||||
signal i2c_go : std_logic;
|
||||
signal sda_in : std_logic;
|
||||
signal sda_o : std_logic;
|
||||
signal scl_o : std_logic;
|
||||
signal wr_l_int : std_logic;
|
||||
signal port_switch : std_logic:= '0';
|
||||
signal sda_o_spd : std_logic;
|
||||
signal scl_o_spd : std_logic;
|
||||
signal GND : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
GND <= '0';
|
||||
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- CLOCK DIVIDER SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
|
||||
cntr_length <= CONV_STD_LOGIC_VECTOR(count_div, (length_ct(count_div)+1));
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr <= (others => '0') after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (scl_cnt_en = '1') then
|
||||
cntr <= cntr + 1 after 1 * sim_timescale;
|
||||
else
|
||||
cntr <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK,RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (cntr = cntr_length) then
|
||||
scl_tick <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
scl_tick <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- ADDRESS REGISTERS SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then wrd_addr <= ADDR_IN after 1 * sim_timescale;
|
||||
dev_addr_int <= DEV_ADDR after 1 * sim_timescale;
|
||||
wr_l_int <= WR_OP after 1 * sim_timescale;
|
||||
wrd_dat <= DAT_IN after 1 * sim_timescale;
|
||||
ENAPH <= AP_EN after 1 * sim_timescale;
|
||||
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK)
|
||||
begin
|
||||
if (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then port_switch <= (DEV_ADDR(3) and not DEV_ADDR(2) and DEV_ADDR(1) and not DEV_ADDR(0)) after 1 * sim_timescale; -- "1010" (SPD)
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
-- send ack right back
|
||||
|
||||
if (RST = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then
|
||||
i2c_go <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (scl_cnt_en = '1') then
|
||||
i2c_go <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if WR_EN = '1'
|
||||
then ACK_L <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
ACK_L <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
---------------------------------------------------------------------------------------------------
|
||||
-- I2C STATE MACHINE SECTION:
|
||||
---------------------------------------------------------------------------------------------------
|
||||
MAIN_FSM : i2c_st
|
||||
port map(
|
||||
WRD_ADD => wrd_addr,
|
||||
WRD_DAT => wrd_dat,
|
||||
DEV_ADDR => dev_addr_int,
|
||||
CONTINUE => CONTINUE,
|
||||
ENAPH => ENAPH,
|
||||
WR_L => wr_l_int,
|
||||
RST => RST,
|
||||
CLK => CLK,
|
||||
SCL_TICK => scl_tick,
|
||||
I2C_GO => i2c_go,
|
||||
SDA_PIN => sda_in,
|
||||
|
||||
I2C_RDATA => I2C_RDATA,
|
||||
SDA => sda_o,
|
||||
SCL => scl_o,
|
||||
SCL_CNT_EN => scl_cnt_en,
|
||||
I2C_RDY => I2C_RDY,
|
||||
I2C_ACT => I2C_ACT,
|
||||
ACK_ERR => ACK_ERR
|
||||
);
|
||||
|
||||
|
||||
sda_o_spd <= sda_o;
|
||||
scl_o_spd <= scl_o;
|
||||
|
||||
--SDA_BUF: IOBUF
|
||||
-- port map
|
||||
-- (
|
||||
-- O => sda_in,
|
||||
-- IO => SDA,
|
||||
-- I => GND,
|
||||
-- T => sda_o_spd
|
||||
-- );
|
||||
|
||||
|
||||
sda_in <= I_SDA_I;
|
||||
O_SDA_O <= GND;
|
||||
O_SDA_T <= sda_o_spd;
|
||||
|
||||
--SCL_BUF: OBUFT
|
||||
-- port map
|
||||
-- (
|
||||
-- O => SCL,
|
||||
-- I => GND,
|
||||
-- T => scl_o_spd
|
||||
-- );
|
||||
|
||||
-- scl_in <= I_SCL_I
|
||||
O_SCL_O <= GND;
|
||||
O_SCL_T <= scl_o_spd;
|
||||
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,435 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: I2C Master Controller Top level
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project:
|
||||
-- File name: i2c_st.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Modelsim
|
||||
-- Synthesis: Xilinx ISE
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 0.65
|
||||
-- Modification date: 03/05/2003
|
||||
-- Limitation:
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
|
||||
entity i2c_st is
|
||||
port (
|
||||
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
|
||||
WRD_DAT : in std_logic_vector(7 downto 0);
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0);
|
||||
CONTINUE : in std_logic;
|
||||
ENAPH : in std_logic; -- Enable Address Phase During Write
|
||||
WR_L : in std_logic;
|
||||
RST : in std_logic; -- reset
|
||||
CLK : in std_logic; -- mpu CLK
|
||||
SCL_TICK : in std_logic; -- 5 usec CLK tick
|
||||
I2C_GO : in std_logic; -- start i2c cycle
|
||||
SDA_PIN : in std_logic; -- i2c data muxed input
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
SDA : out std_logic; -- i2c data
|
||||
SCL : out std_logic; -- i2c CLK
|
||||
SCL_CNT_EN : out std_logic; -- SCL cntr enable
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- ack error
|
||||
);
|
||||
end entity i2c_st;
|
||||
|
||||
architecture translated of i2c_st is
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
---------------------------------------------------------------------
|
||||
type st_type is (idle, en_clk, start1, dev_id1, ack_id1, w_add, w_dat, ack_wr, ack_add, wait1,
|
||||
dis_clk1, start2, dev_id2, ack_id2, data, ack_rd, stop1, ack_rd_mult);
|
||||
|
||||
signal i2c_state : st_type:= idle;
|
||||
signal bit_cntr : std_logic_vector(2 downto 0);
|
||||
signal scl_en : std_logic;
|
||||
signal en_cntr : std_logic;
|
||||
signal cntr_done : std_logic;
|
||||
signal sda_int : std_logic;
|
||||
signal scl_int : std_logic;
|
||||
signal scl_cnt_en_int : std_logic;
|
||||
signal i2c_rdy_int : std_logic;
|
||||
signal i2c_act_int : std_logic;
|
||||
signal i2c_rdata_int : std_logic_vector(7 downto 0);
|
||||
signal ack_err_int : std_logic;
|
||||
signal id_sel : std_logic_vector(7 downto 0);
|
||||
signal id_code_op : std_logic_vector(7 downto 0);
|
||||
|
||||
attribute syn_useioff : boolean;
|
||||
attribute syn_useioff of translated : architecture is true;
|
||||
---------------------------------------------------------------------
|
||||
|
||||
|
||||
begin
|
||||
|
||||
id_sel <= DEV_ADDR & '0';
|
||||
id_code_op <= DEV_ADDR & '1';
|
||||
|
||||
|
||||
|
||||
SRL16E_inst : SRL16E
|
||||
generic map (
|
||||
INIT => X"1111")
|
||||
port map (
|
||||
Q => SDA, -- SRL data output
|
||||
A0 => '1', -- Select[0] input
|
||||
A1 => '1', -- Select[1] input
|
||||
A2 => '1', -- Select[2] input
|
||||
A3 => '1', -- Select[3] input
|
||||
CE => '1', -- Clock enable input
|
||||
CLK => CLK, -- Clock input
|
||||
D => sda_int -- SRL data input
|
||||
);
|
||||
-- SDA <= sda_int;
|
||||
SCL <= scl_int;
|
||||
SCL_CNT_EN <= scl_cnt_en_int;
|
||||
I2C_RDY <= i2c_rdy_int;
|
||||
I2C_ACT <= i2c_act_int;
|
||||
I2C_RDATA <= i2c_rdata_int;
|
||||
ACK_ERR <= ack_err_int;
|
||||
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- state machine
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
case i2c_state is
|
||||
when idle =>
|
||||
if (I2C_GO = '1') then
|
||||
i2c_state <= en_clk after 1 * sim_timescale;
|
||||
else i2c_state <= idle;
|
||||
end if;
|
||||
when en_clk =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start1 after 1 * sim_timescale;
|
||||
else i2c_state <= en_clk;
|
||||
end if;
|
||||
when start1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= start1;
|
||||
end if;
|
||||
when dev_id1 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id1 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id1;
|
||||
end if;
|
||||
when ack_id1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
if ENAPH = '1' then
|
||||
i2c_state <= w_add after 1 * sim_timescale;
|
||||
else
|
||||
i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end if;
|
||||
else i2c_state <= ack_id1;
|
||||
end if;
|
||||
when w_add =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_add after 1 * sim_timescale;
|
||||
else i2c_state <= w_add;
|
||||
end if;
|
||||
when ack_add =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
case WR_L is
|
||||
when '1' => i2c_state <= dis_clk1 after 1 * sim_timescale;
|
||||
when others => i2c_state <= w_dat after 1 * sim_timescale;
|
||||
end case;
|
||||
else i2c_state <= ack_add;
|
||||
end if;
|
||||
when w_dat =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_wr after 1 * sim_timescale;
|
||||
else i2c_state <= w_dat;
|
||||
end if;
|
||||
when ack_wr =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_wr;
|
||||
end if;
|
||||
when dis_clk1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= wait1 after 1 * sim_timescale;
|
||||
else i2c_state <= dis_clk1;
|
||||
end if;
|
||||
when wait1 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= start2 after 1 * sim_timescale;
|
||||
else i2c_state <= wait1;
|
||||
end if;
|
||||
when start2 =>
|
||||
if (SCL_TICK = '1') then
|
||||
i2c_state <= dev_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= start2;
|
||||
end if;
|
||||
when dev_id2 =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
i2c_state <= ack_id2 after 1 * sim_timescale;
|
||||
else i2c_state <= dev_id2;
|
||||
end if;
|
||||
when ack_id2 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_id2;
|
||||
end if;
|
||||
when data =>
|
||||
if ((cntr_done and SCL_TICK) = '1') then
|
||||
case CONTINUE is
|
||||
when '1' => i2c_state <= ack_rd_mult after 1 * sim_timescale; --
|
||||
when others => i2c_state <= ack_rd after 1 * sim_timescale;--
|
||||
end case;
|
||||
else i2c_state <= data;
|
||||
end if;
|
||||
when ack_rd =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= stop1 after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd;
|
||||
end if;
|
||||
when ack_rd_mult =>
|
||||
if ((SCL_TICK and scl_int) = '1')
|
||||
then i2c_state <= data after 1 * sim_timescale;
|
||||
else i2c_state <= ack_rd_mult;
|
||||
end if;
|
||||
when stop1 =>
|
||||
if ((SCL_TICK and scl_int) = '1') then
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
else i2c_state <= stop1;
|
||||
end if;
|
||||
when others =>
|
||||
i2c_state <= idle after 1 * sim_timescale;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- bit counter
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
bit_cntr <= "111" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((en_cntr and scl_int) and SCL_TICK) = '1') then
|
||||
bit_cntr <= bit_cntr - "001" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((bit_cntr = "000") and (scl_int = '1')) then
|
||||
cntr_done <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
cntr_done <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
---------------------------------------------------------------------
|
||||
-- SCL generation
|
||||
-- enable CLK divider
|
||||
|
||||
if (RST = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = dev_id1) or (i2c_state = w_add) or (i2c_state =
|
||||
dev_id2) or (i2c_state = data) or (i2c_state = w_dat)) then
|
||||
en_cntr <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (cntr_done = '1') then
|
||||
en_cntr <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = en_clk) then
|
||||
scl_cnt_en_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = idle) then
|
||||
scl_cnt_en_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- enables tick divider
|
||||
|
||||
--process (CLK, RST)
|
||||
--begin
|
||||
-- if (RST = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- elsif (CLK'event and CLK = '1') then
|
||||
-- if (i2c_state = start1) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = dis_clk1) and (SCL_TICK = '1') then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = start2) then
|
||||
-- scl_en <= '1' after 1 * sim_timescale;
|
||||
-- else
|
||||
-- if (i2c_state = stop1) and (scl_int = '1')
|
||||
-- then
|
||||
-- scl_en <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = start1) or (i2c_state = start2) then
|
||||
scl_en <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if ((i2c_state = dis_clk1) and (SCL_TICK = '1')) or ((i2c_state = stop1) and (scl_int = '1')) then
|
||||
scl_en <= '0' after 1 * sim_timescale;
|
||||
else null;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- tick divider
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
scl_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((scl_en and SCL_TICK) = '1') then
|
||||
scl_int <= not scl_int after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if ((i2c_state = start1) or (i2c_state = start2) or (i2c_state = stop1) or (i2c_state = ack_rd_mult))
|
||||
then sda_int <= '0' after 1 * sim_timescale;
|
||||
else
|
||||
if (i2c_state = dev_id1) then
|
||||
sda_int <= id_sel(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = dev_id2) then
|
||||
sda_int <= id_code_op(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_add) then
|
||||
sda_int <= WRD_ADD(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
elsif (i2c_state = w_dat) then
|
||||
sda_int <= WRD_DAT(conv_integer(bit_cntr)) after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
sda_int <= '1' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (i2c_state = data) and (scl_int = '1') then
|
||||
i2c_rdata_int(conv_integer(bit_cntr)) <= SDA_PIN after 1 *
|
||||
sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = stop1) and (scl_int = '1')) or
|
||||
((i2c_state = ack_rd_mult) and (scl_int and not SDA_PIN and WR_L) = '1')) then
|
||||
i2c_rdy_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
-- if (I2C_GO = '1') then
|
||||
i2c_rdy_int <= '0' after 1 * sim_timescale;
|
||||
-- end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
if (((i2c_state = ack_id1) or (i2c_state = ack_add) or (i2c_state = ack_id2) or (i2c_state = ack_rd_mult) or (i2c_state = ack_wr))
|
||||
and (scl_int and SDA_PIN) = '1') then
|
||||
ack_err_int <= '1' after 1 * sim_timescale;
|
||||
else
|
||||
if (I2C_GO = '1') then
|
||||
ack_err_int <= '0' after 1 * sim_timescale;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i2c_act_int <= '0' when i2c_state = idle else '1';
|
||||
|
||||
end architecture translated;
|
||||
@@ -0,0 +1,167 @@
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity si5332_wrapper is
|
||||
port(
|
||||
clk_100_in : in std_logic;
|
||||
clk_100_areset_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic;
|
||||
|
||||
qsfp2_clk_in : in std_logic;
|
||||
qsfp3_clk_in : in std_logic
|
||||
|
||||
);
|
||||
end entity si5332_wrapper;
|
||||
|
||||
architecture imp of si5332_wrapper is
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
signal man_clk_gen_en : std_logic := '0';
|
||||
signal man_clk_gen_cfg_reset : std_logic := '0';
|
||||
|
||||
|
||||
signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp3_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp3_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp3_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
-----------------------------------
|
||||
i_si5341_clk_conf : entity work.si5341_clk_configurator
|
||||
port map (
|
||||
sys_clk100_in => clk_100_in,
|
||||
tick_1ms_in => tick_1ms,
|
||||
|
||||
sda_in => sda_in,
|
||||
sda_out => sda_out,
|
||||
sda_t_out => sda_t_out,
|
||||
|
||||
scl_in => scl_in,
|
||||
scl_out => scl_out,
|
||||
scl_t_out => scl_t_out,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
man_clk_gen_en_in => man_clk_gen_en,
|
||||
man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_100_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_100_areset_in
|
||||
);
|
||||
|
||||
|
||||
-- i_vio_3 : entity work.vio_3
|
||||
-- port map (
|
||||
-- clk => clk_100_in,
|
||||
-- probe_in0(0) => i2c_mux_access_ok, -- 1
|
||||
-- probe_in1(0) => si5341_access_ok, -- 1
|
||||
-- probe_in2(0) => si5341_config_done, -- 1
|
||||
-- probe_in3(0) => si5341_config_error, -- 1
|
||||
-- probe_in4 => clk_100_freq_r, -- 32
|
||||
-- probe_in5 => clk_100_cnt_r, -- 32
|
||||
-- probe_in6 => qsfp2_freq_r, -- 32
|
||||
-- probe_in7 => qsfp2_cnt_r, -- 32
|
||||
-- probe_in8 => qsfp3_freq_r, -- 32
|
||||
-- probe_in9 => qsfp3_cnt_r, -- 32
|
||||
--
|
||||
-- probe_out0(0) => man_clk_gen_en, -- 1
|
||||
-- probe_out1(0) => man_clk_gen_cfg_reset -- 1
|
||||
-- );
|
||||
|
||||
process(clk_100_in)
|
||||
begin
|
||||
if (rising_edge(clk_100_in)) then
|
||||
clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_100_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_100_freq_r <= clk_100_cnt_r;
|
||||
clk_100_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_100_cnt_r <= clk_100_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp2_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp2_clk_in)) then
|
||||
qsfp2_tick_1ms_r <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp2_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp2_freq_r <= qsfp2_cnt_r;
|
||||
qsfp2_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp2_cnt_r <= qsfp2_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp3_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp3_clk_in)) then
|
||||
qsfp3_tick_1ms_r <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp3_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp3_freq_r <= qsfp3_cnt_r;
|
||||
qsfp3_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp3_cnt_r <= qsfp3_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,183 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity si5341_clk_configurator is
|
||||
port (
|
||||
sys_clk100_in : in std_logic;
|
||||
tick_1ms_in : in std_logic;
|
||||
|
||||
sda_in : in std_logic;
|
||||
sda_out : out std_logic;
|
||||
sda_t_out : out std_logic;
|
||||
|
||||
scl_in : in std_logic;
|
||||
scl_out : out std_logic;
|
||||
scl_t_out : out std_logic;
|
||||
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
man_clk_gen_en_in : in std_logic;
|
||||
man_clk_gen_cfg_reset_in : in std_logic;
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity si5341_clk_configurator;
|
||||
|
||||
architecture imp of si5341_clk_configurator is
|
||||
|
||||
signal clk_gen_cfg_reset_d : std_logic := '0';
|
||||
signal clk_gen_cfg_reset : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
type fsm_state_sm is (idle_st, si5341_reset_lo_st, si5341_reset_hi_st, si5341_config_st, si5341_config_wait_st,
|
||||
si5341_config_check_st, done_st);
|
||||
signal state_d : fsm_state_sm := idle_st;
|
||||
signal tick_cnt_d : integer;
|
||||
|
||||
signal state_test_r : std_logic_vector(2 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
clk_gen_cfg_reset <= man_clk_gen_cfg_reset_in when man_clk_gen_en_in = '1' else clk_gen_cfg_reset_d;
|
||||
|
||||
i_clk_gen_cfg : entity work.clk_gen_cfg
|
||||
generic map (
|
||||
simulation_mode => '0'
|
||||
)
|
||||
port map (
|
||||
sys_clk_in => sys_clk100_in,
|
||||
reset_in => clk_gen_cfg_reset,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
I_SDA_I => sda_in,
|
||||
O_SDA_O => sda_out,
|
||||
O_SDA_T => sda_t_out,
|
||||
|
||||
I_SCL_I => scl_in,
|
||||
O_SCL_O => scl_out,
|
||||
O_SCL_T => scl_t_out
|
||||
);
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok;
|
||||
si5341_access_ok_out <= si5341_access_ok;
|
||||
si5341_config_done_out <= si5341_config_done;
|
||||
si5341_config_error_out <= si5341_config_error;
|
||||
|
||||
process(state_d)
|
||||
begin
|
||||
case state_d is
|
||||
when idle_st => state_test_r <= "000";
|
||||
when si5341_reset_lo_st => state_test_r <= "001";
|
||||
when si5341_reset_hi_st => state_test_r <= "010";
|
||||
when si5341_config_st => state_test_r <= "011";
|
||||
when si5341_config_wait_st => state_test_r <= "100";
|
||||
when si5341_config_check_st => state_test_r <= "101";
|
||||
when done_st => state_test_r <= "110";
|
||||
when others => state_test_r <= "111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_0 : entity work.ila_0
|
||||
-- port map (
|
||||
-- clk => sys_clk100_in,
|
||||
-- probe0 => state_test_r, --3
|
||||
-- probe1(0) => i2c_mux_access_ok, --1
|
||||
-- probe2(0) => si5341_access_ok, --1
|
||||
-- probe3(0) => si5341_config_done, --1
|
||||
-- probe4(0) => si5341_config_error, --1
|
||||
-- probe5(0) => clk_gen_cfg_reset, --1
|
||||
-- probe7(0) => clk_gen_cfg_reset_d, --1
|
||||
-- probe9(0) => tick_1ms_in --1
|
||||
-- );
|
||||
|
||||
process(sys_clk100_in)
|
||||
begin
|
||||
if (rising_edge(sys_clk100_in)) then
|
||||
if (reset_in = '1') then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 500;
|
||||
state_d <= idle_st;
|
||||
else
|
||||
if (tick_1ms_in = '1') then
|
||||
tick_cnt_d <= tick_cnt_d - 1;
|
||||
end if;
|
||||
|
||||
case state_d is
|
||||
when idle_st => --0
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_reset_lo_st;
|
||||
else
|
||||
state_d <= idle_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_lo_st => --1
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 100;
|
||||
state_d <= si5341_reset_hi_st;
|
||||
else
|
||||
state_d <= si5341_reset_lo_st;
|
||||
end if;
|
||||
|
||||
when si5341_reset_hi_st => --2
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '1';
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= si5341_config_st;
|
||||
else
|
||||
state_d <= si5341_reset_hi_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_st => --3
|
||||
if (tick_cnt_d = 0) then
|
||||
clk_gen_cfg_reset_d <= '0';
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_wait_st;
|
||||
else
|
||||
state_d <= si5341_config_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_wait_st => --4
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 1000;
|
||||
state_d <= si5341_config_check_st;
|
||||
else
|
||||
state_d <= si5341_config_wait_st;
|
||||
end if;
|
||||
|
||||
when si5341_config_check_st => --5
|
||||
if (tick_cnt_d = 0) then
|
||||
tick_cnt_d <= 250;
|
||||
state_d <= idle_st;
|
||||
elsif (i2c_mux_access_ok = '1' and si5341_access_ok = '1' and si5341_config_done = '1' and si5341_config_error = '0') then
|
||||
state_d <= done_st;
|
||||
else
|
||||
state_d <= si5341_config_check_st;
|
||||
end if;
|
||||
|
||||
when done_st => --6
|
||||
state_d <= done_st;
|
||||
|
||||
when others => --7
|
||||
state_d <= idle_st;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,380 @@
|
||||
--345678901234567890123456789012345678901234567890123456789012345678901234567890
|
||||
-- 1 2 3 4 5 6 7
|
||||
-- Title: Silicon Lab Si5341 Clock Generator Configuration Design
|
||||
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
|
||||
-- Company: For HiTechGlobal
|
||||
-- Project: HTG-ZRF8
|
||||
-- File name: si5341_gen_cfg.vhd
|
||||
--------------------------------------------------------------------------------
|
||||
-- Purpose: Configures Si5341 Clock Generators on Start-up
|
||||
--------------------------------------------------------------------------------
|
||||
-- Simulator: Xilinx Vivado
|
||||
-- Synthesis: Xilinx Vivado
|
||||
--------------------------------------------------------------------------------
|
||||
-- Revision: 1.00
|
||||
-- Modification date: 20/10/2018
|
||||
-- Limitation: Design requires 12.5MHz input clock.
|
||||
-- Change COUNT_DIV value for other bus frequency.
|
||||
-- Notes:
|
||||
--------------------------------------------------------------------------------
|
||||
-- Modifications List:
|
||||
--
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_arith.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_signed.all;
|
||||
USE ieee.numeric_std.all;
|
||||
use IEEE.std_logic_misc.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
use work.global_types.all;
|
||||
|
||||
entity si5341_gen_cfg is
|
||||
generic (
|
||||
COUNT_DIV : integer range 0 to 1023 := 512; -- sysclk divide coefficient (Valid Values: 2 to 1023)
|
||||
SIZ5341 : integer range 0 to 511 := 511; -- Real Address/Data Array Size (Valid Values: 1 to 511)
|
||||
ADR5341 : addr_si5341_type := (others => (others => '0'));
|
||||
DAT5341 : data_si5341_type := (others => (others => '0'));
|
||||
simulation_mode : std_logic := '0'
|
||||
);
|
||||
port (
|
||||
-- System signals
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
-- External Operation Control
|
||||
START : in std_logic; -- Run Start-Up Clock Genrators Configuration
|
||||
|
||||
-- Status Output
|
||||
i2c_mux_access_ok_out : out std_logic;
|
||||
si5341_access_ok_out : out std_logic;
|
||||
si5341_config_done_out : out std_logic;
|
||||
si5341_config_error_out : out std_logic;
|
||||
|
||||
-- I2C Bus
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic
|
||||
);
|
||||
end entity si5341_gen_cfg;
|
||||
|
||||
architecture si5341_gen_cfg_arch of si5341_gen_cfg is
|
||||
|
||||
component i2c
|
||||
generic (
|
||||
count_div : integer range 0 to 1023:= 512 -- sysclk divide coefficient (2 to 1023 max)
|
||||
);
|
||||
port (
|
||||
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
|
||||
DAT_IN : in std_logic_vector(7 downto 0); -- write data
|
||||
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
|
||||
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
|
||||
AP_EN : in std_logic; -- Enable Address Phase During Write
|
||||
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK : in std_logic; -- main clock
|
||||
RST : in std_logic; -- system reset
|
||||
|
||||
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
|
||||
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
|
||||
-- SDA : inout std_logic; -- i2c data
|
||||
-- SCL : out std_logic; -- i2c CLK
|
||||
|
||||
I_SDA_I : in std_logic;
|
||||
O_SDA_O : out std_logic;
|
||||
O_SDA_T : out std_logic;
|
||||
|
||||
I_SCL_I : in std_logic;
|
||||
O_SCL_O : out std_logic;
|
||||
O_SCL_T : out std_logic;
|
||||
|
||||
I2C_RDY : out std_logic; -- i2c ready
|
||||
I2C_ACT : out std_logic; -- i2c cycle active
|
||||
ACK_ERR : out std_logic -- i2c(ack) error
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
constant sim_timescale : time := 1 ns;
|
||||
|
||||
|
||||
type fsm_state is (IDLE, SI5341_NEW, SI5341_NEW_WR, SI5341_NEW_INC, FINISH, ERROR);
|
||||
|
||||
signal state_r : fsm_state := IDLE;
|
||||
|
||||
signal i2c_rdata : std_logic_vector(7 downto 0);
|
||||
|
||||
signal si5341_adr_arr : addr_si5341_type := ADR5341;
|
||||
signal si5341_dat_arr : data_si5341_type := DAT5341;
|
||||
|
||||
signal dev_addr : std_logic_vector(6 downto 0);
|
||||
|
||||
signal new_adr : std_logic_vector(7 downto 0);
|
||||
signal cur_addr : integer range 0 to 511 := 0;
|
||||
signal inc_adr : std_logic;
|
||||
signal new_da : std_logic_vector(6 downto 0):= (others => '0');
|
||||
signal addr : std_logic_vector(8 downto 0);
|
||||
signal new_dat : std_logic_vector(7 downto 0);
|
||||
signal new_wr : std_logic;
|
||||
signal new_op : std_logic;
|
||||
signal new_apen : std_logic := '0';
|
||||
signal ap_en : std_logic;
|
||||
|
||||
signal dat_in : std_logic_vector(7 downto 0);
|
||||
|
||||
signal word_addr : std_logic_vector(7 downto 0);
|
||||
signal we_i2c : std_logic;
|
||||
signal wr_i2c : std_logic;
|
||||
|
||||
signal ack_err : std_logic;
|
||||
signal i2c_rdy : std_logic;
|
||||
signal i2c_act : std_logic;
|
||||
signal CONTINUE : std_logic;
|
||||
signal ACK_L : std_logic;
|
||||
|
||||
signal i2c_busy : std_logic;
|
||||
signal i2c_act_fall : std_logic := '0';
|
||||
signal i2c_act_rg : std_logic := '0';
|
||||
|
||||
signal addr_itg : integer range 0 to 511;
|
||||
signal si5341_size : integer range 0 to 511;
|
||||
signal si5341_data : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr : std_logic_vector(15 downto 0);
|
||||
signal si5341_addr_h : std_logic_vector(7 downto 0);
|
||||
signal si5341_addr_l : std_logic_vector(7 downto 0);
|
||||
|
||||
signal state_test_r : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
signal i2c_mux_access_ok_r : std_logic := '0';
|
||||
signal si5341_access_ok_r : std_logic := '0';
|
||||
signal si5341_config_done_r : std_logic := '0';
|
||||
signal si5341_config_error_r : std_logic := '0';
|
||||
|
||||
|
||||
begin
|
||||
|
||||
addr_itg <= CONV_INTEGER(cur_addr);
|
||||
si5341_addr <= si5341_adr_arr(addr_itg);
|
||||
si5341_data <= si5341_dat_arr(addr_itg);
|
||||
si5341_size <= SIZ5341;
|
||||
si5341_addr_h <= si5341_addr(15 downto 8); -- Page Number
|
||||
si5341_addr_l <= si5341_addr( 7 downto 0); -- Byte Address
|
||||
|
||||
i2c_mux_access_ok_out <= i2c_mux_access_ok_r;
|
||||
si5341_access_ok_out <= si5341_access_ok_r;
|
||||
si5341_config_done_out <= si5341_config_done_r;
|
||||
si5341_config_error_out <= si5341_config_error_r;
|
||||
|
||||
process(state_r)
|
||||
begin
|
||||
case state_r is
|
||||
when IDLE => state_test_r <= "0000";
|
||||
when SI5341_NEW => state_test_r <= "0011";
|
||||
when SI5341_NEW_WR => state_test_r <= "0101";
|
||||
when SI5341_NEW_INC => state_test_r <= "0110";
|
||||
when FINISH => state_test_r <= "1000";
|
||||
when ERROR => state_test_r <= "1001";
|
||||
when others => state_test_r <= "1111";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- i_ila_1 : entity work.ila_1
|
||||
-- port map (
|
||||
-- clk => CLK,
|
||||
-- probe0 => state_test_r, --4
|
||||
-- probe1 => new_da, --7
|
||||
-- probe2 => new_dat, --8
|
||||
-- probe3(0) => new_wr, --1
|
||||
-- probe4(0) => i2c_busy, --1
|
||||
-- probe7(0) => i2c_rdy, --1
|
||||
-- probe8(0) => i2c_act, --1
|
||||
-- probe9(0) => ack_err, --1
|
||||
-- probe10(0) => START, --1
|
||||
-- probe13 => new_adr -- 8
|
||||
-- );
|
||||
|
||||
---------------------------------------------------------------------------------------------
|
||||
-- I2C Mudule
|
||||
---------------------------------------------------------------------------------------------
|
||||
|
||||
SPD_READ_UNIT: i2c
|
||||
generic map(
|
||||
count_div => COUNT_DIV -- sysclk divide coafficien (2 to 1023 max)
|
||||
)
|
||||
port map(
|
||||
ADDR_IN => word_addr, -- word address
|
||||
DAT_IN => DAT_IN, -- write data
|
||||
DEV_ADDR => dev_addr, -- device address
|
||||
CONTINUE => CONTINUE, -- continue read operation from ADDR_IN
|
||||
AP_EN => ap_en, -- Enable Address Phase During Write
|
||||
WR_OP => wr_i2c, -- write operation WRITE ONE WORD <= '0', RD <= '1'
|
||||
WR_EN => we_i2c, -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
|
||||
CLK => CLK, -- main clock
|
||||
RST => RST, -- system reset
|
||||
|
||||
I2C_RDATA => i2c_rdata, -- i2c read data
|
||||
ACK_L => ACK_L, -- acknowledge WR_EN (active '0')
|
||||
|
||||
I_SDA_I => I_SDA_I,
|
||||
O_SDA_O => O_SDA_O,
|
||||
O_SDA_T => O_SDA_T,
|
||||
|
||||
I_SCL_I => I_SCL_I,
|
||||
O_SCL_O => O_SCL_O,
|
||||
O_SCL_T => O_SCL_T,
|
||||
|
||||
I2C_RDY => i2c_rdy, -- i2c ready
|
||||
I2C_ACT => i2c_act, -- i2c cycle active
|
||||
ACK_ERR => ack_err -- i2c(ack) error
|
||||
);
|
||||
|
||||
CONTINUE <= '0';
|
||||
word_addr <= new_adr;
|
||||
dev_addr <= new_da;
|
||||
we_i2c <= new_wr;
|
||||
wr_i2c <= new_op;
|
||||
dat_in <= new_dat;
|
||||
ap_en <= new_apen;
|
||||
|
||||
I2C_BUSY_RG: process (RST, CLK)
|
||||
begin
|
||||
if RST = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if i2c_act_fall = '1' then
|
||||
i2c_busy <= '0';
|
||||
elsif new_wr = '1' then
|
||||
i2c_busy <= '1';
|
||||
end if;
|
||||
i2c_act_rg <= i2c_act;
|
||||
i2c_act_fall <= i2c_act_rg and not i2c_act;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK, RST)
|
||||
begin
|
||||
if (RST = '1') then
|
||||
i2c_mux_access_ok_r <= '0';
|
||||
si5341_access_ok_r <= '0';
|
||||
si5341_config_done_r <= '0';
|
||||
si5341_config_error_r <= '0';
|
||||
|
||||
cur_addr <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(CLK)) then
|
||||
if inc_adr = '1' then
|
||||
cur_addr <= cur_addr + 1;
|
||||
end if;
|
||||
|
||||
case state_r is
|
||||
|
||||
when IDLE => --0
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= X"55"; -- selects SC0/SD0 from I2C Mux U22 on ZCU208
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (START = '1') then
|
||||
new_da <= "1101010"; -- 6Ah - Si5332 Access
|
||||
new_apen <= '1';
|
||||
new_wr <= '0';
|
||||
i2c_mux_access_ok_r <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SI5341_NEW => --3
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
if (cur_addr = si5341_size) then
|
||||
state_r <= FINISH;
|
||||
else
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Write Register Value
|
||||
when SI5341_NEW_WR => --5
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
inc_adr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if (ack_err = '1') then
|
||||
state_r <= ERROR;
|
||||
new_wr <= '0';
|
||||
else
|
||||
si5341_access_ok_r <= '1';
|
||||
new_wr <= '1';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
else
|
||||
new_wr <= '0';
|
||||
state_r <= SI5341_NEW_WR;
|
||||
end if;
|
||||
|
||||
-- Increment Counter
|
||||
when SI5341_NEW_INC => --6
|
||||
new_adr <= si5341_addr_l;
|
||||
new_dat <= si5341_data;
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
if (i2c_busy = '0') then
|
||||
if ack_err = '1' then
|
||||
inc_adr <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
inc_adr <= '1';
|
||||
state_r <= SI5341_NEW;
|
||||
end if;
|
||||
else
|
||||
inc_adr <= '0';
|
||||
state_r <= SI5341_NEW_INC;
|
||||
end if;
|
||||
|
||||
when FINISH => --8
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_done_r <= '1';
|
||||
state_r <= FINISH;
|
||||
|
||||
when ERROR => --9
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
si5341_config_error_r <= '1';
|
||||
state_r <= ERROR;
|
||||
|
||||
when others => --f
|
||||
new_adr <= X"00";
|
||||
new_dat <= X"00";
|
||||
new_op <= '0';
|
||||
new_wr <= '0';
|
||||
inc_adr <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end si5341_gen_cfg_arch;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,192 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_afifo_64x128",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../alinx_z19_ad9081/alinx_z19_ad9081.gen/sources_1/ip/axis_afifo_64x128",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "block", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_64x128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "block", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../alinx_z19_ad9081/alinx_z19_ad9081.gen/sources_1/ip/axis_afifo_64x128" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
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|
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|
||||
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||||
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,175 @@
|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,192 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x512",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../test_sim/project_1.gen/sources_1/ip/axis_data_fifo_32x512",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x512", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
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|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,173 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_64x128",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_64x128",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Component_Name": [ { "value": "axis_data_fifo_64x128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
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|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9081_fmca_ebz_vcu128/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_64x128" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: axis_demux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m0_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m0_axis_tvalid : out std_logic;
|
||||
m0_axis_tready : in std_logic;
|
||||
|
||||
m1_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m1_axis_tvalid : out std_logic;
|
||||
m1_axis_tready : in std_logic
|
||||
);
|
||||
end axis_demux;
|
||||
|
||||
architecture imp of axis_demux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
--signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
m0_axis_tdata <= s_axis_tdata;
|
||||
m1_axis_tdata <= s_axis_tdata;
|
||||
|
||||
m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
|
||||
m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
|
||||
|
||||
s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
|
||||
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,488 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_demux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="05d5a589"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4b08030d"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="d2fc399b"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="55dda66a"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_dwidth_converter_128b_to_512b",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_128b_to_512b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_dwidth_converter_128b_to_512b", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_128b_to_512b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_dwidth_converter_512b_to_128b",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_512b_to_128b",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_dwidth_converter_512b_to_128b", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_dwidth_converter_512b_to_128b" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 05/18/2021 11:43:02 AM
|
||||
-- Design Name:
|
||||
-- Module Name: axis_mux - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity axis_mux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in std_logic;
|
||||
aselect : in std_logic;
|
||||
|
||||
s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s0_axis_tvalid : in std_logic;
|
||||
s0_axis_tready : out std_logic;
|
||||
s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
s1_axis_tvalid : in std_logic;
|
||||
s1_axis_tready : out std_logic;
|
||||
m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end axis_mux;
|
||||
|
||||
architecture imp of axis_mux is
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
|
||||
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
|
||||
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
|
||||
-- -- Use the port name for ASSOCIATED_RESET.
|
||||
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
|
||||
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
|
||||
|
||||
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
|
||||
|
||||
signal aselect_int : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- i_xpm_cdc_single_0 : xpm_cdc_single
|
||||
-- generic map(
|
||||
-- DEST_SYNC_FF => 4,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map(
|
||||
-- dest_out => aselect_int,
|
||||
-- dest_clk => aclk,
|
||||
-- src_clk => '0',
|
||||
-- src_in => aselect
|
||||
-- );
|
||||
|
||||
aselect_int <= aselect;
|
||||
|
||||
m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
|
||||
m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
|
||||
s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
|
||||
s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,542 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axis_mux</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s0_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s0_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s1_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s1_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s0_axis:s1_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_mux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>555c46b8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_mux</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>925c6e32</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c6faabd4</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aselect</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s0_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s0_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s0_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s1_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWIDTH')) - 1)">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
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<xilinx:tag xilinx:name="ui.data.coregen.dd@774e9648_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@25b4503c_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4372da5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47ed35b3_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@48531ae8_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@8313885_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5478ac48_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="24797529"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e6992404"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="04f2586c"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d79d0840"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="e7b1dc92"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_128",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_128",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_128", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_128" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0x00000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "16", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_240",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
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||||
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||||
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||||
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"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
BIN
Binary file not shown.
+1606
File diff suppressed because it is too large
Load Diff
+6
@@ -0,0 +1,6 @@
|
||||
###############################################################################################################
|
||||
# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32"
|
||||
###############################################################################################################
|
||||
#
|
||||
# This component is not configured in a multi-SLR crossing or auto-pipelining mode.
|
||||
# No timing core-level constraints are needed.
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 100 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+1100
File diff suppressed because it is too large
Load Diff
+1366
File diff suppressed because it is too large
Load Diff
+30
@@ -0,0 +1,30 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Thu Apr 23 10:08:03 2026
|
||||
// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
|
||||
// axis_register_slice_32_ axis_register_slice_32_stub.v
|
||||
// Design : axis_register_slice_32
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xczu19eg-ffvc1760-2-i
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
|
||||
module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready,
|
||||
s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [31:0]s_axis_tdata;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [31:0]m_axis_tdata;
|
||||
endmodule
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
-- Date : Thu Apr 23 10:08:04 2026
|
||||
-- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
|
||||
-- axis_register_slice_32_ axis_register_slice_32_stub.vhdl
|
||||
-- Design : axis_register_slice_32
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xczu19eg-ffvc1760-2-i
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity axis_register_slice_32 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end axis_register_slice_32;
|
||||
|
||||
architecture stub of axis_register_slice_32 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2";
|
||||
begin
|
||||
end;
|
||||
+336
@@ -0,0 +1,336 @@
|
||||
// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
// f_clogb2
|
||||
// f_gcd
|
||||
// f_lcm
|
||||
// f_get_tdata_indx
|
||||
// f_get_tstrb_indx
|
||||
// f_get_tkeep_indx
|
||||
// f_get_tlast_indx
|
||||
// f_get_tid_indx
|
||||
// f_get_tdest_indx
|
||||
// f_get_tuser_indx
|
||||
// f_payload_width
|
||||
// Tasks:
|
||||
// t_display_tdata_error
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Define Signal Set indices
|
||||
localparam G_INDX_SS_TREADY = 0;
|
||||
localparam G_INDX_SS_TDATA = 1;
|
||||
localparam G_INDX_SS_TSTRB = 2;
|
||||
localparam G_INDX_SS_TKEEP = 3;
|
||||
localparam G_INDX_SS_TLAST = 4;
|
||||
localparam G_INDX_SS_TID = 5;
|
||||
localparam G_INDX_SS_TDEST = 6;
|
||||
localparam G_INDX_SS_TUSER = 7;
|
||||
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
|
||||
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
|
||||
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
|
||||
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
|
||||
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
|
||||
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
|
||||
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
|
||||
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
|
||||
|
||||
// Task DRC error levels
|
||||
localparam G_TASK_SEVERITY_ERR = 2;
|
||||
localparam G_TASK_SEVERITY_WARNING = 1;
|
||||
localparam G_TASK_SEVERITY_INFO = 0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Functions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
// Calculates the Greatest Common Divisor between two integers using the
|
||||
// euclidean algorithm.
|
||||
function automatic integer f_gcd (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
if (a == 0) begin
|
||||
f_gcd = b;
|
||||
end else if (b == 0) begin
|
||||
f_gcd = a;
|
||||
end else if (a > b) begin
|
||||
f_gcd = f_gcd(a % b, b);
|
||||
end else begin
|
||||
f_gcd = f_gcd(a, b % a);
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Calculates the Lowest Common Denominator between two integers
|
||||
function integer f_lcm (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
f_lcm = ( a / f_gcd(a, b)) * b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdata_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
f_get_tdata_indx = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tstrb_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
|
||||
// If TDATA exists, then add its width to its base to get the tstrb index
|
||||
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tkeep_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tlast_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tid_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdest_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tuser_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Payload is the sum of all the AXIS signals present except for
|
||||
// TREADY/TVALID
|
||||
function integer f_payload_width (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
|
||||
// Ensure that the return value is never less than 1
|
||||
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
|
||||
end
|
||||
endfunction
|
||||
|
||||
task t_check_tdata_width(
|
||||
input integer data_width,
|
||||
input [8*80-1:0] var_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tdata_width
|
||||
if (data_width%8 != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
|
||||
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
|
||||
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
|
||||
$display(" information.");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task t_check_tuser_width(
|
||||
input integer tuser_width,
|
||||
input [8*80-1:0] tuser_name,
|
||||
input integer tdata_width,
|
||||
input [8*80-1:0] tdata_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tuser_width
|
||||
integer tdata_bytes;
|
||||
tdata_bytes = tdata_width/8;
|
||||
if ((tuser_width%tdata_bytes) != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
|
||||
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
|
||||
$display(" TUSER width in this module is only defined when the TUSER is the");
|
||||
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
|
||||
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
+1318
File diff suppressed because it is too large
Load Diff
+2998
File diff suppressed because it is too large
Load Diff
+125
@@ -0,0 +1,125 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
|
||||
// IP Revision: 29
|
||||
|
||||
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *)
|
||||
(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module axis_register_slice_32 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axis_tvalid,
|
||||
s_axis_tready,
|
||||
s_axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tready,
|
||||
m_axis_tdata
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire s_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire s_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [31 : 0] s_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire m_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [31 : 0] m_axis_tdata;
|
||||
|
||||
axis_register_slice_v1_1_29_axis_register_slice #(
|
||||
.C_FAMILY("zynquplus"),
|
||||
.C_AXIS_TDATA_WIDTH(32),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(1),
|
||||
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
|
||||
.C_REG_CONFIG(8),
|
||||
.C_NUM_SLR_CROSSINGS(0),
|
||||
.C_PIPELINES_MASTER(0),
|
||||
.C_PIPELINES_SLAVE(0),
|
||||
.C_PIPELINES_MIDDLE(0)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclk2x(1'H0),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'H1),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tstrb(4'HF),
|
||||
.s_axis_tkeep(4'HF),
|
||||
.s_axis_tlast(1'H1),
|
||||
.s_axis_tid(1'H0),
|
||||
.s_axis_tdest(1'H0),
|
||||
.s_axis_tuser(1'H0),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,376 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_pulse_intfc_v1_0 is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_aresetn_in : in std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
m0_axis_tready_in : in std_logic;
|
||||
|
||||
m1_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
m1_axis_tready_in : in std_logic;
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
|
||||
-- Ports of Axi Slave Bus Interface S00_AXI
|
||||
s00_axi_aclk_in : in std_logic;
|
||||
s00_axi_aresetn_in : in std_logic;
|
||||
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_awprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_awvalid : in std_logic;
|
||||
s00_axi_awready : out std_logic;
|
||||
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
s00_axi_wvalid : in std_logic;
|
||||
s00_axi_wready : out std_logic;
|
||||
s00_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_bvalid : out std_logic;
|
||||
s00_axi_bready : in std_logic;
|
||||
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_arprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_arvalid : in std_logic;
|
||||
s00_axi_arready : out std_logic;
|
||||
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_rresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_rvalid : out std_logic;
|
||||
s00_axi_rready : in std_logic
|
||||
);
|
||||
end dds_pulse_intfc_v1_0;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0 is
|
||||
|
||||
signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
signal m0_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
signal m1_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_0 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_0 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_0 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_0 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_0 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_0 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_0 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_0 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_1 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_1 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_1 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_1 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_1 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_1 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_2 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_2 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_2 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_2 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_2 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_2 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_2 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_2 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_3 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_3 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_3 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_3 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_3 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_3 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_3 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_3 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg3 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg4 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg5 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg6 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg7 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg8 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg9 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg10 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg11 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg12 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg13 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg14 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg15 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg16 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg17 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg18 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg19 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg20 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg21 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg22 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg23 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg24 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg25 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg26 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg27 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg28 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg29 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg30 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg31 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg32 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg33 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg34 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg35 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg36 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg37 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg38 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg39 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal cnt_reset : std_logic;
|
||||
|
||||
signal dds_enable : std_logic;
|
||||
signal dds_reset_n : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
slv_reg0_out => slv_reg0,
|
||||
slv_reg1_out => slv_reg1,
|
||||
slv_reg2_out => slv_reg2,
|
||||
slv_reg3_out => slv_reg3,
|
||||
slv_reg4_out => slv_reg4,
|
||||
slv_reg5_out => slv_reg5,
|
||||
slv_reg6_out => slv_reg6,
|
||||
slv_reg7_out => slv_reg7,
|
||||
slv_reg8_out => slv_reg8,
|
||||
slv_reg9_out => slv_reg9,
|
||||
slv_reg10_out => slv_reg10,
|
||||
slv_reg11_out => slv_reg11,
|
||||
slv_reg12_out => slv_reg12,
|
||||
slv_reg13_out => slv_reg13,
|
||||
slv_reg14_out => slv_reg14,
|
||||
slv_reg15_out => slv_reg15,
|
||||
slv_reg16_out => slv_reg16,
|
||||
slv_reg17_out => slv_reg17,
|
||||
slv_reg18_out => slv_reg18,
|
||||
slv_reg19_out => slv_reg19,
|
||||
slv_reg20_out => slv_reg20,
|
||||
slv_reg21_out => slv_reg21,
|
||||
slv_reg22_out => slv_reg22,
|
||||
slv_reg23_out => slv_reg23,
|
||||
slv_reg24_out => slv_reg24,
|
||||
slv_reg25_out => slv_reg25,
|
||||
slv_reg26_out => slv_reg26,
|
||||
slv_reg27_out => slv_reg27,
|
||||
slv_reg28_out => slv_reg28,
|
||||
slv_reg29_out => slv_reg29,
|
||||
slv_reg30_out => slv_reg30,
|
||||
slv_reg31_out => slv_reg31,
|
||||
slv_reg32_out => slv_reg32,
|
||||
slv_reg33_out => slv_reg33,
|
||||
slv_reg34_out => slv_reg34,
|
||||
slv_reg35_out => slv_reg35,
|
||||
slv_reg36_in => slv_reg36,
|
||||
slv_reg37_in => slv_reg37,
|
||||
slv_reg38_in => slv_reg38,
|
||||
slv_reg39_in => slv_reg39,
|
||||
|
||||
S_AXI_ACLK => s00_axi_aclk_in,
|
||||
S_AXI_ARESETN => s00_axi_aresetn_in,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
-- Add user logic here
|
||||
|
||||
--slv_reg0 --0x8300_0000
|
||||
process (s00_axi_aclk_in)
|
||||
begin
|
||||
if rising_edge(s00_axi_aclk_in) then
|
||||
if (slv_reg0(0) = '1') then
|
||||
cmd_send_0_r <= "111";
|
||||
else
|
||||
cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
if (slv_reg0(4) = '1') then
|
||||
cmd_send_1_r <= "111";
|
||||
else
|
||||
cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
if (slv_reg0(8) = '1') then
|
||||
cmd_send_2_r <= "111";
|
||||
else
|
||||
cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
if (slv_reg0(12) = '1') then
|
||||
cmd_send_3_r <= "111";
|
||||
else
|
||||
cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dac_holdoff <= slv_reg1(0); --0x8300_0004
|
||||
|
||||
-- <= slv_reg2(3 downto 0); --0x8300_0008
|
||||
|
||||
cnt_reset <= slv_reg3(0); --0x8300_000C
|
||||
dds_enable <= slv_reg3(31);
|
||||
|
||||
scale_0 <= slv_reg4(15 downto 0); --0x8300_0010
|
||||
dds_phase_inc_dwell_time_0 <= slv_reg5; --0x8300_0014
|
||||
dds_phase_inc_step_size_0 <= slv_reg6; --0x8300_0018
|
||||
idle_samples_0 <= slv_reg7; --0x8300_001C
|
||||
dds_samples_0 <= slv_reg8; --0x8300_0020
|
||||
phase_inc_0 <= slv_reg9; --0x8300_0024
|
||||
phase_off_0 <= slv_reg10; --0x8300_0028
|
||||
swap_sf_0 <= slv_reg11; --0x8300_002C
|
||||
|
||||
scale_1 <= slv_reg12(15 downto 0); --0x8300_0030
|
||||
dds_phase_inc_dwell_time_1 <= slv_reg13; --0x8300_0034
|
||||
dds_phase_inc_step_size_1 <= slv_reg14; --0x8300_0038
|
||||
idle_samples_1 <= slv_reg15; --0x8300_003C
|
||||
dds_samples_1 <= slv_reg16; --0x8300_0040
|
||||
phase_inc_1 <= slv_reg17; --0x8300_0044
|
||||
phase_off_1 <= slv_reg18; --0x8300_0048
|
||||
swap_sf_1 <= slv_reg19; --0x8300_004C
|
||||
|
||||
scale_2 <= slv_reg20(15 downto 0); --0x8300_0050
|
||||
dds_phase_inc_dwell_time_2 <= slv_reg21; --0x8300_0054
|
||||
dds_phase_inc_step_size_2 <= slv_reg22; --0x8300_0058
|
||||
idle_samples_2 <= slv_reg23; --0x8300_005C
|
||||
dds_samples_2 <= slv_reg24; --0x8300_0060
|
||||
phase_inc_2 <= slv_reg25; --0x8300_0064
|
||||
phase_off_2 <= slv_reg26; --0x8300_0068
|
||||
swap_sf_2 <= slv_reg27; --0x8300_006C
|
||||
|
||||
scale_3 <= slv_reg28(15 downto 0); --0x8300_0070
|
||||
dds_phase_inc_dwell_time_3 <= slv_reg29; --0x8300_0074
|
||||
dds_phase_inc_step_size_3 <= slv_reg30; --0x8300_0078
|
||||
idle_samples_3 <= slv_reg31; --0x8300_007C
|
||||
dds_samples_3 <= slv_reg32; --0x8300_0080
|
||||
phase_inc_3 <= slv_reg33; --0x8300_0084
|
||||
phase_off_3 <= slv_reg34; --0x8300_0088
|
||||
swap_sf_3 <= slv_reg35; --0x8300_008C
|
||||
|
||||
slv_reg36 <= m0_dds_pulse_data_cnt; --0x8300_0090
|
||||
slv_reg37 <= m0_axis_tvalid_cnt; --0x8300_0094
|
||||
slv_reg38 <= m1_dds_pulse_data_cnt; --0x8300_0098
|
||||
slv_reg39 <= m1_axis_tvalid_cnt; --0x8300_009C
|
||||
|
||||
|
||||
dds_reset_n <= '0' when m_axis_aresetn_in = '0' or dds_enable = '0' else '1';
|
||||
|
||||
i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
|
||||
port map (
|
||||
s_axi_aclk_in => s00_axi_aclk_in,
|
||||
s_axi_aresetn_in => s00_axi_aresetn_in,
|
||||
|
||||
cmd_idx_in => "000",
|
||||
dac_holdoff_in => dac_holdoff,
|
||||
|
||||
cmd_send_0_in => cmd_send_0_r(0),
|
||||
scale_0_in => scale_0,
|
||||
dds_phase_inc_dwell_time_0_in => dds_phase_inc_dwell_time_0,
|
||||
dds_phase_inc_step_size_0_in => dds_phase_inc_step_size_0,
|
||||
idle_samples_0_in => idle_samples_0,
|
||||
dds_samples_0_in => dds_samples_0,
|
||||
phase_inc_0_in => phase_inc_0,
|
||||
phase_off_0_in => phase_off_0,
|
||||
swap_sf_0_in => swap_sf_0,
|
||||
|
||||
cmd_send_1_in => cmd_send_1_r(0),
|
||||
scale_1_in => scale_1,
|
||||
dds_phase_inc_dwell_time_1_in => dds_phase_inc_dwell_time_1,
|
||||
dds_phase_inc_step_size_1_in => dds_phase_inc_step_size_1,
|
||||
idle_samples_1_in => idle_samples_1,
|
||||
dds_samples_1_in => dds_samples_1,
|
||||
phase_inc_1_in => phase_inc_1,
|
||||
phase_off_1_in => phase_off_1,
|
||||
swap_sf_1_in => swap_sf_1,
|
||||
|
||||
cmd_send_2_in => cmd_send_2_r(0),
|
||||
scale_2_in => scale_2,
|
||||
dds_phase_inc_dwell_time_2_in => dds_phase_inc_dwell_time_2,
|
||||
dds_phase_inc_step_size_2_in => dds_phase_inc_step_size_2,
|
||||
idle_samples_2_in => idle_samples_2,
|
||||
dds_samples_2_in => dds_samples_2,
|
||||
phase_inc_2_in => phase_inc_2,
|
||||
phase_off_2_in => phase_off_2,
|
||||
swap_sf_2_in => swap_sf_2,
|
||||
|
||||
cmd_send_3_in => cmd_send_3_r(0),
|
||||
scale_3_in => scale_3,
|
||||
dds_phase_inc_dwell_time_3_in => dds_phase_inc_dwell_time_3,
|
||||
dds_phase_inc_step_size_3_in => dds_phase_inc_step_size_3,
|
||||
idle_samples_3_in => idle_samples_3,
|
||||
dds_samples_3_in => dds_samples_3,
|
||||
phase_inc_3_in => phase_inc_3,
|
||||
phase_off_3_in => phase_off_3,
|
||||
swap_sf_3_in => swap_sf_3,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => dds_reset_n, ---m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_axis_tdata_out,
|
||||
m0_axis_tvalid_out => m0_axis_tvalid_out,
|
||||
m0_axis_tready_in => m0_axis_tready_in,
|
||||
|
||||
m1_axis_tdata_out => m1_axis_tdata_out,
|
||||
m1_axis_tvalid_out => m1_axis_tvalid_out,
|
||||
m1_axis_tready_in => m1_axis_tready_in,
|
||||
|
||||
cnt_reset_in => cnt_reset,
|
||||
m0_axis_tvalid_cnt_out => m0_axis_tvalid_cnt,
|
||||
m0_dds_pulse_data_cnt_out => m0_dds_pulse_data_cnt,
|
||||
m1_axis_tvalid_cnt_out => m1_axis_tvalid_cnt,
|
||||
m1_dds_pulse_data_cnt_out => m1_dds_pulse_data_cnt
|
||||
);
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,943 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_pulse_intfc_v1_0_S00_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
slv_reg0_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg1_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg2_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg3_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg4_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg5_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg6_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg7_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg8_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg9_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg11_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg12_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg13_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg14_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg15_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg16_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg17_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg18_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg19_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg20_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg21_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg22_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg23_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg24_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg25_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg26_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg27_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg28_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg29_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg30_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg31_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg32_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg33_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg34_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg35_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg36_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg37_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg38_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg39_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end dds_pulse_intfc_v1_0_S00_AXI;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0_S00_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 5;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 40
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= x"0000_0001";
|
||||
slv_reg2 <= x"0000_000F";
|
||||
slv_reg3 <= x"8000_0000";
|
||||
slv_reg4 <= x"0000_8000";
|
||||
slv_reg5 <= x"0000_0000";
|
||||
slv_reg6 <= x"0000_D6BF";
|
||||
slv_reg7 <= x"0000_0000";
|
||||
slv_reg8 <= x"0000_04E2";
|
||||
slv_reg9 <= x"0106_24DD";
|
||||
slv_reg10 <= x"0000_0000";
|
||||
slv_reg11 <= x"0000_8000";
|
||||
slv_reg12 <= x"0000_8000";
|
||||
slv_reg13 <= x"0000_0000";
|
||||
slv_reg14 <= x"0000_D6BF";
|
||||
slv_reg15 <= x"0000_0000";
|
||||
slv_reg16 <= x"0000_04E2";
|
||||
slv_reg17 <= x"0106_24DD";
|
||||
slv_reg18 <= x"0000_0000";
|
||||
slv_reg19 <= x"0000_8000";
|
||||
slv_reg20 <= x"0000_8000";
|
||||
slv_reg21 <= x"0000_0000";
|
||||
slv_reg22 <= x"0000_D6BF";
|
||||
slv_reg23 <= x"0000_0000";
|
||||
slv_reg24 <= x"0000_04E2";
|
||||
slv_reg25 <= x"0106_24DD";
|
||||
slv_reg26 <= x"0000_0000";
|
||||
slv_reg27 <= x"0000_8000";
|
||||
slv_reg28 <= x"0000_8000";
|
||||
slv_reg29 <= x"0000_0000";
|
||||
slv_reg30 <= x"0000_D6BF";
|
||||
slv_reg31 <= x"0000_0000";
|
||||
slv_reg32 <= x"0000_04E2";
|
||||
slv_reg33 <= x"0106_24DD";
|
||||
slv_reg34 <= x"0000_0000";
|
||||
slv_reg35 <= x"0000_8000";
|
||||
slv_reg36 <= (others => '0');
|
||||
slv_reg37 <= (others => '0');
|
||||
slv_reg38 <= (others => '0');
|
||||
slv_reg39 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg0(4) <= '0'; -- self clear bit 0
|
||||
slv_reg0(8) <= '0'; -- self clear bit 0
|
||||
slv_reg0(12) <= '0'; -- self clear bit 0
|
||||
slv_reg3(0) <= '0'; -- self clear bit 0
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"000000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 24
|
||||
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 25
|
||||
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 26
|
||||
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 27
|
||||
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 28
|
||||
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 29
|
||||
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 30
|
||||
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 31
|
||||
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 32
|
||||
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 33
|
||||
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 34
|
||||
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 35
|
||||
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 36
|
||||
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 37
|
||||
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 38
|
||||
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 39
|
||||
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
slv_reg24 <= slv_reg24;
|
||||
slv_reg25 <= slv_reg25;
|
||||
slv_reg26 <= slv_reg26;
|
||||
slv_reg27 <= slv_reg27;
|
||||
slv_reg28 <= slv_reg28;
|
||||
slv_reg29 <= slv_reg29;
|
||||
slv_reg30 <= slv_reg30;
|
||||
slv_reg31 <= slv_reg31;
|
||||
slv_reg32 <= slv_reg32;
|
||||
slv_reg33 <= slv_reg33;
|
||||
slv_reg34 <= slv_reg34;
|
||||
slv_reg35 <= slv_reg35;
|
||||
slv_reg36 <= slv_reg36;
|
||||
slv_reg37 <= slv_reg37;
|
||||
slv_reg38 <= slv_reg38;
|
||||
slv_reg39 <= slv_reg39;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"000000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"000001" =>
|
||||
reg_data_out <= slv_reg1;
|
||||
when b"000010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"000011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"000100" =>
|
||||
reg_data_out <= slv_reg4;
|
||||
when b"000101" =>
|
||||
reg_data_out <= slv_reg5;
|
||||
when b"000110" =>
|
||||
reg_data_out <= slv_reg6;
|
||||
when b"000111" =>
|
||||
reg_data_out <= slv_reg7;
|
||||
when b"001000" =>
|
||||
reg_data_out <= slv_reg8;
|
||||
when b"001001" =>
|
||||
reg_data_out <= slv_reg9;
|
||||
when b"001010" =>
|
||||
reg_data_out <= slv_reg10;
|
||||
when b"001011" =>
|
||||
reg_data_out <= slv_reg11;
|
||||
when b"001100" =>
|
||||
reg_data_out <= slv_reg12;
|
||||
when b"001101" =>
|
||||
reg_data_out <= slv_reg13;
|
||||
when b"001110" =>
|
||||
reg_data_out <= slv_reg14;
|
||||
when b"001111" =>
|
||||
reg_data_out <= slv_reg15;
|
||||
when b"010000" =>
|
||||
reg_data_out <= slv_reg16;
|
||||
when b"010001" =>
|
||||
reg_data_out <= slv_reg17;
|
||||
when b"010010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"010011" =>
|
||||
reg_data_out <= slv_reg19;
|
||||
when b"010100" =>
|
||||
reg_data_out <= slv_reg20;
|
||||
when b"010101" =>
|
||||
reg_data_out <= slv_reg21;
|
||||
when b"010110" =>
|
||||
reg_data_out <= slv_reg22;
|
||||
when b"010111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when b"011000" =>
|
||||
reg_data_out <= slv_reg24;
|
||||
when b"011001" =>
|
||||
reg_data_out <= slv_reg25;
|
||||
when b"011010" =>
|
||||
reg_data_out <= slv_reg26;
|
||||
when b"011011" =>
|
||||
reg_data_out <= slv_reg27;
|
||||
when b"011100" =>
|
||||
reg_data_out <= slv_reg28;
|
||||
when b"011101" =>
|
||||
reg_data_out <= slv_reg29;
|
||||
when b"011110" =>
|
||||
reg_data_out <= slv_reg30;
|
||||
when b"011111" =>
|
||||
reg_data_out <= slv_reg31;
|
||||
when b"100000" =>
|
||||
reg_data_out <= slv_reg32;
|
||||
when b"100001" =>
|
||||
reg_data_out <= slv_reg33;
|
||||
when b"100010" =>
|
||||
reg_data_out <= slv_reg34;
|
||||
when b"100011" =>
|
||||
reg_data_out <= slv_reg35;
|
||||
when b"100100" =>
|
||||
reg_data_out <= slv_reg36_in; --slv_reg36;
|
||||
when b"100101" =>
|
||||
reg_data_out <= slv_reg37_in; --slv_reg37;
|
||||
when b"100110" =>
|
||||
reg_data_out <= slv_reg38_in; --slv_reg38;
|
||||
when b"100111" =>
|
||||
reg_data_out <= slv_reg39_in; --slv_reg39;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
slv_reg0_out <= slv_reg0;
|
||||
slv_reg1_out <= slv_reg1;
|
||||
slv_reg2_out <= slv_reg2;
|
||||
slv_reg3_out <= slv_reg3;
|
||||
slv_reg4_out <= slv_reg4;
|
||||
slv_reg5_out <= slv_reg5;
|
||||
slv_reg6_out <= slv_reg6;
|
||||
slv_reg7_out <= slv_reg7;
|
||||
slv_reg8_out <= slv_reg8;
|
||||
slv_reg9_out <= slv_reg9;
|
||||
slv_reg10_out <= slv_reg10;
|
||||
slv_reg11_out <= slv_reg11;
|
||||
slv_reg12_out <= slv_reg12;
|
||||
slv_reg13_out <= slv_reg13;
|
||||
slv_reg14_out <= slv_reg14;
|
||||
slv_reg15_out <= slv_reg15;
|
||||
slv_reg16_out <= slv_reg16;
|
||||
slv_reg17_out <= slv_reg17;
|
||||
slv_reg18_out <= slv_reg18;
|
||||
slv_reg19_out <= slv_reg19;
|
||||
slv_reg20_out <= slv_reg20;
|
||||
slv_reg21_out <= slv_reg21;
|
||||
slv_reg22_out <= slv_reg22;
|
||||
slv_reg23_out <= slv_reg23;
|
||||
slv_reg24_out <= slv_reg24;
|
||||
slv_reg25_out <= slv_reg25;
|
||||
slv_reg26_out <= slv_reg26;
|
||||
slv_reg27_out <= slv_reg27;
|
||||
slv_reg28_out <= slv_reg28;
|
||||
slv_reg29_out <= slv_reg29;
|
||||
slv_reg30_out <= slv_reg30;
|
||||
slv_reg31_out <= slv_reg31;
|
||||
slv_reg32_out <= slv_reg32;
|
||||
slv_reg33_out <= slv_reg33;
|
||||
slv_reg34_out <= slv_reg34;
|
||||
slv_reg35_out <= slv_reg35;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
+227
@@ -0,0 +1,227 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "adder_16signed_16signed_latency2",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ],
|
||||
"Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Add_Mode": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
|
||||
"Out_Width": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Automatic", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Constant": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"B_Value": [ { "value": "0000000000000000", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_In": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_Out": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Borrow_Sense": [ { "value": "Active_Low", "resolve_type": "user", "usage": "all" } ],
|
||||
"SCLR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SSET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Bypass_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_Ctrl_Priority": [ { "value": "Reset_Overrides_Set", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_CE_Priority": [ { "value": "Sync_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass_CE_Priority": [ { "value": "CE_Overrides_Bypass", "resolve_type": "user", "usage": "all" } ],
|
||||
"AINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADD_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_CONSTANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "0000000000000000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYPASS_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCLR_OVERRIDES_SSET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BORROW_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "16" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"BYPASS": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S": [ { "direction": "out", "size_left": "16", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "SCLR", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "CE", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
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||||
+485
@@ -0,0 +1,485 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "afifo_32b_1024_pf512_latency1",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/afifo_32b_1024_pf512_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_register_slice_32",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_register_slice_32", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,216 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 4 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
|
||||
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
|
||||
--
|
||||
-- Phase Inc Start = 2^32 * (1/250) = 17179869
|
||||
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
|
||||
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
|
||||
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
|
||||
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
|
||||
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
|
||||
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
|
||||
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
|
||||
--
|
||||
|
||||
|
||||
signal dds_command_set : dds_command_list(0 to 0) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
)
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
|
||||
-- 1 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
-- x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 2
|
||||
-- -- CW TONE
|
||||
-- 2 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"000004E2", --DDS_SAMPLES (~5 us) - 0x4e2 = 1250 * 4nS = 5 uS
|
||||
---- x"000FFFFF", --DDS_SAMPLES (~5 us) - 0xFFFFF = 1048575 * 4nS = 4.1943 mSec
|
||||
---- x"00000E00", --DDS_SAMPLES (~5 us) - 0x00000E00 = 3584 * 4nS = 14.336 uSec
|
||||
---- x"000FFFFF", --DDS_SAMPLES (~5 us)
|
||||
-- x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
|
||||
-- 3 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
|
||||
-- x"000000FF", --IDLE_SAMPLES
|
||||
-- x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
|
||||
-- x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 4
|
||||
-- -- ??????
|
||||
-- 4 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"00000000", --DDS_SAMPLES (~5 us)
|
||||
-- x"00000000", --PHASE_INC (~6 MHz)
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- )
|
||||
);
|
||||
|
||||
|
||||
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
dds_command_set(0)(0) <= reserv1_in;
|
||||
dds_command_set(0)(1) <= dds_phase_inc_dwell_time_in;
|
||||
dds_command_set(0)(2) <= dds_phase_inc_step_size_in;
|
||||
dds_command_set(0)(3) <= idle_samples_in;
|
||||
dds_command_set(0)(4) <= dds_samples_in;
|
||||
dds_command_set(0)(5) <= phase_inc_in;
|
||||
dds_command_set(0)(6) <= phase_off_in;
|
||||
dds_command_set(0)(7) <= swap_sf_in;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
-- if (rst_in = '1') then
|
||||
-- cmd_idx_r <= 0;
|
||||
-- cmd_send_r <= '0';
|
||||
-- fifo_wr_en_r <= '0';
|
||||
-- state_cnt_r <= 0;
|
||||
-- state_r <= IDLE;
|
||||
-- else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= 0;--conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(0)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state_r <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = DONE else
|
||||
"11";
|
||||
|
||||
-- i_ila_1 : entity work.ila_2
|
||||
-- port map (
|
||||
-- clk => clk_in,
|
||||
-- probe0 => test_state_r, -- 2
|
||||
-- probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
|
||||
-- probe2 => fifo_wr_data_r, -- 32
|
||||
-- probe3(0) => fifo_wr_en_r, -- 1
|
||||
-- probe4(0) => cmd_send_in, -- 1
|
||||
-- probe5(0) => cmd_send_r -- 1
|
||||
-- );
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,365 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "23",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/dds_latency10",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "Phase_Generator_and_SIN_COS_LUT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles3": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF3": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles4": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF4": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles5": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF5": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles6": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF6": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles7": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF7": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles8": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF8": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles9": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF9": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles10": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF10": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles11": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF11": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency12": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC12": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "aclken" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,419 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
holdoff_r <= holdoff_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : dds_pulse_gen
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,415 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component dds_latency10
|
||||
port(
|
||||
-- ce : in std_logic;
|
||||
-- clk : in std_logic;
|
||||
-- sclr : in std_logic;
|
||||
-- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- rdy : out std_logic;
|
||||
-- cosine : out std_logic_vector(15 downto 0);
|
||||
-- sine : out std_logic_vector(15 downto 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0);
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0);
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0);
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0);
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0);
|
||||
signal phase_offset_r : std_logic_vector(31 downto 0);
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
phase_offset_r <= fifo_data_r(223 downto 192);
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
phase_inc_r1 <= phase_inc_r;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data(31 downto 0)
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,341 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_intfc_x4 is
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
cmd_send_0_in : in std_logic;
|
||||
scale_0_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_0_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_0_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_0_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_0_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_0_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_0_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_0_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_1_in : in std_logic;
|
||||
scale_1_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_1_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_1_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_1_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_1_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_1_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_1_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_2_in : in std_logic;
|
||||
scale_2_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_2_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_2_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_2_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_2_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_2_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_2_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_2_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cmd_send_3_in : in std_logic;
|
||||
scale_3_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_3_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_3_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_3_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_3_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_3_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_3_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_3_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_aresetn_in : in std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
m0_axis_tready_in : in std_logic;
|
||||
|
||||
m1_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
m1_axis_tready_in : in std_logic;
|
||||
|
||||
cnt_reset_in : in std_logic;
|
||||
m0_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m0_dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m1_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m1_dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end entity dds_pulse_intfc_x4;
|
||||
|
||||
architecture imp of dds_pulse_intfc_x4 is
|
||||
|
||||
signal m0_dds_intfc_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_0 : std_logic;
|
||||
signal m1_dds_intfc_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_0 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_1 : std_logic;
|
||||
signal m1_dds_intfc_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_1 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_2 : std_logic;
|
||||
signal m1_dds_intfc_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_2 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_3 : std_logic;
|
||||
signal m1_dds_intfc_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_3 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata : std_logic_vector(127 downto 0);
|
||||
signal m0_dds_intfc_tvalid : std_logic;
|
||||
signal m0_dds_intfc_tready : std_logic;
|
||||
signal s0_axis_tready_pipe : std_logic;
|
||||
signal m0_axis_tvalid_pipe : std_logic;
|
||||
signal m0_axis_tvalid_data_pipe_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m0_dds_intfc_tvalid_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal m1_dds_intfc_tdata : std_logic_vector(127 downto 0);
|
||||
signal m1_dds_intfc_tvalid : std_logic;
|
||||
signal m1_dds_intfc_tready : std_logic;
|
||||
signal s1_axis_tready_pipe : std_logic;
|
||||
signal m1_axis_tvalid_pipe : std_logic;
|
||||
signal m1_axis_tvalid_data_pipe_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m1_dds_intfc_tvalid_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
m0_axis_tvalid_cnt_out <= m0_axis_tvalid_data_pipe_cnt_r;
|
||||
m0_dds_pulse_data_cnt_out <= m0_dds_intfc_tvalid_data_cnt_r;
|
||||
m1_axis_tvalid_cnt_out <= m1_axis_tvalid_data_pipe_cnt_r;
|
||||
m1_dds_pulse_data_cnt_out <= m1_dds_intfc_tvalid_data_cnt_r;
|
||||
|
||||
i_dds_pulse_wrapper_0 : entity work.dds_pulse_wrapper
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_0_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_0_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_0_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_0_in,
|
||||
idle_samples_in => idle_samples_0_in,
|
||||
dds_samples_in => dds_samples_0_in,
|
||||
phase_inc_in => phase_inc_0_in,
|
||||
phase_off_in => phase_off_0_in,
|
||||
swap_sf_in => swap_sf_0_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_0,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_0,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_0,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_0,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_1 : entity work.dds_pulse_wrapper
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_1_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_1_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_1_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_1_in,
|
||||
idle_samples_in => idle_samples_1_in,
|
||||
dds_samples_in => dds_samples_1_in,
|
||||
phase_inc_in => phase_inc_1_in,
|
||||
phase_off_in => phase_off_1_in,
|
||||
swap_sf_in => swap_sf_1_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_1,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_1,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_1,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_1,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_2 : entity work.dds_pulse_wrapper
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_2_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_2_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_2_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_2_in,
|
||||
idle_samples_in => idle_samples_2_in,
|
||||
dds_samples_in => dds_samples_2_in,
|
||||
phase_inc_in => phase_inc_2_in,
|
||||
phase_off_in => phase_off_2_in,
|
||||
swap_sf_in => swap_sf_2_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_2,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_2,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_2,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_2,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_3 : entity work.dds_pulse_wrapper
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_3_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_3_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_3_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_3_in,
|
||||
idle_samples_in => idle_samples_3_in,
|
||||
dds_samples_in => dds_samples_3_in,
|
||||
phase_inc_in => phase_inc_3_in,
|
||||
phase_off_in => phase_off_3_in,
|
||||
swap_sf_in => swap_sf_3_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_3,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_3,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_3,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_3,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
----------------m0
|
||||
m0_dds_intfc_tdata(31 downto 0) <= m0_dds_intfc_tdata_0 when m0_dds_intfc_tvalid_0 = '1' else x"FFFF_0000";
|
||||
m0_dds_intfc_tdata(63 downto 32) <= m0_dds_intfc_tdata_1 when m0_dds_intfc_tvalid_1 = '1' else x"FFFF_0000";
|
||||
m0_dds_intfc_tdata(95 downto 64) <= m0_dds_intfc_tdata_2 when m0_dds_intfc_tvalid_2 = '1' else x"FFFF_0000";
|
||||
m0_dds_intfc_tdata(127 downto 96) <= m0_dds_intfc_tdata_3 when m0_dds_intfc_tvalid_3 = '1' else x"FFFF_0000";
|
||||
|
||||
m0_dds_intfc_tvalid <= '1' when m0_dds_intfc_tvalid_0 = '1' or m0_dds_intfc_tvalid_1 = '1' or m0_dds_intfc_tvalid_2 = '1' or m0_dds_intfc_tvalid_3 = '1' else '0';
|
||||
|
||||
m0_dds_intfc_tready <= '1' when m0_dds_intfc_tvalid = '1' and s0_axis_tready_pipe = '1' else '0';
|
||||
|
||||
i_axis_register_slice_128_m0 : entity work.axis_register_slice_128
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => m0_dds_intfc_tdata, -- in
|
||||
s_axis_tvalid => m0_dds_intfc_tvalid, -- in
|
||||
s_axis_tready => s0_axis_tready_pipe, -- out
|
||||
|
||||
m_axis_tdata => m0_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m0_axis_tvalid_pipe, -- out
|
||||
m_axis_tready => m0_axis_tready_in -- in
|
||||
);
|
||||
|
||||
m0_axis_tvalid_out <= m0_axis_tvalid_pipe;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m0_axis_tvalid_data_pipe_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m0_axis_tvalid_pipe = '1' and m0_axis_tready_in = '1') then
|
||||
m0_axis_tvalid_data_pipe_cnt_r <= m0_axis_tvalid_data_pipe_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m0_dds_intfc_tvalid_data_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m0_dds_intfc_tvalid = '1' and m0_dds_intfc_tready = '1') then
|
||||
m0_dds_intfc_tvalid_data_cnt_r <= m0_dds_intfc_tvalid_data_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------m1
|
||||
m1_dds_intfc_tdata(31 downto 0) <= m1_dds_intfc_tdata_0 when m1_dds_intfc_tvalid_0 = '1' else x"FFFF_0000";
|
||||
m1_dds_intfc_tdata(63 downto 32) <= m1_dds_intfc_tdata_1 when m1_dds_intfc_tvalid_1 = '1' else x"FFFF_0000";
|
||||
m1_dds_intfc_tdata(95 downto 64) <= m1_dds_intfc_tdata_2 when m1_dds_intfc_tvalid_2 = '1' else x"FFFF_0000";
|
||||
m1_dds_intfc_tdata(127 downto 96) <= m1_dds_intfc_tdata_3 when m1_dds_intfc_tvalid_3 = '1' else x"FFFF_0000";
|
||||
|
||||
m1_dds_intfc_tvalid <= '1' when m1_dds_intfc_tvalid_0 = '1' or m1_dds_intfc_tvalid_1 = '1' or m1_dds_intfc_tvalid_2 = '1' or m1_dds_intfc_tvalid_3 = '1' else '0';
|
||||
|
||||
m1_dds_intfc_tready <= '1' when m1_dds_intfc_tvalid = '1' and s1_axis_tready_pipe = '1' else '0';
|
||||
|
||||
i_axis_register_slice_128_m1 : entity work.axis_register_slice_128
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => m1_dds_intfc_tdata, -- in
|
||||
s_axis_tvalid => m1_dds_intfc_tvalid, -- in
|
||||
s_axis_tready => s1_axis_tready_pipe, -- out
|
||||
|
||||
m_axis_tdata => m1_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m1_axis_tvalid_pipe, -- out
|
||||
m_axis_tready => m1_axis_tready_in -- in
|
||||
);
|
||||
|
||||
m1_axis_tvalid_out <= m1_axis_tvalid_pipe;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m1_axis_tvalid_data_pipe_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m1_axis_tvalid_pipe = '1' and m1_axis_tready_in = '1') then
|
||||
m1_axis_tvalid_data_pipe_cnt_r <= m1_axis_tvalid_data_pipe_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m1_dds_intfc_tvalid_data_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m1_dds_intfc_tvalid = '1' and m1_dds_intfc_tready = '1') then
|
||||
m1_dds_intfc_tvalid_data_cnt_r <= m1_dds_intfc_tvalid_data_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,295 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_wrapper is
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
mode_in : in std_logic;
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_aresetn_in : in std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(31 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
m0_axis_tready_in : in std_logic;
|
||||
m1_axis_tdata_out : out std_logic_vector(31 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
m1_axis_tready_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper;
|
||||
|
||||
architecture imp of dds_pulse_wrapper is
|
||||
|
||||
attribute keep : string;
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal s_axi_areset : std_logic;
|
||||
signal m_axi_areset : std_logic;
|
||||
|
||||
signal s_axis_tready_0 : std_logic;
|
||||
signal s_axis_tready_1 : std_logic;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
|
||||
m_axi_areset <= not m_axis_aresetn_in; -- synchronous with m_axis_aclk_in
|
||||
|
||||
-- i_vio_0 : entity work.vio_0
|
||||
-- port map (
|
||||
-- clk => s_axi_aclk_in,
|
||||
-- probe_in0 => cmd_send_cnt_r, -- 32
|
||||
-- probe_in1 => pipe_in_ch1_fifo_rden_cnt_r, -- 32
|
||||
-- probe_in2 => dds_pulse_data_cnt_r, -- 32
|
||||
-- probe_in3 => s_axi_aclk_freq_r, -- 32
|
||||
-- probe_in4 => s_axi_aclk_cnt_r, -- 32
|
||||
-- probe_in5 => dds_pulse_data_overflow_cnt_r, -- 32
|
||||
-- probe_in6 => m_axis_tvalid_cnt_r, -- 32
|
||||
|
||||
-- );
|
||||
|
||||
mode <= mode_in;
|
||||
scale <= scale_in;
|
||||
dac_holdoff <= dac_holdoff_in;
|
||||
cmd_idx <= cmd_idx_in;
|
||||
cmd_send <= cmd_send_in;
|
||||
|
||||
reserv1 <= reserv1_in;
|
||||
dds_phase_inc_dwell_time <= dds_phase_inc_dwell_time_in;
|
||||
dds_phase_inc_step_size <= dds_phase_inc_step_size_in;
|
||||
idle_samples <= idle_samples_in;
|
||||
dds_samples <= dds_samples_in;
|
||||
phase_inc <= phase_inc_in;
|
||||
phase_off <= phase_off_in;
|
||||
swap_sf <= swap_sf_in;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
if (s_axi_aresetn_in = '0') then
|
||||
cmd_send_cnt_r <= (others => '0');
|
||||
cmd_send_r <= '0';
|
||||
else
|
||||
cmd_send_r <= cmd_send;
|
||||
if (cmd_send = '1' and cmd_send_r = '0') then
|
||||
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => m_axi_areset
|
||||
);
|
||||
|
||||
-- i_ila_4 : entity work.ila_4
|
||||
-- port map (
|
||||
-- clk => m_axis_aclk_in,
|
||||
-- probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
-- probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
-- probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
-- probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
-- );
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => m_axi_areset,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
-- pulse_i <= dds_pulse_data(15 downto 0);
|
||||
-- pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
-- process(s_axi_aclk_in)
|
||||
-- variable LineOut : line;
|
||||
-- begin
|
||||
-- if (rising_edge(s_axi_aclk_in)) then
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- hwrite(LineOut, dds_pulse_data);
|
||||
-- writeline(DataFile, LineOut);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if(m_axis_aresetn_in = '0') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
dds_pulse_data_overflow_cnt_r <= (others => '0');
|
||||
else
|
||||
if (dds_pulse_dval = '1' and s_axis_tready_0 = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (dds_pulse_dval = '1' and s_axis_tready_0 = '0') then
|
||||
dds_pulse_data_overflow_cnt_r <= dds_pulse_data_overflow_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (pipe_in_ch1_fifo_rden = '1') then
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_axis_register_slice_32_0 : entity work.axis_register_slice_32
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => dds_pulse_data, -- in
|
||||
s_axis_tvalid => dds_pulse_dval, -- in
|
||||
s_axis_tready => s_axis_tready_0, -- out
|
||||
|
||||
m_axis_tdata => m0_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m0_axis_tvalid_out, -- out
|
||||
m_axis_tready => m0_axis_tready_in -- in
|
||||
);
|
||||
|
||||
|
||||
i_axis_register_slice_32_1 : entity work.axis_register_slice_32
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => dds_pulse_data, -- in
|
||||
s_axis_tvalid => dds_pulse_dval, -- in
|
||||
s_axis_tready => s_axis_tready_1, -- out
|
||||
|
||||
m_axis_tdata => m1_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m1_axis_tvalid_out, -- out
|
||||
m_axis_tready => m1_axis_tready_in -- in
|
||||
);
|
||||
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"00000000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => s_axi_areset
|
||||
);
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
|
||||
s_axi_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+168
@@ -0,0 +1,168 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mult_16signed_x_16unsigned_latency3",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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||||
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||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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||||
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|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
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||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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||||
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|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
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|
||||
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|
||||
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||||
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|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
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||||
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|
||||
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||||
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|
||||
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||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"C_MEMORY_TYPE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx36", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "992", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "991", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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File diff suppressed because it is too large
Load Diff
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|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f062d2d_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@10cd760_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@64b4837a_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1edcc17e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7024ec49_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ee4ccf6_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@702143e0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7318cb6e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@47f9d0d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@467c2891_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@79d4f659_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8005bf8b"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6945f44e"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b2bb5fab"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c99d0644"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,114 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_decoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_decoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
select_12b : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(319 downto 0);
|
||||
m_axis_tvalid : out std_logic
|
||||
);
|
||||
end dig_iq_decoder;
|
||||
|
||||
architecture imp of dig_iq_decoder is
|
||||
|
||||
signal tvalid_int : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= tvalid_int;
|
||||
|
||||
|
||||
process(aclk, aresetn)
|
||||
begin
|
||||
if(aresetn = '0')then
|
||||
tvalid_int <= '0';
|
||||
elsif(rising_edge(aclk))then
|
||||
tvalid_int <= s_axis_tvalid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(aclk)
|
||||
begin
|
||||
|
||||
if(rising_edge(aclk))then
|
||||
|
||||
if(select_12b = '0')then
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(32 downto 17 ); -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(49 downto 34 ); -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(66 downto 51 ); -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(83 downto 68 ); -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(100 downto 85 ); -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(117 downto 102 ); -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(134 downto 119 ); -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(151 downto 136 ); -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(168 downto 153 ); -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(185 downto 170 ); -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(202 downto 187 ); -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(219 downto 204 ); -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(236 downto 221 ); -- IMAG[6]
|
||||
else
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(11 downto 0 ) & "0000"; -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(23 downto 12 ) & "0000"; -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(35 downto 24 ) & "0000"; -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(47 downto 36 ) & "0000"; -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(59 downto 48 ) & "0000"; -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(71 downto 60 ) & "0000"; -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(83 downto 72 ) & "0000"; -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(95 downto 84 ) & "0000"; -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(107 downto 96 ) & "0000"; -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(119 downto 108 ) & "0000"; -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(131 downto 120 ) & "0000"; -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(143 downto 132 ) & "0000"; -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(155 downto 144 ) & "0000"; -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(167 downto 156 ) & "0000"; -- IMAG[6]
|
||||
end if;
|
||||
|
||||
m_axis_tdata(239 downto 224 ) <= s_axis_tdata(179 downto 168 ) & "0000"; -- REAL[7]
|
||||
m_axis_tdata(255 downto 240 ) <= s_axis_tdata(191 downto 180 ) & "0000"; -- IMAG[7]
|
||||
m_axis_tdata(271 downto 256 ) <= s_axis_tdata(203 downto 192 ) & "0000"; -- REAL[8]
|
||||
m_axis_tdata(287 downto 272 ) <= s_axis_tdata(215 downto 204 ) & "0000"; -- IMAG[8]
|
||||
m_axis_tdata(303 downto 288 ) <= s_axis_tdata(227 downto 216 ) & "0000"; -- REAL[9]
|
||||
m_axis_tdata(319 downto 304 ) <= s_axis_tdata(239 downto 228 ) & "0000"; -- IMAG[9]
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,978 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_240b_to_512b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
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<spirit:name>xilinx_implementation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_decoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
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||||
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<spirit:name>xilinx_implementation_xilinx_com_user_axis_mux_1_0__ref_view_fileset</spirit:name>
|
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|
||||
<xilinx:subCoreRef>
|
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="axis_mux" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_register_slice" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
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|
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<xilinx:subCoreRef>
|
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
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<xilinx:mode xilinx:name="create_mode"/>
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_subset_converter" xilinx:version="1.1">
|
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<xilinx:mode xilinx:name="create_mode"/>
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||||
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<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/iq_240b_to_512b_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_141a36c4</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>iq_240b_to_512b</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">iq_240b_to_512b_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
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|
||||
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<xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>iq_240b_to_512b</xilinx:displayName>
|
||||
<xilinx:definitionSource>IPI</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-24T16:35:31Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ" xilinx:valueSource="user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
|
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="438683d4"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2dc76fda"/>
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<xilinx:targetDRCs>
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||||
<xilinx:targetDRC xilinx:tool="ipi">
|
||||
<xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
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</xilinx:targetDRC>
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</xilinx:targetDRCs>
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||||
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|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,357 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component iq_240b_to_512b_axis_demux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_demux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component iq_240b_to_512b_iq_decoder_12b_16b_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_iq_decoder_12b_16b_0;
|
||||
component iq_240b_to_512b_axis_mux_16b_12b_iq_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_axis_mux_16b_12b_iq_0;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component iq_240b_to_512b_axis_demux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component iq_240b_to_512b_axis_mux_16b_12b_iq_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component iq_240b_to_512b_iq_decoder_12b_16b_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,367 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:31:28 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_240b_to_512b.bd
|
||||
--Design : iq_240b_to_512b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_240b_to_512b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
overflow : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready_out : out std_logic;
|
||||
sel_12b_16bn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
|
||||
end iq_240b_to_512b;
|
||||
|
||||
architecture STRUCTURE of iq_240b_to_512b is
|
||||
component iq_240b_to_512b_axis_data_fifo_0_0 is
|
||||
port (
|
||||
s_axis_aresetn : in STD_LOGIC;
|
||||
s_axis_aclk : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_data_fifo_0_0;
|
||||
component axis_demux is
|
||||
generic(
|
||||
DWIDTH : integer := 512
|
||||
);
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m0_axis_tvalid : out STD_LOGIC;
|
||||
m0_axis_tready : in STD_LOGIC;
|
||||
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m1_axis_tvalid : out STD_LOGIC;
|
||||
m1_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_demux;
|
||||
component iq_240b_to_512b_xlslice_0_0 is
|
||||
port (
|
||||
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_xlslice_0_0;
|
||||
component dig_iq_decoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
select_12b : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC
|
||||
);
|
||||
end component dig_iq_decoder;
|
||||
component axis_mux is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
aselect : in STD_LOGIC;
|
||||
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s0_axis_tvalid : in STD_LOGIC;
|
||||
s0_axis_tready : out STD_LOGIC;
|
||||
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s1_axis_tvalid : in STD_LOGIC;
|
||||
s1_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component axis_mux;
|
||||
component iq_240b_to_512b_axis_register_slice_28B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_28B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
|
||||
component iq_240b_to_512b_overflow_detect_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
transfer_dropped : out STD_LOGIC
|
||||
);
|
||||
end component iq_240b_to_512b_overflow_detect_0;
|
||||
component iq_240b_to_512b_axis_register_slice_40B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_40B_0;
|
||||
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
|
||||
component iq_240b_to_512b_axis_register_slice_64B_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
|
||||
);
|
||||
end component iq_240b_to_512b_axis_register_slice_64B_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
|
||||
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal const_1b0_dout : STD_LOGIC;
|
||||
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
|
||||
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
|
||||
signal iq_240b_to_512b_overflow : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
|
||||
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
const_1b0_dout <= sel_12b_16bn;
|
||||
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
|
||||
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
|
||||
overflow <= iq_240b_to_512b_overflow;
|
||||
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
|
||||
s_axis_tready_out <= axis_data_fifo_0_M_AXIS_TREADY;
|
||||
|
||||
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
|
||||
port map (
|
||||
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
|
||||
s_axis_aclk => aclk_1,
|
||||
s_axis_aresetn => aresetn_1,
|
||||
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
|
||||
);
|
||||
axis_demux_16b_12b_iq: component axis_demux
|
||||
generic map (
|
||||
DWIDTH => 320
|
||||
)
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m0_axis_tdata => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
m0_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
|
||||
m1_axis_tdata => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
|
||||
s_axis_tdata => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
|
||||
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
|
||||
);
|
||||
axis_mux_16b_12b_iq: component axis_mux
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
aselect => const_1b0_dout,
|
||||
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
|
||||
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
|
||||
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
|
||||
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
|
||||
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
|
||||
);
|
||||
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
|
||||
s_axis_tready => axis_register_slice_0_s_axis_tready,
|
||||
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
|
||||
);
|
||||
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
|
||||
s_axis_tready => axis_demux_0_m1_axis_TREADY,
|
||||
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
|
||||
);
|
||||
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
|
||||
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
|
||||
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
|
||||
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
|
||||
s_axis_tready => axis_mux_0_m_axis_TREADY,
|
||||
s_axis_tvalid => axis_mux_0_m_axis_TVALID
|
||||
);
|
||||
iq_decoder_12b_16b: component dig_iq_decoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
|
||||
s_axis_tvalid => s_axis_1_TVALID,
|
||||
select_12b => const_1b0_dout
|
||||
);
|
||||
overflow_detect: component iq_240b_to_512b_overflow_detect_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
|
||||
m_axis_tready => overflow_detect_M_AXIS_TREADY,
|
||||
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
|
||||
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
|
||||
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
|
||||
transfer_dropped => iq_240b_to_512b_overflow
|
||||
);
|
||||
xlslice_0: component iq_240b_to_512b_xlslice_0_0
|
||||
port map (
|
||||
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
|
||||
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_data_fifo_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
"mode": "slave",
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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||||
+154
@@ -0,0 +1,154 @@
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s0_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s0_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s0_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s0_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s1_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s1_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s1_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s1_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+158
@@ -0,0 +1,158 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_axis_register_slice_28B_0",
|
||||
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_axis_register_slice_28B_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
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||||
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|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+169
@@ -0,0 +1,169 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_overflow_detect_0",
|
||||
"component_reference": "xilinx.com:ip:axis_subset_converter:1.1",
|
||||
"ip_revision": "29",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TREADY": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"M_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_REMAP": [ { "value": "tdata[319:0]", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TDEST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TKEEP_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TSTRB_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"TLAST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_overflow_detect_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "29" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
|
||||
"transfer_dropped": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlconstant_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_240b_to_512b_xlslice_0_0",
|
||||
"component_reference": "xilinx.com:ip:xlslice:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_240b_to_512b_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DIN_WIDTH": [ { "value": "320", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DOUT_WIDTH": [ { "value": "224", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DIN_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_FROM": [ { "value": "223", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DIN_TO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"Din": [ { "direction": "in", "size_left": "319", "size_right": "0" } ],
|
||||
"Dout": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_static_text $IPINST -name "TEXT1" -parent ${Page_0} -text {sel_12b_16bn = 0 -- 16-bit FSW data (Fs <= 600MHz)
|
||||
|
||||
|
||||
|
||||
sel_12b_16bn = 1 -- 12-bit FSW data (Fs = 1200MHz)}
|
||||
|
||||
|
||||
}
|
||||
@@ -0,0 +1,564 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_512b_to_240b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>083caf21</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
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||||
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||||
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||||
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
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||||
<spirit:direction>out</spirit:direction>
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||||
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||||
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||||
<spirit:port>
|
||||
<spirit:name>m_axis_tready</spirit:name>
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<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
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<xilinx:subCoreRef>
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<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
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<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
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<spirit:description>iq_512b_to_240b</spirit:description>
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@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component iq_512b_to_240b_dig_iq_encoder_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_512b_to_240b_dig_iq_encoder_0_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component dig_iq_encoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component dig_iq_encoder;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component dig_iq_encoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1169
File diff suppressed because it is too large
Load Diff
+336
@@ -0,0 +1,336 @@
|
||||
// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
// f_clogb2
|
||||
// f_gcd
|
||||
// f_lcm
|
||||
// f_get_tdata_indx
|
||||
// f_get_tstrb_indx
|
||||
// f_get_tkeep_indx
|
||||
// f_get_tlast_indx
|
||||
// f_get_tid_indx
|
||||
// f_get_tdest_indx
|
||||
// f_get_tuser_indx
|
||||
// f_payload_width
|
||||
// Tasks:
|
||||
// t_display_tdata_error
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Define Signal Set indices
|
||||
localparam G_INDX_SS_TREADY = 0;
|
||||
localparam G_INDX_SS_TDATA = 1;
|
||||
localparam G_INDX_SS_TSTRB = 2;
|
||||
localparam G_INDX_SS_TKEEP = 3;
|
||||
localparam G_INDX_SS_TLAST = 4;
|
||||
localparam G_INDX_SS_TID = 5;
|
||||
localparam G_INDX_SS_TDEST = 6;
|
||||
localparam G_INDX_SS_TUSER = 7;
|
||||
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
|
||||
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
|
||||
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
|
||||
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
|
||||
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
|
||||
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
|
||||
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
|
||||
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
|
||||
|
||||
// Task DRC error levels
|
||||
localparam G_TASK_SEVERITY_ERR = 2;
|
||||
localparam G_TASK_SEVERITY_WARNING = 1;
|
||||
localparam G_TASK_SEVERITY_INFO = 0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Functions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
// Calculates the Greatest Common Divisor between two integers using the
|
||||
// euclidean algorithm.
|
||||
function automatic integer f_gcd (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
if (a == 0) begin
|
||||
f_gcd = b;
|
||||
end else if (b == 0) begin
|
||||
f_gcd = a;
|
||||
end else if (a > b) begin
|
||||
f_gcd = f_gcd(a % b, b);
|
||||
end else begin
|
||||
f_gcd = f_gcd(a, b % a);
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Calculates the Lowest Common Denominator between two integers
|
||||
function integer f_lcm (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
f_lcm = ( a / f_gcd(a, b)) * b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdata_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
f_get_tdata_indx = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tstrb_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
|
||||
// If TDATA exists, then add its width to its base to get the tstrb index
|
||||
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tkeep_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tlast_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tid_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdest_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tuser_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Payload is the sum of all the AXIS signals present except for
|
||||
// TREADY/TVALID
|
||||
function integer f_payload_width (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
|
||||
// Ensure that the return value is never less than 1
|
||||
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
|
||||
end
|
||||
endfunction
|
||||
|
||||
task t_check_tdata_width(
|
||||
input integer data_width,
|
||||
input [8*80-1:0] var_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tdata_width
|
||||
if (data_width%8 != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
|
||||
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
|
||||
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
|
||||
$display(" information.");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task t_check_tuser_width(
|
||||
input integer tuser_width,
|
||||
input [8*80-1:0] tuser_name,
|
||||
input integer tdata_width,
|
||||
input [8*80-1:0] tdata_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tuser_width
|
||||
integer tdata_bytes;
|
||||
tdata_bytes = tdata_width/8;
|
||||
if ((tuser_width%tdata_bytes) != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
|
||||
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
|
||||
$display(" TUSER width in this module is only defined when the TUSER is the");
|
||||
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
|
||||
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
+1318
File diff suppressed because it is too large
Load Diff
+2998
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+152
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_axis_dwidth_converter_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user