257 lines
9.0 KiB
VHDL
257 lines
9.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: Erisys
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-- Engineer: Jason M Blevins
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--
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-- Create Date: 07/08/2023
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-- Design Name:
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-- Module Name: top - imp
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_si5341 is
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generic (
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SIM_ENABLED : boolean := FALSE;
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FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0409_2025";
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MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
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);
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Port(
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pl_clk0_p : in std_logic;
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pl_clk0_n : in std_logic;
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-- QSFP2_SI570_CLOCK_P : in std_logic;
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-- QSFP2_SI570_CLOCK_N : in std_logic; --//CLK3_N
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-- QSFP3_SI570_CLOCK_P : in std_logic;
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-- QSFP3_SI570_CLOCK_N : in std_logic; --//CLK1_N
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PL_SCL : inout std_logic;
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PL_SDA : inout std_logic
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);
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end top_si5341;
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architecture imp of top_si5341 is
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signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
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attribute keep : string;
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attribute keep of fpga_revision_date_r : signal is "true";
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signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
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attribute keep of minor_rev_r : signal is "true";
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signal clk_200 : std_logic;
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signal clk_200_resetn_r : std_logic_vector(0 to 31) := (others => '0');
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signal clk_200_resetn : std_logic;
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signal clk_100 : std_logic;
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signal clk_100_reset_r : std_logic_vector(0 to 31) := (others => '1');
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signal clk_100_reset : std_logic;
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signal tick_1ms : std_logic;
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signal sda_i : std_logic;
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signal sda_o : std_logic;
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signal sda_t : std_logic;
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signal scl_i : std_logic;
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signal scl_o : std_logic;
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signal scl_t : std_logic;
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signal i2c_mux_access_ok : std_logic;
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signal si5341_access_ok : std_logic;
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signal si5341_config_done : std_logic;
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signal si5341_config_error : std_logic;
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signal man_clk_gen_en : std_logic;
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signal man_clk_gty_rst_n : std_logic;
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signal man_clk_gen_cfg_reset : std_logic;
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signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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begin
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i_pl_clk0_ibufds : entity work.IBUFDS
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port map (
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I => pl_clk0_p,
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IB => pl_clk0_n,
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O => clk_200
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);
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process(clk_200)
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begin
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if (rising_edge(clk_200)) then
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clk_200_resetn_r <= clk_200_resetn_r(1 to 31) & '1';
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end if;
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end process;
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clk_200_resetn <= clk_200_resetn_r(0);
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i_bufgce_div : BUFGCE_DIV
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generic map (
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BUFGCE_DIVIDE => 2, -- 1-8
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-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
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IS_CE_INVERTED => '0', -- Optional inversion for CE
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IS_CLR_INVERTED => '0', -- Optional inversion for CLR
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IS_I_INVERTED => '0', -- Optional inversion for I
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SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS
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)
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port map (
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O => clk_100, -- 1-bit output: Buffer
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CE => '1', -- 1-bit input: Buffer enable
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CLR => '0', -- 1-bit input: Asynchronous clear
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I => clk_200 -- 1-bit input: Buffer
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);
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process(clk_100)
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begin
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if (rising_edge(clk_100)) then
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clk_100_reset_r <= clk_100_reset_r(1 to 31) & '0';
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end if;
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end process;
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clk_100_reset <= clk_100_reset_r(0);
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i_si5341_clk_conf : entity work.si5341_clk_configurator
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port map (
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sys_clk100_in => clk_100,
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tick_1ms_in => tick_1ms,
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si5341_clk_gty_rst_n_out => open,
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si5341_clk_sync_n_out => open,
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si5341_clk_lol_n_in => '1',
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si5341_clk_intr_n_in => '1',
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sda_in => sda_i,
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sda_out => sda_o,
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sda_t_out => sda_t,
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scl_in => scl_i,
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scl_out => scl_o,
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scl_t_out => scl_t,
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clk_gen_i2c_buf_sel_out => open,
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i2c_rst_n_out => open,
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i2c_mux_access_ok_out => i2c_mux_access_ok,
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si5341_access_ok_out => si5341_access_ok,
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si5341_config_done_out => si5341_config_done,
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si5341_config_error_out => si5341_config_error,
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man_clk_gen_en_in => man_clk_gen_en,
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man_clk_gty_rst_n_in => man_clk_gty_rst_n,
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man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
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reset_in => clk_100_reset
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);
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i_scl_iobuf : IOBUF
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port map (
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O => scl_i,
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I => scl_o,
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IO => PL_SCL,
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T => scl_t
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);
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i_sda_iobuf : IOBUF
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port map (
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O => sda_i,
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I => sda_o,
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IO => PL_SDA,
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T => sda_t
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);
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i_tick_gen : entity work.tick_gen
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generic map (
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CLOCK_SPEED_MHZ => 100
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)
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port map (
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clk_in => clk_100,
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tick_1us_out => open,
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tick_1ms_out => tick_1ms,
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tick_500ms_out => open,
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tick_750ms_out => open,
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tick_1s_out => open,
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prog_us_tick_rate_in => x"0000_0000",
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prog_us_tick_out => open,
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reset_in => clk_100_reset
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);
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process(clk_100)
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begin
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if (rising_edge(clk_100)) then
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fpga_revision_date_r <= FPGA_REVISION_DATE;
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minor_rev_r <= MINOR_REV;
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end if;
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end process;
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i_vio_0 : entity work.vio_0
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port map (
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clk => clk_100,
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probe_in0 => fpga_revision_date_r, -- 32
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probe_in1 => minor_rev_r, -- 8
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probe_in2(0) => i2c_mux_access_ok, -- 1
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probe_in3(0) => si5341_access_ok, -- 1
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probe_in4(0) => si5341_config_done, -- 1
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probe_in5(0) => si5341_config_error, -- 1
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probe_in6 => clk_100_freq_r, -- 32
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probe_in7 => clk_100_cnt_r, -- 32
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probe_out2(0) => man_clk_gen_en, -- 1
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probe_out3(0) => man_clk_gty_rst_n, -- 1
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probe_out4(0) => man_clk_gen_cfg_reset -- 1
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);
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process(clk_100)
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begin
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if (rising_edge(clk_100)) then
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clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
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if (clk_100_tick_1ms_r(0 to 1) = "01") then
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clk_100_freq_r <= clk_100_cnt_r;
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clk_100_cnt_r <= (others => '0');
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else
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clk_100_cnt_r <= clk_100_cnt_r + 1;
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end if;
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end if;
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end process;
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end imp;
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