---------------------------------------------------------------------------------- -- Company: Erisys -- Engineer: Jason M Blevins -- -- Create Date: 07/08/2023 -- Design Name: -- Module Name: top - imp -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_si5341 is generic ( SIM_ENABLED : boolean := FALSE; FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0409_2025"; MINOR_REV : std_logic_vector( 7 downto 0) := x"01" ); Port( pl_clk0_p : in std_logic; pl_clk0_n : in std_logic; -- QSFP2_SI570_CLOCK_P : in std_logic; -- QSFP2_SI570_CLOCK_N : in std_logic; --//CLK3_N -- QSFP3_SI570_CLOCK_P : in std_logic; -- QSFP3_SI570_CLOCK_N : in std_logic; --//CLK1_N PL_SCL : inout std_logic; PL_SDA : inout std_logic ); end top_si5341; architecture imp of top_si5341 is signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0'); attribute keep : string; attribute keep of fpga_revision_date_r : signal is "true"; signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0'); attribute keep of minor_rev_r : signal is "true"; signal clk_200 : std_logic; signal clk_200_resetn_r : std_logic_vector(0 to 31) := (others => '0'); signal clk_200_resetn : std_logic; signal clk_100 : std_logic; signal clk_100_reset_r : std_logic_vector(0 to 31) := (others => '1'); signal clk_100_reset : std_logic; signal tick_1ms : std_logic; signal sda_i : std_logic; signal sda_o : std_logic; signal sda_t : std_logic; signal scl_i : std_logic; signal scl_o : std_logic; signal scl_t : std_logic; signal i2c_mux_access_ok : std_logic; signal si5341_access_ok : std_logic; signal si5341_config_done : std_logic; signal si5341_config_error : std_logic; signal man_clk_gen_en : std_logic; signal man_clk_gty_rst_n : std_logic; signal man_clk_gen_cfg_reset : std_logic; signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0'); signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); begin i_pl_clk0_ibufds : entity work.IBUFDS port map ( I => pl_clk0_p, IB => pl_clk0_n, O => clk_200 ); process(clk_200) begin if (rising_edge(clk_200)) then clk_200_resetn_r <= clk_200_resetn_r(1 to 31) & '1'; end if; end process; clk_200_resetn <= clk_200_resetn_r(0); i_bufgce_div : BUFGCE_DIV generic map ( BUFGCE_DIVIDE => 2, -- 1-8 -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins IS_CE_INVERTED => '0', -- Optional inversion for CE IS_CLR_INVERTED => '0', -- Optional inversion for CLR IS_I_INVERTED => '0', -- Optional inversion for I SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS ) port map ( O => clk_100, -- 1-bit output: Buffer CE => '1', -- 1-bit input: Buffer enable CLR => '0', -- 1-bit input: Asynchronous clear I => clk_200 -- 1-bit input: Buffer ); process(clk_100) begin if (rising_edge(clk_100)) then clk_100_reset_r <= clk_100_reset_r(1 to 31) & '0'; end if; end process; clk_100_reset <= clk_100_reset_r(0); i_si5341_clk_conf : entity work.si5341_clk_configurator port map ( sys_clk100_in => clk_100, tick_1ms_in => tick_1ms, si5341_clk_gty_rst_n_out => open, si5341_clk_sync_n_out => open, si5341_clk_lol_n_in => '1', si5341_clk_intr_n_in => '1', sda_in => sda_i, sda_out => sda_o, sda_t_out => sda_t, scl_in => scl_i, scl_out => scl_o, scl_t_out => scl_t, clk_gen_i2c_buf_sel_out => open, i2c_rst_n_out => open, i2c_mux_access_ok_out => i2c_mux_access_ok, si5341_access_ok_out => si5341_access_ok, si5341_config_done_out => si5341_config_done, si5341_config_error_out => si5341_config_error, man_clk_gen_en_in => man_clk_gen_en, man_clk_gty_rst_n_in => man_clk_gty_rst_n, man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset, reset_in => clk_100_reset ); i_scl_iobuf : IOBUF port map ( O => scl_i, I => scl_o, IO => PL_SCL, T => scl_t ); i_sda_iobuf : IOBUF port map ( O => sda_i, I => sda_o, IO => PL_SDA, T => sda_t ); i_tick_gen : entity work.tick_gen generic map ( CLOCK_SPEED_MHZ => 100 ) port map ( clk_in => clk_100, tick_1us_out => open, tick_1ms_out => tick_1ms, tick_500ms_out => open, tick_750ms_out => open, tick_1s_out => open, prog_us_tick_rate_in => x"0000_0000", prog_us_tick_out => open, reset_in => clk_100_reset ); process(clk_100) begin if (rising_edge(clk_100)) then fpga_revision_date_r <= FPGA_REVISION_DATE; minor_rev_r <= MINOR_REV; end if; end process; i_vio_0 : entity work.vio_0 port map ( clk => clk_100, probe_in0 => fpga_revision_date_r, -- 32 probe_in1 => minor_rev_r, -- 8 probe_in2(0) => i2c_mux_access_ok, -- 1 probe_in3(0) => si5341_access_ok, -- 1 probe_in4(0) => si5341_config_done, -- 1 probe_in5(0) => si5341_config_error, -- 1 probe_in6 => clk_100_freq_r, -- 32 probe_in7 => clk_100_cnt_r, -- 32 probe_out2(0) => man_clk_gen_en, -- 1 probe_out3(0) => man_clk_gty_rst_n, -- 1 probe_out4(0) => man_clk_gen_cfg_reset -- 1 ); process(clk_100) begin if (rising_edge(clk_100)) then clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms; if (clk_100_tick_1ms_r(0 to 1) = "01") then clk_100_freq_r <= clk_100_cnt_r; clk_100_cnt_r <= (others => '0'); else clk_100_cnt_r <= clk_100_cnt_r + 1; end if; end if; end process; end imp;