611 lines
29 KiB
XML
611 lines
29 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>dds_pulse_wrapper</spirit:name>
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|
<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>m_axis_out</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:master/>
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|
<spirit:portMaps>
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|
<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axis_tdata_out</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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|
<spirit:portMap>
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|
<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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|
<spirit:name>m_axis_tvalid_out</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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|
<spirit:physicalPort>
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|
<spirit:name>m_axis_tready_in</spirit:name>
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|
</spirit:physicalPort>
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|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
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|
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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|
<spirit:displayName>Synthesis</spirit:displayName>
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|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>VHDL</spirit:language>
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|
<spirit:modelName>dds_pulse_wrapper</spirit:modelName>
|
|
<spirit:fileSetRef>
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|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:fileSetRef>
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|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>d4e6fb9a</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
<spirit:language>VHDL</spirit:language>
|
|
<spirit:modelName>dds_pulse_wrapper</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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|
<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
|
|
<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>d4e6fb9a</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_xpgui</spirit:name>
|
|
<spirit:displayName>UI Layout</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>c12c7cc7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
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<spirit:name>clk_in</spirit:name>
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<spirit:wire>
|
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<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
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<spirit:port>
|
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<spirit:name>m_axis_aclk_in</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_tdata_out</spirit:name>
|
|
<spirit:wire>
|
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<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_tvalid_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_tready_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rst_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="boolean">
|
|
<spirit:name>SIM_ENABLED</spirit:name>
|
|
<spirit:displayName>Sim Enabled</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIM_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
|
|
<spirit:name>FPGA_REVISION_DATE</spirit:name>
|
|
<spirit:displayName>Fpga Revision Date</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FPGA_REVISION_DATE" spirit:bitStringLength="32">0x10242023</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_0/ila_0.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false3.i_ila_2</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_3/ila_3.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false2.i_ila_3</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/dds_latency10/dds_latency10.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/addsub/addsub.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_4/ila_4.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false1.i_ila_4</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_2/ila_2.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/vio_0/vio_0.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false.i_vio_0</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_cmd_gen.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_2x_top.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_gen.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_wrapper.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_45020dae</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="c_addsub" xilinx:version="12.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_data_fifo" xilinx:version="2.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="fifo_generator" xilinx:version="13.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="vio" xilinx:version="3.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="dds_compiler" xilinx:version="6.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="mult_gen" xilinx:version="12.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="ila" xilinx:version="6.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_0/ila_0.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false3.i_ila_2</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/axis_data_fifo_512x128/axis_data_fifo_512x128.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_3/ila_3.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false2.i_ila_3</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/dds_latency10/dds_latency10.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/addsub/addsub.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_4/ila_4.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false1.i_ila_4</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/ila_2/ila_2.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>src/vio_0/vio_0.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
<spirit:userFileType>CELL_NAME_sim_false.i_vio_0</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_cmd_gen.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_2x_top.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_gen.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>dds_pulse_wrapper.vhd</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="c_addsub" xilinx:version="12.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_data_fifo" xilinx:version="2.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="fifo_generator" xilinx:version="13.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="vio" xilinx:version="3.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="dds_compiler" xilinx:version="6.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="mult_gen" xilinx:version="12.0">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="ila" xilinx:version="6.2">
|
|
<xilinx:mode xilinx:name="create_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/dds_pulse_wrapper_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_c12c7cc7</spirit:userFileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>dds_pulse_wrapper_v1_0</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SIM_ENABLED</spirit:name>
|
|
<spirit:displayName>Sim Enabled</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SIM_ENABLED">FALSE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dds_pulse_wrapper_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FPGA_REVISION_DATE</spirit:name>
|
|
<spirit:displayName>Fpga Revision Date</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_REVISION_DATE" spirit:bitStringLength="32">0x10242023</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>dds_pulse_wrapper_v1_0</xilinx:displayName>
|
|
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
|
<xilinx:xpmLibraries>
|
|
<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
|
|
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
|
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
|
|
</xilinx:xpmLibraries>
|
|
<xilinx:coreRevision>22</xilinx:coreRevision>
|
|
<xilinx:coreCreationDateTime>2023-10-24T20:32:50Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="nopcore"/>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="f253464a"/>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="be956492"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="9d1ccaa9"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="2da5c247"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="9c2ef043"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|