Erisys/alinx_z19_ad9082
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nsantana f2906ec2b4 more updates for address map
2026-06-03 00:53:45 -04:00

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ALINX_Z19_AD9082

Block Diagram

image

Board's Picture

image3

Address Map

image2

QSFP Interface Registers Base Address: 0x8000_0000

Address
Offset		 Bit Register Name Bit(s) Name Description Read/Write
0x00 31:0 reg0 fpga_revision_date mmddyyyy (0x09212025 <= current version) R
0x04 reg1 R
31:24
23:15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0		 minor_rev
reserved
qsfp4_intl
qsfp4_modprsl
qsfp4_playback_interface_ready
reserved
qsfp3_intl
qsfp3_modprsl
qsfp3_capture_interface_ready
reserved
qsfp2_intl
qsfp2_modprsl
qsfp2_capture_interface_ready
reserved
qsfp1_intl
qsfp1_modprsl
qsfp1_capture_interface_ready		 0x02 <= (current value)
Reserved
0 = Active, 1 = Not Active
0 = Present, 1 = Not Present
0 = Not Ready, 1 = Ready
Reserved
0 = Active, 1 = Not Active
0 = Present, 1 = Not Present
0 = Not Ready, 1 = Ready
Reserved
0 = Active, 1 = Not Active
0 = Present, 1 = Not Present
0 = Not Ready, 1 = Ready
Reserved
0 = Active, 1 = Not Active
0 = Present, 1 = Not Present
0 = Not Ready, 1 = Ready
0x08 reg2 R/W
31:0 Reserved
0x0c reg3 R/W
31:0 reserved
0x10 reg4 R/W
31:0 reserved
0x14 reg5 R/W
31:13
12
11:9
8
7:5
4
3:1
0		 reserved
qsfp4_reset_n
reserved
qsfp3_reset_n
reserved
qsfp2_reset_n
reserved
qsfp1_reset_n
0 = Reset, 1 = Normal

0 = Reset, 1 = Normal

0 = Reset, 1 = Normal

0 = Reset, 1 = Normal
0x18 reg6 R/W
31:0 reserved
0x1c reg7 R/W
31:0 reserved
0x20 reg8 R/W
31
30:1
0		 counters_rst
reserved
dig_iq_mode_50g_40g_n		 0 = Normal, 1 = Reset

0 = 40G mode, 1 = 50G mode
0x24 reg9 R/W
31:0 reserved
0x28 reg10 R/W
31
30:13
12
11:10
9:8
7:0		 rx_path_disable
reserved
tx_chan1to4_en
reserved
dac_src_data_sel
reserved		 0 = enabled, 1 = disabled

0 = disabled, 1 = enabled

0 = QuadSendRecv, 1 = Fiber, 2 = ADC_LOOPBACK
0x2C 31:0 reg11 clk_125_freq (KHz) R
0x30 31:0 reg12 clk_125_cnt R
0x34 31:0 reg13 clk_250_freq (KHz) R
0x38 31:0 reg14 clk_250_cnt R
0x3C 31:0 reg15 rx_device_clk_freq 375000 (in KHz) R
0x40 31:0 reg16 tx_device_clk_freq 375000 (in KHz) R
0x44 31:0 reg17 qsfp1_s_axis_aclk_freq 40G mode: 161132 (in KHz)
50G mode: 195312 (in KHz)		 R
0x48 31:0 reg18 qsfp1_s_axis_aclk_cnt R
0x4c 31:0 reg19 qsfp2_s_axis_aclk_freq 40G mode: 161132 (KHz)
50G mode: 195312 (KHz)		 R
0x50 31:0 reg20 qsfp2_s_axis_aclk_cnt R
0x54 31:0 reg21 qsfp3_s_axis_aclk_freq 40G mode: 161132 (in KHz)
50G mode: 195312 (in KHz)		 R
0x58 31:0 reg22 qsfp3_s_axis_aclk_cnt R
0x5C 31:0 reg23 qsfp4_s_axis_aclk_freq 40G mode: 161132 (in KHz)
50G mode: 195312 (in KHz)		 R
0x60 31:0 reg24 qsfp4_s_axis_aclk_cnt R
0x64 31:0 reg25 qsfp1_rx_tvalid_240b_cnt R/W
0x68 31:0 reg26 qsfp1_rx_overflow_240b_cnt R/W
0x6C 31:0 reg27 qsfp1_rx_fifo_aempty_512b_cnt R/W
0x70 31:0 reg28 qsfp1_rx_data_ready_cnt R/W
0x74 31:0 reg29 qsfp1_tx_tvalid_128b_cnt R/W
0x78 31:0 reg30 qsfp1_tx_tvalid_240b_cnt R/W
0x7C 31:0 reg31 qsfp1_rx_overflow_128b_cnt R/W
0x80 31:0 reg32 qsfp2_rx_tvalid_240b_cnt R/W
0x84 31:0 reg33 qsfp2_rx_overflow_240b_cnt R/W
0x88 31:0 reg34 qsfp2_rx_fifo_aempty_512b_cnt R/W
0x8C 31:0 reg35 qsfp2_rx_data_ready_cnt R/W
0x90 31:0 reg36 qsfp2_tx_tvalid_128b_cnt R/W
0x94 31:0 reg37 qsfp2_tx_tvalid_240b_cnt R/W
0x98 31:0 reg38 qsfp2_rx_overflow_128b_cnt R/W
0x9C 31:0 reg39 qsfp3_rx_tvalid_240b_cnt R/W
0xA0 31:0 reg40 qsfp3_rx_overflow_240b_cnt R/W
0xA4 31:0 reg41 qsfp3_rx_fifo_aempty_512b_cnt R/W
0xA8 31:0 reg42 qsfp3_rx_data_ready_cnt R/W
0xAC 31:0 reg43 qsfp3_tx_tvalid_128b_cnt R/W
0xB0 31:0 reg44 qsfp3_tx_tvalid_240b_cnt R/W
0xB4 31:0 reg45 qsfp3_rx_overflow_128b_cnt R/W
0xB8 31:0 reg46 qsfp4_rx_tvalid_240b_cnt R/W
0xBC 31:0 reg47 qsfp4_rx_overflow_240b_cnt R/W
0xC0 31:0 reg48 qsfp4_rx_fifo_aempty_512b_cnt R/W
0xC4 31:0 reg49 qsfp4_rx_data_ready_cnt R/W
0xC8 31:0 reg50 qsfp4_tx_tvalid_128b_cnt R/W
0xCC 31:0 reg51 qsfp4_tx_tvalid_240b_cnt R/W
0xD0 31:0 reg52 qsfp4_rx_overflow_128b_cnt R/W
0xD4 31:0 reg53 adc_rx_tvalid_256b_cnt R/W
0xD8 31:0 reg54 reserved R/W
0xDC 31:0 reg55 reserved R/W
0xE0 31:0 reg56 tx_tvalid_256b_cnt R/W
0xE4 31:0 reg57 mem_xfer_tx_upload_tvalid_256b_cnt R/W
0xE8 31:0 reg58 reserved R/W
0xEC 31:0 reg59 reserved R/W
0xF0 31:0 reg60 dac_tx_tvalid_128b_cnt R/W
0xF4 31:0 reg61 reserved R/W
0xF8 31:0 reg62 reserved R/W
0xFC 31:0 reg63 reserved R/W

CMAC_1 Ethernet Core Registers Base Address: 0x8101_0000

Address
Offset		 Bit Register Name Bit(s) Name Description Read/Write
0x00 31:1
0		 reg0 gt_reset_reg Reserved
1 = Reset, self-clearing		 R/W
0x04 31:0 reg1 reset_reg R/W
0x0C 31:1
0		 reg2 configuration_tx_reg1 Reserved1
0 = Disable, 1 = Enable		 R/W
0x14 31:1
0		 reg4 configuration_rx_reg1 Reserved1
0 = Disable, 1 = Enable		 R/W
0x24 31:16
15:8
7:0		 reg5 core_version_reg Reserved
Major Version
Minor Version		 R/W
0x90 31:1
0		 reg6 gt_loopback Reserved
0 = Normal,
Near End PMA Loopback		 R/W

CMAC_1 Ethernet Interface Registers Base Address: 0x8100_0000

Address
Offset		 Bit Register Name Bit(s) Name Description Read/Write
0x00 31:0 reg0 dest_mac_addr_lo Destination MAC address (lower 32-bit) R/W
0x04 31:0 reg1 dest_mac_addr_hi Destination MAC address (upper 16-bit) R/W
0x08 31:0 reg2 src_mac_addr_lo Source MAC address (lower 32-bit) R/W
0x0C 31:0 reg3 src_mac_addr_hi Source MAC address (upper 16-bit) R/W
0x10 31:16
30:0		 reg4 Reserved
ether_type
Ethernet Type		 R/W
0x14 31:1
0		 reg5 Reserved
prog_full_man
Programable Full Manual Control, For Debug Only		 R/W
0x18 31:0 reg6 prog_full_on Programable Full On Threshold R/W
0x1C 31:0 reg7 prog_full_off Programable Full Off Threshold R/W
R/W
0x40 31:0 reg16 tx_frame_cnt ????? R
0x44 31:0 reg17 tx_frame_underrun_cnt ????? R
0x48 31:0 reg18 tx_pause_cnt ????? R
0x4C 31:0 reg19 rx_frame_cnt ????? R
0x50 31:0 reg20 rx_frame_err_cnt ????? R
0x54 31:0 reg21 rx_pause_cnt ????? R
0x58 31:0 reg22 rx_fifo_overflow_cnt ????? R

CMAC_4 Ethernet Core Registers Base Address: 0x8201_0000

Address
Offset		 Bit Register Name Bit(s) Name Description Read/Write
0x00 31:1
0		 reg0 gt_reset_reg Reserved
1 = Reset, self-clearing		 R/W
0x04 31:0 reg1 reset_reg R/W
0x0C 31:1
0		 reg2 configuration_tx_reg1 Reserved1
0 = Disable, 1 = Enable		 R/W
0x14 31:1
0		 reg4 configuration_rx_reg1 Reserved1
0 = Disable, 1 = Enable		 R/W
0x24 31:16
15:8
7:0		 reg5 core_version_reg Reserved
Major Version
Minor Version		 R/W
0x90 31:1
0		 reg6 gt_loopback Reserved
0 = Normal,
Near End PMA Loopback		 R/W

CMAC_4 Ethernet Interface Registers Base Address: 0x8200_0000

Address
Offset		 Bit Register Name Bit(s) Name Description Read/Write
0x00 31:0 reg0 dest_mac_addr_lo Destination MAC address (lower 32-bit) R/W
0x04 31:0 reg1 dest_mac_addr_hi Destination MAC address (upper 16-bit) R/W
0x08 31:0 reg2 src_mac_addr_lo Source MAC address (lower 32-bit) R/W
0x0C 31:0 reg3 src_mac_addr_hi Source MAC address (upper 16-bit) R/W
0x10 31:16
30:0		 reg4 Reserved
ether_type
Ethernet Type		 R/W
0x14 31:1
0		 reg5 Reserved
prog_full_man
Programable Full Manual Control, For Debug Only		 R/W
0x18 31:0 reg6 prog_full_on Programable Full On Threshold R/W
0x1C 31:0 reg7 prog_full_off Programable Full Off Threshold R/W
R/W
0x40 31:0 reg16 tx_frame_cnt ????? R
0x44 31:0 reg17 tx_frame_underrun_cnt ????? R
0x48 31:0 reg18 tx_pause_cnt ????? R
0x4C 31:0 reg19 rx_frame_cnt ????? R
0x50 31:0 reg20 rx_frame_err_cnt ????? R
0x54 31:0 reg21 rx_pause_cnt ????? R
0x58 31:0 reg22 rx_fifo_overflow_cnt ????? R

How to re-create Project in Vivado

  1. Clone the hdl repository from https://github.com/analogdevicesinc/hdl
  2. Follow instructions to build all the libraries
  3. check out this project into a project folder, for example //projects/ALINX_Z19
  4. open Vivado and add the following user repository(s):
    //adi/hdl/library
  5. cd to //projects/ALINX_Z19/alinx_z19_ad9082
  6. type source ./create_proj.tcl
  7. After the project is re-created correctly, run "Create HDL Wrapper..." from the Sources tab for system.bd
  8. Click on "Generate Bitstream"

How to update project file after adding or removing project files

  1. remove system_wrapper.vhd from Design Sources since this file is auto-generated.
  2. remove system_top.dcp from Design Sources from Utility\utils_1\Design Checkpoint.
  3. in the Tcl console, cd to //projects/ALINX_Z19/alinx_z19_ad9082
  4. type write_project_tcl -force create_proj.tcl
  5. Make sure to commit create_proj.tcl and all modified and added files to git

How to read or write registers using devmem from Linux's command line

Usage: devmem ADDRESS [WIDTH [VALUE]]

Read/write from physical address

    ADDRESS Address to act upon
    WIDTH   Width (8/16/...)
    VALUE   Data to be written

Memory Read Example

To read the FPGA Revision Register type:
devmem 0x80000000
0x10212024 <-- response

Memory Write Example

To write a32-bit register type:
devmem 0x80000028 32 0x12345678

How to Build Atomic Rules Yocto ARDSoC Project for Alinx_AD9082

  1. clone this repo https://github.com/AtomicRulesLLC/yocto-ardsoc#
  2. cd proj_ar/yocto-ardsoc
  3. git checkout scarthgap_mt
  4. sudo ./scripts/plnx-env-setup.sh
  5. cd sources
  6. git submodule update
  7. cd ..
  8. source setupsdk z19-9082 build_z19_9082
  9. bitbake ardsoc-image-core --> if all builds successfully see Output Artifacts below

Notes on how to re-generate BOOT.BIN

  1. replace the .xsa file with your latest at this location:
    proj_ar/yocto-ardsoc/sources/meta-atomicrules/meta-atomicrules-ardsoc/meta-z19-9082/recipes-bsp/external-hdf/files/system.xsa --> for AD9082
  2. cd proj_ar/yocto-ardsoc/build_z19_ad9082
  3. rm -rf tmp/
  4. cd ..
  5. sudo ./scripts/plnx-env-setup.sh
  6. source setupsdk z19-9082 build_z19_9082
  7. bitbake ardsoc-image-core --> if all builds successfully see Output Artifacts below

Output Artifacts

  1. Once you have a new build with your xsa the artifacts can be found here:
    a) proj_ar/yocto-ardsoc/build_z19_9082/tmp/deploy/images/ardsoc-z19-zynqmp/boot.bin
    b) proj_ar/yocto-ardsoc/build_z19_9082/tmp/deploy/images/ardsoc-z19-zynqmp/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs.wic.gz

to copy new boot.bin to board:
ex. scp boot.bin root@10.1.1.169:/boot

Misc Stuff

dtc -I dtb -O dts system.dtb -o system.dts
dtc -I dts -O dtb system.dts -o system.dtb

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