266 lines
13 KiB
VHDL
266 lines
13 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity qsfp_capture_intfc_128 is
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port (
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qsfp_capture_aclk_in : in std_logic;
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qsfp_capture_aresetn_in : in std_logic;
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qsfp_capture_tdata_240b_in : in std_logic_vector(239 downto 0);
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qsfp_capture_tvalid_240b_in : in std_logic;
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qsfp_capture_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
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qsfp_capture_fifo_aempty_512b_cnt_out : out std_logic_vector( 31 downto 0);
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qsfp_capture_iq_240b_to_512b_overflow_cnt_out : out std_logic_vector( 31 downto 0);
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qsfp_capture_rx_data_ready_out : out std_logic;
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qsfp_capture_rx_data_ready_cnt_out : out std_logic_vector( 31 downto 0);
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tx_device_clk_in : in std_logic;
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tx_device_clk_aresetn_in : in std_logic;
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tx_tdata_128b_out : out std_logic_vector(127 downto 0);
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tx_tvalid_128b_out : out std_logic;
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tx_tready_128b_in : in std_logic;
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tx_tvalid_128b_cnt_out : out std_logic_vector( 31 downto 0);
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chan1to4_mode_sel_in : in std_logic;
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cnt_reset_in : in std_logic
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);
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end entity qsfp_capture_intfc_128;
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architecture arch_imp of qsfp_capture_intfc_128 is
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signal qsfp_rx_data_ready : std_logic;
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signal qsfp_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp_prog_full_240b : std_logic;
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signal qsfp_afull_240b : std_logic;
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signal qsfp_aempty_240b : std_logic;
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signal qsfp_rx_data_ready_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp_iq_240b_to_512b_overflow : std_logic;
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signal qsfp_iq_240b_to_512b_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp_tdata_512b : std_logic_vector(511 downto 0);
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signal qsfp_tvalid_512b : std_logic;
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signal qsfp_tready_512b : std_logic;
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signal qsfp_tdata_512b_pipe : std_logic_vector(511 downto 0);
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signal qsfp_tvalid_512b_pipe : std_logic;
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signal qsfp_tready_512b_pipe : std_logic;
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signal qsfp_almost_empty_512b_pipe : std_logic;
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signal qsfp_almost_empty_512b_pipe_r : std_logic := '1';
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signal qsfp_fifo_aempty_512b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal axis_dwidth_converter_512b_to_128b_tdata_128 : std_logic_vector(127 downto 0);
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signal axis_dwidth_converter_512b_to_128b_tvalid_128 : std_logic;
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signal axis_dwidth_converter_512b_to_128b_tready : std_logic;
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signal axis_dwidth_converter_512b_to_32b_tdata_32b : std_logic_vector(31 downto 0);
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signal axis_dwidth_converter_512b_to_32b_tvalid_32b : std_logic;
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signal axis_dwidth_converter_512b_to_32b_tready : std_logic;
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signal qsfp_tdata_128b : std_logic_vector(127 downto 0);
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signal qsfp_tvalid_128b : std_logic;
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signal qsfp_tready_128b : std_logic;
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signal tx_tvalid_128b : std_logic;
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signal tx_fifo_aempty_128b : std_logic;
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signal tx_fifo_aempty_128b_r : std_logic := '1';
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signal tx_fifo_prog_aempty_128 : std_logic;
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signal tx_tvalid_128b_ena : std_logic;
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signal tx_tready_128b_ena : std_logic;
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signal tx_pre_buff_rdy_r : std_logic := '0';
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signal tx_tvalid_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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begin
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qsfp_capture_rx_data_ready_out <= qsfp_rx_data_ready;
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qsfp_capture_rx_data_ready_cnt_out <= qsfp_rx_data_ready_cnt_r;
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qsfp_capture_tvalid_240b_cnt_out <= qsfp_tvalid_240b_cnt_r;
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qsfp_capture_iq_240b_to_512b_overflow_cnt_out <= qsfp_iq_240b_to_512b_overflow_cnt_r;
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qsfp_capture_fifo_aempty_512b_cnt_out <= qsfp_fifo_aempty_512b_cnt_r;
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tx_tvalid_128b_cnt_out <= tx_tvalid_128b_cnt_r;
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-- ***240 to 128 converter
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i_iq_240b_to_512b : entity work.iq_240b_to_512b
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port map (
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aclk => qsfp_capture_aclk_in, -- in
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aresetn => qsfp_capture_aresetn_in, -- in
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s_axis_tdata => qsfp_capture_tdata_240b_in, -- in
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s_axis_tvalid => qsfp_capture_tvalid_240b_in, -- in
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prog_full => qsfp_prog_full_240b, -- out
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almost_full => qsfp_afull_240b, --out
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m_axis_tdata => qsfp_tdata_512b, -- out
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m_axis_tvalid => qsfp_tvalid_512b, -- out
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m_axis_tready => qsfp_tready_512b, -- in
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almost_empty => qsfp_aempty_240b, -- out
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overflow => qsfp_iq_240b_to_512b_overflow, -- out
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sel_12b_16bn => '0' -- 16-bit samples -- in
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);
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qsfp_rx_data_ready <= not qsfp_prog_full_240b;
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process(qsfp_capture_aclk_in)
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begin
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if (rising_edge(qsfp_capture_aclk_in)) then
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if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
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qsfp_tvalid_240b_cnt_r <= (others => '0');
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elsif (qsfp_capture_tvalid_240b_in = '1') then
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qsfp_tvalid_240b_cnt_r <= qsfp_tvalid_240b_cnt_r + 1;
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end if;
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if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
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qsfp_rx_data_ready_cnt_r <= (others => '0');
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elsif (qsfp_rx_data_ready = '0') then
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qsfp_rx_data_ready_cnt_r <= qsfp_rx_data_ready_cnt_r + 1;
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end if;
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if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
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qsfp_iq_240b_to_512b_overflow_cnt_r <= (others => '0');
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elsif (qsfp_iq_240b_to_512b_overflow = '1') then
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qsfp_iq_240b_to_512b_overflow_cnt_r <= qsfp_iq_240b_to_512b_overflow_cnt_r + 1;
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end if;
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end if;
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end process;
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-- i_qsfp_reg_slice_512 : entity work.axis_register_slice_512
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-- port map (
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-- aclk => qsfp_capture_aclk_in, -- in
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-- aresetn => qsfp_capture_aresetn_in, -- in
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-- s_axis_tdata => qsfp_tdata_512b, -- in
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-- s_axis_tvalid => qsfp_tvalid_512b, -- in
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-- s_axis_tready => qsfp_tready_512b, -- out
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-- m_axis_tdata => qsfp_tdata_512b_pipe, -- out
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-- m_axis_tvalid => qsfp_tvalid_512b_pipe, -- out
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-- m_axis_tready => qsfp_tready_512b_pipe -- in
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-- );
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-- this fifo is actually 64 words deep
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i_axis_data_fifo_32x512 : entity work.axis_data_fifo_32x512
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port map (
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s_axis_aclk => qsfp_capture_aclk_in,
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s_axis_aresetn => qsfp_capture_aresetn_in,
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s_axis_tdata => qsfp_tdata_512b,
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s_axis_tvalid => qsfp_tvalid_512b,
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s_axis_tready => qsfp_tready_512b,
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m_axis_aclk => tx_device_clk_in,
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m_axis_tdata => qsfp_tdata_512b_pipe, -- out
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m_axis_tvalid => qsfp_tvalid_512b_pipe, -- out
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m_axis_tready => qsfp_tready_512b_pipe, -- in
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almost_empty => qsfp_almost_empty_512b_pipe
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);
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process(tx_device_clk_in)
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begin
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if (rising_edge(tx_device_clk_in)) then
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qsfp_almost_empty_512b_pipe_r <= qsfp_almost_empty_512b_pipe;
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if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
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qsfp_fifo_aempty_512b_cnt_r <= (others => '0');
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elsif (qsfp_almost_empty_512b_pipe = '1' and qsfp_almost_empty_512b_pipe_r = '0') then
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qsfp_fifo_aempty_512b_cnt_r <= qsfp_fifo_aempty_512b_cnt_r + 1;
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end if;
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end if;
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end process;
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-- i_ila_128_4_qsfp1 : ila_128_4
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-- port map (
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-- clk => qsfp_capture_aclk_in,
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-- probe0 => qsfp_tvalid_240b,
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-- probe1 => qsfp_aempty_240b,
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-- probe2 => qsfp_afull_240b,
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-- probe3 => qsfp_rx_data_ready,
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-- probe4 => qsfp_tvalid_512b,
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-- probe5 => qsfp_tready_512b,
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-- probe6 => qsfp_afull_512b,
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-- probe7 => qsfp_prog_full_512b,
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-- probe8 => qsfp_almost_empty_512b_pipe)
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-- );
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qsfp_tready_512b_pipe <= axis_dwidth_converter_512b_to_32b_tready when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tready;
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i_axis_dwidth_converter_512b_to_128b : entity work.axis_dwidth_converter_512b_to_128b
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port map (
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aclk => tx_device_clk_in, -- in
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aresetn => tx_device_clk_aresetn_in, -- in
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s_axis_tdata => qsfp_tdata_512b_pipe, -- in
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s_axis_tvalid => qsfp_tvalid_512b_pipe, -- in
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s_axis_tready => axis_dwidth_converter_512b_to_128b_tready, -- out
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m_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, -- out
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m_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, -- out
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m_axis_tready => qsfp_tready_128b -- in
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);
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-- i_axis_dwidth_converter_512b_to_32b : entity work.axis_dwidth_converter_512b_to_32b
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-- port map (
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-- aclk => tx_device_clk_in, -- in
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-- aresetn => tx_device_clk_aresetn_in, -- in
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-- s_axis_tdata => qsfp_tdata_512b_pipe, -- in
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-- s_axis_tvalid => qsfp_tvalid_512b_pipe, -- in
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-- s_axis_tready => axis_dwidth_converter_512b_to_32b_tready, -- out
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-- m_axis_tdata => axis_dwidth_converter_512b_to_32b_tdata_32b, -- out
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-- m_axis_tvalid => axis_dwidth_converter_512b_to_32b_tvalid_32b, -- out
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-- m_axis_tready => qsfp_tready_128b -- in
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-- );
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-- qsfp_tdata_128b <= axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tdata_128;
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-- qsfp_tvalid_128b <= axis_dwidth_converter_512b_to_32b_tvalid_32b when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tvalid_128;
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-- big FIFO before JESD TX PORT - actually 64 words deep
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i_tx_fifo_32kx128 : entity work.axis_data_fifo_32kx128
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port map (
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s_axis_aclk => tx_device_clk_in, -- in
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s_axis_aresetn => tx_device_clk_aresetn_in, -- in
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s_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, ---qsfp_tdata_128b, -- in
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s_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, --qsfp_tvalid_128b, -- in
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s_axis_tready => qsfp_tready_128b, -- out
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-- m_axis_aclk => tx_device_clk_in, -- in
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m_axis_tdata => tx_tdata_128b_out, -- out
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m_axis_tvalid => tx_tvalid_128b, -- out
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m_axis_tready => tx_tready_128b_ena, -- in
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almost_empty => tx_fifo_aempty_128b,-- out
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prog_empty => tx_fifo_prog_aempty_128 -- out
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);
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tx_tvalid_128b_ena <= tx_pre_buff_rdy_r and tx_tvalid_128b;
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tx_tready_128b_ena <= tx_pre_buff_rdy_r and tx_tready_128b_in;
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process(tx_device_clk_in)
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begin
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if (rising_edge(tx_device_clk_in)) then
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tx_fifo_aempty_128b_r <= tx_fifo_aempty_128b;
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if ((tx_fifo_aempty_128b = '1') and (tx_fifo_aempty_128b_r = '1')) then
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tx_pre_buff_rdy_r <= '0';
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elsif (tx_fifo_prog_aempty_128 = '0') then
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tx_pre_buff_rdy_r <= '1';
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end if;
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if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
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tx_tvalid_128b_cnt_r <= (others => '0');
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elsif (tx_tvalid_128b_ena = '1' and tx_tready_128b_ena = '1') then
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tx_tvalid_128b_cnt_r <= tx_tvalid_128b_cnt_r + 1;
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end if;
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end if;
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end process;
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tx_tvalid_128b_out <= tx_tvalid_128b_ena;
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end architecture arch_imp;
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