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alinx_z19_ad9082/ip_repo/qsfp_intfc_1_0/component.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>user.org</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>qsfp_intfc</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S00_AXI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_awaddr</spirit:name>
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<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_awprot</spirit:name>
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<spirit:name>AWVALID</spirit:name>
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<spirit:name>s00_axi_awvalid</spirit:name>
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<spirit:name>AWREADY</spirit:name>
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<spirit:name>s00_axi_awready</spirit:name>
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<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
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<spirit:name>WSTRB</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_wstrb</spirit:name>
</spirit:physicalPort>
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<spirit:name>WVALID</spirit:name>
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<spirit:name>WREADY</spirit:name>
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<spirit:name>BRESP</spirit:name>
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<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
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<spirit:name>s00_axi_araddr</spirit:name>
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<spirit:logicalPort>
<spirit:name>ARPROT</spirit:name>
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<spirit:name>ARREADY</spirit:name>
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<spirit:name>RDATA</spirit:name>
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<spirit:name>RRESP</spirit:name>
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<spirit:name>RREADY</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_rready</spirit:name>
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</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:parameter>
<spirit:name>WIZ_NUM_REG</spirit:name>
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
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<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S00_AXI_RST</spirit:name>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_aresetn</spirit:name>
</spirit:physicalPort>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
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</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S00_AXI_CLK</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
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<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
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<spirit:physicalPort>
<spirit:name>s00_axi_aclk</spirit:name>
</spirit:physicalPort>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:description>100 MHz</spirit:description>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ"/>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
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<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S00_AXI</spirit:name>
<spirit:addressBlock>
<spirit:name>S00_AXI_reg</spirit:name>
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<spirit:usage>register</spirit:usage>
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<spirit:parameter>
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
</spirit:parameter>
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<spirit:model>
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<spirit:view>
<spirit:name>xilinx_softwaredriver</spirit:name>
<spirit:displayName>Software Driver</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
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<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
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<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:name>bd_tcl</spirit:name>
<spirit:displayName>Block Diagram</spirit:displayName>
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<spirit:localName>bd_tcl_view_fileset</spirit:localName>
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<spirit:name>viewChecksum</spirit:name>
<spirit:value>45a2f450</spirit:value>
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</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>qsfp_intfc_v1_0</spirit:modelName>
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<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset</spirit:localName>
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<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset</spirit:localName>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:name>clk_125_in</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:name>clk_125_reset_n_in</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:name>clk_250_in</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wire>
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<spirit:port>
<spirit:name>clk_100_in</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:port>
<spirit:name>clk_100_reset_in</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_SI570_CLOCK_P</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_SI570_CLOCK_N</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX1_P</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wire>
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<spirit:port>
<spirit:name>QSFP1_TX1_N</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_RX1_P</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX2_P</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
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<spirit:name>QSFP1_TX2_N</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_RX2_P</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_RX2_N</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX3_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX3_N</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_RX3_P</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_RX3_N</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX4_P</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>QSFP1_TX4_N</spirit:name>
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