1530 lines
72 KiB
Verilog
1530 lines
72 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top #(
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parameter FPGA_REVISION_DATE = 32'h09222025,
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parameter MINOR_REV = 8'h02,
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parameter TX_JESD_L = 8,
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parameter TX_NUM_LINKS = 1,
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parameter RX_JESD_L = 8,
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parameter RX_NUM_LINKS = 1,
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parameter SHARED_DEVCLK = 0,
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parameter JESD_MODE = "8B10B"
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) (
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// input [12:0] gpio_bd_i,
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// output [ 7:0] gpio_bd_o,
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input QSFP1_INTL_LS,
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input QSFP1_MODPRSL_LS,
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output QSFP1_RESETL_LS,
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input QSFP1_RX1_N,
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input QSFP1_RX1_P,
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input QSFP1_RX2_N,
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input QSFP1_RX2_P,
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input QSFP1_RX3_N,
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input QSFP1_RX3_P,
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input QSFP1_RX4_N,
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input QSFP1_RX4_P,
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input QSFP1_SI570_CLOCK_N, //CLK2_N
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input QSFP1_SI570_CLOCK_P,
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output QSFP1_TX1_N,
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output QSFP1_TX1_P,
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output QSFP1_TX2_N,
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output QSFP1_TX2_P,
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output QSFP1_TX3_N,
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output QSFP1_TX3_P,
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output QSFP1_TX4_N,
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output QSFP1_TX4_P,
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input QSFP2_INTL_LS,
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input QSFP2_MODPRSL_LS,
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output QSFP2_RESETL_LS,
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input QSFP2_RX1_N,
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input QSFP2_RX1_P,
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input QSFP2_RX2_N,
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input QSFP2_RX2_P,
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input QSFP2_RX3_N,
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input QSFP2_RX3_P,
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input QSFP2_RX4_N,
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input QSFP2_RX4_P,
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input QSFP2_SI570_CLOCK_N,//CLK3_N
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input QSFP2_SI570_CLOCK_P,
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output QSFP2_TX1_N,
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output QSFP2_TX1_P,
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output QSFP2_TX2_N,
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output QSFP2_TX2_P,
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output QSFP2_TX3_N,
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output QSFP2_TX3_P,
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output QSFP2_TX4_N,
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output QSFP2_TX4_P,
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input QSFP3_INTL_LS,
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input QSFP3_MODPRSL_LS,
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output QSFP3_RESETL_LS,
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input QSFP3_RX1_N,
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input QSFP3_RX1_P,
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input QSFP3_RX2_N,
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input QSFP3_RX2_P,
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input QSFP3_RX3_N,
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input QSFP3_RX3_P,
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input QSFP3_RX4_N,
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input QSFP3_RX4_P,
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input QSFP3_SI570_CLOCK_N,//CLK1_N
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input QSFP3_SI570_CLOCK_P,
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output QSFP3_TX1_N,
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output QSFP3_TX1_P,
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output QSFP3_TX2_N,
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output QSFP3_TX2_P,
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output QSFP3_TX3_N,
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output QSFP3_TX3_P,
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output QSFP3_TX4_N,
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output QSFP3_TX4_P,
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input QSFP4_INTL_LS,
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input QSFP4_MODPRSL_LS,
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output QSFP4_RESETL_LS,
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input QSFP4_RX1_N,
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input QSFP4_RX1_P,
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input QSFP4_RX2_N,
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input QSFP4_RX2_P,
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input QSFP4_RX3_N,
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input QSFP4_RX3_P,
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input QSFP4_RX4_N,
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input QSFP4_RX4_P,
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input QSFP4_SI570_CLOCK_N,//CLK0_N
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input QSFP4_SI570_CLOCK_P,
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output QSFP4_TX1_N,
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output QSFP4_TX1_P,
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output QSFP4_TX2_N,
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output QSFP4_TX2_P,
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output QSFP4_TX3_N,
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output QSFP4_TX3_P,
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output QSFP4_TX4_N,
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output QSFP4_TX4_P,
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inout pll_scl,
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inout pll_sda,
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// FMC HPC IOs
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input [1:0] agc0,
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input [1:0] agc1,
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input [1:0] agc2,
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input [1:0] agc3,
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input clkin6_n,
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input clkin6_p,
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input clkin10_n,
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input clkin10_p,
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input clkin8_n,
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input clkin8_p,
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input fpga_refclk_in_n,
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input fpga_refclk_in_p,
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input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
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input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
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output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
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output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
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input fpga_syncin_0_n,
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input fpga_syncin_0_p,
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inout fpga_syncin_1_n,
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inout fpga_syncin_1_p,
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output fpga_syncout_0_n,
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output fpga_syncout_0_p,
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inout fpga_syncout_1_n,
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inout fpga_syncout_1_p,
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inout [10:0] gpio,
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inout hmc_gpio1,
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output hmc_sync,
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input [1:0] irqb,
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output rstb,
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output [1:0] rxen,
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output spi0_csb,
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input spi0_miso,
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output spi0_mosi,
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output spi0_sclk,
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output spi1_csb,
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output spi1_sclk,
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inout spi1_sdio,
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input sysref2_n,
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input sysref2_p,
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output [1:0] txen
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);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire [ 2:0] spi0_csn;
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wire [ 2:0] spi1_csn;
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wire spi1_mosi;
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wire spi1_miso;
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wire ref_clk;
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wire ref_clk_div2;
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wire ref_clk_div2_bufg;
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wire sysref;
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wire [TX_NUM_LINKS-1:0] tx_syncin;
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wire [RX_NUM_LINKS-1:0] rx_syncout;
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wire [7:0] rx_data_p_loc;
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wire [7:0] rx_data_n_loc;
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wire [7:0] tx_data_p_loc;
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wire [7:0] tx_data_n_loc;
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wire clkin6;
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wire clkin10;
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wire clkin8;
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wire clkin8_bufg;
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wire tx_device_clk;
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wire rx_device_clk_internal;
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wire rx_device_clk;
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wire clk_125;
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wire clk_125_aresetn;
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wire clk_250;
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wire clk_250_aresetn;
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wire vio_enable;
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wire vio_rstb;
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wire rstb_i;
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////
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wire rx_device_clk_1;
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wire rx_device_clk_aresetn;
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wire [255:0] adc_rx_tdata_256b;
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wire adc_rx_tvalid_256b;
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wire adc_rx_tdata_256b_overflow;
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wire adc_rx_fifo_tready_256b;
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////
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wire tx_device_clk_1;
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wire tx_device_clk_aresetn;
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wire [255:0] mem_xfer_tx_upload_tdata_256b;
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wire mem_xfer_tx_upload_tvalid_256b;
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wire mem_xfer_tx_upload_tready_256b;
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reg [31:0] mem_xfer_tx_upload_tvalid_256b_cnt_r = 32'h0;
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wire [255:0] dac_tx_tdata_256b;
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wire dac_tx_tvalid_256b;
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wire dac_tx_tready_256b;
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wire [255:0] dac_tx_tdata_256b_pipe;
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wire dac_tx_tvalid_256b_pipe;
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wire dac_tx_tready_256b_pipe;
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reg [31:0] dac_tx_tvalid_256b_cnt_r = 32'h0;
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////
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wire qsfp1_aclk;
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wire qsfp1_aresetn;
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wire [239:0] qsfp1_capture_tdata_240b;
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wire qsfp1_capture_tvalid_240b;
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wire qsfp1_capture_rx_data_ready;
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wire [31:0] qsfp1_capture_tvalid_240b_cnt;
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wire [31:0] qsfp1_capture_overflow_240b_cnt;
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wire [31:0] qsfp1_capture_fifo_aempty_512b_cnt;
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wire [31:0] qsfp1_capture_rx_data_ready_cnt;
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wire [239:0] qsfp1_playback_tdata_240b;
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wire qsfp1_playback_tvalid_240b;
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wire qsfp1_playback_tready_240b;
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wire [31:0] qsfp1_playback_tvalid_128b_cnt;
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wire [31:0] qsfp1_playback_tvalid_240b_cnt;
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////
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wire qsfp2_aclk;
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wire qsfp2_aresetn;
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wire [239:0] qsfp2_capture_tdata_240b;
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wire qsfp2_capture_tvalid_240b;
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wire qsfp2_capture_rx_data_ready;
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wire [31:0] qsfp2_capture_tvalid_240b_cnt;
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wire [31:0] qsfp2_capture_overflow_240b_cnt;
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wire [31:0] qsfp2_capture_fifo_aempty_512b_cnt;
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wire [31:0] qsfp2_capture_rx_data_ready_cnt;
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wire [239:0] qsfp2_playback_tdata_240b;
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wire qsfp2_playback_tvalid_240b;
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wire qsfp2_playback_tready_240b;
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wire [31:0] qsfp2_playback_tvalid_128b_cnt;
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wire [31:0] qsfp2_playback_tvalid_240b_cnt;
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////
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wire qsfp3_aclk;
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wire qsfp3_aresetn;
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wire [239:0] qsfp3_capture_tdata_240b;
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wire qsfp3_capture_tvalid_240b;
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wire qsfp3_capture_rx_data_ready;
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wire [31:0] qsfp3_capture_tvalid_240b_cnt;
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wire [31:0] qsfp3_capture_overflow_240b_cnt;
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wire [31:0] qsfp3_capture_fifo_aempty_512b_cnt;
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wire [31:0] qsfp3_capture_rx_data_ready_cnt;
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wire [239:0] qsfp3_playback_tdata_240b;
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wire qsfp3_playback_tvalid_240b;
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wire qsfp3_playback_tready_240b;
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wire [31:0] qsfp3_playback_tvalid_128b_cnt;
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wire [31:0] qsfp3_playback_tvalid_240b_cnt;
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////
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wire qsfp4_aclk;
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wire qsfp4_aresetn;
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wire [239:0] qsfp4_capture_tdata_240b;
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wire qsfp4_capture_tvalid_240b;
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wire qsfp4_capture_rx_data_ready;
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wire [31:0] qsfp4_capture_tvalid_240b_cnt;
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wire [31:0] qsfp4_capture_overflow_240b_cnt;
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wire [31:0] qsfp4_capture_fifo_aempty_512b_cnt;
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wire [31:0] qsfp4_capture_rx_data_ready_cnt;
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wire [239:0] qsfp4_playback_tdata_240b;
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wire qsfp4_playback_tvalid_240b;
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wire qsfp4_playback_tready_240b;
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wire [31:0] qsfp4_playback_tvalid_128b_cnt;
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wire [31:0] qsfp4_playback_tvalid_240b_cnt;
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////
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wire [255:0] tx_tdata_256b;
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wire tx_tvalid_256b;
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wire tx_tready_256b;
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reg [31:0] tx_tvalid_256b_cnt_r = 32'h0;
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// wire [255:0] dds_intfc_tdata_256b = 256'h0;
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// wire dds_intfc_tvalid_256b = 1'b0;
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// wire dds_intfc_tready_256b;
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wire [31:0] slv_reg9;
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wire [31:0] slv_reg10;
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wire [31:0] slv_reg31;
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wire [31:0] slv_reg38;
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wire [31:0] slv_reg45;
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wire [31:0] slv_reg52;
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wire [1:0] dac_src_data_sel;
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wire [1:0] vio_dac_src_data_sel;
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wire [1:0] dac_src_data_sel_i;
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wire chan1to4_mode_sel;
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wire playback_path_data_enable_n;
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wire clk_100;
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wire clk_100_aresetn;
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wire [31:0] M11_AXI_0_araddr;
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wire [2:0] M11_AXI_0_arprot;
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wire M11_AXI_0_arready;
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wire M11_AXI_0_arvalid;
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wire [31:0] M11_AXI_0_awaddr;
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wire [2:0] M11_AXI_0_awprot;
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wire M11_AXI_0_awready;
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wire M11_AXI_0_awvalid;
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wire M11_AXI_0_bready;
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wire [1:0] M11_AXI_0_bresp;
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wire M11_AXI_0_bvalid;
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wire [31:0] M11_AXI_0_rdata;
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wire M11_AXI_0_rready;
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wire [1:0] M11_AXI_0_rresp;
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wire M11_AXI_0_rvalid;
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wire [31:0] M11_AXI_0_wdata;
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wire M11_AXI_0_wready;
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wire [3:0] M11_AXI_0_wstrb;
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wire M11_AXI_0_wvalid;
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wire sda_i;
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wire sda_o;
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wire sda_t;
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wire scl_i;
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wire scl_o;
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wire scl_t;
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wire dac_tx_tready_en;
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wire vio_man_tx_tready;
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wire mxfe_rx_data_offload_s_axis_tready;
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wire [63:0] chan0_0_adc_rx_tdata_64b;
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wire [127:0] chan0_0_adc_rx_tdata_128b;
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wire chan0_0_adc_rx_tvalid_128b;
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wire chan0_0_adc_rx_tready_128b;
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wire [31:0] chan0_0_adc_rx_tvalid_128b_cnt;
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wire [63:0] chan0_1_adc_rx_tdata_64b;
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wire [127:0] chan0_1_adc_rx_tdata_128b;
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wire chan0_1_adc_rx_tvalid_128b;
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wire chan0_1_adc_rx_tready_128b;
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wire [31:0] chan0_1_adc_rx_tvalid_128b_cnt;
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wire [63:0] chan1_0_adc_rx_tdata_64b;
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wire [127:0] chan1_0_adc_rx_tdata_128b;
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wire chan1_0_adc_rx_tvalid_128b;
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wire chan1_0_adc_rx_tready_128b;
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wire [31:0] chan1_0_adc_rx_tvalid_128b_cnt;
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wire [63:0] chan1_1_adc_rx_tdata_64b;
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wire [127:0] chan1_1_adc_rx_tdata_128b;
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wire chan1_1_adc_rx_tvalid_128b;
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wire chan1_1_adc_rx_tready_128b;
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wire [31:0] chan1_1_adc_rx_tvalid_128b_cnt;
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wire [127:0] ch0_0_tx_tdata_128b;
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wire ch0_0_tx_tvalid_128b;
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wire [127:0] ch0_1_tx_tdata_128b;
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wire ch0_1_tx_tvalid_128b;
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wire [127:0] ch1_0_tx_tdata_128b;
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wire ch1_0_tx_tvalid_128b;
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wire [127:0] ch1_1_tx_tdata_128b;
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wire ch1_1_tx_tvalid_128b;
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wire [511:0] capture_dwidth_converter_512b_to_256b_tdata;
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wire capture_dwidth_converter_512b_to_256b_tvalid;
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wire capture_dwidth_converter_512b_to_256b_tready;
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wire capture_dwidth_converter_512b_to_256b_tready_i;
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wire [31:0] qsfp1_rx_overflow_128b_cnt;
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wire [31:0] qsfp2_rx_overflow_128b_cnt;
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wire [31:0] qsfp3_rx_overflow_128b_cnt;
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wire [31:0] qsfp4_rx_overflow_128b_cnt;
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wire [63:0] chan0_0_adc_rx_tdata_64b_pipe;
|
|
wire chan0_0_adc_rx_tvalid_64b_pipe;
|
|
wire chan0_0_adc_rx_tready_64b_pipe;
|
|
wire [63:0] chan0_1_adc_rx_tdata_64b_pipe;
|
|
wire chan0_1_adc_rx_tvalid_64b_pipe;
|
|
wire chan0_1_adc_rx_tready_64b_pipe;
|
|
|
|
reg [31:0] adc_rx_tvalid_256b_cnt_r = 32'h0;
|
|
|
|
wire [31:0] dac_chan0_s0;
|
|
wire [31:0] dac_chan0_s2;
|
|
wire [31:0] dac_chan0_s4;
|
|
wire [31:0] dac_chan0_s6;
|
|
|
|
wire [31:0] dac_chan0_s1;
|
|
wire [31:0] dac_chan0_s3;
|
|
wire [31:0] dac_chan0_s5;
|
|
wire [31:0] dac_chan0_s7;
|
|
|
|
wire [31:0] dac_chan1_s0;
|
|
wire [31:0] dac_chan1_s2;
|
|
wire [31:0] dac_chan1_s4;
|
|
wire [31:0] dac_chan1_s6;
|
|
|
|
wire [31:0] dac_chan1_s1;
|
|
wire [31:0] dac_chan1_s3;
|
|
wire [31:0] dac_chan1_s5;
|
|
wire [31:0] dac_chan1_s7;
|
|
|
|
wire [31:0] adc_chan0_s0;
|
|
wire [31:0] adc_chan1_s0;
|
|
wire [31:0] adc_chan0_s1;
|
|
wire [31:0] adc_chan1_s1;
|
|
wire [31:0] adc_chan0_s2;
|
|
wire [31:0] adc_chan1_s2;
|
|
wire [31:0] adc_chan0_s3;
|
|
wire [31:0] adc_chan1_s3;
|
|
|
|
|
|
////////////////////////////////////////////////////////////////
|
|
|
|
// instantiations
|
|
|
|
IBUFDS_GTE4 i_ibufds_ref_clk (
|
|
.CEB (1'd0),
|
|
.I (fpga_refclk_in_p),
|
|
.IB (fpga_refclk_in_n),
|
|
.O (ref_clk),
|
|
.ODIV2 (ref_clk_div2)
|
|
);
|
|
|
|
BUFG_GT i_bufgt_ref_clk (
|
|
.I (ref_clk_div2),
|
|
.CE (1'b1),
|
|
.CEMASK (1'b0),
|
|
.CLR (1'b0),
|
|
.CLRMASK (1'b0),
|
|
.DIV (3'b000),
|
|
.O (ref_clk_div2_bufg)
|
|
);
|
|
|
|
////
|
|
IBUFDS i_ibufds_sysref (
|
|
.I (sysref2_p),
|
|
.IB (sysref2_n),
|
|
.O (sysref)
|
|
);
|
|
|
|
/////
|
|
IBUFDS i_ibufds_clkin6 (
|
|
.I (clkin6_p),
|
|
.IB (clkin6_n),
|
|
.O (clkin6)
|
|
);
|
|
|
|
BUFG i_bufg_tx_device_clk (
|
|
.I (clkin6),
|
|
.O (tx_device_clk)
|
|
);
|
|
|
|
////
|
|
IBUFDS i_ibufds_clkin10 (
|
|
.I (clkin10_p),
|
|
.IB (clkin10_n),
|
|
.O (clkin10)
|
|
);
|
|
|
|
BUFG i_bufg_rx_device_clk (
|
|
.I (clkin10),
|
|
.O (rx_device_clk)
|
|
);
|
|
|
|
/////
|
|
IBUFDS_GTE4 i_ibufds_clkin8 (
|
|
.I (clkin8_p),
|
|
.IB (clkin8_n),
|
|
.CEB (1'b0),
|
|
.O (),
|
|
.ODIV2 (clkin8)
|
|
);
|
|
|
|
BUFG_GT i_bufgt_clkin8 (
|
|
.I (clkin8),
|
|
.CE (1'b1),
|
|
.CEMASK (1'b0),
|
|
.CLR (1'b0),
|
|
.CLRMASK (1'b0),
|
|
.DIV (3'b000),
|
|
.O (clkin8_bufg)
|
|
);
|
|
|
|
///
|
|
IBUFDS i_ibufds_syncin_0 (
|
|
.I (fpga_syncin_0_p),
|
|
.IB (fpga_syncin_0_n),
|
|
.O (tx_syncin[0])
|
|
);
|
|
|
|
OBUFDS i_obufds_syncout_0 (
|
|
.I (rx_syncout[0]),
|
|
.O (fpga_syncout_0_p),
|
|
.OB (fpga_syncout_0_n)
|
|
);
|
|
|
|
|
|
// assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
|
|
|
|
// spi
|
|
|
|
assign spi0_csb = spi0_csn[0];
|
|
assign spi1_csb = spi1_csn[0];
|
|
|
|
ad_3w_spi #(
|
|
.NUM_OF_SLAVES (1)
|
|
)
|
|
i_spi (
|
|
.spi_csn (spi1_csn[0]),
|
|
.spi_clk (spi1_sclk),
|
|
.spi_mosi (spi1_mosi),
|
|
.spi_miso (spi1_miso),
|
|
.spi_sdio (spi1_sdio),
|
|
.spi_dir ()
|
|
);
|
|
|
|
// gpios
|
|
|
|
ad_iobuf #(
|
|
.DATA_WIDTH (12)
|
|
)
|
|
i_iobuf (
|
|
.dio_t (gpio_t[43:32]),
|
|
.dio_i (gpio_o[43:32]),
|
|
.dio_o (gpio_i[43:32]),
|
|
.dio_p ({hmc_gpio1, // 43
|
|
gpio[10:0]}) // 42-32
|
|
);
|
|
|
|
assign gpio_i[44] = agc0[0];
|
|
assign gpio_i[45] = agc0[1];
|
|
assign gpio_i[46] = agc1[0];
|
|
assign gpio_i[47] = agc1[1];
|
|
assign gpio_i[48] = agc2[0];
|
|
assign gpio_i[49] = agc2[1];
|
|
assign gpio_i[50] = agc3[0];
|
|
assign gpio_i[51] = agc3[1];
|
|
assign gpio_i[52] = irqb[0];
|
|
assign gpio_i[53] = irqb[1];
|
|
|
|
assign hmc_sync = gpio_o[54];
|
|
assign rstb = gpio_o[55];
|
|
assign rxen[0] = gpio_o[56];
|
|
assign rxen[1] = gpio_o[57];
|
|
assign txen[0] = gpio_o[58];
|
|
assign txen[1] = gpio_o[59];
|
|
|
|
assign rstb = rstb_i;
|
|
|
|
generate
|
|
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B")
|
|
begin
|
|
assign tx_syncin[1] = fpga_syncin_1_p;
|
|
end
|
|
else
|
|
begin
|
|
ad_iobuf #(
|
|
.DATA_WIDTH (2)
|
|
)
|
|
i_syncin_iobuf (
|
|
.dio_t (gpio_t[61:60]),
|
|
.dio_i (gpio_o[61:60]),
|
|
.dio_o (gpio_i[61:60]),
|
|
.dio_p ({fpga_syncin_1_n, // 61
|
|
fpga_syncin_1_p})); // 60
|
|
end
|
|
|
|
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B")
|
|
begin
|
|
assign fpga_syncout_1_p = rx_syncout[1];
|
|
assign fpga_syncout_1_n = 0;
|
|
end
|
|
else
|
|
begin
|
|
ad_iobuf #(
|
|
.DATA_WIDTH(2)
|
|
)
|
|
i_syncout_iobuf (
|
|
.dio_t (gpio_t[63:62]),
|
|
.dio_i (gpio_o[63:62]),
|
|
.dio_o (gpio_i[63:62]),
|
|
.dio_p ({fpga_syncout_1_n, // 63
|
|
fpga_syncout_1_p}) // 62
|
|
);
|
|
end
|
|
endgenerate
|
|
/* Board GPIOS. Buttons, LEDs, etc... */
|
|
// assign gpio_i[20: 8] = gpio_bd_i;
|
|
// assign gpio_bd_o = gpio_o[7:0];
|
|
|
|
// vio_0 i_vio_0 (
|
|
// .clk (clk_125),
|
|
// .probe_in0 (gpio_o[7:0]), // 8
|
|
|
|
// .probe_out0 (gpio_i[20: 8]), // 13
|
|
// .probe_out1 (vio_enable), // 1
|
|
// .probe_out2 (vio_man_tx_tready), // 1
|
|
|
|
// .probe_out3 (vio_dac_src_data_sel), // 2
|
|
// .probe_out4 (vio_playback_path_data_enable_n) // 1
|
|
// );
|
|
|
|
assign dac_src_data_sel_i = dac_src_data_sel; //(vio_enable == 1'b1) ? vio_dac_src_data_sel : dac_src_data_sel;
|
|
|
|
/*
|
|
ila_0 i_ila_0 (
|
|
.clk (clk_125),
|
|
.probe0 (rstb_i),
|
|
.probe1 (spi0_csn[0]),
|
|
.probe2 (spi0_miso),
|
|
.probe3 (spi0_mosi),
|
|
.probe4 (spi1_csn),
|
|
.probe5 (spi0_sclk),
|
|
.probe6 (spi1_miso),
|
|
.probe7 (spi1_mosi),
|
|
.probe8 (spi1_sclk)
|
|
);
|
|
*/
|
|
// Unused GPIOs
|
|
assign gpio_i[59:54] = gpio_o[59:54];
|
|
assign gpio_i[94:64] = gpio_o[94:64];
|
|
assign gpio_i[31:21] = gpio_o[31:21];
|
|
assign gpio_i[7:0] = gpio_o[7:0];
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.gpio_i (gpio_i),
|
|
.gpio_o (gpio_o),
|
|
.gpio_t (gpio_t),
|
|
.spi0_csn (spi0_csn),
|
|
.spi0_miso (spi0_miso),
|
|
.spi0_mosi (spi0_mosi),
|
|
.spi0_sclk (spi0_sclk),
|
|
.spi1_csn (spi1_csn),
|
|
.spi1_miso (spi1_miso),
|
|
.spi1_mosi (spi1_mosi),
|
|
.spi1_sclk (spi1_sclk),
|
|
// FMC HPC
|
|
.rx_data_0_n (rx_data_n_loc[0]),
|
|
.rx_data_0_p (rx_data_p_loc[0]),
|
|
.rx_data_1_n (rx_data_n_loc[1]),
|
|
.rx_data_1_p (rx_data_p_loc[1]),
|
|
.rx_data_2_n (rx_data_n_loc[2]),
|
|
.rx_data_2_p (rx_data_p_loc[2]),
|
|
.rx_data_3_n (rx_data_n_loc[3]),
|
|
.rx_data_3_p (rx_data_p_loc[3]),
|
|
.rx_data_4_n (rx_data_n_loc[4]),
|
|
.rx_data_4_p (rx_data_p_loc[4]),
|
|
.rx_data_5_n (rx_data_n_loc[5]),
|
|
.rx_data_5_p (rx_data_p_loc[5]),
|
|
.rx_data_6_n (rx_data_n_loc[6]),
|
|
.rx_data_6_p (rx_data_p_loc[6]),
|
|
.rx_data_7_n (rx_data_n_loc[7]),
|
|
.rx_data_7_p (rx_data_p_loc[7]),
|
|
.tx_data_0_n (tx_data_n_loc[0]),
|
|
.tx_data_0_p (tx_data_p_loc[0]),
|
|
.tx_data_1_n (tx_data_n_loc[1]),
|
|
.tx_data_1_p (tx_data_p_loc[1]),
|
|
.tx_data_2_n (tx_data_n_loc[2]),
|
|
.tx_data_2_p (tx_data_p_loc[2]),
|
|
.tx_data_3_n (tx_data_n_loc[3]),
|
|
.tx_data_3_p (tx_data_p_loc[3]),
|
|
.tx_data_4_n (tx_data_n_loc[4]),
|
|
.tx_data_4_p (tx_data_p_loc[4]),
|
|
.tx_data_5_n (tx_data_n_loc[5]),
|
|
.tx_data_5_p (tx_data_p_loc[5]),
|
|
.tx_data_6_n (tx_data_n_loc[6]),
|
|
.tx_data_6_p (tx_data_p_loc[6]),
|
|
.tx_data_7_n (tx_data_n_loc[7]),
|
|
.tx_data_7_p (tx_data_p_loc[7]),
|
|
.ref_clk_q0 (ref_clk),
|
|
.ref_clk_q1 (ref_clk),
|
|
.rx_device_clk (rx_device_clk),
|
|
.tx_device_clk (tx_device_clk),
|
|
.rx_sync_0 (rx_syncout),
|
|
.tx_sync_0 (tx_syncin),
|
|
.rx_sysref_0 (sysref),
|
|
.tx_sysref_0 (sysref),
|
|
|
|
// these signals are sync to rx_device_clk
|
|
.rx_device_clk_out (rx_device_clk_1),
|
|
.rx_device_clk_aresetn_out (rx_device_clk_aresetn),
|
|
.packed_fifo_wr_data_out (adc_rx_tdata_256b), // out ADC Rx Data
|
|
.packed_fifo_wr_en_out (adc_rx_tvalid_256b), // out
|
|
.packed_fifo_wr_overflow_out (adc_rx_tdata_256b_overflow), // out
|
|
|
|
.tx_device_clk_out (tx_device_clk_1),
|
|
.tx_device_clk_aresetn_out (tx_device_clk_aresetn),
|
|
.mxfe_tx_data_offload_m_axis_tdata (mem_xfer_tx_upload_tdata_256b), // out mem transfer from uP
|
|
.mxfe_tx_data_offload_m_axis_tvalid (mem_xfer_tx_upload_tvalid_256b), // out
|
|
.mxfe_tx_data_offload_m_axis_tready (mem_xfer_tx_upload_tready_256b), // in
|
|
.mxfe_tx_data_offload_m_axis_tkeep (), // out
|
|
.mxfe_tx_data_offload_m_axis_tlast (), // out
|
|
|
|
.util_mxfe_upack_s_axis_tdata (dac_tx_tdata_256b_pipe ), // in DAC Tx Data
|
|
.util_mxfe_upack_s_axis_tvalid (dac_tx_tvalid_256b_pipe), // in
|
|
.util_mxfe_upack_s_axis_tready (dac_tx_tready_256b_pipe), // out
|
|
|
|
.sys_cpu_clk_out (clk_100),
|
|
.sys_cpu_aresetn_out (clk_100_aresetn),
|
|
.M11_AXI_0_araddr (M11_AXI_0_araddr),
|
|
.M11_AXI_0_arprot (M11_AXI_0_arprot),
|
|
.M11_AXI_0_arready (M11_AXI_0_arready),
|
|
.M11_AXI_0_arvalid (M11_AXI_0_arvalid),
|
|
.M11_AXI_0_awaddr (M11_AXI_0_awaddr),
|
|
.M11_AXI_0_awprot (M11_AXI_0_awprot),
|
|
.M11_AXI_0_awready (M11_AXI_0_awready),
|
|
.M11_AXI_0_awvalid (M11_AXI_0_awvalid),
|
|
.M11_AXI_0_bready (M11_AXI_0_bready),
|
|
.M11_AXI_0_bresp (M11_AXI_0_bresp),
|
|
.M11_AXI_0_bvalid (M11_AXI_0_bvalid),
|
|
.M11_AXI_0_rdata (M11_AXI_0_rdata),
|
|
.M11_AXI_0_rready (M11_AXI_0_rready),
|
|
.M11_AXI_0_rresp (M11_AXI_0_rresp),
|
|
.M11_AXI_0_rvalid (M11_AXI_0_rvalid),
|
|
.M11_AXI_0_wdata (M11_AXI_0_wdata),
|
|
.M11_AXI_0_wready (M11_AXI_0_wready),
|
|
.M11_AXI_0_wstrb (M11_AXI_0_wstrb),
|
|
.M11_AXI_0_wvalid (M11_AXI_0_wvalid),
|
|
|
|
.Res_0 (mxfe_rx_data_offload_s_axis_tready),
|
|
|
|
.pl_clk1_clk250_out (clk_250),
|
|
.pl_clk1_clk250_aresetn_out (clk_250_aresetn),
|
|
|
|
.pl_clk2_clk125_out (clk_125),
|
|
.pl_clk2_clk125_aresetn_out (clk_125_aresetn)
|
|
);
|
|
|
|
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
|
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
|
|
|
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
|
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
|
|
|
// ila_5 i_ila_rx (
|
|
// .clk (rx_device_clk_1),
|
|
// .probe0 (adc_rx_tdata_256b[15:0]), // 16
|
|
// .probe1 (adc_rx_tdata_256b[31:16]), // 16
|
|
// .probe2 (adc_rx_tdata_256b[47:32]), // 16
|
|
// .probe3 (adc_rx_tdata_256b[63:48]), // 16
|
|
// .probe4 (adc_rx_tdata_256b[79:64]), // 16
|
|
// .probe5 (adc_rx_tdata_256b[95:80]), // 16
|
|
// .probe6 (adc_rx_tdata_256b[111:96]), // 16
|
|
// .probe7 (adc_rx_tdata_256b[127:112]), // 16
|
|
// .probe8 (adc_rx_tdata_256b[143:128]), // 16
|
|
// .probe9 (adc_rx_tdata_256b[159:144]), // 16
|
|
// .probe10 (adc_rx_tdata_256b[175:160]), // 16
|
|
// .probe11 (adc_rx_tdata_256b[191:176]), // 16
|
|
// .probe12 (adc_rx_tdata_256b[207:192]), // 16
|
|
// .probe13 (adc_rx_tdata_256b[223:208]), // 16
|
|
// .probe14 (adc_rx_tdata_256b[239:224]), // 16
|
|
// .probe15 (adc_rx_tdata_256b[255:240]), // 16
|
|
// .probe16 (adc_rx_tvalid_256b), // 1
|
|
// .probe17 (adc_rx_fifo_tready_256b) // 1
|
|
// );
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
qsfp_intfc_v1_0 #(
|
|
.FPGA_REVISION_DATE (FPGA_REVISION_DATE),
|
|
.MINOR_REV (MINOR_REV),
|
|
// Parameters of Axi Slave Bus Interface S00_AXI
|
|
.C_S00_AXI_DATA_WIDTH (32),
|
|
.C_S00_AXI_ADDR_WIDTH (8)
|
|
)
|
|
i_qsfp_intfc_v1_0 (
|
|
.clk_125_in (clk_125),
|
|
.clk_125_reset_n_in (clk_125_aresetn),
|
|
|
|
.clk_250_in (clk_250),
|
|
.clk_250_reset_n_in (clk_250_aresetn),
|
|
|
|
.rx_device_clk_in (rx_device_clk_1),
|
|
.tx_device_clk_in (tx_device_clk_1),
|
|
|
|
.clkin8_in (clkin8_bufg),
|
|
// .sysref_in (sysref),
|
|
.ref_clk_div2_in (ref_clk_div2_bufg),
|
|
///////////
|
|
.QSFP1_SI570_CLOCK_P (QSFP1_SI570_CLOCK_P),
|
|
.QSFP1_SI570_CLOCK_N (QSFP1_SI570_CLOCK_N),
|
|
.QSFP1_TX1_P (QSFP1_TX1_P),
|
|
.QSFP1_TX1_N (QSFP1_TX1_N),
|
|
.QSFP1_RX1_P (QSFP1_RX1_P),
|
|
.QSFP1_RX1_N (QSFP1_RX1_N),
|
|
|
|
.QSFP1_TX2_P (QSFP1_TX2_P),
|
|
.QSFP1_TX2_N (QSFP1_TX2_N),
|
|
.QSFP1_RX2_P (QSFP1_RX2_P),
|
|
.QSFP1_RX2_N (QSFP1_RX2_N),
|
|
|
|
.QSFP1_TX3_P (QSFP1_TX3_P),
|
|
.QSFP1_TX3_N (QSFP1_TX3_N),
|
|
.QSFP1_RX3_P (QSFP1_RX3_P),
|
|
.QSFP1_RX3_N (QSFP1_RX3_N),
|
|
|
|
.QSFP1_TX4_P (QSFP1_TX4_P),
|
|
.QSFP1_TX4_N (QSFP1_TX4_N),
|
|
.QSFP1_RX4_P (QSFP1_RX4_P),
|
|
.QSFP1_RX4_N (QSFP1_RX4_N),
|
|
|
|
.QSFP1_RESETL_LS (QSFP1_RESETL_LS),
|
|
.QSFP1_MODPRSL_LS (QSFP1_MODPRSL_LS),
|
|
.QSFP1_INTL_LS (QSFP1_INTL_LS),
|
|
///////////
|
|
.QSFP2_SI570_CLOCK_P (QSFP2_SI570_CLOCK_P),
|
|
.QSFP2_SI570_CLOCK_N (QSFP2_SI570_CLOCK_N),
|
|
.QSFP2_TX1_P (QSFP2_TX1_P),
|
|
.QSFP2_TX1_N (QSFP2_TX1_N),
|
|
.QSFP2_RX1_P (QSFP2_RX1_P),
|
|
.QSFP2_RX1_N (QSFP2_RX1_N),
|
|
|
|
.QSFP2_TX2_P (QSFP2_TX2_P),
|
|
.QSFP2_TX2_N (QSFP2_TX2_N),
|
|
.QSFP2_RX2_P (QSFP2_RX2_P),
|
|
.QSFP2_RX2_N (QSFP2_RX2_N),
|
|
|
|
.QSFP2_TX3_P (QSFP2_TX3_P),
|
|
.QSFP2_TX3_N (QSFP2_TX3_N),
|
|
.QSFP2_RX3_P (QSFP2_RX3_P),
|
|
.QSFP2_RX3_N (QSFP2_RX3_N),
|
|
|
|
.QSFP2_TX4_P (QSFP2_TX4_P),
|
|
.QSFP2_TX4_N (QSFP2_TX4_N),
|
|
.QSFP2_RX4_P (QSFP2_RX4_P),
|
|
.QSFP2_RX4_N (QSFP2_RX4_N),
|
|
|
|
.QSFP2_RESETL_LS (QSFP2_RESETL_LS),
|
|
.QSFP2_MODPRSL_LS (QSFP2_MODPRSL_LS),
|
|
.QSFP2_INTL_LS (QSFP2_INTL_LS),
|
|
///////////
|
|
.QSFP3_SI570_CLOCK_P (QSFP3_SI570_CLOCK_P),
|
|
.QSFP3_SI570_CLOCK_N (QSFP3_SI570_CLOCK_N),
|
|
.QSFP3_TX1_P (QSFP3_TX1_P),
|
|
.QSFP3_TX1_N (QSFP3_TX1_N),
|
|
.QSFP3_RX1_P (QSFP3_RX1_P),
|
|
.QSFP3_RX1_N (QSFP3_RX1_N),
|
|
|
|
.QSFP3_TX2_P (QSFP3_TX2_P),
|
|
.QSFP3_TX2_N (QSFP3_TX2_N),
|
|
.QSFP3_RX2_P (QSFP3_RX2_P),
|
|
.QSFP3_RX2_N (QSFP3_RX2_N),
|
|
|
|
.QSFP3_TX3_P (QSFP3_TX3_P),
|
|
.QSFP3_TX3_N (QSFP3_TX3_N),
|
|
.QSFP3_RX3_P (QSFP3_RX3_P),
|
|
.QSFP3_RX3_N (QSFP3_RX3_N),
|
|
|
|
.QSFP3_TX4_P (QSFP3_TX4_P),
|
|
.QSFP3_TX4_N (QSFP3_TX4_N),
|
|
.QSFP3_RX4_P (QSFP3_RX4_P),
|
|
.QSFP3_RX4_N (QSFP3_RX4_N),
|
|
|
|
.QSFP3_RESETL_LS (QSFP3_RESETL_LS),
|
|
.QSFP3_MODPRSL_LS (QSFP3_MODPRSL_LS),
|
|
.QSFP3_INTL_LS (QSFP3_INTL_LS),
|
|
///////////
|
|
.QSFP4_SI570_CLOCK_P (QSFP4_SI570_CLOCK_P),
|
|
.QSFP4_SI570_CLOCK_N (QSFP4_SI570_CLOCK_N),
|
|
.QSFP4_TX1_P (QSFP4_TX1_P),
|
|
.QSFP4_TX1_N (QSFP4_TX1_N),
|
|
.QSFP4_RX1_P (QSFP4_RX1_P),
|
|
.QSFP4_RX1_N (QSFP4_RX1_N),
|
|
|
|
.QSFP4_TX2_P (QSFP4_TX2_P),
|
|
.QSFP4_TX2_N (QSFP4_TX2_N),
|
|
.QSFP4_RX2_P (QSFP4_RX2_P),
|
|
.QSFP4_RX2_N (QSFP4_RX2_N),
|
|
|
|
.QSFP4_TX3_P (QSFP4_TX3_P),
|
|
.QSFP4_TX3_N (QSFP4_TX3_N),
|
|
.QSFP4_RX3_P (QSFP4_RX3_P),
|
|
.QSFP4_RX3_N (QSFP4_RX3_N),
|
|
|
|
.QSFP4_TX4_P (QSFP4_TX4_P),
|
|
.QSFP4_TX4_N (QSFP4_TX4_N),
|
|
.QSFP4_RX4_P (QSFP4_RX4_P),
|
|
.QSFP4_RX4_N (QSFP4_RX4_N),
|
|
|
|
.QSFP4_RESETL_LS (QSFP4_RESETL_LS),
|
|
.QSFP4_MODPRSL_LS (QSFP4_MODPRSL_LS),
|
|
.QSFP4_INTL_LS (QSFP4_INTL_LS),
|
|
///////
|
|
.qsfp1_aclk_out (qsfp1_aclk),
|
|
.qsfp1_aresetn_out (qsfp1_aresetn),
|
|
.qsfp1_rx_tdata_240b_out (qsfp1_capture_tdata_240b),
|
|
.qsfp1_rx_tvalid_240b_out (qsfp1_capture_tvalid_240b),
|
|
.qsfp1_rx_data_ready_in (qsfp1_capture_rx_data_ready),
|
|
|
|
.qsfp1_tx_tdata_240b_in (qsfp1_playback_tdata_240b),
|
|
.qsfp1_tx_tvalid_240b_in (qsfp1_playback_tvalid_240b),
|
|
.qsfp1_tx_tready_240b_out (qsfp1_playback_tready_240b),
|
|
|
|
.qsfp1_rx_tvalid_240b_cnt_in (qsfp1_capture_tvalid_240b_cnt),
|
|
.qsfp1_rx_overflow_240b_cnt_in (qsfp1_capture_overflow_240b_cnt),
|
|
.qsfp1_rx_fifo_aempty_512b_cnt_in (qsfp1_capture_fifo_aempty_512b_cnt),
|
|
.qsfp1_rx_data_ready_cnt_in (qsfp1_capture_rx_data_ready_cnt),
|
|
.qsfp1_tx_tvalid_128b_cnt_in (qsfp1_playback_tvalid_128b_cnt),
|
|
.qsfp1_tx_tvalid_240b_cnt_in (qsfp1_playback_tvalid_240b_cnt),
|
|
.qsfp1_rx_overflow_128b_cnt_in (qsfp1_rx_overflow_128b_cnt),
|
|
///////
|
|
.qsfp2_aclk_out (qsfp2_aclk),
|
|
.qsfp2_aresetn_out (qsfp2_aresetn),
|
|
.qsfp2_rx_tdata_240b_out (qsfp2_capture_tdata_240b),
|
|
.qsfp2_rx_tvalid_240b_out (qsfp2_capture_tvalid_240b),
|
|
.qsfp2_rx_data_ready_in (qsfp2_capture_rx_data_ready),
|
|
|
|
.qsfp2_tx_tdata_240b_in (qsfp2_playback_tdata_240b),
|
|
.qsfp2_tx_tvalid_240b_in (qsfp2_playback_tvalid_240b),
|
|
.qsfp2_tx_tready_240b_out (qsfp2_playback_tready_240b),
|
|
|
|
.qsfp2_rx_tvalid_240b_cnt_in (qsfp2_capture_tvalid_240b_cnt),
|
|
.qsfp2_rx_overflow_240b_cnt_in (qsfp2_capture_overflow_240b_cnt),
|
|
.qsfp2_rx_fifo_aempty_512b_cnt_in (qsfp2_capture_fifo_aempty_512b_cnt),
|
|
.qsfp2_rx_data_ready_cnt_in (qsfp2_capture_rx_data_ready_cnt),
|
|
.qsfp2_tx_tvalid_128b_cnt_in (qsfp2_playback_tvalid_128b_cnt),
|
|
.qsfp2_tx_tvalid_240b_cnt_in (qsfp2_playback_tvalid_240b_cnt),
|
|
.qsfp2_rx_overflow_128b_cnt_in (qsfp2_rx_overflow_128b_cnt),
|
|
///////
|
|
.qsfp3_aclk_out (qsfp3_aclk),
|
|
.qsfp3_aresetn_out (qsfp3_aresetn),
|
|
.qsfp3_rx_tdata_240b_out (qsfp3_capture_tdata_240b),
|
|
.qsfp3_rx_tvalid_240b_out (qsfp3_capture_tvalid_240b),
|
|
.qsfp3_rx_data_ready_in (qsfp3_capture_rx_data_ready),
|
|
|
|
.qsfp3_tx_tdata_240b_in (qsfp3_playback_tdata_240b),
|
|
.qsfp3_tx_tvalid_240b_in (qsfp3_playback_tvalid_240b),
|
|
.qsfp3_tx_tready_240b_out (qsfp3_playback_tready_240b),
|
|
|
|
.qsfp3_rx_tvalid_240b_cnt_in (qsfp3_capture_tvalid_240b_cnt),
|
|
.qsfp3_rx_overflow_240b_cnt_in (qsfp3_capture_overflow_240b_cnt),
|
|
.qsfp3_rx_fifo_aempty_512b_cnt_in (qsfp3_capture_fifo_aempty_512b_cnt),
|
|
.qsfp3_rx_data_ready_cnt_in (qsfp3_capture_rx_data_ready_cnt),
|
|
.qsfp3_tx_tvalid_128b_cnt_in (qsfp3_playback_tvalid_128b_cnt),
|
|
.qsfp3_tx_tvalid_240b_cnt_in (qsfp3_playback_tvalid_240b_cnt),
|
|
.qsfp3_rx_overflow_128b_cnt_in (qsfp3_rx_overflow_128b_cnt),
|
|
///////
|
|
.qsfp4_aclk_out (qsfp4_aclk),
|
|
.qsfp4_aresetn_out (qsfp4_aresetn),
|
|
.qsfp4_rx_tdata_240b_out (qsfp4_capture_tdata_240b),
|
|
.qsfp4_rx_tvalid_240b_out (qsfp4_capture_tvalid_240b),
|
|
.qsfp4_rx_data_ready_in (qsfp4_capture_rx_data_ready),
|
|
|
|
.qsfp4_tx_tdata_240b_in (qsfp4_playback_tdata_240b),
|
|
.qsfp4_tx_tvalid_240b_in (qsfp4_playback_tvalid_240b),
|
|
.qsfp4_tx_tready_240b_out (qsfp4_playback_tready_240b),
|
|
|
|
.qsfp4_rx_tvalid_240b_cnt_in (qsfp4_capture_tvalid_240b_cnt),
|
|
.qsfp4_rx_overflow_240b_cnt_in (qsfp4_capture_overflow_240b_cnt),
|
|
.qsfp4_rx_fifo_aempty_512b_cnt_in (qsfp4_capture_fifo_aempty_512b_cnt),
|
|
.qsfp4_rx_data_ready_cnt_in (qsfp4_capture_rx_data_ready_cnt),
|
|
.qsfp4_tx_tvalid_128b_cnt_in (qsfp4_playback_tvalid_128b_cnt),
|
|
.qsfp4_tx_tvalid_240b_cnt_in (qsfp4_playback_tvalid_240b_cnt),
|
|
.qsfp4_rx_overflow_128b_cnt_in (qsfp4_rx_overflow_128b_cnt),
|
|
|
|
.tx_tvalid_256b_cnt_in (tx_tvalid_256b_cnt_r),
|
|
.mem_xfer_tx_upload_tvalid_256b_cnt_in (mem_xfer_tx_upload_tvalid_256b_cnt_r),
|
|
.dac_tx_tvalid_256b_cnt_in (dac_tx_tvalid_256b_cnt_r),
|
|
.adc_rx_tvalid_256b_cnt_in (adc_rx_tvalid_256b_cnt_r),
|
|
|
|
.cnt_reset_out (cnt_reset),
|
|
|
|
.slv_reg9_out (slv_reg9),
|
|
.slv_reg10_out (slv_reg10),
|
|
|
|
.slv_reg31_out (slv_reg31),
|
|
.slv_reg38_out (slv_reg38),
|
|
.slv_reg45_out (slv_reg45),
|
|
.slv_reg52_out (slv_reg52),
|
|
|
|
.sys_cpu_clk_in (clk_100),
|
|
.s00_axi_aresetn_in (clk_100_aresetn),
|
|
.s00_axi_awaddr (M11_AXI_0_awaddr[7:0]),
|
|
.s00_axi_awprot (M11_AXI_0_awprot),
|
|
.s00_axi_awvalid (M11_AXI_0_awvalid),
|
|
.s00_axi_awready (M11_AXI_0_awready),
|
|
.s00_axi_wdata (M11_AXI_0_wdata),
|
|
.s00_axi_wstrb (M11_AXI_0_wstrb),
|
|
.s00_axi_wvalid (M11_AXI_0_wvalid),
|
|
.s00_axi_wready (M11_AXI_0_wready),
|
|
.s00_axi_bresp (M11_AXI_0_bresp),
|
|
.s00_axi_bvalid (M11_AXI_0_bvalid),
|
|
.s00_axi_bready (M11_AXI_0_bready),
|
|
.s00_axi_araddr (M11_AXI_0_araddr[7:0]),
|
|
.s00_axi_arprot (M11_AXI_0_arprot),
|
|
.s00_axi_arvalid (M11_AXI_0_arvalid),
|
|
.s00_axi_arready (M11_AXI_0_arready),
|
|
.s00_axi_rdata (M11_AXI_0_rdata),
|
|
.s00_axi_rresp (M11_AXI_0_rresp),
|
|
.s00_axi_rvalid (M11_AXI_0_rvalid),
|
|
.s00_axi_rready (M11_AXI_0_rready)
|
|
);
|
|
|
|
//assign qsfp_loopback_en = slv_reg10[0]; //0x8000_0028
|
|
//assign = slv_reg10[7:1];
|
|
assign dac_src_data_sel = slv_reg10[9:8];
|
|
//assign = slv_reg10[11:10];
|
|
assign chan1to4_mode_sel = slv_reg10[12];
|
|
//assign = slv_reg10[14:13];
|
|
//assign = slv_reg10[15];
|
|
//assign = slv_reg10[30:16];
|
|
assign playback_path_data_enable_n = slv_reg10[31];
|
|
|
|
|
|
///////////////////////////////
|
|
// ****>>>> FROM QSFP1 CAPTURE INTERFACE
|
|
qsfp_capture_intfc_128 i_qsfp1_capture_intfc_128 (
|
|
.qsfp_capture_aclk_in (qsfp1_aclk),
|
|
.qsfp_capture_aresetn_in (qsfp1_aresetn),
|
|
.qsfp_capture_tdata_240b_in (qsfp1_capture_tdata_240b),
|
|
.qsfp_capture_tvalid_240b_in (qsfp1_capture_tvalid_240b),
|
|
.qsfp_capture_tvalid_240b_cnt_out (qsfp1_capture_tvalid_240b_cnt),
|
|
.qsfp_capture_fifo_aempty_512b_cnt_out (qsfp1_capture_fifo_aempty_512b_cnt),
|
|
.qsfp_capture_iq_240b_to_512b_overflow_cnt_out (qsfp1_capture_overflow_240b_cnt),
|
|
|
|
.qsfp_capture_rx_data_ready_out (qsfp1_capture_rx_data_ready),
|
|
.qsfp_capture_rx_data_ready_cnt_out (qsfp1_capture_rx_data_ready_cnt),
|
|
|
|
.tx_device_clk_in (tx_device_clk_1),
|
|
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
|
|
.tx_tdata_128b_out (ch0_0_tx_tdata_128b), // out
|
|
.tx_tvalid_128b_out (ch0_0_tx_tvalid_128b), // out
|
|
.tx_tready_128b_in (capture_dwidth_converter_512b_to_256b_tready_i), // in
|
|
.tx_tvalid_128b_cnt_out (ch0_0_tx_tvalid_128b_cnt),
|
|
|
|
.chan1to4_mode_sel_in (chan1to4_mode_sel),
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
qsfp_capture_intfc_128 i_qsfp2_capture_intfc_128 (
|
|
.qsfp_capture_aclk_in (qsfp2_aclk),
|
|
.qsfp_capture_aresetn_in (qsfp2_aresetn),
|
|
.qsfp_capture_tdata_240b_in (qsfp2_capture_tdata_240b),
|
|
.qsfp_capture_tvalid_240b_in (qsfp2_capture_tvalid_240b),
|
|
.qsfp_capture_tvalid_240b_cnt_out (qsfp2_capture_tvalid_240b_cnt),
|
|
.qsfp_capture_fifo_aempty_512b_cnt_out (qsfp2_capture_fifo_aempty_512b_cnt),
|
|
.qsfp_capture_iq_240b_to_512b_overflow_cnt_out (qsfp2_capture_overflow_240b_cnt),
|
|
|
|
.qsfp_capture_rx_data_ready_out (qsfp2_capture_rx_data_ready),
|
|
.qsfp_capture_rx_data_ready_cnt_out (qsfp2_capture_rx_data_ready_cnt),
|
|
|
|
.tx_device_clk_in (tx_device_clk_1),
|
|
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
|
|
.tx_tdata_128b_out (ch0_1_tx_tdata_128b), // out
|
|
.tx_tvalid_128b_out (ch0_1_tx_tvalid_128b), // out
|
|
.tx_tready_128b_in (capture_dwidth_converter_512b_to_256b_tready_i), // in
|
|
.tx_tvalid_128b_cnt_out (ch0_1_tx_tvalid_128b_cnt),
|
|
|
|
.chan1to4_mode_sel_in (chan1to4_mode_sel),
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
qsfp_capture_intfc_128 i_qsfp3_capture_intfc_128 (
|
|
.qsfp_capture_aclk_in (qsfp3_aclk),
|
|
.qsfp_capture_aresetn_in (qsfp3_aresetn),
|
|
.qsfp_capture_tdata_240b_in (qsfp3_capture_tdata_240b),
|
|
.qsfp_capture_tvalid_240b_in (qsfp3_capture_tvalid_240b),
|
|
.qsfp_capture_tvalid_240b_cnt_out (qsfp3_capture_tvalid_240b_cnt),
|
|
.qsfp_capture_fifo_aempty_512b_cnt_out (qsfp3_capture_fifo_aempty_512b_cnt),
|
|
.qsfp_capture_iq_240b_to_512b_overflow_cnt_out (qsfp3_capture_overflow_240b_cnt),
|
|
|
|
.qsfp_capture_rx_data_ready_out (qsfp3_capture_rx_data_ready),
|
|
.qsfp_capture_rx_data_ready_cnt_out (qsfp3_capture_rx_data_ready_cnt),
|
|
|
|
.tx_device_clk_in (tx_device_clk_1),
|
|
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
|
|
.tx_tdata_128b_out (ch1_0_tx_tdata_128b),
|
|
.tx_tvalid_128b_out (ch1_0_tx_tvalid_128b),
|
|
.tx_tready_128b_in (capture_dwidth_converter_512b_to_256b_tready_i),
|
|
.tx_tvalid_128b_cnt_out (ch1_0_tx_tvalid_128b_cnt),
|
|
|
|
.chan1to4_mode_sel_in (chan1to4_mode_sel),
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
qsfp_capture_intfc_128 i_qsfp4_capture_intfc_128 (
|
|
.qsfp_capture_aclk_in (qsfp4_aclk),
|
|
.qsfp_capture_aresetn_in (qsfp4_aresetn),
|
|
.qsfp_capture_tdata_240b_in (qsfp4_capture_tdata_240b),
|
|
.qsfp_capture_tvalid_240b_in (qsfp4_capture_tvalid_240b),
|
|
.qsfp_capture_tvalid_240b_cnt_out (qsfp4_capture_tvalid_240b_cnt),
|
|
.qsfp_capture_fifo_aempty_512b_cnt_out (qsfp4_capture_fifo_aempty_512b_cnt),
|
|
.qsfp_capture_iq_240b_to_512b_overflow_cnt_out (qsfp4_capture_overflow_240b_cnt),
|
|
|
|
.qsfp_capture_rx_data_ready_out (qsfp4_capture_rx_data_ready),
|
|
.qsfp_capture_rx_data_ready_cnt_out (qsfp4_capture_rx_data_ready_cnt),
|
|
|
|
.tx_device_clk_in (tx_device_clk_1),
|
|
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
|
|
.tx_tdata_128b_out (ch1_1_tx_tdata_128b),
|
|
.tx_tvalid_128b_out (ch1_1_tx_tvalid_128b),
|
|
.tx_tready_128b_in (capture_dwidth_converter_512b_to_256b_tready_i),
|
|
.tx_tvalid_128b_cnt_out (ch1_1_tx_tvalid_128b_cnt),
|
|
|
|
.chan1to4_mode_sel_in (chan1to4_mode_sel),
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
assign dac_chan0_s0 = ch0_0_tx_tdata_128b[31:0];
|
|
assign dac_chan0_s2 = ch0_0_tx_tdata_128b[63:32];
|
|
assign dac_chan0_s4 = ch0_0_tx_tdata_128b[95:64];
|
|
assign dac_chan0_s6 = ch0_0_tx_tdata_128b[127:96];
|
|
|
|
assign dac_chan0_s1 = ch0_1_tx_tdata_128b[31:0];
|
|
assign dac_chan0_s3 = ch0_1_tx_tdata_128b[63:32];
|
|
assign dac_chan0_s5 = ch0_1_tx_tdata_128b[95:64];
|
|
assign dac_chan0_s7 = ch0_1_tx_tdata_128b[127:96];
|
|
|
|
assign dac_chan1_s0 = ch1_0_tx_tdata_128b[31:0];
|
|
assign dac_chan1_s2 = ch1_0_tx_tdata_128b[63:32];
|
|
assign dac_chan1_s4 = ch1_0_tx_tdata_128b[95:64];
|
|
assign dac_chan1_s6 = ch1_0_tx_tdata_128b[127:96];
|
|
|
|
assign dac_chan1_s1 = ch1_1_tx_tdata_128b[31:0];
|
|
assign dac_chan1_s3 = ch1_1_tx_tdata_128b[63:32];
|
|
assign dac_chan1_s5 = ch1_1_tx_tdata_128b[95:64];
|
|
assign dac_chan1_s7 = ch1_1_tx_tdata_128b[127:96];
|
|
|
|
assign capture_dwidth_converter_512b_to_256b_tdata = {
|
|
dac_chan1_s7, // s7 255:224
|
|
dac_chan0_s7, // s7 223:192
|
|
dac_chan1_s6, // s6 191:160
|
|
dac_chan0_s6, // s6 159:128
|
|
dac_chan1_s5, // s5 127:96
|
|
dac_chan0_s5, // s5 95:64
|
|
dac_chan1_s4, // s4 63:32
|
|
dac_chan0_s4, // s4 31:0
|
|
|
|
dac_chan1_s3, // s3 255:224
|
|
dac_chan0_s3, // s3 223:192
|
|
dac_chan1_s2, // s2 191:160
|
|
dac_chan0_s2, // s2 159:128
|
|
dac_chan1_s1, // s1 127:96
|
|
dac_chan0_s1, // s1 95:64
|
|
dac_chan1_s0, // s0 63:32
|
|
dac_chan0_s0 // s0 31:0
|
|
};
|
|
|
|
assign capture_dwidth_converter_512b_to_256b_tvalid = ch0_0_tx_tvalid_128b & ch0_1_tx_tvalid_128b & ch1_0_tx_tvalid_128b & ch1_1_tx_tvalid_128b;
|
|
assign capture_dwidth_converter_512b_to_256b_tready_i = capture_dwidth_converter_512b_to_256b_tvalid & capture_dwidth_converter_512b_to_256b_tready;
|
|
|
|
axis_dwidth_converter_512b_to_256b i_axis_dwidth_converter_512b_to_256b (
|
|
.aclk (tx_device_clk_1), // in
|
|
.aresetn (tx_device_clk_aresetn), // in
|
|
.s_axis_tdata (capture_dwidth_converter_512b_to_256b_tdata), // in
|
|
.s_axis_tvalid (capture_dwidth_converter_512b_to_256b_tvalid), // in
|
|
.s_axis_tready (capture_dwidth_converter_512b_to_256b_tready), // out
|
|
|
|
.m_axis_tdata (tx_tdata_256b), // out
|
|
.m_axis_tvalid (tx_tvalid_256b), // out
|
|
.m_axis_tready (tx_tready_256b) // in
|
|
);
|
|
|
|
// assign tx_tdata_256b = 256'h0;
|
|
// assign tx_tvalid_256b = 1'b0;
|
|
|
|
|
|
///////////////////////////////////////////
|
|
//// to DAC - data source from DMA Tx axis data, QSFP1 and DDS_INTFC
|
|
/////////////////////////////////////////////
|
|
// assign dac_tx_tdata_256b = (dac_src_data_sel_i[0] == 1'b0) ? mem_xfer_tx_upload_tdata_256b : tx_tdata_256b;
|
|
//// (dac_src_data_sel_i == 2'b01) ? tx_tdata_256b :
|
|
//// (dac_src_data_sel_i == 2'b10) ? dds_intfc_tdata_256b : 256'h0;
|
|
//
|
|
// assign dac_tx_tvalid_256b = (dac_src_data_sel_i[0] == 1'b0) ? mem_xfer_tx_upload_tvalid_256b : tx_tvalid_256b;
|
|
//// (dac_src_data_sel_i == 2'b01) ? tx_tvalid_256b :
|
|
//// (dac_src_data_sel_i == 2'b10) ? dds_intfc_tvalid_256b : 1'b0;
|
|
//
|
|
// assign mem_xfer_tx_upload_tready_256b = (dac_src_data_sel_i[0] == 1'b0) ? dac_tx_tready_256b : 1'b0;
|
|
// assign tx_tready_256b = (dac_src_data_sel_i[0] == 1'b1) ? dac_tx_tready_256b : 1'b0;
|
|
//// assign dds_intfc_tready_256b = (dac_src_data_sel_i _i == 2'b10) ? dac_tx_tready_256b : 1'b0;
|
|
|
|
|
|
axis_mux_256b i_dac_axis_mux_256b (
|
|
.aclk (tx_device_clk_1), // input
|
|
.aresetn (tx_device_clk_aresetn), // input
|
|
.aselect (dac_src_data_sel_i[0]), // input
|
|
|
|
.s0_axis_tdata (mem_xfer_tx_upload_tdata_256b), // input
|
|
.s0_axis_tvalid (mem_xfer_tx_upload_tvalid_256b), // input
|
|
.s0_axis_tready (mem_xfer_tx_upload_tready_256b), // output
|
|
|
|
.s1_axis_tdata (tx_tdata_256b), // input
|
|
.s1_axis_tvalid (tx_tvalid_256b), // input
|
|
.s1_axis_tready (tx_tready_256b), // output
|
|
|
|
.m_axis_tdata (dac_tx_tdata_256b), // output
|
|
.m_axis_tvalid (dac_tx_tvalid_256b), // output
|
|
.m_axis_tready (dac_tx_tready_256b) // input
|
|
);
|
|
|
|
axis_register_slice_256b i_util_mxfe_upack_reg_slice_256b (
|
|
.aclk (tx_device_clk_1), // in
|
|
.aresetn (tx_device_clk_aresetn), // in
|
|
.s_axis_tdata (dac_tx_tdata_256b), // in
|
|
.s_axis_tvalid (dac_tx_tvalid_256b), // in
|
|
.s_axis_tready (dac_tx_tready_256b), // out
|
|
.m_axis_tdata (dac_tx_tdata_256b_pipe), // out
|
|
.m_axis_tvalid (dac_tx_tvalid_256b_pipe), // out
|
|
.m_axis_tready (dac_tx_tready_en) // in
|
|
);
|
|
|
|
assign dac_tx_tready_en = dac_tx_tready_256b_pipe; //(vio_man_tx_tready == 1'b0) ? dac_tx_tready_256b_pipe : vio_man_tx_tready;
|
|
|
|
// ila_5 i_ila_tx (
|
|
// .clk (tx_device_clk_1),
|
|
// .probe0 (dac_tx_tdata_256b_pipe[15:0]), // 16
|
|
// .probe1 (dac_tx_tdata_256b_pipe[31:16]), // 16
|
|
// .probe2 (dac_tx_tdata_256b_pipe[47:32]), // 16
|
|
// .probe3 (dac_tx_tdata_256b_pipe[63:48]), // 16
|
|
// .probe4 (dac_tx_tdata_256b_pipe[79:64]), // 16
|
|
// .probe5 (dac_tx_tdata_256b_pipe[95:80]), // 16
|
|
// .probe6 (dac_tx_tdata_256b_pipe[111:96]), // 16
|
|
// .probe7 (dac_tx_tdata_256b_pipe[127:112]), // 16
|
|
// .probe8 (dac_tx_tdata_256b_pipe[143:128]), // 16
|
|
// .probe9 (dac_tx_tdata_256b_pipe[159:144]), // 16
|
|
// .probe10 (dac_tx_tdata_256b_pipe[175:160]), // 16
|
|
// .probe11 (dac_tx_tdata_256b_pipe[191:176]), // 16
|
|
// .probe12 (dac_tx_tdata_256b_pipe[207:192]), // 16
|
|
// .probe13 (dac_tx_tdata_256b_pipe[223:208]), // 16
|
|
// .probe14 (dac_tx_tdata_256b_pipe[239:224]), // 16
|
|
// .probe15 (dac_tx_tdata_256b_pipe[255:240]), // 16
|
|
// .probe16 (dac_tx_tvalid_256b_pipe), // 1
|
|
// .probe17 (dac_tx_tready_en) // 1
|
|
// );
|
|
|
|
///////////////////////////////
|
|
// ****>>>> TO QSFP4 PLAYBACK INTERFACE
|
|
|
|
|
|
assign adc_chan0_s0 = adc_rx_tdata_256b[31:0];
|
|
assign adc_chan1_s0 = adc_rx_tdata_256b[63:32];
|
|
assign adc_chan0_s1 = adc_rx_tdata_256b[95:64];
|
|
assign adc_chan1_s1 = adc_rx_tdata_256b[127:96];
|
|
assign adc_chan0_s2 = adc_rx_tdata_256b[159:128];
|
|
assign adc_chan1_s2 = adc_rx_tdata_256b[191:160];
|
|
assign adc_chan0_s3 = adc_rx_tdata_256b[223:192];
|
|
assign adc_chan1_s3 = adc_rx_tdata_256b[255:224];
|
|
|
|
|
|
assign chan0_0_adc_rx_tdata_64b = {adc_chan0_s2, adc_chan0_s0}; // ch0 - s2:s0
|
|
|
|
axis_register_slice_64b i_chan0_0_axis_register_slice_64b (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan0_0_adc_rx_tdata_64b), // in
|
|
.s_axis_tvalid (adc_rx_tvalid_256b), // in
|
|
.s_axis_tready (), // out
|
|
|
|
.m_axis_tdata (chan0_0_adc_rx_tdata_64b_pipe), // out
|
|
.m_axis_tvalid (chan0_0_adc_rx_tvalid_64b_pipe), // out
|
|
.m_axis_tready (chan0_0_adc_rx_tready_64b_pipe) // in
|
|
);
|
|
|
|
axis_dwidth_converter_64b_to_128b i_axis_dwidth_converter_64b_to_128b_chan0_0 (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan0_0_adc_rx_tdata_64b_pipe), // in
|
|
.s_axis_tvalid (chan0_0_adc_rx_tvalid_64b_pipe), // in
|
|
.s_axis_tready (chan0_0_adc_rx_tready_64b_pipe), // out
|
|
|
|
.m_axis_tdata (chan0_0_adc_rx_tdata_128b), // out
|
|
.m_axis_tvalid (chan0_0_adc_rx_tvalid_128b), // out
|
|
.m_axis_tready (chan0_0_adc_rx_tready_128b) // in
|
|
);
|
|
|
|
qsfp_playback_intfc_128 i_qsfp1_playback_intfc (
|
|
.rx_device_clk_in (rx_device_clk_1),
|
|
.rx_device_clk_aresetn_in (rx_device_clk_aresetn),
|
|
.rx_tdata_128b_in (chan0_0_adc_rx_tdata_128b),
|
|
.rx_tvalid_128b_in (chan0_0_adc_rx_tvalid_128b),
|
|
.rx_tready_128b_out (chan0_0_adc_rx_tready_128b),
|
|
.rx_tvalid_128b_cnt_out (chan0_0_adc_rx_tvalid_128b_cnt),
|
|
.rx_tvalid_128b_en_cnt_out (qsfp1_playback_tvalid_128b_cnt),
|
|
.rx_overflow_128b_cnt_out (qsfp1_rx_overflow_128b_cnt),
|
|
.playback_data_path_enable_n_in (playback_path_data_enable_n),
|
|
|
|
.qsfp_playback_aclk_in (qsfp1_aclk),
|
|
.qsfp_playback_aresetn_in (qsfp1_aresetn),
|
|
.qsfp_playback_tdata_240b_out (qsfp1_playback_tdata_240b),
|
|
.qsfp_playback_tvalid_240b_out (qsfp1_playback_tvalid_240b),
|
|
.qsfp_playback_tready_240b_in (qsfp1_playback_tready_240b),
|
|
.qsfp_playback_tvalid_240b_cnt_out (qsfp1_playback_tvalid_240b_cnt),
|
|
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
/////////////////////////////////////
|
|
assign chan0_1_adc_rx_tdata_64b = {adc_chan0_s3, adc_chan0_s1}; // ch0 - s3:s1
|
|
|
|
axis_register_slice_64b i_chan0_1_axis_register_slice_64b (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan0_1_adc_rx_tdata_64b), // in
|
|
.s_axis_tvalid (adc_rx_tvalid_256b), // in
|
|
.s_axis_tready (), // out
|
|
|
|
.m_axis_tdata (chan0_1_adc_rx_tdata_64b_pipe), // out
|
|
.m_axis_tvalid (chan0_1_adc_rx_tvalid_64b_pipe), // out
|
|
.m_axis_tready (chan0_1_adc_rx_tready_64b_pipe) // in
|
|
);
|
|
|
|
axis_dwidth_converter_64b_to_128b i_axis_dwidth_converter_64b_to_128b_chan0_1 (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan0_1_adc_rx_tdata_64b_pipe), // in
|
|
.s_axis_tvalid (chan0_1_adc_rx_tvalid_64b_pipe), // in
|
|
.s_axis_tready (chan0_1_adc_rx_tready_64b_pipe), // out
|
|
|
|
.m_axis_tdata (chan0_1_adc_rx_tdata_128b), // out
|
|
.m_axis_tvalid (chan0_1_adc_rx_tvalid_128b), // out
|
|
.m_axis_tready (chan0_1_adc_rx_tready_128b) // in
|
|
);
|
|
|
|
qsfp_playback_intfc_128 i_qsfp2_playback_intfc (
|
|
.rx_device_clk_in (rx_device_clk_1),
|
|
.rx_device_clk_aresetn_in (rx_device_clk_aresetn),
|
|
.rx_tdata_128b_in (chan0_1_adc_rx_tdata_128b),
|
|
.rx_tvalid_128b_in (chan0_1_adc_rx_tvalid_128b),
|
|
.rx_tready_128b_out (chan0_1_adc_rx_tready_128b),
|
|
.rx_tvalid_128b_cnt_out (chan0_1_adc_rx_tvalid_128b_cnt),
|
|
.rx_tvalid_128b_en_cnt_out (qsfp2_playback_tvalid_128b_cnt),
|
|
.rx_overflow_128b_cnt_out (qsfp2_rx_overflow_128b_cnt),
|
|
.playback_data_path_enable_n_in (playback_path_data_enable_n),
|
|
|
|
.qsfp_playback_aclk_in (qsfp2_aclk),
|
|
.qsfp_playback_aresetn_in (qsfp2_aresetn),
|
|
.qsfp_playback_tdata_240b_out (qsfp2_playback_tdata_240b),
|
|
.qsfp_playback_tvalid_240b_out (qsfp2_playback_tvalid_240b),
|
|
.qsfp_playback_tready_240b_in (qsfp2_playback_tready_240b),
|
|
.qsfp_playback_tvalid_240b_cnt_out (qsfp2_playback_tvalid_240b_cnt),
|
|
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
///////////////////////////////////////
|
|
assign chan1_0_adc_rx_tdata_64b = {adc_chan1_s2, adc_chan1_s0}; // ch1 - s2:s0
|
|
|
|
axis_dwidth_converter_64b_to_128b i_axis_dwidth_converter_64b_to_128b_chan1_0 (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan1_0_adc_rx_tdata_64b), // in
|
|
.s_axis_tvalid (adc_rx_tvalid_256b), // in
|
|
.s_axis_tready (), // out
|
|
|
|
.m_axis_tdata (chan1_0_adc_rx_tdata_128b), // out
|
|
.m_axis_tvalid (chan1_0_adc_rx_tvalid_128b), // out
|
|
.m_axis_tready (chan1_0_adc_rx_tready_128b) // in
|
|
);
|
|
|
|
qsfp_playback_intfc_128 i_qsfp3_playback_intfc (
|
|
.rx_device_clk_in (rx_device_clk_1),
|
|
.rx_device_clk_aresetn_in (rx_device_clk_aresetn),
|
|
.rx_tdata_128b_in (chan1_0_adc_rx_tdata_128b),
|
|
.rx_tvalid_128b_in (chan1_0_adc_rx_tvalid_128b),
|
|
.rx_tready_128b_out (chan1_0_adc_rx_tready_128b),
|
|
.rx_tvalid_128b_cnt_out (chan1_0_adc_rx_tvalid_128b_cnt),
|
|
.rx_tvalid_128b_en_cnt_out (qsfp3_playback_tvalid_128b_cnt),
|
|
.rx_overflow_128b_cnt_out (qsfp3_rx_overflow_128b_cnt),
|
|
.playback_data_path_enable_n_in (playback_path_data_enable_n),
|
|
|
|
.qsfp_playback_aclk_in (qsfp3_aclk),
|
|
.qsfp_playback_aresetn_in (qsfp3_aresetn),
|
|
.qsfp_playback_tdata_240b_out (qsfp3_playback_tdata_240b),
|
|
.qsfp_playback_tvalid_240b_out (qsfp3_playback_tvalid_240b),
|
|
.qsfp_playback_tready_240b_in (qsfp3_playback_tready_240b),
|
|
.qsfp_playback_tvalid_240b_cnt_out (qsfp3_playback_tvalid_240b_cnt),
|
|
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
/////////////////////////////////////
|
|
assign chan1_1_adc_rx_tdata_64b = {adc_chan1_s3, adc_chan1_s1}; // ch1 - s3:s1
|
|
|
|
axis_dwidth_converter_64b_to_128b i_axis_dwidth_converter_64b_to_128b_chan1_1 (
|
|
.aclk (rx_device_clk_1), // in
|
|
.aresetn (rx_device_clk_aresetn), // in
|
|
.s_axis_tdata (chan1_1_adc_rx_tdata_64b), // in
|
|
.s_axis_tvalid (adc_rx_tvalid_256b), // in
|
|
.s_axis_tready (), // out
|
|
|
|
.m_axis_tdata (chan1_1_adc_rx_tdata_128b), // out
|
|
.m_axis_tvalid (chan1_1_adc_rx_tvalid_128b), // out
|
|
.m_axis_tready (chan1_1_adc_rx_tready_128b) // in
|
|
);
|
|
|
|
qsfp_playback_intfc_128 i_qsfp4_playback_intfc (
|
|
.rx_device_clk_in (rx_device_clk_1),
|
|
.rx_device_clk_aresetn_in (rx_device_clk_aresetn),
|
|
.rx_tdata_128b_in (chan1_1_adc_rx_tdata_128b),
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|
.rx_tvalid_128b_in (chan1_1_adc_rx_tvalid_128b),
|
|
.rx_tready_128b_out (chan1_1_adc_rx_tready_128b),
|
|
.rx_tvalid_128b_cnt_out (chan1_1_adc_rx_tvalid_128b_cnt),
|
|
.rx_tvalid_128b_en_cnt_out (qsfp4_playback_tvalid_128b_cnt),
|
|
.rx_overflow_128b_cnt_out (qsfp4_rx_overflow_128b_cnt),
|
|
.playback_data_path_enable_n_in (playback_path_data_enable_n),
|
|
|
|
.qsfp_playback_aclk_in (qsfp4_aclk),
|
|
.qsfp_playback_aresetn_in (qsfp4_aresetn),
|
|
.qsfp_playback_tdata_240b_out (qsfp4_playback_tdata_240b),
|
|
.qsfp_playback_tvalid_240b_out (qsfp4_playback_tvalid_240b),
|
|
.qsfp_playback_tready_240b_in (qsfp4_playback_tready_240b),
|
|
.qsfp_playback_tvalid_240b_cnt_out (qsfp4_playback_tvalid_240b_cnt),
|
|
|
|
.cnt_reset_in (cnt_reset)
|
|
);
|
|
|
|
|
|
always @(posedge tx_device_clk_1)
|
|
begin
|
|
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
|
|
mem_xfer_tx_upload_tvalid_256b_cnt_r <= 32'h0;
|
|
else if (mem_xfer_tx_upload_tvalid_256b == 1'b1 && mem_xfer_tx_upload_tready_256b == 1'b1)
|
|
mem_xfer_tx_upload_tvalid_256b_cnt_r <= mem_xfer_tx_upload_tvalid_256b_cnt_r + 1;
|
|
end
|
|
|
|
always @(posedge tx_device_clk_1)
|
|
begin
|
|
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
|
|
dac_tx_tvalid_256b_cnt_r <= 32'h0;
|
|
else if (dac_tx_tvalid_256b_pipe == 1'b1 && dac_tx_tready_en == 1'b1)
|
|
dac_tx_tvalid_256b_cnt_r <= dac_tx_tvalid_256b_cnt_r + 1;
|
|
end
|
|
|
|
always @(posedge tx_device_clk_1)
|
|
begin
|
|
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
|
|
tx_tvalid_256b_cnt_r <= 32'h0;
|
|
else if (tx_tvalid_256b == 1'b1 && tx_tready_256b == 1'b1)
|
|
tx_tvalid_256b_cnt_r <= tx_tvalid_256b_cnt_r + 1;
|
|
end
|
|
|
|
always @(posedge rx_device_clk_1)
|
|
begin
|
|
if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
|
|
adc_rx_tvalid_256b_cnt_r <= 32'h0;
|
|
else if (adc_rx_tvalid_256b == 1'b1)
|
|
adc_rx_tvalid_256b_cnt_r <= adc_rx_tvalid_256b_cnt_r + 1;
|
|
end
|
|
|
|
//////////////////////////
|
|
si5332_wrapper i_si5332_wrapper (
|
|
.clk_100_in (clk_100),
|
|
.clk_100_areset_in (~clk_100_aresetn),
|
|
|
|
.sda_in (sda_i),
|
|
.sda_out (sda_o),
|
|
.sda_t_out (sda_t),
|
|
|
|
.scl_in (scl_i),
|
|
.scl_out (scl_o),
|
|
.scl_t_out (scl_t)
|
|
);
|
|
|
|
IOBUF i_scl_iobuf (
|
|
.O (scl_i),
|
|
.I (scl_o),
|
|
.IO (pll_scl),
|
|
.T (scl_t)
|
|
);
|
|
|
|
IOBUF i_sda_iobuf (
|
|
.O (sda_i),
|
|
.I (sda_o),
|
|
.IO (pll_sda),
|
|
.T (sda_t)
|
|
);
|
|
|
|
|
|
endmodule
|