174 lines
5.0 KiB
Verilog
174 lines
5.0 KiB
Verilog
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
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//Date : Thu Mar 5 18:53:36 2026
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//Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
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//Command : generate_target raw_eth_wrapper.bd
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//Design : raw_eth_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module raw_eth_wrapper_cmac_4
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(axil_clk_0,
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axil_resetn_0,
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clk_100_0,
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clk_100_reset_0,
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cmac_gt_0_grx_n,
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cmac_gt_0_grx_p,
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cmac_gt_0_gtx_n,
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cmac_gt_0_gtx_p,
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cmac_refclk_0_clk_n,
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cmac_refclk_0_clk_p,
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m_axis_aclk,
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m_axis_aresetn,
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m_axis_tdata,
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m_axis_tready,
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m_axis_tvalid,
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s_axil_0_araddr,
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s_axil_0_arprot,
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s_axil_0_arready,
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s_axil_0_arvalid,
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s_axil_0_awaddr,
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s_axil_0_awprot,
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s_axil_0_awready,
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s_axil_0_awvalid,
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s_axil_0_bready,
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s_axil_0_bresp,
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s_axil_0_bvalid,
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s_axil_0_rdata,
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s_axil_0_rready,
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s_axil_0_rresp,
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s_axil_0_rvalid,
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s_axil_0_wdata,
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s_axil_0_wready,
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s_axil_0_wstrb,
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s_axil_0_wvalid,
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s_axis_aresetn,
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s_axis_clk,
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s_axis_tdata,
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s_axis_tready,
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s_axis_tvalid);
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input axil_clk_0;
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input axil_resetn_0;
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input clk_100_0;
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input clk_100_reset_0;
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input [3:0]cmac_gt_0_grx_n;
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input [3:0]cmac_gt_0_grx_p;
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output [3:0]cmac_gt_0_gtx_n;
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output [3:0]cmac_gt_0_gtx_p;
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input cmac_refclk_0_clk_n;
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input cmac_refclk_0_clk_p;
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input m_axis_aclk;
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input m_axis_aresetn;
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output [511:0]m_axis_tdata;
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input m_axis_tready;
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output m_axis_tvalid;
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input [31:0]s_axil_0_araddr;
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input [2:0]s_axil_0_arprot;
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output s_axil_0_arready;
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input s_axil_0_arvalid;
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input [31:0]s_axil_0_awaddr;
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input [2:0]s_axil_0_awprot;
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output s_axil_0_awready;
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input s_axil_0_awvalid;
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input s_axil_0_bready;
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output [1:0]s_axil_0_bresp;
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output s_axil_0_bvalid;
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output [31:0]s_axil_0_rdata;
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input s_axil_0_rready;
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output [1:0]s_axil_0_rresp;
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output s_axil_0_rvalid;
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input [31:0]s_axil_0_wdata;
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output s_axil_0_wready;
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input [3:0]s_axil_0_wstrb;
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input s_axil_0_wvalid;
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input s_axis_aresetn;
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input s_axis_clk;
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input [511:0]s_axis_tdata;
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output s_axis_tready;
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input s_axis_tvalid;
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wire axil_clk_0;
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wire axil_resetn_0;
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wire clk_100_0;
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wire clk_100_reset_0;
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wire [3:0]cmac_gt_0_grx_n;
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wire [3:0]cmac_gt_0_grx_p;
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wire [3:0]cmac_gt_0_gtx_n;
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wire [3:0]cmac_gt_0_gtx_p;
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wire cmac_refclk_0_clk_n;
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wire cmac_refclk_0_clk_p;
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wire m_axis_aclk;
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wire m_axis_aresetn;
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wire [511:0]m_axis_tdata;
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wire m_axis_tready;
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wire m_axis_tvalid;
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wire [31:0]s_axil_0_araddr;
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wire [2:0]s_axil_0_arprot;
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wire s_axil_0_arready;
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wire s_axil_0_arvalid;
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wire [31:0]s_axil_0_awaddr;
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wire [2:0]s_axil_0_awprot;
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wire s_axil_0_awready;
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wire s_axil_0_awvalid;
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wire s_axil_0_bready;
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wire [1:0]s_axil_0_bresp;
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wire s_axil_0_bvalid;
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wire [31:0]s_axil_0_rdata;
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wire s_axil_0_rready;
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wire [1:0]s_axil_0_rresp;
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wire s_axil_0_rvalid;
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wire [31:0]s_axil_0_wdata;
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wire s_axil_0_wready;
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wire [3:0]s_axil_0_wstrb;
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wire s_axil_0_wvalid;
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wire s_axis_aresetn;
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wire s_axis_clk;
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wire [511:0]s_axis_tdata;
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wire s_axis_tready;
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wire s_axis_tvalid;
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raw_eth_cmac_4 raw_eth_cmac_4_i
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(.axil_clk_0(axil_clk_0),
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.axil_resetn_0(axil_resetn_0),
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.clk_100_0(clk_100_0),
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.clk_100_reset_0(clk_100_reset_0),
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.cmac_gt_0_grx_n(cmac_gt_0_grx_n),
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.cmac_gt_0_grx_p(cmac_gt_0_grx_p),
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.cmac_gt_0_gtx_n(cmac_gt_0_gtx_n),
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.cmac_gt_0_gtx_p(cmac_gt_0_gtx_p),
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.cmac_refclk_0_clk_n(cmac_refclk_0_clk_n),
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.cmac_refclk_0_clk_p(cmac_refclk_0_clk_p),
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.m_axis_aclk(m_axis_aclk),
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.m_axis_aresetn(m_axis_aresetn),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tready(m_axis_tready),
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.m_axis_tvalid(m_axis_tvalid),
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.s_axil_0_araddr(s_axil_0_araddr),
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.s_axil_0_arprot(s_axil_0_arprot),
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.s_axil_0_arready(s_axil_0_arready),
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.s_axil_0_arvalid(s_axil_0_arvalid),
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.s_axil_0_awaddr(s_axil_0_awaddr),
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.s_axil_0_awprot(s_axil_0_awprot),
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.s_axil_0_awready(s_axil_0_awready),
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.s_axil_0_awvalid(s_axil_0_awvalid),
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.s_axil_0_bready(s_axil_0_bready),
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.s_axil_0_bresp(s_axil_0_bresp),
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.s_axil_0_bvalid(s_axil_0_bvalid),
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.s_axil_0_rdata(s_axil_0_rdata),
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.s_axil_0_rready(s_axil_0_rready),
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.s_axil_0_rresp(s_axil_0_rresp),
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.s_axil_0_rvalid(s_axil_0_rvalid),
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.s_axil_0_wdata(s_axil_0_wdata),
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.s_axil_0_wready(s_axil_0_wready),
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.s_axil_0_wstrb(s_axil_0_wstrb),
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.s_axil_0_wvalid(s_axil_0_wvalid),
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.s_axis_aresetn(s_axis_aresetn),
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.s_axis_clk(s_axis_clk),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tready(s_axis_tready),
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.s_axis_tvalid(s_axis_tvalid));
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endmodule
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