80 lines
2.0 KiB
VHDL
80 lines
2.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer: Jason M Blevins
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--
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-- Create Date: 01/05/2026 11:59:12 AM
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-- Design Name:
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-- Module Name: eth_flowctrl_rx - behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity eth_flowctrl_rx is
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Port (
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clk : in STD_LOGIC;
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resetn : in STD_LOGIC;
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rx_pause : in STD_LOGIC;
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rx_pause_quanta8 : in STD_LOGIC_VECTOR(15 downto 0);
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rx_pause_cnt : out std_logic_vector(31 downto 0);
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pause : out STD_LOGIC
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);
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end eth_flowctrl_rx;
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architecture behavioral of eth_flowctrl_rx is
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signal pause_r : std_logic := '0';
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signal cnt_r : unsigned(15 downto 0) := (others => '0');
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signal rx_pause_cnt_r : unsigned(31 downto 0) := (others => '0');
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begin
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pause <= pause_r;
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rx_pause_cnt <= std_logic_vector(rx_pause_cnt_r);
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process(clk)
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begin
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if(rising_edge(clk))then
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if(resetn = '0')then
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cnt_r <= (others => '0');
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pause_r <= '0';
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rx_pause_cnt_r <= (others => '0');
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else
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if(rx_pause = '1')then
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rx_pause_cnt_r <= rx_pause_cnt_r +1;
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cnt_r <= unsigned(rx_pause_quanta8);
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if(unsigned(rx_pause_quanta8) = 0)then
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pause_r <= '0';
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else
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pause_r <= '1';
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end if;
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else
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if(cnt_r > 0)then
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cnt_r <= cnt_r -1;
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end if;
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if(cnt_r = 1)then
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pause_r <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavioral;
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