652 lines
33 KiB
Tcl
652 lines
33 KiB
Tcl
|
|
################################################################
|
|
# This is a generated script based on design: raw_eth_test
|
|
#
|
|
# Though there are limitations about the generated script,
|
|
# the main purpose of this utility is to make learning
|
|
# IP Integrator Tcl commands easier.
|
|
################################################################
|
|
|
|
namespace eval _tcl {
|
|
proc get_script_folder {} {
|
|
set script_path [file normalize [info script]]
|
|
set script_folder [file dirname $script_path]
|
|
return $script_folder
|
|
}
|
|
}
|
|
variable script_folder
|
|
set script_folder [_tcl::get_script_folder]
|
|
|
|
################################################################
|
|
# Check if script is running in correct Vivado version.
|
|
################################################################
|
|
set scripts_vivado_version 2023.2
|
|
set current_vivado_version [version -short]
|
|
|
|
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|
puts ""
|
|
if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
|
|
|
|
} else {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
|
|
|
}
|
|
|
|
return 1
|
|
}
|
|
|
|
################################################################
|
|
# START
|
|
################################################################
|
|
|
|
# To test this script, run the following commands from Vivado Tcl console:
|
|
# source raw_eth_test_script.tcl
|
|
|
|
|
|
# The design that will be created by this Tcl script contains the following
|
|
# module references:
|
|
# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker
|
|
|
|
# Please add the sources of those modules before sourcing this Tcl script.
|
|
|
|
|
|
set bCheckIPsPassed 1
|
|
##################################################################
|
|
# CHECK IPs
|
|
##################################################################
|
|
set bCheckIPs 1
|
|
if { $bCheckIPs == 1 } {
|
|
set list_check_ips "\
|
|
xilinx.com:ip:cmac_usplus:3.1\
|
|
xilinx.com:ip:system_ila:1.1\
|
|
xilinx.com:ip:util_vector_logic:2.0\
|
|
xilinx.com:ip:c_counter_binary:12.0\
|
|
xilinx.com:ip:smartconnect:1.0\
|
|
xilinx.com:ip:proc_sys_reset:5.0\
|
|
user:user:axi_regs_32:1.0\
|
|
xilinx.com:ip:xlslice:1.0\
|
|
xilinx.com:ip:xlconcat:2.1\
|
|
xilinx.com:ip:xpm_cdc_gen:1.0\
|
|
xilinx.com:ip:xlconstant:1.1\
|
|
"
|
|
|
|
set list_ips_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
|
|
foreach ip_vlnv $list_check_ips {
|
|
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
if { $ip_obj eq "" } {
|
|
lappend list_ips_missing $ip_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_ips_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
set bCheckIPsPassed 0
|
|
}
|
|
|
|
}
|
|
|
|
##################################################################
|
|
# CHECK Modules
|
|
##################################################################
|
|
set bCheckModules 1
|
|
if { $bCheckModules == 1 } {
|
|
set list_check_mods "\
|
|
eth_flowctrl_rx\
|
|
eth_frame_packer\
|
|
eth_flowctrl_tx\
|
|
eth_frame_unpacker\
|
|
"
|
|
|
|
set list_mods_missing ""
|
|
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
|
|
|
foreach mod_vlnv $list_check_mods {
|
|
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
|
lappend list_mods_missing $mod_vlnv
|
|
}
|
|
}
|
|
|
|
if { $list_mods_missing ne "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
|
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
|
set bCheckIPsPassed 0
|
|
}
|
|
}
|
|
|
|
if { $bCheckIPsPassed != 1 } {
|
|
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
return 3
|
|
}
|
|
|
|
##################################################################
|
|
# DESIGN PROCs
|
|
##################################################################
|
|
|
|
|
|
# Hierarchical cell: ETH_regs
|
|
proc create_hier_cell_ETH_regs { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -from 47 -to 0 dest_addr
|
|
create_bd_pin -dir O -from 47 -to 0 source_addr
|
|
create_bd_pin -dir O -from 15 -to 0 EtherType
|
|
create_bd_pin -dir I cmac_clk
|
|
create_bd_pin -dir I aclk
|
|
create_bd_pin -dir I aresetn
|
|
create_bd_pin -dir O -from 0 -to 0 prog_full_manual
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_on
|
|
create_bd_pin -dir O -from 31 -to 0 prog_full_off
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt
|
|
|
|
# Create instance: axi_regs_32_0, and set properties
|
|
set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ]
|
|
|
|
# Create instance: xlslice_0, and set properties
|
|
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_0
|
|
|
|
|
|
# Create instance: xlconcat_0, and set properties
|
|
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_0
|
|
|
|
|
|
# Create instance: xlconcat_1, and set properties
|
|
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {32} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
] $xlconcat_1
|
|
|
|
|
|
# Create instance: xlslice_1, and set properties
|
|
set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_1
|
|
|
|
|
|
# Create instance: xlslice_2, and set properties
|
|
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
|
|
set_property CONFIG.DIN_FROM {15} $xlslice_2
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_0, and set properties
|
|
set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_0
|
|
|
|
|
|
# Create instance: const_1b0, and set properties
|
|
set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ]
|
|
set_property CONFIG.CONST_VAL {0} $const_1b0
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_1, and set properties
|
|
set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {48} \
|
|
] $xpm_cdc_gen_1
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_2, and set properties
|
|
set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {16} \
|
|
] $xpm_cdc_gen_2
|
|
|
|
|
|
# Create instance: const_32b0, and set properties
|
|
set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {32} \
|
|
] $const_32b0
|
|
|
|
|
|
# Create instance: xlslice_3, and set properties
|
|
set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ]
|
|
set_property CONFIG.DIN_FROM {0} $xlslice_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_3, and set properties
|
|
set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {1} \
|
|
] $xpm_cdc_gen_3
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_4, and set properties
|
|
set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_4
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_5, and set properties
|
|
set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_5
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_16, and set properties
|
|
set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_16
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_17, and set properties
|
|
set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_17
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_18, and set properties
|
|
set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_18
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_19, and set properties
|
|
set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_19
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_20, and set properties
|
|
set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_20
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_21, and set properties
|
|
set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_21
|
|
|
|
|
|
# Create instance: xpm_cdc_gen_22, and set properties
|
|
set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ]
|
|
set_property -dict [list \
|
|
CONFIG.DEST_SYNC_FF {2} \
|
|
CONFIG.SIM_ASSERT_CHK {false} \
|
|
CONFIG.SRC_INPUT_REG {false} \
|
|
CONFIG.WIDTH {32} \
|
|
] $xpm_cdc_gen_22
|
|
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk]
|
|
connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN]
|
|
connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in]
|
|
connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in]
|
|
connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in]
|
|
connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in]
|
|
connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in]
|
|
connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in]
|
|
connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in]
|
|
connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in]
|
|
connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk]
|
|
connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk]
|
|
connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in]
|
|
connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in]
|
|
connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in]
|
|
connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in]
|
|
connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in]
|
|
connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in]
|
|
connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in]
|
|
connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in]
|
|
connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in]
|
|
connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in]
|
|
connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1]
|
|
connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1]
|
|
connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in]
|
|
connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in]
|
|
connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr]
|
|
connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in]
|
|
connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in]
|
|
connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr]
|
|
connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in]
|
|
connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in]
|
|
connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in]
|
|
connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType]
|
|
connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual]
|
|
connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on]
|
|
connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off]
|
|
connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in]
|
|
connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
# Hierarchical cell: Ethernet
|
|
proc create_hier_cell_Ethernet { parentCell nameHier } {
|
|
|
|
variable script_folder
|
|
|
|
if { $parentCell eq "" || $nameHier eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"}
|
|
return
|
|
}
|
|
|
|
# Get object for parentCell
|
|
set parentObj [get_bd_cells $parentCell]
|
|
if { $parentObj == "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
return
|
|
}
|
|
|
|
# Make sure parentObj is hier blk
|
|
set parentType [get_property TYPE $parentObj]
|
|
if { $parentType ne "hier" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
return
|
|
}
|
|
|
|
# Save current instance; Restore later
|
|
set oldCurInst [current_bd_instance .]
|
|
|
|
# Set parent object as current
|
|
current_bd_instance $parentObj
|
|
|
|
# Create cell and set as current instance
|
|
set hier_obj [create_bd_cell -type hier $nameHier]
|
|
current_bd_instance $hier_obj
|
|
|
|
# Create interface pins
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS
|
|
|
|
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS
|
|
|
|
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL
|
|
|
|
|
|
# Create pins
|
|
create_bd_pin -dir O -type clk axis_aclk
|
|
create_bd_pin -dir O -from 0 -to 0 axis_aresetn
|
|
create_bd_pin -dir I -type clk axil_clk
|
|
create_bd_pin -dir I clk_100_reset
|
|
create_bd_pin -dir I clk_100
|
|
create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt
|
|
create_bd_pin -dir I -type rst axil_resetn
|
|
create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow
|
|
|
|
# Create instance: eth_flowctrl_rx_i, and set properties
|
|
set block_name eth_flowctrl_rx
|
|
set block_cell_name eth_flowctrl_rx_i
|
|
if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_rx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: cmac_usplus_i, and set properties
|
|
set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CMAC_CAUI4_MODE {1} \
|
|
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
|
|
CONFIG.ENABLE_AXI_INTERFACE {1} \
|
|
CONFIG.ENABLE_PIPELINE_REG {1} \
|
|
CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \
|
|
CONFIG.GT_REF_CLK_FREQ {156.25} \
|
|
CONFIG.RX_CHECK_ACK {0} \
|
|
CONFIG.RX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_FLOW_CONTROL {1} \
|
|
CONFIG.TX_SA_GPP {0x000000000000} \
|
|
CONFIG.TX_SA_PPP {0x000000000000} \
|
|
CONFIG.USER_INTERFACE {AXIS} \
|
|
] $cmac_usplus_i
|
|
|
|
|
|
# Create instance: eth_frame_packer_i, and set properties
|
|
set block_name eth_frame_packer
|
|
set block_cell_name eth_frame_packer_i
|
|
if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_packer_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_flowctrl_tx_i, and set properties
|
|
set block_name eth_flowctrl_tx
|
|
set block_cell_name eth_flowctrl_tx_i
|
|
if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_flowctrl_tx_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: eth_frame_unpacker_i, and set properties
|
|
set block_name eth_frame_unpacker
|
|
set block_cell_name eth_frame_unpacker_i
|
|
if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $eth_frame_unpacker_i eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: system_ila_i, and set properties
|
|
set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_MON_TYPE {MIX} \
|
|
CONFIG.C_NUM_MONITOR_SLOTS {6} \
|
|
CONFIG.C_NUM_OF_PROBES {20} \
|
|
CONFIG.C_SLOT {5} \
|
|
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \
|
|
CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
|
|
] $system_ila_i
|
|
|
|
|
|
# Create instance: ETH_regs
|
|
create_hier_cell_ETH_regs $hier_obj ETH_regs
|
|
|
|
# Create instance: rst_inv_i, and set properties
|
|
set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ]
|
|
set_property -dict [list \
|
|
CONFIG.C_OPERATION {not} \
|
|
CONFIG.C_SIZE {1} \
|
|
] $rst_inv_i
|
|
|
|
|
|
# Create instance: counter_i, and set properties
|
|
set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ]
|
|
set_property -dict [list \
|
|
CONFIG.CE {true} \
|
|
CONFIG.Fb_Latency_Configuration {Automatic} \
|
|
CONFIG.Latency_Configuration {Automatic} \
|
|
CONFIG.Load {false} \
|
|
CONFIG.Load_Sense {Active_High} \
|
|
CONFIG.Output_Width {32} \
|
|
CONFIG.Restrict_Count {false} \
|
|
CONFIG.SCLR {true} \
|
|
CONFIG.SSET {false} \
|
|
CONFIG.Sync_Threshold_Output {false} \
|
|
] $counter_i
|
|
|
|
|
|
# Create instance: smartcon_i, and set properties
|
|
set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ]
|
|
set_property -dict [list \
|
|
CONFIG.NUM_MI {2} \
|
|
CONFIG.NUM_SI {1} \
|
|
] $smartcon_i
|
|
|
|
|
|
# Create instance: proc_sys_reset_0, and set properties
|
|
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL]
|
|
connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI]
|
|
connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk]
|
|
connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS]
|
|
connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS]
|
|
connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI]
|
|
connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS]
|
|
connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off]
|
|
connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on]
|
|
connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk]
|
|
connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn]
|
|
connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk]
|
|
connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset]
|
|
connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in]
|
|
connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn]
|
|
connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt]
|
|
connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0]
|
|
connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins eth_flowctrl_rx_i/rx_pause] [get_bd_pins system_ila_i/probe16]
|
|
connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8] [get_bd_pins system_ila_i/probe17]
|
|
connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt]
|
|
connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9]
|
|
connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8]
|
|
connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins eth_frame_packer_i/pause] [get_bd_pins system_ila_i/probe15]
|
|
connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14]
|
|
connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19]
|
|
connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13]
|
|
connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18]
|
|
connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type]
|
|
connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac]
|
|
connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac]
|
|
connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt]
|
|
connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE]
|
|
connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR]
|
|
connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual]
|
|
connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset]
|
|
connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt]
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
}
|
|
|
|
|
|
proc available_tcl_procs { } {
|
|
puts "##################################################################"
|
|
puts "# Available Tcl procedures to recreate hierarchical blocks:"
|
|
puts "#"
|
|
puts "# create_hier_cell_Ethernet parentCell nameHier"
|
|
puts "# create_hier_cell_ETH_regs parentCell nameHier"
|
|
puts "#"
|
|
puts "##################################################################"
|
|
}
|
|
|
|
available_tcl_procs
|