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moving repo from git to local repo

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Nick Santana
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
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source/raw_eth_wrapper_cmac_4.v
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
//Date : Thu Mar 5 18:53:36 2026
//Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
//Command : generate_target raw_eth_wrapper.bd
//Design : raw_eth_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module raw_eth_wrapper_cmac_4
(axil_clk_0,
axil_resetn_0,
clk_100_0,
clk_100_reset_0,
cmac_gt_0_grx_n,
cmac_gt_0_grx_p,
cmac_gt_0_gtx_n,
cmac_gt_0_gtx_p,
cmac_refclk_0_clk_n,
cmac_refclk_0_clk_p,
m_axis_aclk,
m_axis_aresetn,
m_axis_tdata,
m_axis_tready,
m_axis_tvalid,
s_axil_0_araddr,
s_axil_0_arprot,
s_axil_0_arready,
s_axil_0_arvalid,
s_axil_0_awaddr,
s_axil_0_awprot,
s_axil_0_awready,
s_axil_0_awvalid,
s_axil_0_bready,
s_axil_0_bresp,
s_axil_0_bvalid,
s_axil_0_rdata,
s_axil_0_rready,
s_axil_0_rresp,
s_axil_0_rvalid,
s_axil_0_wdata,
s_axil_0_wready,
s_axil_0_wstrb,
s_axil_0_wvalid,
s_axis_aresetn,
s_axis_clk,
s_axis_tdata,
s_axis_tready,
s_axis_tvalid);
input axil_clk_0;
input axil_resetn_0;
input clk_100_0;
input clk_100_reset_0;
input [3:0]cmac_gt_0_grx_n;
input [3:0]cmac_gt_0_grx_p;
output [3:0]cmac_gt_0_gtx_n;
output [3:0]cmac_gt_0_gtx_p;
input cmac_refclk_0_clk_n;
input cmac_refclk_0_clk_p;
input m_axis_aclk;
input m_axis_aresetn;
output [511:0]m_axis_tdata;
input m_axis_tready;
output m_axis_tvalid;
input [31:0]s_axil_0_araddr;
input [2:0]s_axil_0_arprot;
output s_axil_0_arready;
input s_axil_0_arvalid;
input [31:0]s_axil_0_awaddr;
input [2:0]s_axil_0_awprot;
output s_axil_0_awready;
input s_axil_0_awvalid;
input s_axil_0_bready;
output [1:0]s_axil_0_bresp;
output s_axil_0_bvalid;
output [31:0]s_axil_0_rdata;
input s_axil_0_rready;
output [1:0]s_axil_0_rresp;
output s_axil_0_rvalid;
input [31:0]s_axil_0_wdata;
output s_axil_0_wready;
input [3:0]s_axil_0_wstrb;
input s_axil_0_wvalid;
input s_axis_aresetn;
input s_axis_clk;
input [511:0]s_axis_tdata;
output s_axis_tready;
input s_axis_tvalid;
wire axil_clk_0;
wire axil_resetn_0;
wire clk_100_0;
wire clk_100_reset_0;
wire [3:0]cmac_gt_0_grx_n;
wire [3:0]cmac_gt_0_grx_p;
wire [3:0]cmac_gt_0_gtx_n;
wire [3:0]cmac_gt_0_gtx_p;
wire cmac_refclk_0_clk_n;
wire cmac_refclk_0_clk_p;
wire m_axis_aclk;
wire m_axis_aresetn;
wire [511:0]m_axis_tdata;
wire m_axis_tready;
wire m_axis_tvalid;
wire [31:0]s_axil_0_araddr;
wire [2:0]s_axil_0_arprot;
wire s_axil_0_arready;
wire s_axil_0_arvalid;
wire [31:0]s_axil_0_awaddr;
wire [2:0]s_axil_0_awprot;
wire s_axil_0_awready;
wire s_axil_0_awvalid;
wire s_axil_0_bready;
wire [1:0]s_axil_0_bresp;
wire s_axil_0_bvalid;
wire [31:0]s_axil_0_rdata;
wire s_axil_0_rready;
wire [1:0]s_axil_0_rresp;
wire s_axil_0_rvalid;
wire [31:0]s_axil_0_wdata;
wire s_axil_0_wready;
wire [3:0]s_axil_0_wstrb;
wire s_axil_0_wvalid;
wire s_axis_aresetn;
wire s_axis_clk;
wire [511:0]s_axis_tdata;
wire s_axis_tready;
wire s_axis_tvalid;
raw_eth_cmac_4 raw_eth_cmac_4_i
(.axil_clk_0(axil_clk_0),
.axil_resetn_0(axil_resetn_0),
.clk_100_0(clk_100_0),
.clk_100_reset_0(clk_100_reset_0),
.cmac_gt_0_grx_n(cmac_gt_0_grx_n),
.cmac_gt_0_grx_p(cmac_gt_0_grx_p),
.cmac_gt_0_gtx_n(cmac_gt_0_gtx_n),
.cmac_gt_0_gtx_p(cmac_gt_0_gtx_p),
.cmac_refclk_0_clk_n(cmac_refclk_0_clk_n),
.cmac_refclk_0_clk_p(cmac_refclk_0_clk_p),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_tdata(m_axis_tdata),
.m_axis_tready(m_axis_tready),
.m_axis_tvalid(m_axis_tvalid),
.s_axil_0_araddr(s_axil_0_araddr),
.s_axil_0_arprot(s_axil_0_arprot),
.s_axil_0_arready(s_axil_0_arready),
.s_axil_0_arvalid(s_axil_0_arvalid),
.s_axil_0_awaddr(s_axil_0_awaddr),
.s_axil_0_awprot(s_axil_0_awprot),
.s_axil_0_awready(s_axil_0_awready),
.s_axil_0_awvalid(s_axil_0_awvalid),
.s_axil_0_bready(s_axil_0_bready),
.s_axil_0_bresp(s_axil_0_bresp),
.s_axil_0_bvalid(s_axil_0_bvalid),
.s_axil_0_rdata(s_axil_0_rdata),
.s_axil_0_rready(s_axil_0_rready),
.s_axil_0_rresp(s_axil_0_rresp),
.s_axil_0_rvalid(s_axil_0_rvalid),
.s_axil_0_wdata(s_axil_0_wdata),
.s_axil_0_wready(s_axil_0_wready),
.s_axil_0_wstrb(s_axil_0_wstrb),
.s_axil_0_wvalid(s_axil_0_wvalid),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_clk(s_axis_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tready(s_axis_tready),
.s_axis_tvalid(s_axis_tvalid));
endmodule