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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
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source/ad_3w_spi.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//
// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves.
// The expected transfer format is defined in ADI_SPI technical specification
// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
//
// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the
// instruction defines the direction of the SDIO during data transfer. (READ
// is 1 and WRITE is 0)
//
module ad_3w_spi #(
parameter NUM_OF_SLAVES = 8
) (
input [NUM_OF_SLAVES-1:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio,
output spi_dir
);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
source/ad_iobuf.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_iobuf #(
parameter DATA_WIDTH = 1
) (
input [(DATA_WIDTH-1):0] dio_t,
input [(DATA_WIDTH-1):0] dio_i,
output [(DATA_WIDTH-1):0] dio_o,
inout [(DATA_WIDTH-1):0] dio_p
);
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate
endmodule
source/eth_flowctrl_rx.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M Blevins
--
-- Create Date: 01/05/2026 11:59:12 AM
-- Design Name:
-- Module Name: eth_flowctrl_rx - behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity eth_flowctrl_rx is
Port (
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
rx_pause : in STD_LOGIC;
rx_pause_quanta8 : in STD_LOGIC_VECTOR(15 downto 0);
rx_pause_cnt : out std_logic_vector(31 downto 0);
pause : out STD_LOGIC
);
end eth_flowctrl_rx;
architecture behavioral of eth_flowctrl_rx is
signal pause_r : std_logic := '0';
signal cnt_r : unsigned(15 downto 0) := (others => '0');
signal rx_pause_cnt_r : unsigned(31 downto 0) := (others => '0');
begin
pause <= pause_r;
rx_pause_cnt <= std_logic_vector(rx_pause_cnt_r);
process(clk)
begin
if(rising_edge(clk))then
if(resetn = '0')then
cnt_r <= (others => '0');
pause_r <= '0';
rx_pause_cnt_r <= (others => '0');
else
if(rx_pause = '1')then
rx_pause_cnt_r <= rx_pause_cnt_r +1;
cnt_r <= unsigned(rx_pause_quanta8);
if(unsigned(rx_pause_quanta8) = 0)then
pause_r <= '0';
else
pause_r <= '1';
end if;
else
if(cnt_r > 0)then
cnt_r <= cnt_r -1;
end if;
if(cnt_r = 1)then
pause_r <= '0';
end if;
end if;
end if;
end if;
end process;
end behavioral;
source/eth_flowctrl_tx.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M Blevins
--
-- Create Date: 01/05/2026 11:59:12 AM
-- Design Name:
-- Module Name: eth_flowctrl_tx - behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity eth_flowctrl_tx is
Port (
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
prog_full_manual : in STD_LOGIC;
data_cnt : in STD_LOGIC_VECTOR(31 downto 0);
prog_full_on : in STD_LOGIC_VECTOR(31 downto 0);
prog_full_off : in STD_LOGIC_VECTOR(31 downto 0);
ctl_tx_resend_pause : out STD_LOGIC;
ctl_tx_pause_req : out STD_LOGIC_VECTOR (8 downto 0);
tx_pause_cnt : out std_logic_vector(31 downto 0)
);
end eth_flowctrl_tx;
architecture behavioral of eth_flowctrl_tx is
signal cnt : unsigned(3 downto 0);
signal cnt_r : unsigned(3 downto 0) := (others => '0');
signal tx_pause_cnt_i : unsigned(31 downto 0);
signal tx_pause_cnt_r : unsigned(31 downto 0) := (others => '0');
type state_type is (s0, s1, s2, s3);
signal state : state_type;
signal state_r : state_type := s0;
signal resend_pause : std_logic;
signal pause_req : std_logic_vector(8 downto 0);
signal resend_pause_r : std_logic := '0';
signal pause_req_r : std_logic_vector(8 downto 0) := (others => '0');
signal prog_full_r : std_logic := '0';
begin
ctl_tx_resend_pause <= resend_pause_r;
ctl_tx_pause_req <= pause_req_r;
tx_pause_cnt <= std_logic_vector(tx_pause_cnt_r);
process(clk)
begin
if(rising_edge(clk))then
if(resetn = '0')then
resend_pause_r <= '0';
pause_req_r <= (others => '0');
state_r <= s0;
cnt_r <= (others => '0');
prog_full_r <= '0';
tx_pause_cnt_r <= (others => '0');
else
resend_pause_r <= resend_pause;
pause_req_r <= pause_req;
state_r <= state;
cnt_r <= cnt;
tx_pause_cnt_r <= tx_pause_cnt_i;
if(unsigned(data_cnt) > unsigned(prog_full_on) or prog_full_manual = '1')then
prog_full_r <= '1';
elsif (unsigned(data_cnt) <= unsigned(prog_full_off) and prog_full_manual = '0')then
prog_full_r <= '0';
end if;
end if;
end if;
end process;
process(state_r, cnt_r, prog_full_r, resend_pause_r, pause_req_r, tx_pause_cnt_r)
begin
-- defaults
state <= state_r;
cnt <= cnt_r;
resend_pause <= resend_pause_r;
pause_req <= pause_req_r;
tx_pause_cnt_i <= tx_pause_cnt_r;
case state_r is
when s0 =>
if(prog_full_r = '1')then
state <= s1;
tx_pause_cnt_i <= tx_pause_cnt_r +1;
end if;
when s1 =>
pause_req <= "100000000";
cnt <= cnt_r +1;
if(cnt_r = 15)then
state <= s2;
end if;
when s2 =>
if(prog_full_r = '0')then
state <= s3;
tx_pause_cnt_i <= tx_pause_cnt_r +1;
end if;
when s3 =>
pause_req <= (others => '0');
cnt <= cnt_r +1;
if(cnt_r = 0)then
resend_pause <= '1';
else
resend_pause <= '0';
end if;
if(cnt_r = 15)then
state <= s0;
end if;
when others =>
end case;
end process;
end behavioral;
source/eth_frame_packer.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2025 05:40:20 PM
-- Design Name:
-- Module Name: eth_frame_packer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eth_frame_packer is
port (
clk : in std_logic;
resetn : in std_logic;
pause : in std_logic := '0';
cfg_dst_mac : in std_logic_vector(47 downto 0); -- DA
cfg_src_mac : in std_logic_vector(47 downto 0); -- SA
cfg_eth_type : in std_logic_vector(15 downto 0); -- EtherType/Length
-- AXIS payload in (512-bit, 64B beats; multiples of 64B, aligned)
s_axis_tdata : in std_logic_vector(511 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
-- AXIS to CMAC TX client (512-bit)
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tkeep : out std_logic_vector(63 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic; -- error flag to CMAC
tx_cnt : out std_logic_vector(31 downto 0);
underrun_cnt : out std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture rtl of eth_frame_packer is
---------------------------------------------------------------------------
-- Functions (VHDL-93 safe)
---------------------------------------------------------------------------
function mk_header(
da : std_logic_vector(47 downto 0);
sa : std_logic_vector(47 downto 0);
ety : std_logic_vector(15 downto 0)
) return std_logic_vector is
variable h : std_logic_vector(111 downto 0);
begin
-- DA [0..5]
h( 7 downto 0) := da(47 downto 40);
h( 15 downto 8) := da(39 downto 32);
h( 23 downto 16) := da(31 downto 24);
h( 31 downto 24) := da(23 downto 16);
h( 39 downto 32) := da(15 downto 8);
h( 47 downto 40) := da( 7 downto 0);
-- SA [6..11]
h( 55 downto 48) := sa(47 downto 40);
h( 63 downto 56) := sa(39 downto 32);
h( 71 downto 64) := sa(31 downto 24);
h( 79 downto 72) := sa(23 downto 16);
h( 87 downto 80) := sa(15 downto 8);
h( 95 downto 88) := sa( 7 downto 0);
-- Type/Len [12..13]
h(103 downto 96) := ety(15 downto 8);
h(111 downto 104) := ety( 7 downto 0);
return h;
end function;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
type state_type is (IDLE, RUN, FLUSH);
signal state : state_type;
signal state_r : state_type := IDLE;
signal carry_r : std_logic_vector(111 downto 0) := (others => '0');
signal carry : std_logic_vector(111 downto 0);
signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0');
signal m_tdata : std_logic_vector(511 downto 0);
signal m_tkeep_r : std_logic_vector(63 downto 0) := (others => '1');
signal m_tkeep : std_logic_vector(63 downto 0);
signal m_tlast_r : std_logic := '0';
signal m_tlast : std_logic;
signal m_tvalid_r : std_logic := '0';
signal m_tvalid : std_logic;
signal m_tuser_r : std_logic := '0';
signal m_tuser : std_logic;
signal header : std_logic_vector(111 downto 0);
signal underrun_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
header <= mk_header(cfg_dst_mac, cfg_src_mac, cfg_eth_type);
---------------------------------------------------------------------------
-- Drive Outputs
---------------------------------------------------------------------------
m_axis_tuser <= m_tuser_r;
m_axis_tdata <= m_tdata_r;
m_axis_tkeep <= m_tkeep_r;
m_axis_tlast <= m_tlast_r;
m_axis_tvalid <= m_tvalid_r;
underrun_cnt <= underrun_cnt_r;
tx_cnt <= tx_cnt_r;
---------------------------------------------------------------------------
-- Combinational next-state / next-data
---------------------------------------------------------------------------
process(state_r, carry_r, s_axis_tlast, s_axis_tvalid, m_axis_tready, m_tvalid_r,
m_tdata_r, m_tkeep_r, m_tlast_r, m_tuser_r, header, s_axis_tdata, pause)
begin
-- Defaults
state <= state_r;
carry <= carry_r;
m_tdata <= m_tdata_r;
m_tkeep <= m_tkeep_r;
m_tlast <= m_tlast_r;
m_tuser <= m_tuser_r;
m_tvalid <= m_tvalid_r;
s_axis_tready <= '0';
case state_r is
-----------------------------------------------------------------------
when IDLE =>
--s_axis_tready <= m_axis_tready or not(m_tvalid_r);
--m_tvalid <= (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0')) or (not(m_axis_tready) and m_tvalid_r);
if(m_axis_tready = '1')then
m_tvalid <= '0';
end if;
if (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0') and pause = '0') then
s_axis_tready <= '1';
-- Emit first beat = [14B header] ++ [first 50B payload]
m_tdata <= s_axis_tdata(399 downto 0) & header;
m_tkeep <= (others => '1');
m_tvalid <= '1';
m_tuser <= '0';
m_tlast <= '0';
-- Next carry = bytes 50..63
carry <= s_axis_tdata(511 downto 400);
if s_axis_tlast = '1' then
state <= FLUSH;
else
state <= RUN;
end if;
end if;
-----------------------------------------------------------------------
when RUN =>
s_axis_tready <= m_axis_tready;
if(s_axis_tvalid = '0')then
m_tuser <= '1'; -- s_axis_tvalid must be '1' or else this is an error condition, tx data underrun.
end if;
if (m_axis_tready = '1') then
-- Steady-state emit = [prev carry 14B] ++ [new payload 0..49]
m_tdata <= s_axis_tdata(399 downto 0) & carry_r;
--m_tkeep <= (others => '1');
--m_tvalid <= '1';
--m_tlast <= '0';
-- Next carry = bytes 50..63
carry <= s_axis_tdata(511 downto 400);
if s_axis_tlast = '1' then
state <= FLUSH;
else
state <= RUN;
end if;
end if;
-----------------------------------------------------------------------
when FLUSH =>
--s_axis_tready <= '0';
-- if(s_axis_tvalid = '0')then
-- m_tuser <= '1';
-- end if;
if (m_axis_tready = '1') then
-- Emit the final 14B tail
m_tdata <= std_logic_vector(to_unsigned(0, 400)) & carry_r;
m_tkeep <= x"0000000000003FFF";
m_tlast <= '1';
--m_tvalid <= '1';
state <= IDLE;
end if;
--when others =>
end case;
end process;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
if resetn = '0' then
state_r <= IDLE;
m_tvalid_r <= '0';
underrun_cnt_r <= (others => '0');
tx_cnt_r <= (others => '0');
else
state_r <= state;
m_tvalid_r <= m_tvalid;
if(m_tlast_r = '1' and m_tvalid_r = '1' and m_tuser_r = '1' and m_axis_tready = '1')then
underrun_cnt_r <= std_logic_vector(unsigned(underrun_cnt_r) +1);
end if;
if(m_tlast_r = '1' and m_tvalid_r = '1' and m_axis_tready = '1')then
tx_cnt_r <= std_logic_vector(unsigned(tx_cnt_r) +1);
end if;
end if;
carry_r <= carry;
m_tdata_r <= m_tdata;
m_tkeep_r <= m_tkeep;
m_tlast_r <= m_tlast;
m_tuser_r <= m_tuser;
end if;
end process;
end architecture;
source/eth_frame_unpacker.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2025 05:47:45 PM
-- Design Name:
-- Module Name: eth_frame_unpacker - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eth_frame_unpacker is
port (
clk : in std_logic;
resetn : in std_logic; -- active-low synchronous reset
s_axis_tdata : in std_logic_vector(511 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tlast : in std_logic;
s_axis_tkeep : in std_logic_vector(63 downto 0);
s_axis_tuser : in std_logic; -- frame error indicator (qualified by s_axis_tvalid and s_axis_tlast)
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic; -- frame error indicator (qualified by m_axis_tvalid and m_axis_tlast)
rx_frame_err_cnt : out std_logic_vector(31 downto 0);
rx_frame_cnt : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of eth_frame_unpacker is
type state_type is (IDLE, RUN);
signal state_r : state_type := IDLE;
signal state : state_type;
signal carry : std_logic_vector(399 downto 0);
signal carry_r : std_logic_vector(399 downto 0) := (others => '0');
signal frame_err_cnt_i : std_logic_vector(31 downto 0);
signal frame_err_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal frame_cnt_i : std_logic_vector(31 downto 0);
signal frame_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_tvalid : std_logic;
signal m_tvalid_r : std_logic := '0';
signal m_tdata : std_logic_vector(511 downto 0);
signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0');
signal m_tuser : std_logic;
signal m_tuser_r : std_logic := '0';
signal m_tlast : std_logic;
signal m_tlast_r : std_logic := '0';
begin
-- Drive outputs
m_axis_tuser <= m_tuser_r;
m_axis_tdata <= m_tdata_r;
m_axis_tlast <= m_tlast_r;
m_axis_tvalid <= m_tvalid_r;
rx_frame_err_cnt <= frame_err_cnt_r;
rx_frame_cnt <= frame_cnt_r;
-----------------------------------------------------------------------------
-- Combinational next-state / next-data
-----------------------------------------------------------------------------
process(state_r, carry_r, m_tdata_r, m_tuser_r, m_tlast_r, frame_err_cnt_r,
s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser, frame_cnt_r)
begin
-- Defaults
state <= state_r;
carry <= carry_r;
frame_err_cnt_i <= frame_err_cnt_r;
frame_cnt_i <= frame_cnt_r;
m_tvalid <= '0';
m_tdata <= m_tdata_r;
m_tuser <= m_tuser_r;
m_tlast <= m_tlast_r;
case state_r is
-------------------------------------------------------------------------
when IDLE =>
if s_axis_tvalid = '1' then
-- cache high 50B; no output yet (need second beat to form first 64B payload)
carry(399 downto 0) <= s_axis_tdata(511 downto 112);
state <= RUN;
end if;
-------------------------------------------------------------------------
when RUN =>
if s_axis_tvalid = '1' then
carry(399 downto 0) <= s_axis_tdata(511 downto 112);
m_tdata <= s_axis_tdata(111 downto 0) & carry_r;
m_tvalid <= '1';
m_tuser <= s_axis_tuser;
m_tlast <= s_axis_tlast;
if(s_axis_tlast = '1')then
state <= IDLE;
frame_cnt_i <= std_logic_vector(unsigned(frame_cnt_r) +1);
end if;
if(s_axis_tlast = '1' and s_axis_tuser = '1')then
frame_err_cnt_i <= std_logic_vector(unsigned(frame_err_cnt_r) +1);
end if;
end if;
-------------------------------------------------------------------------
end case;
end process;
-----------------------------------------------------------------------------
-- Regs
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
if resetn = '0' then
state_r <= IDLE;
frame_err_cnt_r <= (others => '0');
frame_cnt_r <= (others => '0');
m_tvalid_r <= '0';
else
state_r <= state;
frame_err_cnt_r <= frame_err_cnt_i;
frame_cnt_r <= frame_cnt_i;
m_tvalid_r <= m_tvalid;
end if;
carry_r <= carry;
m_tdata_r <= m_tdata;
m_tuser_r <= m_tuser;
m_tlast_r <= m_tlast;
end if;
end process;
end architecture;
source/qsfp1_capture_intfc.vhd
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity qsfp1_capture_intfc is
port (
qsfp1_capture_aclk_in : in std_logic;
qsfp1_capture_aresetn_in : in std_logic;
qsfp1_capture_tdata_240b_in : in std_logic_vector(239 downto 0);
qsfp1_capture_tvalid_240b_in : in std_logic;
qsfp1_capture_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
qsfp1_capture_fifo_aempty_512b_cnt_out : out std_logic_vector( 31 downto 0);
qsfp1_capture_iq_240b_to_512b_overflow_cnt_out : out std_logic_vector( 31 downto 0);
qsfp1_capture_rx_data_ready_out : out std_logic;
qsfp1_capture_rx_data_ready_cnt_out : out std_logic_vector( 31 downto 0);
tx_device_clk_in : in std_logic;
tx_device_clk_aresetn_in : in std_logic;
tx_fifo_tdata_256b_out : out std_logic_vector(255 downto 0);
tx_fifo_tvalid_256b_out : out std_logic;
tx_fifo_tready_256b_in : in std_logic;
tx_fifo_tvalid_256b_cnt_out : out std_logic_vector( 31 downto 0);
chan1to4_mode_sel_in : in std_logic;
cnt_reset_in : in std_logic
);
end entity qsfp1_capture_intfc;
architecture arch_imp of qsfp1_capture_intfc is
signal qsfp1_rx_data_ready : std_logic;
signal qsfp1_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp1_prog_full_240b : std_logic;
signal qsfp1_afull_240b : std_logic;
signal qsfp1_aempty_240b : std_logic;
signal qsfp1_rx_data_ready_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp1_iq_240b_to_512b_overflow : std_logic;
signal qsfp1_iq_240b_to_512b_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp1_tdata_512b : std_logic_vector(511 downto 0);
signal qsfp1_tvalid_512b : std_logic;
signal qsfp1_tready_512b : std_logic;
signal qsfp1_tdata_512b_pipe : std_logic_vector(511 downto 0);
signal qsfp1_tvalid_512b_pipe : std_logic;
signal qsfp1_tready_512b_pipe : std_logic;
signal qsfp1_almost_empty_512b_pipe : std_logic;
signal qsfp1_almost_empty_512b_pipe_r : std_logic := '1';
signal qsfp1_fifo_aempty_512b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal axis_dwidth_converter_tdata_512b_to_256b : std_logic_vector(255 downto 0);
signal axis_dwidth_converter_tvalid_512b_to_256b : std_logic;
signal tx_fifo_tready_256b : std_logic;
signal tx_fifo_tvalid_256b : std_logic;
signal tx_fifo_aempty_256b : std_logic;
signal tx_fifo_aempty_256b_r : std_logic := '1';
signal tx_fifo_prog_aempty_256b : std_logic;
signal tx_fifo_tvalid_256b_ena : std_logic;
signal tx_fifo_tready_256b_ena : std_logic;
signal tx_pre_buff_rdy_r : std_logic := '0';
signal tx_fifo_tvalid_256b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
qsfp1_capture_rx_data_ready_out <= qsfp1_rx_data_ready;
qsfp1_capture_rx_data_ready_cnt_out <= qsfp1_rx_data_ready_cnt_r;
qsfp1_capture_tvalid_240b_cnt_out <= qsfp1_tvalid_240b_cnt_r;
qsfp1_capture_iq_240b_to_512b_overflow_cnt_out <= qsfp1_iq_240b_to_512b_overflow_cnt_r;
qsfp1_capture_fifo_aempty_512b_cnt_out <= qsfp1_fifo_aempty_512b_cnt_r;
tx_fifo_tvalid_256b_cnt_out <= tx_fifo_tvalid_256b_cnt_r;
-- ***240 to 512 converter
i_iq_240b_to_512b : entity work.iq_240b_to_512b
port map (
aclk => qsfp1_capture_aclk_in, -- in
aresetn => qsfp1_capture_aresetn_in, -- in
s_axis_tdata => qsfp1_capture_tdata_240b_in, -- in
s_axis_tvalid => qsfp1_capture_tvalid_240b_in, -- in
prog_full => qsfp1_prog_full_240b, -- out
almost_full => qsfp1_afull_240b, -- out
m_axis_tdata => qsfp1_tdata_512b, -- out
m_axis_tvalid => qsfp1_tvalid_512b, -- out
m_axis_tready => qsfp1_tready_512b, -- in
almost_empty => qsfp1_aempty_240b, -- out
overflow => qsfp1_iq_240b_to_512b_overflow, -- out
sel_12b_16bn => '0' -- 16-bit samples -- in
);
qsfp1_rx_data_ready <= not qsfp1_prog_full_240b;
process(qsfp1_capture_aclk_in)
begin
if (rising_edge(qsfp1_capture_aclk_in)) then
if (qsfp1_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp1_tvalid_240b_cnt_r <= (others => '0');
elsif (qsfp1_capture_tvalid_240b_in = '1') then
qsfp1_tvalid_240b_cnt_r <= qsfp1_tvalid_240b_cnt_r + 1;
end if;
if (qsfp1_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp1_rx_data_ready_cnt_r <= (others => '0');
elsif (qsfp1_rx_data_ready = '0') then
qsfp1_rx_data_ready_cnt_r <= qsfp1_rx_data_ready_cnt_r + 1;
end if;
if (qsfp1_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp1_iq_240b_to_512b_overflow_cnt_r <= (others => '0');
elsif (qsfp1_iq_240b_to_512b_overflow = '1') then
qsfp1_iq_240b_to_512b_overflow_cnt_r <= qsfp1_iq_240b_to_512b_overflow_cnt_r + 1;
end if;
end if;
end process;
-- this fifo is actually 64 words deep
i_axis_data_fifo_32x512 : entity work.axis_data_fifo_32x512
port map (
s_axis_aclk => qsfp1_capture_aclk_in,
s_axis_aresetn => qsfp1_capture_aresetn_in,
s_axis_tdata => qsfp1_tdata_512b, -- in
s_axis_tvalid => qsfp1_tvalid_512b, -- in
s_axis_tready => qsfp1_tready_512b, -- out
m_axis_aclk => tx_device_clk_in,
m_axis_tdata => qsfp1_tdata_512b_pipe, -- out
m_axis_tvalid => qsfp1_tvalid_512b_pipe, -- out
m_axis_tready => qsfp1_tready_512b_pipe, -- in
almost_empty => qsfp1_almost_empty_512b_pipe
);
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
qsfp1_almost_empty_512b_pipe_r <= qsfp1_almost_empty_512b_pipe;
if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp1_fifo_aempty_512b_cnt_r <= (others => '0');
elsif (qsfp1_almost_empty_512b_pipe = '1' and qsfp1_almost_empty_512b_pipe_r = '0') then
qsfp1_fifo_aempty_512b_cnt_r <= qsfp1_fifo_aempty_512b_cnt_r + 1;
end if;
end if;
end process;
-- i_ila_256b_4_qsfp1 : ila_256b_4
-- port map (
-- clk => qsfp1_capture_aclk_in,
-- probe0 => qsfp1_tvalid_240b,
-- probe1 => qsfp1_aempty_240b,
-- probe2 => qsfp1_afull_240b,
-- probe3 => qsfp1_rx_data_ready,
-- probe4 => qsfp1_tvalid_512b,
-- probe5 => qsfp1_tready_512b,
-- probe6 => qsfp1_afull_512b,
-- probe7 => qsfp1_prog_full_512b,
-- probe8 => qsfp1_almost_empty_512b_pipe)
-- );
i_axis_dwidth_converter_512b_to_256b : entity work.axis_dwidth_converter_512b_to_256b
port map (
aclk => tx_device_clk_in, -- in
aresetn => tx_device_clk_aresetn_in, -- in
s_axis_tdata => qsfp1_tdata_512b_pipe, -- in
s_axis_tvalid => qsfp1_tvalid_512b_pipe, -- in
s_axis_tready => qsfp1_tready_512b_pipe, -- out
m_axis_tdata => axis_dwidth_converter_tdata_512b_to_256b, -- out
m_axis_tvalid => axis_dwidth_converter_tvalid_512b_to_256b, -- out
m_axis_tready => tx_fifo_tready_256b -- in
);
-- big FIFO before JESD TX PORT - actually 64 words deep
i_tx_fifo_32kx256 : entity work.axis_data_fifo_32kx256
port map (
s_axis_aclk => tx_device_clk_in, -- in
s_axis_aresetn => tx_device_clk_aresetn_in, -- in
s_axis_tdata => axis_dwidth_converter_tdata_512b_to_256b, -- in
s_axis_tvalid => axis_dwidth_converter_tvalid_512b_to_256b, -- in
s_axis_tready => tx_fifo_tready_256b, -- out
m_axis_tdata => tx_fifo_tdata_256b_out, -- out
m_axis_tvalid => tx_fifo_tvalid_256b, -- out
m_axis_tready => tx_fifo_tready_256b_ena, -- in
almost_empty => tx_fifo_aempty_256b, -- out
prog_empty => tx_fifo_prog_aempty_256b -- out
);
tx_fifo_tvalid_256b_ena <= tx_pre_buff_rdy_r and tx_fifo_tvalid_256b;
tx_fifo_tready_256b_ena <= tx_pre_buff_rdy_r and tx_fifo_tready_256b_in;
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
tx_fifo_aempty_256b_r <= tx_fifo_aempty_256b;
if ((tx_fifo_aempty_256b = '1') and (tx_fifo_aempty_256b_r = '1')) then
tx_pre_buff_rdy_r <= '0';
elsif (tx_fifo_prog_aempty_256b = '0') then
tx_pre_buff_rdy_r <= '1';
end if;
if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
tx_fifo_tvalid_256b_cnt_r <= (others => '0');
elsif (tx_fifo_tvalid_256b_ena = '1' and tx_fifo_tready_256b_ena = '1') then
tx_fifo_tvalid_256b_cnt_r <= tx_fifo_tvalid_256b_cnt_r + 1;
end if;
end if;
end process;
tx_fifo_tvalid_256b_out <= tx_fifo_tvalid_256b_ena;
end architecture arch_imp;
source/qsfp4_playback_intfc.vhd
+218
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity qsfp4_playback_intfc is
port (
rx_device_clk_in : in std_logic;
rx_device_clk_aresetn_in : in std_logic;
rx_tdata_256b_in : in std_logic_vector(255 downto 0);
rx_tvalid_256b_in : in std_logic;
rx_tready_256b_out : out std_logic;
rx_tvalid_256b_cnt_out : out std_logic_vector( 31 downto 0);
rx_tvalid_256b_en_cnt_out : out std_logic_vector( 31 downto 0);
playback_data_path_enable_n_in : in std_logic;
qsfp4_playback_aclk_in : in std_logic;
qsfp4_playback_aresetn_in : in std_logic;
qsfp4_playback_tdata_240b_out : out std_logic_vector(239 downto 0);
qsfp4_playback_tvalid_240b_out : out std_logic;
qsfp4_playback_tready_240b_in : in std_logic;
qsfp4_playback_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
cnt_reset_in : in std_logic
);
end entity qsfp4_playback_intfc;
architecture arch_imp of qsfp4_playback_intfc is
signal playback_data_path_enable_r : std_logic_vector(0 to 31) := (others => '0');
signal rx_path_fifo_rst_n : std_logic;
signal qsfp4_fifo_rst_n : std_logic;
signal iq_512b_to_240b_rst_n : std_logic;
signal playback_data_path_enable : std_logic;
signal rx_tvalid_256b_en : std_logic;
signal rx_tvalid_256b_en_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_tvalid_256b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_tready_256b : std_logic;
signal rx_tdata_256b_pipe : std_logic_vector(255 downto 0);
signal rx_tvalid_256b_pipe : std_logic;
signal axis_dwidth_converter_tdata_256b_to_512b : std_logic_vector(511 downto 0);
signal axis_dwidth_converter_tvalid_256b_to_512b : std_logic;
signal axis_dwidth_converter_tready_256b_to_512b : std_logic;
signal rx_tdata_512b_pipe : std_logic_vector(511 downto 0);
signal rx_tvalid_512b_pipe : std_logic;
signal rx_tready_512b_pipe : std_logic;
signal iq_512b_to_240b_tdata : std_logic_vector(239 downto 0);
signal iq_512b_to_240b_tvalid : std_logic;
signal iq_512b_to_240b_tready : std_logic;
signal rx_tready_240b : std_logic;
signal rx_tdata_240b_pipe : std_logic_vector(239 downto 0);
signal rx_tvalid_240b_pipe : std_logic;
signal rx_fifo_tready_240b : std_logic;
signal qsfp4_playback_tvalid_240b : std_logic;
signal qsfp4_playback_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
qsfp4_playback_tvalid_240b_out <= qsfp4_playback_tvalid_240b;
qsfp4_playback_tvalid_240b_cnt_out <= qsfp4_playback_tvalid_240b_cnt_r;
rx_tvalid_256b_cnt_out <= rx_tvalid_256b_cnt_r;
rx_tvalid_256b_en_cnt_out <= rx_tvalid_256b_en_cnt_r;
rx_tready_256b_out <= rx_tready_256b;
process(rx_device_clk_in, rx_device_clk_aresetn_in)
begin
if (rx_device_clk_aresetn_in = '0') then
playback_data_path_enable_r <= (others => '0');
elsif (rising_edge(rx_device_clk_in)) then
if (playback_data_path_enable_n_in = '1') then
playback_data_path_enable_r <= (others => '0');
else
playback_data_path_enable_r <= playback_data_path_enable_r(1 to 31) & '1';
end if;
end if;
end process;
rx_path_fifo_rst_n <= playback_data_path_enable_r(27);
qsfp4_fifo_rst_n <= playback_data_path_enable_r(20);
iq_512b_to_240b_rst_n <= playback_data_path_enable_r(16);
playback_data_path_enable <= playback_data_path_enable_r(0);
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
if (cnt_reset_in = '1') then
rx_tvalid_256b_cnt_r <= (others => '0');
elsif (rx_tvalid_256b_in = '1') then
rx_tvalid_256b_cnt_r <= rx_tvalid_256b_cnt_r + 1;
end if;
end if;
end process;
rx_tvalid_256b_en <= rx_tvalid_256b_in when playback_data_path_enable = '1' else '0';
i_rx_register_slice_256b : entity work.axis_register_slice_256b
port map (
aclk => rx_device_clk_in,
aresetn => rx_path_fifo_rst_n,
s_axis_tdata => rx_tdata_256b_in, -- in
s_axis_tvalid => rx_tvalid_256b_en, -- in
s_axis_tready => rx_tready_256b, -- out
m_axis_tdata => rx_tdata_256b_pipe, -- out
m_axis_tvalid => rx_tvalid_256b_pipe, -- out
m_axis_tready => axis_dwidth_converter_tready_256b_to_512b -- in
);
i_ila_4 : entity work.ila_4
port map (
clk => rx_device_clk_in,
probe0 => rx_tvalid_256b_in, -- 1
probe1 => rx_tvalid_256b_en, -- 1
probe2 => rx_tready_256b, -- 1
probe3 => axis_dwidth_converter_tready_256b_to_512b, -- 1
probe4 => rx_tready_512b_pipe, --1
probe5 => iq_512b_to_240b_tready, --1
probe6 => rx_fifo_tready_240b --1
);
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
if (rx_path_fifo_rst_n = '0' or cnt_reset_in = '1') then
rx_tvalid_256b_en_cnt_r <= (others => '0');
elsif (rx_tvalid_256b_pipe = '1' and axis_dwidth_converter_tready_256b_to_512b = '1') then
rx_tvalid_256b_en_cnt_r <= rx_tvalid_256b_en_cnt_r + 1;
end if;
end if;
end process;
i_axis_dwidth_converter_256b_to_512b : entity work.axis_dwidth_converter_256b_to_512b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_256b_pipe, -- in
s_axis_tvalid => rx_tvalid_256b_pipe, -- in
s_axis_tready => axis_dwidth_converter_tready_256b_to_512b, -- out
m_axis_tdata => axis_dwidth_converter_tdata_256b_to_512b, -- out
m_axis_tvalid => axis_dwidth_converter_tvalid_256b_to_512b, -- out
m_axis_tready => rx_tready_512b_pipe -- in
);
i_qsfp4_reg_slice_512b : entity work.axis_register_slice_512b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => axis_dwidth_converter_tdata_256b_to_512b, -- in
s_axis_tvalid => axis_dwidth_converter_tvalid_256b_to_512b, -- in
s_axis_tready => rx_tready_512b_pipe, -- out
m_axis_tdata => rx_tdata_512b_pipe, -- out
m_axis_tvalid => rx_tvalid_512b_pipe, -- out
m_axis_tready => iq_512b_to_240b_tready -- in
);
i_iq_512b_to_240b : entity work.iq_512b_to_240b
port map (
aclk => rx_device_clk_in, -- in
aresetn => iq_512b_to_240b_rst_n, -- in
s_axis_tdata => rx_tdata_512b_pipe, -- in
s_axis_tvalid => rx_tvalid_512b_pipe, -- in
s_axis_tready => iq_512b_to_240b_tready, -- out
m_axis_tdata => iq_512b_to_240b_tdata, -- out
m_axis_tvalid => iq_512b_to_240b_tvalid, -- out
m_axis_tready => rx_fifo_tready_240b --rx_tready_240b -- in
);
-- i_qsfp4_reg_slice_240b : entity work.axis_register_slice_240b
-- port map (
-- aclk => rx_device_clk_in, -- in
-- aresetn => rx_path_fifo_rst_n, -- in
-- s_axis_tdata => iq_512b_to_240b_tdata, -- in
-- s_axis_tvalid => iq_512b_to_240b_tvalid, -- in
-- s_axis_tready => rx_tready_240b, -- out
-- m_axis_tdata => rx_tdata_240b_pipe, -- out
-- m_axis_tvalid => rx_tvalid_240b_pipe, -- out
-- m_axis_tready => rx_fifo_tready_240b -- in
-- );
-- this fifo is actually 32 words deep
i_qsfp4_fifo : entity work.axis_data_fifo_32x240
port map (
s_axis_aclk => rx_device_clk_in, -- in
s_axis_aresetn => qsfp4_fifo_rst_n, -- in
s_axis_tdata => iq_512b_to_240b_tdata, --rx_tdata_240b_pipe, -- in
s_axis_tvalid => iq_512b_to_240b_tvalid, --rx_tvalid_240b_pipe, -- in
s_axis_tready => rx_fifo_tready_240b, -- out
m_axis_aclk => qsfp4_playback_aclk_in, -- in
m_axis_tdata => qsfp4_playback_tdata_240b_out, -- out
m_axis_tvalid => qsfp4_playback_tvalid_240b, -- out
m_axis_tready => qsfp4_playback_tready_240b_in -- in
);
process(qsfp4_playback_aclk_in)
begin
if (rising_edge(qsfp4_playback_aclk_in)) then
if (qsfp4_fifo_rst_n = '0' or cnt_reset_in = '1') then
qsfp4_playback_tvalid_240b_cnt_r <= (others => '0');
elsif (qsfp4_playback_tvalid_240b = '1' and qsfp4_playback_tready_240b_in = '1') then
qsfp4_playback_tvalid_240b_cnt_r <= qsfp4_playback_tvalid_240b_cnt_r + 1;
end if;
end if;
end process;
end architecture arch_imp;
source/qsfp_capture_intfc_128.vhd
+265
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity qsfp_capture_intfc_128 is
port (
qsfp_capture_aclk_in : in std_logic;
qsfp_capture_aresetn_in : in std_logic;
qsfp_capture_tdata_240b_in : in std_logic_vector(239 downto 0);
qsfp_capture_tvalid_240b_in : in std_logic;
qsfp_capture_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
qsfp_capture_fifo_aempty_512b_cnt_out : out std_logic_vector( 31 downto 0);
qsfp_capture_iq_240b_to_512b_overflow_cnt_out : out std_logic_vector( 31 downto 0);
qsfp_capture_rx_data_ready_out : out std_logic;
qsfp_capture_rx_data_ready_cnt_out : out std_logic_vector( 31 downto 0);
tx_device_clk_in : in std_logic;
tx_device_clk_aresetn_in : in std_logic;
tx_tdata_128b_out : out std_logic_vector(127 downto 0);
tx_tvalid_128b_out : out std_logic;
tx_tready_128b_in : in std_logic;
tx_tvalid_128b_cnt_out : out std_logic_vector( 31 downto 0);
chan1to4_mode_sel_in : in std_logic;
cnt_reset_in : in std_logic
);
end entity qsfp_capture_intfc_128;
architecture arch_imp of qsfp_capture_intfc_128 is
signal qsfp_rx_data_ready : std_logic;
signal qsfp_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp_prog_full_240b : std_logic;
signal qsfp_afull_240b : std_logic;
signal qsfp_aempty_240b : std_logic;
signal qsfp_rx_data_ready_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp_iq_240b_to_512b_overflow : std_logic;
signal qsfp_iq_240b_to_512b_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp_tdata_512b : std_logic_vector(511 downto 0);
signal qsfp_tvalid_512b : std_logic;
signal qsfp_tready_512b : std_logic;
signal qsfp_tdata_512b_pipe : std_logic_vector(511 downto 0);
signal qsfp_tvalid_512b_pipe : std_logic;
signal qsfp_tready_512b_pipe : std_logic;
signal qsfp_almost_empty_512b_pipe : std_logic;
signal qsfp_almost_empty_512b_pipe_r : std_logic := '1';
signal qsfp_fifo_aempty_512b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal axis_dwidth_converter_512b_to_128b_tdata_128 : std_logic_vector(127 downto 0);
signal axis_dwidth_converter_512b_to_128b_tvalid_128 : std_logic;
signal axis_dwidth_converter_512b_to_128b_tready : std_logic;
signal axis_dwidth_converter_512b_to_32b_tdata_32b : std_logic_vector(31 downto 0);
signal axis_dwidth_converter_512b_to_32b_tvalid_32b : std_logic;
signal axis_dwidth_converter_512b_to_32b_tready : std_logic;
signal qsfp_tdata_128b : std_logic_vector(127 downto 0);
signal qsfp_tvalid_128b : std_logic;
signal qsfp_tready_128b : std_logic;
signal tx_tvalid_128b : std_logic;
signal tx_fifo_aempty_128b : std_logic;
signal tx_fifo_aempty_128b_r : std_logic := '1';
signal tx_fifo_prog_aempty_128 : std_logic;
signal tx_tvalid_128b_ena : std_logic;
signal tx_tready_128b_ena : std_logic;
signal tx_pre_buff_rdy_r : std_logic := '0';
signal tx_tvalid_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
qsfp_capture_rx_data_ready_out <= qsfp_rx_data_ready;
qsfp_capture_rx_data_ready_cnt_out <= qsfp_rx_data_ready_cnt_r;
qsfp_capture_tvalid_240b_cnt_out <= qsfp_tvalid_240b_cnt_r;
qsfp_capture_iq_240b_to_512b_overflow_cnt_out <= qsfp_iq_240b_to_512b_overflow_cnt_r;
qsfp_capture_fifo_aempty_512b_cnt_out <= qsfp_fifo_aempty_512b_cnt_r;
tx_tvalid_128b_cnt_out <= tx_tvalid_128b_cnt_r;
-- ***240 to 128 converter
i_iq_240b_to_512b : entity work.iq_240b_to_512b
port map (
aclk => qsfp_capture_aclk_in, -- in
aresetn => qsfp_capture_aresetn_in, -- in
s_axis_tdata => qsfp_capture_tdata_240b_in, -- in
s_axis_tvalid => qsfp_capture_tvalid_240b_in, -- in
prog_full => qsfp_prog_full_240b, -- out
almost_full => qsfp_afull_240b, --out
m_axis_tdata => qsfp_tdata_512b, -- out
m_axis_tvalid => qsfp_tvalid_512b, -- out
m_axis_tready => qsfp_tready_512b, -- in
almost_empty => qsfp_aempty_240b, -- out
overflow => qsfp_iq_240b_to_512b_overflow, -- out
sel_12b_16bn => '0' -- 16-bit samples -- in
);
qsfp_rx_data_ready <= not qsfp_prog_full_240b;
process(qsfp_capture_aclk_in)
begin
if (rising_edge(qsfp_capture_aclk_in)) then
if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp_tvalid_240b_cnt_r <= (others => '0');
elsif (qsfp_capture_tvalid_240b_in = '1') then
qsfp_tvalid_240b_cnt_r <= qsfp_tvalid_240b_cnt_r + 1;
end if;
if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp_rx_data_ready_cnt_r <= (others => '0');
elsif (qsfp_rx_data_ready = '0') then
qsfp_rx_data_ready_cnt_r <= qsfp_rx_data_ready_cnt_r + 1;
end if;
if (qsfp_capture_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp_iq_240b_to_512b_overflow_cnt_r <= (others => '0');
elsif (qsfp_iq_240b_to_512b_overflow = '1') then
qsfp_iq_240b_to_512b_overflow_cnt_r <= qsfp_iq_240b_to_512b_overflow_cnt_r + 1;
end if;
end if;
end process;
-- i_qsfp_reg_slice_512 : entity work.axis_register_slice_512
-- port map (
-- aclk => qsfp_capture_aclk_in, -- in
-- aresetn => qsfp_capture_aresetn_in, -- in
-- s_axis_tdata => qsfp_tdata_512b, -- in
-- s_axis_tvalid => qsfp_tvalid_512b, -- in
-- s_axis_tready => qsfp_tready_512b, -- out
-- m_axis_tdata => qsfp_tdata_512b_pipe, -- out
-- m_axis_tvalid => qsfp_tvalid_512b_pipe, -- out
-- m_axis_tready => qsfp_tready_512b_pipe -- in
-- );
-- this fifo is actually 64 words deep
i_axis_data_fifo_32x512 : entity work.axis_data_fifo_32x512
port map (
s_axis_aclk => qsfp_capture_aclk_in,
s_axis_aresetn => qsfp_capture_aresetn_in,
s_axis_tdata => qsfp_tdata_512b,
s_axis_tvalid => qsfp_tvalid_512b,
s_axis_tready => qsfp_tready_512b,
m_axis_aclk => tx_device_clk_in,
m_axis_tdata => qsfp_tdata_512b_pipe, -- out
m_axis_tvalid => qsfp_tvalid_512b_pipe, -- out
m_axis_tready => qsfp_tready_512b_pipe, -- in
almost_empty => qsfp_almost_empty_512b_pipe
);
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
qsfp_almost_empty_512b_pipe_r <= qsfp_almost_empty_512b_pipe;
if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
qsfp_fifo_aempty_512b_cnt_r <= (others => '0');
elsif (qsfp_almost_empty_512b_pipe = '1' and qsfp_almost_empty_512b_pipe_r = '0') then
qsfp_fifo_aempty_512b_cnt_r <= qsfp_fifo_aempty_512b_cnt_r + 1;
end if;
end if;
end process;
-- i_ila_128_4_qsfp1 : ila_128_4
-- port map (
-- clk => qsfp_capture_aclk_in,
-- probe0 => qsfp_tvalid_240b,
-- probe1 => qsfp_aempty_240b,
-- probe2 => qsfp_afull_240b,
-- probe3 => qsfp_rx_data_ready,
-- probe4 => qsfp_tvalid_512b,
-- probe5 => qsfp_tready_512b,
-- probe6 => qsfp_afull_512b,
-- probe7 => qsfp_prog_full_512b,
-- probe8 => qsfp_almost_empty_512b_pipe)
-- );
qsfp_tready_512b_pipe <= axis_dwidth_converter_512b_to_32b_tready when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tready;
i_axis_dwidth_converter_512b_to_128b : entity work.axis_dwidth_converter_512b_to_128b
port map (
aclk => tx_device_clk_in, -- in
aresetn => tx_device_clk_aresetn_in, -- in
s_axis_tdata => qsfp_tdata_512b_pipe, -- in
s_axis_tvalid => qsfp_tvalid_512b_pipe, -- in
s_axis_tready => axis_dwidth_converter_512b_to_128b_tready, -- out
m_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, -- out
m_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, -- out
m_axis_tready => qsfp_tready_128b -- in
);
-- i_axis_dwidth_converter_512b_to_32b : entity work.axis_dwidth_converter_512b_to_32b
-- port map (
-- aclk => tx_device_clk_in, -- in
-- aresetn => tx_device_clk_aresetn_in, -- in
-- s_axis_tdata => qsfp_tdata_512b_pipe, -- in
-- s_axis_tvalid => qsfp_tvalid_512b_pipe, -- in
-- s_axis_tready => axis_dwidth_converter_512b_to_32b_tready, -- out
-- m_axis_tdata => axis_dwidth_converter_512b_to_32b_tdata_32b, -- out
-- m_axis_tvalid => axis_dwidth_converter_512b_to_32b_tvalid_32b, -- out
-- m_axis_tready => qsfp_tready_128b -- in
-- );
-- qsfp_tdata_128b <= axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b & axis_dwidth_converter_512b_to_32b_tdata_32b when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tdata_128;
-- qsfp_tvalid_128b <= axis_dwidth_converter_512b_to_32b_tvalid_32b when chan1to4_mode_sel_in = '1' else axis_dwidth_converter_512b_to_128b_tvalid_128;
-- big FIFO before JESD TX PORT - actually 64 words deep
i_tx_fifo_32kx128 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => tx_device_clk_in, -- in
s_axis_aresetn => tx_device_clk_aresetn_in, -- in
s_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, ---qsfp_tdata_128b, -- in
s_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, --qsfp_tvalid_128b, -- in
s_axis_tready => qsfp_tready_128b, -- out
-- m_axis_aclk => tx_device_clk_in, -- in
m_axis_tdata => tx_tdata_128b_out, -- out
m_axis_tvalid => tx_tvalid_128b, -- out
m_axis_tready => tx_tready_128b_ena, -- in
almost_empty => tx_fifo_aempty_128b,-- out
prog_empty => tx_fifo_prog_aempty_128 -- out
);
tx_tvalid_128b_ena <= tx_pre_buff_rdy_r and tx_tvalid_128b;
tx_tready_128b_ena <= tx_pre_buff_rdy_r and tx_tready_128b_in;
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
tx_fifo_aempty_128b_r <= tx_fifo_aempty_128b;
if ((tx_fifo_aempty_128b = '1') and (tx_fifo_aempty_128b_r = '1')) then
tx_pre_buff_rdy_r <= '0';
elsif (tx_fifo_prog_aempty_128 = '0') then
tx_pre_buff_rdy_r <= '1';
end if;
if (tx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
tx_tvalid_128b_cnt_r <= (others => '0');
elsif (tx_tvalid_128b_ena = '1' and tx_tready_128b_ena = '1') then
tx_tvalid_128b_cnt_r <= tx_tvalid_128b_cnt_r + 1;
end if;
end if;
end process;
tx_tvalid_128b_out <= tx_tvalid_128b_ena;
end architecture arch_imp;
source/qsfp_playback_intfc_128.vhd
+238
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity qsfp_playback_intfc_128 is
port (
rx_device_clk_in : in std_logic;
rx_device_clk_aresetn_in : in std_logic;
rx_tdata_128b_in : in std_logic_vector(127 downto 0);
rx_tvalid_128b_in : in std_logic;
rx_tready_128b_out : out std_logic;
rx_tvalid_128b_cnt_out : out std_logic_vector( 31 downto 0);
rx_tvalid_128b_en_cnt_out : out std_logic_vector( 31 downto 0);
rx_overflow_128b_cnt_out : out std_logic_vector( 31 downto 0);
playback_data_path_enable_n_in : in std_logic;
qsfp_playback_aclk_in : in std_logic;
qsfp_playback_aresetn_in : in std_logic;
qsfp_playback_tdata_240b_out : out std_logic_vector(239 downto 0);
qsfp_playback_tvalid_240b_out : out std_logic;
qsfp_playback_tready_240b_in : in std_logic;
qsfp_playback_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
cnt_reset_in : in std_logic
);
end entity qsfp_playback_intfc_128;
architecture arch_imp of qsfp_playback_intfc_128 is
signal playback_data_path_enable_r : std_logic_vector(0 to 31) := (others => '0');
signal rx_path_fifo_rst_n : std_logic;
signal rx_path_fifo_rst_1_n : std_logic;
signal qsfp_fifo_rst_n : std_logic;
signal qsfp_fifo_rst_n_r : std_logic_vector(0 to 2) := (others => '0');
signal iq_512b_to_240b_rst_n : std_logic;
signal playback_data_path_enable : std_logic;
signal rx_tvalid_128b_en : std_logic;
signal rx_tvalid_128b_en_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_tvalid_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_tready_128b : std_logic;
signal rx_tdata_128b_pipe : std_logic_vector(127 downto 0);
signal rx_tvalid_128b_pipe : std_logic;
signal rx_tready_128b_pipe : std_logic;
signal rx_tdata_512b : std_logic_vector(511 downto 0);
signal rx_tvalid_512b : std_logic;
signal rx_tready_512b : std_logic;
signal rx_tdata_512b_pipe : std_logic_vector(511 downto 0);
signal rx_tvalid_512b_pipe : std_logic;
signal rx_tready_512b_pipe : std_logic;
signal rx_tdata_240b : std_logic_vector(239 downto 0);
signal rx_tvalid_240b : std_logic;
signal rx_tready_240b : std_logic;
signal rx_tdata_240b_pipe : std_logic_vector(239 downto 0);
signal rx_tvalid_240b_pipe : std_logic;
signal rx_tready_240b_pipe : std_logic;
signal qsfp_playback_tvalid_240b : std_logic;
signal qsfp_playback_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_overflow_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
qsfp_playback_tvalid_240b_out <= qsfp_playback_tvalid_240b;
qsfp_playback_tvalid_240b_cnt_out <= qsfp_playback_tvalid_240b_cnt_r;
rx_tvalid_128b_cnt_out <= rx_tvalid_128b_cnt_r;
rx_tvalid_128b_en_cnt_out <= rx_tvalid_128b_en_cnt_r;
rx_tready_128b_out <= rx_tready_128b;
rx_overflow_128b_cnt_out <= rx_overflow_128b_cnt_r;
process(rx_device_clk_in, rx_device_clk_aresetn_in)
begin
if (rx_device_clk_aresetn_in = '0') then
playback_data_path_enable_r <= (others => '0');
elsif (rising_edge(rx_device_clk_in)) then
if (playback_data_path_enable_n_in = '1') then
playback_data_path_enable_r <= (others => '0');
else
playback_data_path_enable_r <= playback_data_path_enable_r(1 to 31) & '1';
end if;
end if;
end process;
rx_path_fifo_rst_n <= playback_data_path_enable_r(27);
rx_path_fifo_rst_1_n <= playback_data_path_enable_r(26);
iq_512b_to_240b_rst_n <= playback_data_path_enable_r(20);
qsfp_fifo_rst_n <= playback_data_path_enable_r(16);
playback_data_path_enable <= playback_data_path_enable_r(0);
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
if (cnt_reset_in = '1') then
rx_tvalid_128b_cnt_r <= (others => '0');
elsif (rx_tvalid_128b_in = '1') then
rx_tvalid_128b_cnt_r <= rx_tvalid_128b_cnt_r + 1;
end if;
end if;
end process;
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
if ((rx_path_fifo_rst_n = '1' and rx_path_fifo_rst_1_n = '0') or cnt_reset_in = '1') then
rx_overflow_128b_cnt_r <= (others => '0');
elsif (rx_tvalid_128b_en = '1' and rx_tready_128b = '0') then
rx_overflow_128b_cnt_r <= rx_overflow_128b_cnt_r + 1;
end if;
end if;
end process;
rx_tvalid_128b_en <= rx_tvalid_128b_in when playback_data_path_enable = '1' else '0';
i_rx_register_slice_128b : entity work.axis_register_slice_128b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_128b_in, -- in
s_axis_tvalid => rx_tvalid_128b_en, -- in
s_axis_tready => rx_tready_128b, -- out
m_axis_tdata => rx_tdata_128b_pipe, -- out
m_axis_tvalid => rx_tvalid_128b_pipe, -- out
m_axis_tready => rx_tready_128b_pipe -- in
);
-- i_ila_4 : entity work.ila_4
-- port map (
-- clk => rx_device_clk_in,
-- probe0 => rx_tdata_128b_in, -- 128
-- probe1 => rx_tvalid_128b_en, -- 1
-- probe2 => rx_tready_128b, -- 1
-- probe3 => rx_tvalid_128b_cnt_r -- 32
-- );
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
if ((rx_path_fifo_rst_n = '1' and rx_path_fifo_rst_1_n = '0') or cnt_reset_in = '1') then
rx_tvalid_128b_en_cnt_r <= (others => '0');
elsif (rx_tvalid_128b_pipe = '1' and rx_tready_128b_pipe = '1') then
rx_tvalid_128b_en_cnt_r <= rx_tvalid_128b_en_cnt_r + 1;
end if;
end if;
end process;
i_axis_dwidth_converter_128b_to_512b : entity work.axis_dwidth_converter_128b_to_512b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_128b_pipe, -- in
s_axis_tvalid => rx_tvalid_128b_pipe,-- in
s_axis_tready => rx_tready_128b_pipe,-- out
m_axis_tdata => rx_tdata_512b, -- out
m_axis_tvalid => rx_tvalid_512b, -- out
m_axis_tready => rx_tready_512b -- in
);
i_qsfp_reg_slice_512 : entity work.axis_register_slice_512b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_512b, -- in
s_axis_tvalid => rx_tvalid_512b, -- in
s_axis_tready => rx_tready_512b, -- out
m_axis_tdata => rx_tdata_512b_pipe, -- out
m_axis_tvalid => rx_tvalid_512b_pipe, -- out
m_axis_tready => rx_tready_512b_pipe -- in
);
i_iq_512b_to_240b : entity work.iq_512b_to_240b
port map (
aclk => rx_device_clk_in, -- in
aresetn => iq_512b_to_240b_rst_n, -- in
s_axis_tdata => rx_tdata_512b_pipe, --in
s_axis_tvalid => rx_tvalid_512b_pipe, --in
s_axis_tready => rx_tready_512b_pipe, --out
m_axis_tdata => rx_tdata_240b, --out
m_axis_tvalid => rx_tvalid_240b, --out
m_axis_tready => rx_tready_240b --in
);
i_qsfp_reg_slice_240b : entity work.axis_register_slice_240b
port map (
aclk => rx_device_clk_in, -- in
aresetn => rx_path_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_240b, --in
s_axis_tvalid => rx_tvalid_240b, --in
s_axis_tready => rx_tready_240b, --out
m_axis_tdata => rx_tdata_240b_pipe, --out
m_axis_tvalid => rx_tvalid_240b_pipe, --out
m_axis_tready => rx_tready_240b_pipe --in
);
i_qsfp_fifo : entity work.axis_data_afifo_32x240
port map (
s_axis_aclk => rx_device_clk_in, -- in
s_axis_aresetn => qsfp_fifo_rst_n, -- in
s_axis_tdata => rx_tdata_240b_pipe, --in rx_tdata_240b, --in
s_axis_tvalid => rx_tvalid_240b_pipe, --in rx_tvalid_240b, --in
s_axis_tready => rx_tready_240b_pipe, --out rx_tready_240b, --out
m_axis_aclk => qsfp_playback_aclk_in, -- in
m_axis_tdata => qsfp_playback_tdata_240b_out, --out
m_axis_tvalid => qsfp_playback_tvalid_240b, --out
m_axis_tready => qsfp_playback_tready_240b_in --in
);
process(qsfp_playback_aclk_in)
begin
if (rising_edge(qsfp_playback_aclk_in)) then
qsfp_fifo_rst_n_r <= qsfp_fifo_rst_n_r(1 to 2) & qsfp_fifo_rst_n;
end if;
end process;
process(qsfp_playback_aclk_in)
begin
if (rising_edge(qsfp_playback_aclk_in)) then
if ((qsfp_fifo_rst_n_r(1) = '1' and qsfp_fifo_rst_n_r(0) = '0') or cnt_reset_in = '1') then
qsfp_playback_tvalid_240b_cnt_r <= (others => '0');
elsif (qsfp_playback_tvalid_240b = '1' and qsfp_playback_tready_240b_in = '1') then
qsfp_playback_tvalid_240b_cnt_r <= qsfp_playback_tvalid_240b_cnt_r + 1;
end if;
end if;
end process;
end architecture arch_imp;
source/raw_eth_wrapper_cmac_4.v
+173
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
//Date : Thu Mar 5 18:53:36 2026
//Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
//Command : generate_target raw_eth_wrapper.bd
//Design : raw_eth_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module raw_eth_wrapper_cmac_4
(axil_clk_0,
axil_resetn_0,
clk_100_0,
clk_100_reset_0,
cmac_gt_0_grx_n,
cmac_gt_0_grx_p,
cmac_gt_0_gtx_n,
cmac_gt_0_gtx_p,
cmac_refclk_0_clk_n,
cmac_refclk_0_clk_p,
m_axis_aclk,
m_axis_aresetn,
m_axis_tdata,
m_axis_tready,
m_axis_tvalid,
s_axil_0_araddr,
s_axil_0_arprot,
s_axil_0_arready,
s_axil_0_arvalid,
s_axil_0_awaddr,
s_axil_0_awprot,
s_axil_0_awready,
s_axil_0_awvalid,
s_axil_0_bready,
s_axil_0_bresp,
s_axil_0_bvalid,
s_axil_0_rdata,
s_axil_0_rready,
s_axil_0_rresp,
s_axil_0_rvalid,
s_axil_0_wdata,
s_axil_0_wready,
s_axil_0_wstrb,
s_axil_0_wvalid,
s_axis_aresetn,
s_axis_clk,
s_axis_tdata,
s_axis_tready,
s_axis_tvalid);
input axil_clk_0;
input axil_resetn_0;
input clk_100_0;
input clk_100_reset_0;
input [3:0]cmac_gt_0_grx_n;
input [3:0]cmac_gt_0_grx_p;
output [3:0]cmac_gt_0_gtx_n;
output [3:0]cmac_gt_0_gtx_p;
input cmac_refclk_0_clk_n;
input cmac_refclk_0_clk_p;
input m_axis_aclk;
input m_axis_aresetn;
output [511:0]m_axis_tdata;
input m_axis_tready;
output m_axis_tvalid;
input [31:0]s_axil_0_araddr;
input [2:0]s_axil_0_arprot;
output s_axil_0_arready;
input s_axil_0_arvalid;
input [31:0]s_axil_0_awaddr;
input [2:0]s_axil_0_awprot;
output s_axil_0_awready;
input s_axil_0_awvalid;
input s_axil_0_bready;
output [1:0]s_axil_0_bresp;
output s_axil_0_bvalid;
output [31:0]s_axil_0_rdata;
input s_axil_0_rready;
output [1:0]s_axil_0_rresp;
output s_axil_0_rvalid;
input [31:0]s_axil_0_wdata;
output s_axil_0_wready;
input [3:0]s_axil_0_wstrb;
input s_axil_0_wvalid;
input s_axis_aresetn;
input s_axis_clk;
input [511:0]s_axis_tdata;
output s_axis_tready;
input s_axis_tvalid;
wire axil_clk_0;
wire axil_resetn_0;
wire clk_100_0;
wire clk_100_reset_0;
wire [3:0]cmac_gt_0_grx_n;
wire [3:0]cmac_gt_0_grx_p;
wire [3:0]cmac_gt_0_gtx_n;
wire [3:0]cmac_gt_0_gtx_p;
wire cmac_refclk_0_clk_n;
wire cmac_refclk_0_clk_p;
wire m_axis_aclk;
wire m_axis_aresetn;
wire [511:0]m_axis_tdata;
wire m_axis_tready;
wire m_axis_tvalid;
wire [31:0]s_axil_0_araddr;
wire [2:0]s_axil_0_arprot;
wire s_axil_0_arready;
wire s_axil_0_arvalid;
wire [31:0]s_axil_0_awaddr;
wire [2:0]s_axil_0_awprot;
wire s_axil_0_awready;
wire s_axil_0_awvalid;
wire s_axil_0_bready;
wire [1:0]s_axil_0_bresp;
wire s_axil_0_bvalid;
wire [31:0]s_axil_0_rdata;
wire s_axil_0_rready;
wire [1:0]s_axil_0_rresp;
wire s_axil_0_rvalid;
wire [31:0]s_axil_0_wdata;
wire s_axil_0_wready;
wire [3:0]s_axil_0_wstrb;
wire s_axil_0_wvalid;
wire s_axis_aresetn;
wire s_axis_clk;
wire [511:0]s_axis_tdata;
wire s_axis_tready;
wire s_axis_tvalid;
raw_eth_cmac_4 raw_eth_cmac_4_i
(.axil_clk_0(axil_clk_0),
.axil_resetn_0(axil_resetn_0),
.clk_100_0(clk_100_0),
.clk_100_reset_0(clk_100_reset_0),
.cmac_gt_0_grx_n(cmac_gt_0_grx_n),
.cmac_gt_0_grx_p(cmac_gt_0_grx_p),
.cmac_gt_0_gtx_n(cmac_gt_0_gtx_n),
.cmac_gt_0_gtx_p(cmac_gt_0_gtx_p),
.cmac_refclk_0_clk_n(cmac_refclk_0_clk_n),
.cmac_refclk_0_clk_p(cmac_refclk_0_clk_p),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_tdata(m_axis_tdata),
.m_axis_tready(m_axis_tready),
.m_axis_tvalid(m_axis_tvalid),
.s_axil_0_araddr(s_axil_0_araddr),
.s_axil_0_arprot(s_axil_0_arprot),
.s_axil_0_arready(s_axil_0_arready),
.s_axil_0_arvalid(s_axil_0_arvalid),
.s_axil_0_awaddr(s_axil_0_awaddr),
.s_axil_0_awprot(s_axil_0_awprot),
.s_axil_0_awready(s_axil_0_awready),
.s_axil_0_awvalid(s_axil_0_awvalid),
.s_axil_0_bready(s_axil_0_bready),
.s_axil_0_bresp(s_axil_0_bresp),
.s_axil_0_bvalid(s_axil_0_bvalid),
.s_axil_0_rdata(s_axil_0_rdata),
.s_axil_0_rready(s_axil_0_rready),
.s_axil_0_rresp(s_axil_0_rresp),
.s_axil_0_rvalid(s_axil_0_rvalid),
.s_axil_0_wdata(s_axil_0_wdata),
.s_axil_0_wready(s_axil_0_wready),
.s_axil_0_wstrb(s_axil_0_wstrb),
.s_axil_0_wvalid(s_axil_0_wvalid),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_clk(s_axis_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tready(s_axis_tready),
.s_axis_tvalid(s_axis_tvalid));
endmodule
source/system_raw_eth_top.v
+1264
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source/system_top.v
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source/tick_gen.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tick_gen is
generic(
CLOCK_SPEED_MHZ : integer := 100
);
port(
clk_in : in std_logic;
tick_1us_out : out std_logic;
tick_1ms_out : out std_logic;
tick_500ms_out : out std_logic;
tick_750ms_out : out std_logic;
tick_1s_out : out std_logic;
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
prog_us_tick_out : out std_logic;
reset_in : in std_logic
);
end entity tick_gen;
architecture imp of tick_gen is
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
signal usec_cnt_r : integer range 0 to 999;
signal msec_cnt_r : integer range 0 to 499;
signal msec_cnt1_r : integer range 0 to 999;
signal tick_1us_r : std_logic;
signal tick_1ms_r : std_logic;
signal tick_500ms_r : std_logic;
signal tick_750ms_r : std_logic;
signal tick_1s_r : std_logic;
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
signal prog_us_tick_r : std_logic;
begin
tick_1us_out <= tick_1us_r;
tick_1ms_out <= tick_1ms_r;
tick_500ms_out <= tick_500ms_r;
tick_750ms_out <= tick_750ms_r;
tick_1s_out <= tick_1s_r;
prog_us_tick_out <= prog_us_tick_r;
process(clk_in, reset_in)
begin
if(reset_in = '1') then
sysclk_cnt_r <= 0;
usec_cnt_r <= 0;
msec_cnt_r <= 0;
msec_cnt1_r <= 0;
tick_1us_r <= '1';
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '0';
elsif rising_edge(clk_in) then
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_us_tick_r <= '0';
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
sysclk_cnt_r <= 0;
tick_1us_r <= '1';
else
sysclk_cnt_r <= sysclk_cnt_r + 1;
tick_1us_r <= '0';
end if;
if(tick_1us_r = '1') then
if(usec_cnt_r = 999) then -- 1000us
usec_cnt_r <= 0;
tick_1ms_r <= '1';
else
usec_cnt_r <= usec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt_r = 499) then -- 500ms
msec_cnt_r <= 0;
tick_500ms_r <= '1';
else
msec_cnt_r <= msec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt1_r = 749) then -- 750ms
tick_750ms_r <= '1';
end if;
if(msec_cnt1_r = 999) then -- 1s
msec_cnt1_r <= 0;
tick_1s_r <= '1';
else
msec_cnt1_r <= msec_cnt1_r + 1;
end if;
end if;
if(tick_1us_r = '1') then
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '1';
else
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
end if;
end if;
end if;
end process;
end architecture imp;