moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_1kx240_1",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "2048", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_1kx240_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"prog_full": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
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{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,337 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/08/2023
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_p_intfc
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
--
|
||||
--p_enable_in_0 : out std_logic;
|
||||
--p_enable_in_1 : out std_logic;
|
||||
--p_enable_in_2 : out std_logic;
|
||||
--p_enable_in_3 : out std_logic;
|
||||
--p_enable_out_0 : out std_logic;
|
||||
--p_enable_out_1 : out std_logic;
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
--
|
||||
--p_ready_in_0 : in std_logic;
|
||||
--p_ready_in_1 : in std_logic;
|
||||
--p_ready_in_2 : in std_logic;
|
||||
--p_ready_in_3 : in std_logic;
|
||||
--p_ready_out_0 : in std_logic;
|
||||
--p_ready_out_1 : in std_logic;
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
--
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end dig_iq_p_intfc;
|
||||
|
||||
architecture arch_imp of dig_iq_p_intfc is
|
||||
|
||||
--signal p_ready : std_logic_vector(7 downto 0);
|
||||
signal strb_in_r : std_logic := '0';
|
||||
signal strb_int : std_logic;
|
||||
signal addr_int : std_logic_vector(11 downto 0);
|
||||
signal sel_int : std_logic_vector(2 downto 0);
|
||||
signal write_int : std_logic;
|
||||
signal wdata_int : std_logic_vector(31 downto 0);
|
||||
signal p_addr_r : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal p_write_r : std_logic := '0';
|
||||
signal p_wdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal p_enable_r : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_enable_r1 : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_strb_r : std_logic := '0';
|
||||
signal p_ready_r : std_logic := '0';
|
||||
signal p_rdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
SAME_CLKS_FALSE_GEN :
|
||||
if SAME_CLKS = 0 generate
|
||||
begin
|
||||
|
||||
i_cdc_pulse_strb : xpm_cdc_pulse
|
||||
generic map (
|
||||
DEST_SYNC_FF => 7, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
REG_OUTPUT => 1, -- DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
RST_USED => 0, -- DECIMAL; 0=no reset, 1=implement reset
|
||||
SIM_ASSERT_CHK => 0 -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
)
|
||||
port map (
|
||||
dest_rst => '0',
|
||||
dest_pulse => strb_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => reg_clk,
|
||||
src_pulse => strb_in,
|
||||
src_rst => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_addr : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 12 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => addr_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => addr_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_sel : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 3 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => sel_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => sel_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_wdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => wdata_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => wdata_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_single_write : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => write_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => '0',
|
||||
src_in => write_in
|
||||
);
|
||||
|
||||
i_cdc_single_ready : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => ready_out,
|
||||
dest_clk => reg_clk,
|
||||
src_clk => '0',
|
||||
src_in => p_ready_r
|
||||
);
|
||||
|
||||
i_cdc_array_rdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => rdata_out,
|
||||
dest_clk => reg_clk,
|
||||
src_in => p_rdata_r,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
SAME_CLKS_TRUE_GEN :
|
||||
if SAME_CLKS = 1 generate
|
||||
begin
|
||||
|
||||
strb_int <= not(strb_in_r) and strb_in;
|
||||
addr_int <= addr_in;
|
||||
sel_int <= sel_in;
|
||||
wdata_int <= wdata_in;
|
||||
write_int <= write_in;
|
||||
ready_out <= p_ready_r;
|
||||
rdata_out <= p_rdata_r;
|
||||
|
||||
end generate;
|
||||
---------------------------------------
|
||||
|
||||
|
||||
|
||||
-- APB Interface Ports
|
||||
p_addr <= p_addr_r;
|
||||
p_write <= p_write_r;
|
||||
p_wdata <= p_wdata_r;
|
||||
|
||||
p_enable <= p_enable_r1;
|
||||
--p_enable_in_0 <= p_enable_r1(0);
|
||||
--p_enable_in_1 <= p_enable_r1(1);
|
||||
--p_enable_in_2 <= p_enable_r1(2);
|
||||
--p_enable_in_3 <= p_enable_r1(3);
|
||||
--p_enable_out_0 <= p_enable_r1(4);
|
||||
--p_enable_out_1 <= p_enable_r1(5);
|
||||
|
||||
--p_ready(0) <= p_ready_in_0;
|
||||
--p_ready(1) <= p_ready_in_1;
|
||||
--p_ready(2) <= p_ready_in_2;
|
||||
--p_ready(3) <= p_ready_in_3;
|
||||
--p_ready(4) <= p_ready_out_0;
|
||||
--p_ready(5) <= p_ready_out_1;
|
||||
|
||||
|
||||
process(clk_125)
|
||||
begin
|
||||
if(rising_edge(clk_125))then
|
||||
if(clk_125_resetn = '0')then
|
||||
strb_in_r <= '0';
|
||||
p_addr_r <= (others => '0');
|
||||
p_write_r <= '0';
|
||||
p_wdata_r <= (others => '0');
|
||||
p_enable_r <= (others => '0');
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_strb_r <= '0';
|
||||
p_ready_r <= '0';
|
||||
p_rdata_r <= (others => '0');
|
||||
else
|
||||
strb_in_r <= strb_in;
|
||||
|
||||
p_strb_r <= strb_int;
|
||||
|
||||
if(strb_int = '1')then
|
||||
p_addr_r <= addr_int;
|
||||
p_write_r <= write_int;
|
||||
p_wdata_r <= wdata_int;
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_enable_r <= "00000001";
|
||||
when "001" =>
|
||||
p_enable_r <= "00000010";
|
||||
when "010" =>
|
||||
p_enable_r <= "00000100";
|
||||
when "011" =>
|
||||
p_enable_r <= "00001000";
|
||||
when "100" =>
|
||||
p_enable_r <= "00010000";
|
||||
when "101" =>
|
||||
p_enable_r <= "00100000";
|
||||
when "110" =>
|
||||
p_enable_r <= "01000000";
|
||||
when "111" =>
|
||||
p_enable_r <= "10000000";
|
||||
when others =>
|
||||
p_enable_r <= "00000000";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
if(p_strb_r = '1')then
|
||||
|
||||
p_enable_r1 <= p_enable_r;
|
||||
if(p_enable_r /= "00000000")then
|
||||
p_ready_r <= '0';
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
if(p_ready = "11111111")then
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_ready_r <= '1';
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_rdata_r <= p_rdata_0;
|
||||
when "001" =>
|
||||
p_rdata_r <= p_rdata_1;
|
||||
when "010" =>
|
||||
p_rdata_r <= p_rdata_2;
|
||||
when "011" =>
|
||||
p_rdata_r <= p_rdata_3;
|
||||
when "100" =>
|
||||
p_rdata_r <= p_rdata_4;
|
||||
when "101" =>
|
||||
p_rdata_r <= p_rdata_5;
|
||||
when "110" =>
|
||||
p_rdata_r <= p_rdata_6;
|
||||
when "111" =>
|
||||
p_rdata_r <= p_rdata_7;
|
||||
when others =>
|
||||
p_rdata_r <= x"DEADBEEF";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,592 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/02/2023 02:07:25 PM
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_x2 - structural
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_x2 is
|
||||
port (
|
||||
clk_125_resetn_in : in std_logic;
|
||||
clk_125_in : in std_logic;
|
||||
|
||||
aclk_in : in std_logic;
|
||||
aresetn_in : in std_logic;
|
||||
cmd_strb_in : in std_logic;
|
||||
cmd_addr_in : in std_logic_vector(11 downto 0);
|
||||
cmd_write_in : in std_logic;
|
||||
cmd_sel_in : in std_logic_vector(2 downto 0);
|
||||
cmd_wdata_in : in std_logic_vector(31 downto 0);
|
||||
cmd_ready_out : out std_logic;
|
||||
cmd_rdata_out : out std_logic_vector(31 downto 0);
|
||||
dig_iq_interface_reset_in : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_resetn : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_rx_enable : in std_logic_vector(1 downto 0);
|
||||
--
|
||||
dig_iq_interface_ready_out : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_cc_overflow : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_tx_overflow : out std_logic_vector(PORT_CNT-1 downto 0);
|
||||
rx_data_ready_in : in std_logic_vector(1 downto 0);
|
||||
|
||||
axis_0_aclk_out : out std_logic;
|
||||
axis_0_aresetn_out : out std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
s0_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s0_axis_tvalid_in : in std_logic;
|
||||
s0_axis_tready_out : out std_logic;
|
||||
|
||||
axis_1_aclk_out : out std_logic;
|
||||
axis_1_aresetn_out : out std_logic;
|
||||
m1_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
s1_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s1_axis_tvalid_in : in std_logic;
|
||||
s1_axis_tready_out : out std_logic;
|
||||
|
||||
tx_data_channel_reset_in : in std_logic;
|
||||
tx_data_clear_in : in std_logic;
|
||||
|
||||
qsfp0_ref_clk_n_in : in std_logic;
|
||||
qsfp0_ref_clk_p_in : in std_logic;
|
||||
qsfp0_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txp_out : out std_logic_vector(3 downto 0);
|
||||
|
||||
qsfp1_ref_clk_n_in : in std_logic;
|
||||
qsfp1_ref_clk_p_in : in std_logic;
|
||||
qsfp1_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txp_out : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end dig_iq_x2;
|
||||
|
||||
architecture structural of dig_iq_x2 is
|
||||
|
||||
component DIG_IQ_HS_CUSTOM1X is
|
||||
port(
|
||||
INIT_CLK : in std_logic := '0';
|
||||
INTERFACE_RESET : in std_logic := '1';
|
||||
IntL : in std_logic := '1';
|
||||
MGTREFCLK_N : in std_logic := '1';
|
||||
MGTREFCLK_P : in std_logic := '0';
|
||||
ModPrsL : in std_logic := '1';
|
||||
PADDR : in std_logic_vector (11 downto 0) := (others => '0');
|
||||
PCLK : in std_logic := '0';
|
||||
PENABLE : in std_logic := '0';
|
||||
PRESETn : in std_logic := '0';
|
||||
PSEL : in std_logic := '0';
|
||||
PWDATA : in std_logic_vector (31 downto 0) := (others => '0');
|
||||
PWRITE : in std_logic := '0';
|
||||
RXN : in std_logic_vector (3 downto 0) := (others => '1');
|
||||
RXP : in std_logic_vector (3 downto 0) := (others => '0');
|
||||
RX_DATA_READY : in std_logic := '1';
|
||||
SCL_I : in std_logic := '0';
|
||||
SDA_I : in std_logic := '0';
|
||||
TX_DATA_CLEAR : in std_logic := '0';
|
||||
TX_DATA_DAT : in std_logic_vector (239 downto 0) := (others => '0');
|
||||
TX_DATA_EN : in std_logic := '0';
|
||||
TX_DATA_CHANNEL_RESET : in std_logic := '0';
|
||||
RX_DATA_CHANNEL_RESET : out std_logic;
|
||||
DATA_CLK : out std_logic ;
|
||||
INTERFACE_READY : out std_logic ;
|
||||
ModselL : out std_logic ;
|
||||
PRDATA : out std_logic_vector (31 downto 0);
|
||||
PREADY : out std_logic ;
|
||||
RX_DATA_DAT : out std_logic_vector (239 downto 0);
|
||||
RX_DATA_EN : out std_logic ;
|
||||
SCL_O : out std_logic ;
|
||||
SCL_OE : out std_logic ;
|
||||
SDA_O : out std_logic ;
|
||||
SDA_OE : out std_logic ;
|
||||
TXN : out std_logic_vector (3 downto 0);
|
||||
TXP : out std_logic_vector (3 downto 0);
|
||||
TX_DATA_READY : out std_logic
|
||||
);
|
||||
end component DIG_IQ_HS_CUSTOM1X;
|
||||
|
||||
component dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
--
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component dig_iq_p_intfc;
|
||||
|
||||
component axis_clock_converter_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
m_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component axis_data_fifo_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal p_addr : std_logic_vector(11 downto 0);
|
||||
signal p_write : std_logic;
|
||||
signal p_wdata : std_logic_vector(31 downto 0);
|
||||
signal p_enable : std_logic_vector(7 downto 0);
|
||||
signal p_ready : std_logic_vector(7 downto 0);
|
||||
|
||||
type SLV_32_ARRAY is array (integer range 0 to 1) of std_logic_vector(31 downto 0);
|
||||
signal p_rdata : SLV_32_ARRAY;
|
||||
|
||||
type SLV_4_ARRAY is array (integer range 0 to 1) of std_logic_vector(3 downto 0);
|
||||
signal qsfp_rx_rxn : SLV_4_ARRAY;
|
||||
signal qsfp_rx_rxp : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txn : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txp : SLV_4_ARRAY;
|
||||
|
||||
type SLV_240_ARRAY is array (integer range 0 to 1) of std_logic_vector(239 downto 0);
|
||||
--signal tx_data_r : SLV_240_ARRAY;
|
||||
--signal rx_data_r : SLV_240_ARRAY;
|
||||
signal rx_data : SLV_240_ARRAY;
|
||||
signal s_axis_tdata : SLV_240_ARRAY;
|
||||
--signal m_axis_tdata_int : SLV_240_ARRAY;
|
||||
--signal tx_fifo_m_tdata : SLV_240_ARRAY;
|
||||
|
||||
signal clk : std_logic_vector(1 downto 0);
|
||||
--signal resetn : std_logic_vector(1 downto 0);
|
||||
--signal rx_enable : std_logic_vector(1 downto 0);
|
||||
signal interface_reset : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_n : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_p : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal rx_data_en : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal tx_data_ready : std_logic_vector(1 downto 0);
|
||||
signal s_axis_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal m_axis_tvalid_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_tready : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_r : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
--signal tx_fifo_m_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal s_axis_tready_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_fifo_overflow_int : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
|
||||
signal dig_iq_interface_ready : std_logic_vector(1 downto 0);
|
||||
signal axis_0_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
signal axis_1_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
|
||||
type array_32b_type is array (0 to 1) of std_logic_vector(0 to 31);
|
||||
signal tx_data_channel_reset_r : array_32b_type := (others => (others => '0'));
|
||||
signal tx_data_clear_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
p_ready(7 downto 2) <= (others => '1');
|
||||
|
||||
i_dig_iq_p_intfc : dig_iq_p_intfc
|
||||
generic map(
|
||||
SAME_CLKS => 1
|
||||
)
|
||||
port map(
|
||||
reg_clk => clk_125_in,
|
||||
reg_resetn => clk_125_resetn_in,
|
||||
--
|
||||
strb_in => cmd_strb_in,
|
||||
addr_in => cmd_addr_in,
|
||||
write_in => cmd_write_in,
|
||||
sel_in => cmd_sel_in,
|
||||
wdata_in => cmd_wdata_in,
|
||||
ready_out => cmd_ready_out,
|
||||
rdata_out => cmd_rdata_out,
|
||||
--
|
||||
clk_125 => clk_125_in,
|
||||
clk_125_resetn => clk_125_resetn_in,
|
||||
--
|
||||
p_addr => p_addr,
|
||||
p_write => p_write,
|
||||
p_wdata => p_wdata,
|
||||
p_enable => p_enable,
|
||||
p_ready => p_ready,
|
||||
p_rdata_0 => p_rdata(0),
|
||||
p_rdata_1 => p_rdata(1),
|
||||
p_rdata_2 => (others => '0'),
|
||||
p_rdata_3 => (others => '0'),
|
||||
p_rdata_4 => (others => '0'),
|
||||
p_rdata_5 => (others => '0'),
|
||||
p_rdata_6 => (others => '0'),
|
||||
p_rdata_7 => (others => '0')
|
||||
);
|
||||
|
||||
i_cdc_0 : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 2 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => interface_reset,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => dig_iq_interface_reset_in
|
||||
);
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
dig_iq_interface_ready_out <= dig_iq_interface_ready;
|
||||
|
||||
axis_0_aclk_out <= clk(0);
|
||||
axis_0_aresetn_out <= axis_0_aresetn_r(0);
|
||||
s_axis_tdata(0) <= s0_axis_tdata_in;
|
||||
s_axis_tvalid(0) <= s0_axis_tvalid_in;
|
||||
s0_axis_tready_out <= tx_data_ready(0);--s_axis_tready_int(0);
|
||||
m0_axis_tdata_out <= rx_data(0);--m_axis_tdata_int(0);
|
||||
m0_axis_tvalid_out <= rx_data_en(0);--m_axis_tvalid_int(0);
|
||||
|
||||
axis_1_aclk_out <= clk(1);
|
||||
axis_1_aresetn_out <= axis_1_aresetn_r(0);
|
||||
s_axis_tdata(1) <= s1_axis_tdata_in;
|
||||
s_axis_tvalid(1) <= s1_axis_tvalid_in;
|
||||
s1_axis_tready_out <= tx_data_ready(1);--s_axis_tready_int(1);
|
||||
m1_axis_tdata_out <= rx_data(1);--m_axis_tdata_int(1);
|
||||
m1_axis_tvalid_out <= rx_data_en(1);--m_axis_tvalid_int(1);
|
||||
|
||||
qsfp_ref_clk_n(0) <= qsfp0_ref_clk_n_in;
|
||||
qsfp_ref_clk_n(1) <= qsfp1_ref_clk_n_in;
|
||||
|
||||
qsfp_ref_clk_p(0) <= qsfp0_ref_clk_p_in;
|
||||
qsfp_ref_clk_p(1) <= qsfp1_ref_clk_p_in;
|
||||
|
||||
qsfp_rx_rxn(0) <= qsfp0_rx_rxn_in;
|
||||
qsfp_rx_rxn(1) <= qsfp1_rx_rxn_in;
|
||||
|
||||
qsfp_rx_rxp(0) <= qsfp0_rx_rxp_in;
|
||||
qsfp_rx_rxp(1) <= qsfp1_rx_rxp_in;
|
||||
|
||||
qsfp0_tx_txn_out <= qsfp_tx_txn(0);
|
||||
qsfp1_tx_txn_out <= qsfp_tx_txn(1);
|
||||
|
||||
qsfp0_tx_txp_out <= qsfp_tx_txp(0);
|
||||
qsfp1_tx_txp_out <= qsfp_tx_txp(1);
|
||||
|
||||
|
||||
process(clk(0))
|
||||
begin
|
||||
if (rising_edge(clk(0))) then
|
||||
if (dig_iq_interface_ready(0) = '1') then
|
||||
axis_0_aresetn_r <= axis_0_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_0_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk(1))
|
||||
begin
|
||||
if (rising_edge(clk(1))) then
|
||||
if (dig_iq_interface_ready(1) = '1') then
|
||||
axis_1_aresetn_r <= axis_1_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_1_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
GEN_0:
|
||||
for i in 0 to 1 generate
|
||||
begin
|
||||
|
||||
|
||||
-- i_cdc_resetn : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => resetn(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_resetn(i)
|
||||
-- );
|
||||
|
||||
-- i_cdc_rx_enable : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => rx_enable(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_rx_enable(i)
|
||||
-- );
|
||||
|
||||
|
||||
process(clk(i))
|
||||
begin
|
||||
if (rising_edge(clk(i))) then
|
||||
tx_data_clear_r(i) <= tx_data_clear_in;
|
||||
tx_data_channel_reset_r(i) <= tx_data_channel_reset_r(i)(1 to 31) & '0';
|
||||
|
||||
if (tx_data_channel_reset_in = '1') then
|
||||
tx_data_channel_reset_r(i) <= (others => '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
i_dig_iq : DIG_IQ_HS_CUSTOM1X
|
||||
port map(
|
||||
INIT_CLK => clk_125_in,
|
||||
INTERFACE_RESET => interface_reset(i),
|
||||
IntL => '1',
|
||||
MGTREFCLK_N => qsfp_ref_clk_n(i),
|
||||
MGTREFCLK_P => qsfp_ref_clk_p(i),
|
||||
ModPrsL => '0',
|
||||
PADDR => p_addr,
|
||||
PCLK => clk_125_in,
|
||||
PENABLE => p_enable(i),
|
||||
PRESETn => clk_125_resetn_in,
|
||||
PSEL => '1',
|
||||
PWDATA => p_wdata,
|
||||
PWRITE => p_write,
|
||||
RXN => qsfp_rx_rxn(i),
|
||||
RXP => qsfp_rx_rxp(i),
|
||||
RX_DATA_READY => rx_data_ready_in(i),
|
||||
SCL_I => '0',
|
||||
SDA_I => '0',
|
||||
TX_DATA_CHANNEL_RESET => tx_data_channel_reset_r(i)(0),
|
||||
TX_DATA_CLEAR => tx_data_clear_r(i),
|
||||
TX_DATA_DAT => s_axis_tdata(i),--tx_data_r(i),
|
||||
TX_DATA_EN => s_axis_tvalid(i),--tx_data_en_r(i),
|
||||
DATA_CLK => clk(i),
|
||||
INTERFACE_READY => dig_iq_interface_ready(i),
|
||||
ModselL => open,
|
||||
PRDATA => p_rdata(i),
|
||||
PREADY => p_ready(i),
|
||||
RX_DATA_CHANNEL_RESET => open,
|
||||
RX_DATA_DAT => rx_data(i),
|
||||
RX_DATA_EN => rx_data_en(i),
|
||||
SCL_O => open,
|
||||
SCL_OE => open,
|
||||
SDA_O => open,
|
||||
SDA_OE => open,
|
||||
TXN => qsfp_tx_txn(i),
|
||||
TXP => qsfp_tx_txp(i),
|
||||
TX_DATA_READY => tx_data_ready(i)
|
||||
);
|
||||
|
||||
-- GEN_1:
|
||||
-- for j in 0 to 239 generate
|
||||
-- begin
|
||||
|
||||
-- i_FD_rx_data : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
-- end generate;
|
||||
|
||||
-- rx_data_en_int(i) <= rx_data_en(i) and rx_enable(i);
|
||||
|
||||
-- i_FD_rx_data_en : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- i_clock_converter : axis_clock_converter_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => resetn(i),
|
||||
-- m_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => clk(i),
|
||||
-- s_axis_tvalid => rx_data_en_r(i),
|
||||
-- s_axis_tready => cc_overflow_tready(i),
|
||||
-- s_axis_tdata => rx_data_r(i),
|
||||
-- m_axis_aclk => aclk_in,
|
||||
-- m_axis_tvalid => m_axis_tvalid_int(i),
|
||||
-- m_axis_tready => m_axis_tvalid_int(i),
|
||||
-- m_axis_tdata => m_axis_tdata_int(i)
|
||||
-- );
|
||||
|
||||
-- cc_overflow_int(i) <= not(cc_overflow_tready(i)) and rx_data_en_r(i);
|
||||
|
||||
-- i_FDRE_cc_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_cc_overflow(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- CE => cc_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => resetn(i) -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- R&S Documentation states:
|
||||
--
|
||||
-- TX_DATA_READY signal -- TX channel is receptive. After the deactivation of this signal,
|
||||
-- up to five more enabled data samples are allowed on the TX_DATA_DAT
|
||||
-- bus.
|
||||
-- Thus, we can pipeline the tx_data between the output of the FIFO and the R&S core.
|
||||
--
|
||||
-- ** PIPELINING IS CURRENTLY COMMENTED OUT **
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
-- i_tx_fifo : axis_data_fifo_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => aclk_in,
|
||||
-- s_axis_tvalid => s_axis_tvalid(i),
|
||||
-- s_axis_tready => s_axis_tready_int(i),
|
||||
-- s_axis_tdata => s_axis_tdata(i),
|
||||
-- m_axis_aclk => clk(i),
|
||||
-- m_axis_tvalid => tx_fifo_m_tvalid(i),
|
||||
-- m_axis_tready => tx_data_ready(i),
|
||||
-- m_axis_tdata => tx_fifo_m_tdata(i)
|
||||
-- );
|
||||
|
||||
--tx_fifo_overflow_int(i) <= not(s_axis_tready_int(i)) and s_axis_tvalid(i);
|
||||
|
||||
-- i_FDRE_tx_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_tx_overflow(i), -- 1-bit output: Data
|
||||
-- C => aclk_in, -- 1-bit input: Clock
|
||||
-- CE => tx_fifo_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => aresetn_in -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_int(i) <= tx_fifo_m_tvalid(i) and tx_data_ready(i);
|
||||
|
||||
--i_FD_tx_data_en : FD --RE
|
||||
--generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
--port map (
|
||||
-- Q => tx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_r(i) <= tx_data_en_int(i);
|
||||
|
||||
--GEN_2:
|
||||
--for j in 0 to 239 generate
|
||||
-- begin
|
||||
--
|
||||
-- i_FD_tx_data : FD --RE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => tx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_fifo_m_tdata(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
--
|
||||
-- end generate;
|
||||
|
||||
-- tx_data_r(i) <= tx_fifo_m_tdata(i);
|
||||
|
||||
end generate;
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
end structural;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity tick_gen is
|
||||
generic(
|
||||
CLOCK_SPEED_MHZ : integer := 100
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
tick_1us_out : out std_logic;
|
||||
tick_1ms_out : out std_logic;
|
||||
tick_500ms_out : out std_logic;
|
||||
tick_750ms_out : out std_logic;
|
||||
tick_1s_out : out std_logic;
|
||||
|
||||
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
|
||||
prog_us_tick_out : out std_logic;
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity tick_gen;
|
||||
|
||||
architecture imp of tick_gen is
|
||||
|
||||
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
|
||||
signal usec_cnt_r : integer range 0 to 999;
|
||||
signal msec_cnt_r : integer range 0 to 499;
|
||||
signal msec_cnt1_r : integer range 0 to 999;
|
||||
signal tick_1us_r : std_logic;
|
||||
signal tick_1ms_r : std_logic;
|
||||
signal tick_500ms_r : std_logic;
|
||||
signal tick_750ms_r : std_logic;
|
||||
signal tick_1s_r : std_logic;
|
||||
|
||||
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
|
||||
signal prog_us_tick_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
tick_1us_out <= tick_1us_r;
|
||||
tick_1ms_out <= tick_1ms_r;
|
||||
tick_500ms_out <= tick_500ms_r;
|
||||
tick_750ms_out <= tick_750ms_r;
|
||||
tick_1s_out <= tick_1s_r;
|
||||
prog_us_tick_out <= prog_us_tick_r;
|
||||
|
||||
process(clk_in, reset_in)
|
||||
begin
|
||||
if(reset_in = '1') then
|
||||
sysclk_cnt_r <= 0;
|
||||
usec_cnt_r <= 0;
|
||||
msec_cnt_r <= 0;
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_us_tick_r <= '0';
|
||||
|
||||
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
|
||||
sysclk_cnt_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
else
|
||||
sysclk_cnt_r <= sysclk_cnt_r + 1;
|
||||
tick_1us_r <= '0';
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(usec_cnt_r = 999) then -- 1000us
|
||||
usec_cnt_r <= 0;
|
||||
tick_1ms_r <= '1';
|
||||
else
|
||||
usec_cnt_r <= usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt_r = 499) then -- 500ms
|
||||
msec_cnt_r <= 0;
|
||||
tick_500ms_r <= '1';
|
||||
else
|
||||
msec_cnt_r <= msec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt1_r = 749) then -- 750ms
|
||||
tick_750ms_r <= '1';
|
||||
end if;
|
||||
if(msec_cnt1_r = 999) then -- 1s
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1s_r <= '1';
|
||||
else
|
||||
msec_cnt1_r <= msec_cnt1_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '1';
|
||||
else
|
||||
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user