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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
127 changed files with 97045 additions and 0 deletions
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ip_repo/qsfp_intfc_1_0/bd/bd.tcl
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}
ip_repo/qsfp_intfc_1_0/component.xml
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ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
Library xpm;
use xpm.vcomponents.all;
entity qsfp_init_fsm is
port(
clk_125_in : in std_logic;
clk_125_aresetn_in : in std_logic;
mode_50g_40g_n_in : in std_logic;
qsfp1_reset_n_in : in std_logic;
qsfp4_reset_n_in : in std_logic;
cmd_strb_out : out std_logic;
cmd_addr_out : out std_logic_vector(11 downto 0);
cmd_write_out : out std_logic;
cmd_sel_out : out std_logic_vector( 2 downto 0);
cmd_wdata_out : out std_logic_vector(31 downto 0);
cmd_ready_in : in std_logic;
fsm_running_out : out std_logic
);
end entity qsfp_init_fsm;
architecture imp of qsfp_init_fsm is
type fsm_state is (IDLE, QSFP1_INIT_WAIT, QSFP1_INIT, QSFP4_INIT_WAIT, QSFP4_INIT, DONE, ERROR);
signal state_r : fsm_state := IDLE;
signal state_cnt_r : integer := 0;
signal qsfp1_reset_n : std_logic_vector(0 to 0);
signal qsfp1_reset_b : std_logic_vector(0 to 0);
signal qsfp1_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
signal qsfp4_reset_n : std_logic_vector(0 to 0);
signal qsfp4_reset_b : std_logic_vector(0 to 0);
signal qsfp4_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
signal qsfp1_reset_r : std_logic := '0';
signal qsfp4_reset_r : std_logic := '0';
signal cmd_addr_r : std_logic_vector (11 downto 0) := (others => '0');
signal cmd_sel_r : std_logic_vector ( 2 downto 0) := (others => '0');
signal cmd_strb_r : std_logic := '0';
signal cmd_wdata_r : std_logic_vector (31 downto 0) := (others => '0');
signal cmd_write_r : std_logic := '0';
signal fsm_running_r : std_logic := '0';
begin
cmd_strb_out <= cmd_strb_r;
cmd_addr_out <= cmd_addr_r;
cmd_write_out <= cmd_write_r;
cmd_sel_out <= cmd_sel_r;
cmd_wdata_out <= cmd_wdata_r;
fsm_running_out <= fsm_running_r;
--
qsfp1_reset_n(0) <= qsfp1_reset_n_in;
i_cdc_qsfp1_reset_n : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 1 -- DECIMAL; range: 1-1024
)
port map (
dest_out => qsfp1_reset_b,
dest_clk => clk_125_in,
src_clk => '0',
src_in => qsfp1_reset_n
);
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
qsfp1_reset_n_r <= qsfp1_reset_n_r(1 to 31) & qsfp1_reset_b(0);
end if;
end process;
--
qsfp4_reset_n(0) <= qsfp4_reset_n_in;
i_cdc_qsfp4_reset_n : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 1 -- DECIMAL; range: 1-1024
)
port map (
dest_out => qsfp4_reset_b,
dest_clk => clk_125_in,
src_clk => '0',
src_in => qsfp4_reset_n
);
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
qsfp4_reset_n_r <= qsfp4_reset_n_r(1 to 31) & qsfp4_reset_b(0);
end if;
end process;
process(clk_125_in)
begin
if (clk_125_aresetn_in = '0') then
qsfp1_reset_r <= '0';
qsfp4_reset_r <= '0';
cmd_sel_r <= (others => '0');
cmd_addr_r <= (others => '0');
cmd_wdata_r <= (others => '0');
cmd_write_r <= '0';
cmd_strb_r <= '0';
state_cnt_r <= 0;
state_r <= IDLE;
elsif (rising_edge(clk_125_in)) then
cmd_strb_r <= '0';
if (qsfp1_reset_n_r(1) = '1' and qsfp1_reset_n_r(0) = '0') then
qsfp1_reset_r <= '1';
end if;
if (qsfp4_reset_n_r(1) = '1' and qsfp4_reset_n_r(0) = '0') then
qsfp4_reset_r <= '1';
end if;
case (state_r) is
when IDLE =>
if (qsfp1_reset_r = '1') then
fsm_running_r <= '1';
cmd_sel_r <= "000";
cmd_addr_r <= x"001";
if (mode_50g_40g_n_in = '1') then
cmd_wdata_r <= x"0000_0001";
else
cmd_wdata_r <= x"0000_0011";
end if;
cmd_write_r <= '1';
cmd_strb_r <= '1';
state_cnt_r <= 0;
state_r <= QSFP1_INIT_WAIT;
elsif (qsfp4_reset_r = '1') then
fsm_running_r <= '1';
cmd_sel_r <= "001";
cmd_addr_r <= x"001";
if (mode_50g_40g_n_in = '1') then
cmd_wdata_r <= x"0000_0001";
else
cmd_wdata_r <= x"0000_0011";
end if;
cmd_write_r <= '1';
cmd_strb_r <= '1';
state_cnt_r <= 0;
state_r <= QSFP4_INIT_WAIT;
else
fsm_running_r <= '0';
state_r <= IDLE;
end if;
when QSFP1_INIT_WAIT =>
if (state_cnt_r = 8) then
state_cnt_r <= 0;
state_r <= QSFP1_INIT;
else
state_cnt_r <= state_cnt_r + 1;
state_r <= QSFP1_INIT_WAIT;
end if;
when QSFP1_INIT =>
if (state_cnt_r = 32) then
qsfp1_reset_r <= '0';
state_r <= ERROR;
else
state_cnt_r <= state_cnt_r + 1;
if (cmd_ready_in = '1') then
qsfp1_reset_r <= '0';
state_r <= DONE;
else
state_r <= QSFP1_INIT;
end if;
end if;
when QSFP4_INIT_WAIT =>
if (state_cnt_r = 8) then
state_cnt_r <= 0;
state_r <= QSFP4_INIT;
else
state_cnt_r <= state_cnt_r + 1;
state_r <= QSFP4_INIT_WAIT;
end if;
when QSFP4_INIT =>
if (state_cnt_r = 32) then
qsfp4_reset_r <= '0';
state_r <= ERROR;
else
state_cnt_r <= state_cnt_r + 1;
if (cmd_ready_in = '1') then
qsfp4_reset_r <= '0';
state_r <= DONE;
else
state_r <= QSFP4_INIT;
end if;
end if;
when DONE =>
cmd_write_r <= '0';
state_r <= IDLE;
when ERROR =>
cmd_write_r <= '0';
state_r <= IDLE;
when others =>
state_r <= IDLE;
end case;
end if;
end process;
end architecture imp;
ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd
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ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd
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ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_1.vhd
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity qsfp_intfc_v1_1 is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0603_2024";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk_125_in : in std_logic;
clk_125_reset_n_in : in std_logic;
clk_250_in : in std_logic;
clk_250_reset_n_in : in std_logic;
rx_device_clk_in : in std_logic;
tx_device_clk_in : in std_logic;
clkin8_in : in std_logic;
-- sysref_in : in std_logic;
ref_clk_div2_in : in std_logic;
QSFP1_RESETL_LS : out std_logic;
QSFP1_MODPRSL_LS : in std_logic;
QSFP1_INTL_LS : in std_logic;
-----------------
QSFP2_RESETL_LS : out std_logic;
QSFP2_MODPRSL_LS : in std_logic;
QSFP2_INTL_LS : in std_logic;
-----------------
QSFP3_RESETL_LS : out std_logic;
QSFP3_MODPRSL_LS : in std_logic;
QSFP3_INTL_LS : in std_logic;
-----------------
QSFP4_RESETL_LS : out std_logic;
QSFP4_MODPRSL_LS : in std_logic;
QSFP4_INTL_LS : in std_logic;
----
cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cmac_4_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cmac_rx_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
mem_xfer_tx_upload_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
dac_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
adc_tvalid_256b_cnt_in : in std_logic_vector(31 downto 0);
cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cmac_4_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cnt_reset_out : out std_logic;
slv_reg9_out : out std_logic_vector(31 downto 0);
slv_reg10_out : out std_logic_vector(31 downto 0);
slv_reg31_out : out std_logic_vector(31 downto 0);
slv_reg38_out : out std_logic_vector(31 downto 0);
slv_reg45_out : out std_logic_vector(31 downto 0);
slv_reg52_out : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
sys_cpu_clk_in : in std_logic;
s00_axi_aresetn_in : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end qsfp_intfc_v1_1;
architecture arch_imp of qsfp_intfc_v1_1 is
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
attribute keep of minor_rev_r : signal is "true";
--
signal qsfp1_reset_n : std_logic;
signal qsfp1_modprsl : std_logic;
signal qsfp1_intl : std_logic;
signal qsfp2_reset_n : std_logic;
signal qsfp2_modprsl : std_logic;
signal qsfp2_intl : std_logic;
signal qsfp3_reset_n : std_logic;
signal qsfp3_modprsl : std_logic;
signal qsfp3_intl : std_logic;
signal qsfp4_reset_n : std_logic;
signal qsfp4_modprsl : std_logic;
signal qsfp4_intl : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal rx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal tx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clkin8_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clkin8_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clkin8_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal sys_cpu_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal sys_cpu_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal sys_cpu_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal ref_clk_div2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal ref_clk_div2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal ref_clk_div2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal slv_reg0 : std_logic_vector(31 downto 0);
signal slv_reg1 : std_logic_vector(31 downto 0);
signal slv_reg2 : std_logic_vector(31 downto 0);
signal slv_reg3 : std_logic_vector(31 downto 0);
signal slv_reg4 : std_logic_vector(31 downto 0);
signal slv_reg5 : std_logic_vector(31 downto 0);
signal slv_reg6 : std_logic_vector(31 downto 0);
signal slv_reg7 : std_logic_vector(31 downto 0);
signal slv_reg8 : std_logic_vector(31 downto 0);
signal vio_cnt_reset : std_logic;
signal cnt_rst : std_logic;
signal s00_axi_areset : std_logic;
begin
cnt_reset_out <= cnt_rst;--vio_cnt_reset when vio_enable = '1' else cnt_rst;
s00_axi_areset <= not s00_axi_aresetn_in;
-- Instantiation of Axi Bus Interface S00_AXI
qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
slv_reg0_in => slv_reg0, -- 0x8000_0000
slv_reg1_in => slv_reg1, -- 0x8000_0004
slv_reg2_in => slv_reg2, -- 0x8000_0008
slv_reg3_out => slv_reg3, -- 0x8000_000C
slv_reg4_out => slv_reg4, -- 0x8000_0010
slv_reg5_out => slv_reg5, -- 0x8000_0014
slv_reg6_out => slv_reg6, -- 0x8000_0018
slv_reg7_out => slv_reg7, -- 0x8000_001C
slv_reg8_out => slv_reg8, -- 0x8000_0020
slv_reg9_out => slv_reg9_out, -- 0x8000_0024
slv_reg10_out => slv_reg10_out, -- 0x8000_0028
slv_reg11_in => clk_125_freq_r, -- 0x8000_002C
slv_reg12_in => clk_125_cnt_r, -- 0x8000_0030
slv_reg13_in => clk_250_freq_r, -- 0x8000_0034
slv_reg14_in => clk_250_cnt_r, -- 0x8000_0038
slv_reg15_in => rx_device_clk_freq_r, -- 0x8000_003C
slv_reg16_in => tx_device_clk_freq_r, -- 0x8000_0040
slv_reg17_in => (others => '0'), -- 0x8000_0044
slv_reg18_in => (others => '0'), -- 0x8000_0048
slv_reg19_in => (others => '0'), -- 0x8000_004C
slv_reg20_in => (others => '0'), -- 0x8000_0050
slv_reg21_in => (others => '0'), -- 0x8000_0054
slv_reg22_in => (others => '0'), -- 0x8000_0058
slv_reg23_in => (others => '0'), -- 0x8000_005C
slv_reg24_in => (others => '0'), -- 0x8000_0060
slv_reg25_in => (others => '0'), -- 0x8000_0064
slv_reg26_in => (others => '0'), -- 0x8000_0068
slv_reg27_in => (others => '0'), -- 0x8000_006C
slv_reg28_in => (others => '0'), -- 0x8000_0070
slv_reg29_in => (others => '0'), -- 0x8000_0074
slv_reg30_in => (others => '0'), -- 0x8000_0078
slv_reg31_in => (others => '0'), -- 0x8000_007C
slv_reg32_in => (others => '0'), -- 0x8000_0080
slv_reg33_in => (others => '0'), -- 0x8000_0084
slv_reg34_in => (others => '0'), -- 0x8000_0088
slv_reg35_in => (others => '0'), -- 0x8000_008C
slv_reg36_in => (others => '0'), -- 0x8000_0090
slv_reg37_in => (others => '0'), -- 0x8000_0094
slv_reg38_in => (others => '0'), -- 0x8000_0098
slv_reg39_in => (others => '0'), -- 0x8000_009C
slv_reg40_in => (others => '0'), -- 0x8000_00A0
slv_reg41_in => (others => '0'), -- 0x8000_00A4
slv_reg42_in => (others => '0'), -- 0x8000_00A8
slv_reg43_in => (others => '0'), -- 0x8000_00AC
slv_reg44_in => (others => '0'), -- 0x8000_00B0
slv_reg45_in => (others => '0'), -- 0x8000_00B4
slv_reg46_in => (others => '0'), -- 0x8000_00B8
slv_reg47_in => (others => '0'), -- 0x8000_00BC
slv_reg48_in => (others => '0'), -- 0x8000_00C0
slv_reg49_in => (others => '0'), -- 0x8000_00C4
slv_reg50_in => (others => '0'), -- 0x8000_00C8
slv_reg51_in => (others => '0'), -- 0x8000_00CC
slv_reg52_in => (others => '0'), -- 0x8000_00D0
slv_reg53_in => adc_tvalid_256b_cnt_in, -- 0x8000_00D4
slv_reg54_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00D8
slv_reg55_in => cmac_4_tx_tvalid_512b_cnt_in, -- 0x8000_00DC
slv_reg56_in => cmac_rx_tvalid_256b_cnt_in, -- 0x8000_00E0
slv_reg57_in => mem_xfer_tx_upload_tvalid_256b_cnt_in,-- 0x8000_00E4
slv_reg58_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00E8
slv_reg59_in => cmac_4_rx_tvalid_512b_cnt_in, -- 0x8000_00EC
slv_reg60_in => dac_tvalid_256b_cnt_in, -- 0x8000_00F0
slv_reg61_in => (others => '0'), -- 0x8000_00F4
slv_reg62_in => (others => '0'), -- 0x8000_00F8
slv_reg63_in => (others => '0'), -- 0x8000_00FC
S_AXI_ACLK => sys_cpu_clk_in,
S_AXI_ARESETN => s00_axi_aresetn_in,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
------------
slv_reg0 <= fpga_revision_date_r; -- 0x8000_0000
------------
slv_reg1(0) <= '0';
slv_reg1(1) <= qsfp1_modprsl;
slv_reg1(2) <= qsfp1_intl;
slv_reg1(3) <= '0';
slv_reg1(4) <= '0';
slv_reg1(5) <= qsfp2_modprsl;
slv_reg1(6) <= qsfp2_intl;
slv_reg1(7) <= '0';
slv_reg1(8) <= '0';
slv_reg1(9) <= qsfp3_modprsl;
slv_reg1(10) <= qsfp3_intl;
slv_reg1(11) <= '0';
slv_reg1(12) <= '0';
slv_reg1(13) <= qsfp4_modprsl;
slv_reg1(14) <= qsfp4_intl;
slv_reg1(15) <= '0';
slv_reg1(23 downto 16) <= (others => '0');
slv_reg1(31 downto 24) <= minor_rev_r; -- 0x8000_0004
------------
slv_reg2 <= (others => '0'); -- 0x8000_0008
------------
--
-- <= slv_reg3(17 downto 16);
-- <= slv_reg3(12); -- 0x8000_0014
-- <= slv_reg3(11 downto 0); -- 0x8000_000C
------------
-- <= slv_reg4(17 downto 16); -- 0x8000_0010
------------
qsfp1_reset_n <= slv_reg5(0); -- 0x8000_0014
-- <= slv_reg5(3 dwonto 1);
qsfp2_reset_n <= slv_reg5(4);
-- <= slv_reg5(7 dwonto 5);
qsfp3_reset_n <= slv_reg5(8);
-- <= slv_reg5(11 dwonto 9);
qsfp4_reset_n <= slv_reg5(12);
-- <= slv_reg5(31 dwonto 13);
------------
-- <= slv_reg6(31 downto 0); -- 0x8000_0018
------------
-- <= slv_reg7(0); -- 0x8000_001C
------------
-- <= slv_reg8(0); -- 0x8000_0020
-- <= slv_reg8(24);
-- <= slv_reg8(28);
cnt_rst <= slv_reg8(31);
QSFP1_RESETL_LS <= qsfp1_reset_n;
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
qsfp1_intl <= QSFP1_INTL_LS;
-------
QSFP2_RESETL_LS <= qsfp2_reset_n;
qsfp2_modprsl <= QSFP2_MODPRSL_LS;
qsfp2_intl <= QSFP2_INTL_LS;
-------
QSFP3_RESETL_LS <= qsfp3_reset_n;
qsfp3_modprsl <= QSFP3_MODPRSL_LS;
qsfp3_intl <= QSFP3_INTL_LS;
-------
QSFP4_RESETL_LS <= qsfp4_reset_n;
qsfp4_modprsl <= QSFP4_MODPRSL_LS;
qsfp4_intl <= QSFP4_INTL_LS;
------------------------------------------------
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 100
)
port map (
clk_in => sys_cpu_clk_in,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000_0000",
prog_us_tick_out => open,
reset_in => s00_axi_areset
);
process(sys_cpu_clk_in)
begin
if (rising_edge(sys_cpu_clk_in)) then
fpga_revision_date_r <= FPGA_REVISION_DATE;
minor_rev_r <= MINOR_REV;
end if;
end process;
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_125_tick_1ms_r(0 to 1) = "01") then
clk_125_freq_r <= clk_125_cnt_r;
clk_125_cnt_r <= (others => '0');
else
clk_125_cnt_r <= clk_125_cnt_r + 1;
end if;
end if;
end process;
process(clk_250_in)
begin
if (rising_edge(clk_250_in)) then
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_250_tick_1ms_r(0 to 1) = "01") then
clk_250_freq_r <= clk_250_cnt_r;
clk_250_cnt_r <= (others => '0');
else
clk_250_cnt_r <= clk_250_cnt_r + 1;
end if;
end if;
end process;
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
rx_device_clk_tick_1ms_r <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then
rx_device_clk_freq_r <= rx_device_clk_cnt_r;
rx_device_clk_cnt_r <= (others => '0');
else
rx_device_clk_cnt_r <= rx_device_clk_cnt_r + 1;
end if;
end if;
end process;
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
tx_device_clk_tick_1ms_r <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then
tx_device_clk_freq_r <= tx_device_clk_cnt_r;
tx_device_clk_cnt_r <= (others => '0');
else
tx_device_clk_cnt_r <= tx_device_clk_cnt_r + 1;
end if;
end if;
end process;
process(clkin8_in)
begin
if (rising_edge(clkin8_in)) then
clkin8_tick_1ms_r <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
if (clkin8_tick_1ms_r(0 to 1) = "01") then
clkin8_freq_r <= clkin8_cnt_r;
clkin8_cnt_r <= (others => '0');
else
clkin8_cnt_r <= clkin8_cnt_r + 1;
end if;
end if;
end process;
process(sys_cpu_clk_in)
begin
if (rising_edge(sys_cpu_clk_in)) then
sys_cpu_clk_tick_1ms_r <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then
sys_cpu_clk_freq_r <= sys_cpu_clk_cnt_r;
sys_cpu_clk_cnt_r <= (others => '0');
else
sys_cpu_clk_cnt_r <= sys_cpu_clk_cnt_r + 1;
end if;
end if;
end process;
process(ref_clk_div2_in)
begin
if (rising_edge(ref_clk_div2_in)) then
ref_clk_div2_tick_1ms_r <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then
ref_clk_div2_freq_r <= ref_clk_div2_cnt_r;
ref_clk_div2_cnt_r <= (others => '0');
else
ref_clk_div2_cnt_r <= ref_clk_div2_cnt_r + 1;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
ip_repo/qsfp_intfc_1_0/src/axis_data_fifo_1kx240_1/axis_data_fifo_1kx240_1.xci
+175
View File
@@ -0,0 +1,175 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axis_data_fifo_1kx240_1",
"cell_name": "i_qsfp0_to_qsfp1_fifo",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "11",
"gen_directory": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "2048", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "axis_data_fifo_1kx240_1", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcvu37p" } ],
"PACKAGE": [ { "value": "fsvh2892" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "11" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
"prog_full": [ { "direction": "out" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}
ip_repo/qsfp_intfc_1_0/src/axis_data_fifo_32x240/axis_data_fifo_32x240.xci
+193
View File
@@ -0,0 +1,193 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axis_data_fifo_32x240",
"cell_name": "i_qsfp0_to_qsfp1_fifo",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "11",
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcvu37p" } ],
"PACKAGE": [ { "value": "fsvh2892" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "11" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
},
"M_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "m_axis_aclk" } ]
}
}
}
}
}
}
ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp
BIN
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Binary file not shown.
ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd
+337
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@@ -0,0 +1,337 @@
----------------------------------------------------------------------------------
-- Company: Erisys
-- Engineer: Jason M Blevins
--
-- Create Date: 07/08/2023
-- Design Name:
-- Module Name: dig_iq_p_intfc
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library xpm;
use xpm.vcomponents.all;
entity dig_iq_p_intfc is
generic(
SAME_CLKS : natural range 0 to 1 := 0
);
port (
reg_clk : in std_logic;
reg_resetn : in std_logic;
strb_in : in std_logic;
addr_in : in std_logic_vector(11 downto 0);
write_in : in std_logic;
sel_in : in std_logic_vector(2 downto 0);
wdata_in : in std_logic_vector(31 downto 0);
ready_out : out std_logic;
rdata_out : out std_logic_vector(31 downto 0);
----------------------------------------------------------
clk_125 : in std_logic;
clk_125_resetn : in std_logic;
--
p_addr : out std_logic_vector(11 downto 0);
p_write : out std_logic;
p_wdata : out std_logic_vector(31 downto 0);
--
--p_enable_in_0 : out std_logic;
--p_enable_in_1 : out std_logic;
--p_enable_in_2 : out std_logic;
--p_enable_in_3 : out std_logic;
--p_enable_out_0 : out std_logic;
--p_enable_out_1 : out std_logic;
p_enable : out std_logic_vector(7 downto 0);
--
--p_ready_in_0 : in std_logic;
--p_ready_in_1 : in std_logic;
--p_ready_in_2 : in std_logic;
--p_ready_in_3 : in std_logic;
--p_ready_out_0 : in std_logic;
--p_ready_out_1 : in std_logic;
p_ready : in std_logic_vector(7 downto 0);
--
p_rdata_0 : in std_logic_vector(31 downto 0);
p_rdata_1 : in std_logic_vector(31 downto 0);
p_rdata_2 : in std_logic_vector(31 downto 0);
p_rdata_3 : in std_logic_vector(31 downto 0);
p_rdata_4 : in std_logic_vector(31 downto 0);
p_rdata_5 : in std_logic_vector(31 downto 0);
p_rdata_6 : in std_logic_vector(31 downto 0);
p_rdata_7 : in std_logic_vector(31 downto 0)
);
end dig_iq_p_intfc;
architecture arch_imp of dig_iq_p_intfc is
--signal p_ready : std_logic_vector(7 downto 0);
signal strb_in_r : std_logic := '0';
signal strb_int : std_logic;
signal addr_int : std_logic_vector(11 downto 0);
signal sel_int : std_logic_vector(2 downto 0);
signal write_int : std_logic;
signal wdata_int : std_logic_vector(31 downto 0);
signal p_addr_r : std_logic_vector(11 downto 0) := (others => '0');
signal p_write_r : std_logic := '0';
signal p_wdata_r : std_logic_vector(31 downto 0) := (others => '0');
signal p_enable_r : std_logic_vector(7 downto 0) := (others => '0');
signal p_enable_r1 : std_logic_vector(7 downto 0) := (others => '0');
signal p_strb_r : std_logic := '0';
signal p_ready_r : std_logic := '0';
signal p_rdata_r : std_logic_vector(31 downto 0) := (others => '0');
begin
SAME_CLKS_FALSE_GEN :
if SAME_CLKS = 0 generate
begin
i_cdc_pulse_strb : xpm_cdc_pulse
generic map (
DEST_SYNC_FF => 7, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
REG_OUTPUT => 1, -- DECIMAL; 0=disable registered output, 1=enable registered output
RST_USED => 0, -- DECIMAL; 0=no reset, 1=implement reset
SIM_ASSERT_CHK => 0 -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
)
port map (
dest_rst => '0',
dest_pulse => strb_int,
dest_clk => clk_125,
src_clk => reg_clk,
src_pulse => strb_in,
src_rst => '0'
);
i_cdc_array_addr : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 12 -- DECIMAL; range: 1-1024
)
port map (
dest_out => addr_int,
dest_clk => clk_125,
src_in => addr_in,
src_clk => '0'
);
i_cdc_array_sel : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 3 -- DECIMAL; range: 1-1024
)
port map (
dest_out => sel_int,
dest_clk => clk_125,
src_in => sel_in,
src_clk => '0'
);
i_cdc_array_wdata : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 32 -- DECIMAL; range: 1-1024
)
port map (
dest_out => wdata_int,
dest_clk => clk_125,
src_in => wdata_in,
src_clk => '0'
);
i_cdc_single_write : xpm_cdc_single
generic map (
DEST_SYNC_FF => 4,
INIT_SYNC_FF => 0,
SIM_ASSERT_CHK => 0,
SRC_INPUT_REG => 0
)
port map (
dest_out => write_int,
dest_clk => clk_125,
src_clk => '0',
src_in => write_in
);
i_cdc_single_ready : xpm_cdc_single
generic map (
DEST_SYNC_FF => 4,
INIT_SYNC_FF => 0,
SIM_ASSERT_CHK => 0,
SRC_INPUT_REG => 0
)
port map (
dest_out => ready_out,
dest_clk => reg_clk,
src_clk => '0',
src_in => p_ready_r
);
i_cdc_array_rdata : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 32 -- DECIMAL; range: 1-1024
)
port map (
dest_out => rdata_out,
dest_clk => reg_clk,
src_in => p_rdata_r,
src_clk => '0'
);
end generate;
SAME_CLKS_TRUE_GEN :
if SAME_CLKS = 1 generate
begin
strb_int <= not(strb_in_r) and strb_in;
addr_int <= addr_in;
sel_int <= sel_in;
wdata_int <= wdata_in;
write_int <= write_in;
ready_out <= p_ready_r;
rdata_out <= p_rdata_r;
end generate;
---------------------------------------
-- APB Interface Ports
p_addr <= p_addr_r;
p_write <= p_write_r;
p_wdata <= p_wdata_r;
p_enable <= p_enable_r1;
--p_enable_in_0 <= p_enable_r1(0);
--p_enable_in_1 <= p_enable_r1(1);
--p_enable_in_2 <= p_enable_r1(2);
--p_enable_in_3 <= p_enable_r1(3);
--p_enable_out_0 <= p_enable_r1(4);
--p_enable_out_1 <= p_enable_r1(5);
--p_ready(0) <= p_ready_in_0;
--p_ready(1) <= p_ready_in_1;
--p_ready(2) <= p_ready_in_2;
--p_ready(3) <= p_ready_in_3;
--p_ready(4) <= p_ready_out_0;
--p_ready(5) <= p_ready_out_1;
process(clk_125)
begin
if(rising_edge(clk_125))then
if(clk_125_resetn = '0')then
strb_in_r <= '0';
p_addr_r <= (others => '0');
p_write_r <= '0';
p_wdata_r <= (others => '0');
p_enable_r <= (others => '0');
p_enable_r1 <= (others => '0');
p_strb_r <= '0';
p_ready_r <= '0';
p_rdata_r <= (others => '0');
else
strb_in_r <= strb_in;
p_strb_r <= strb_int;
if(strb_int = '1')then
p_addr_r <= addr_int;
p_write_r <= write_int;
p_wdata_r <= wdata_int;
case sel_int is
when "000" =>
p_enable_r <= "00000001";
when "001" =>
p_enable_r <= "00000010";
when "010" =>
p_enable_r <= "00000100";
when "011" =>
p_enable_r <= "00001000";
when "100" =>
p_enable_r <= "00010000";
when "101" =>
p_enable_r <= "00100000";
when "110" =>
p_enable_r <= "01000000";
when "111" =>
p_enable_r <= "10000000";
when others =>
p_enable_r <= "00000000";
end case;
end if;
if(p_strb_r = '1')then
p_enable_r1 <= p_enable_r;
if(p_enable_r /= "00000000")then
p_ready_r <= '0';
end if;
else
if(p_ready = "11111111")then
p_enable_r1 <= (others => '0');
p_ready_r <= '1';
case sel_int is
when "000" =>
p_rdata_r <= p_rdata_0;
when "001" =>
p_rdata_r <= p_rdata_1;
when "010" =>
p_rdata_r <= p_rdata_2;
when "011" =>
p_rdata_r <= p_rdata_3;
when "100" =>
p_rdata_r <= p_rdata_4;
when "101" =>
p_rdata_r <= p_rdata_5;
when "110" =>
p_rdata_r <= p_rdata_6;
when "111" =>
p_rdata_r <= p_rdata_7;
when others =>
p_rdata_r <= x"DEADBEEF";
end case;
end if;
end if;
end if;
end if;
end process;
end arch_imp;
ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd
+592
View File
@@ -0,0 +1,592 @@
----------------------------------------------------------------------------------
-- Company: Erisys
-- Engineer: Jason M Blevins
--
-- Create Date: 07/02/2023 02:07:25 PM
-- Design Name:
-- Module Name: dig_iq_x2 - structural
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library xpm;
use xpm.vcomponents.all;
library UNISIM;
use UNISIM.VComponents.all;
entity dig_iq_x2 is
port (
clk_125_resetn_in : in std_logic;
clk_125_in : in std_logic;
aclk_in : in std_logic;
aresetn_in : in std_logic;
cmd_strb_in : in std_logic;
cmd_addr_in : in std_logic_vector(11 downto 0);
cmd_write_in : in std_logic;
cmd_sel_in : in std_logic_vector(2 downto 0);
cmd_wdata_in : in std_logic_vector(31 downto 0);
cmd_ready_out : out std_logic;
cmd_rdata_out : out std_logic_vector(31 downto 0);
dig_iq_interface_reset_in : in std_logic_vector(1 downto 0);
--dig_iq_resetn : in std_logic_vector(1 downto 0);
--dig_iq_rx_enable : in std_logic_vector(1 downto 0);
--
dig_iq_interface_ready_out : out std_logic_vector(1 downto 0); --async
--dig_iq_cc_overflow : out std_logic_vector(1 downto 0); --async
--dig_iq_tx_overflow : out std_logic_vector(PORT_CNT-1 downto 0);
rx_data_ready_in : in std_logic_vector(1 downto 0);
axis_0_aclk_out : out std_logic;
axis_0_aresetn_out : out std_logic;
m0_axis_tdata_out : out std_logic_vector(239 downto 0);
m0_axis_tvalid_out : out std_logic;
s0_axis_tdata_in : in std_logic_vector(239 downto 0);
s0_axis_tvalid_in : in std_logic;
s0_axis_tready_out : out std_logic;
axis_1_aclk_out : out std_logic;
axis_1_aresetn_out : out std_logic;
m1_axis_tdata_out : out std_logic_vector(239 downto 0);
m1_axis_tvalid_out : out std_logic;
s1_axis_tdata_in : in std_logic_vector(239 downto 0);
s1_axis_tvalid_in : in std_logic;
s1_axis_tready_out : out std_logic;
tx_data_channel_reset_in : in std_logic;
tx_data_clear_in : in std_logic;
qsfp0_ref_clk_n_in : in std_logic;
qsfp0_ref_clk_p_in : in std_logic;
qsfp0_rx_rxn_in : in std_logic_vector(3 downto 0);
qsfp0_rx_rxp_in : in std_logic_vector(3 downto 0);
qsfp0_tx_txn_out : out std_logic_vector(3 downto 0);
qsfp0_tx_txp_out : out std_logic_vector(3 downto 0);
qsfp1_ref_clk_n_in : in std_logic;
qsfp1_ref_clk_p_in : in std_logic;
qsfp1_rx_rxn_in : in std_logic_vector(3 downto 0);
qsfp1_rx_rxp_in : in std_logic_vector(3 downto 0);
qsfp1_tx_txn_out : out std_logic_vector(3 downto 0);
qsfp1_tx_txp_out : out std_logic_vector(3 downto 0)
);
end dig_iq_x2;
architecture structural of dig_iq_x2 is
component DIG_IQ_HS_CUSTOM1X is
port(
INIT_CLK : in std_logic := '0';
INTERFACE_RESET : in std_logic := '1';
IntL : in std_logic := '1';
MGTREFCLK_N : in std_logic := '1';
MGTREFCLK_P : in std_logic := '0';
ModPrsL : in std_logic := '1';
PADDR : in std_logic_vector (11 downto 0) := (others => '0');
PCLK : in std_logic := '0';
PENABLE : in std_logic := '0';
PRESETn : in std_logic := '0';
PSEL : in std_logic := '0';
PWDATA : in std_logic_vector (31 downto 0) := (others => '0');
PWRITE : in std_logic := '0';
RXN : in std_logic_vector (3 downto 0) := (others => '1');
RXP : in std_logic_vector (3 downto 0) := (others => '0');
RX_DATA_READY : in std_logic := '1';
SCL_I : in std_logic := '0';
SDA_I : in std_logic := '0';
TX_DATA_CLEAR : in std_logic := '0';
TX_DATA_DAT : in std_logic_vector (239 downto 0) := (others => '0');
TX_DATA_EN : in std_logic := '0';
TX_DATA_CHANNEL_RESET : in std_logic := '0';
RX_DATA_CHANNEL_RESET : out std_logic;
DATA_CLK : out std_logic ;
INTERFACE_READY : out std_logic ;
ModselL : out std_logic ;
PRDATA : out std_logic_vector (31 downto 0);
PREADY : out std_logic ;
RX_DATA_DAT : out std_logic_vector (239 downto 0);
RX_DATA_EN : out std_logic ;
SCL_O : out std_logic ;
SCL_OE : out std_logic ;
SDA_O : out std_logic ;
SDA_OE : out std_logic ;
TXN : out std_logic_vector (3 downto 0);
TXP : out std_logic_vector (3 downto 0);
TX_DATA_READY : out std_logic
);
end component DIG_IQ_HS_CUSTOM1X;
component dig_iq_p_intfc is
generic(
SAME_CLKS : natural range 0 to 1 := 0
);
port (
reg_clk : in std_logic;
reg_resetn : in std_logic;
--
strb_in : in std_logic;
addr_in : in std_logic_vector(11 downto 0);
write_in : in std_logic;
sel_in : in std_logic_vector(2 downto 0);
wdata_in : in std_logic_vector(31 downto 0);
ready_out : out std_logic;
rdata_out : out std_logic_vector(31 downto 0);
----------------------------------------------------------
clk_125 : in std_logic;
clk_125_resetn : in std_logic;
--
p_addr : out std_logic_vector(11 downto 0);
p_write : out std_logic;
p_wdata : out std_logic_vector(31 downto 0);
p_enable : out std_logic_vector(7 downto 0);
p_ready : in std_logic_vector(7 downto 0);
p_rdata_0 : in std_logic_vector(31 downto 0);
p_rdata_1 : in std_logic_vector(31 downto 0);
p_rdata_2 : in std_logic_vector(31 downto 0);
p_rdata_3 : in std_logic_vector(31 downto 0);
p_rdata_4 : in std_logic_vector(31 downto 0);
p_rdata_5 : in std_logic_vector(31 downto 0);
p_rdata_6 : in std_logic_vector(31 downto 0);
p_rdata_7 : in std_logic_vector(31 downto 0)
);
end component dig_iq_p_intfc;
component axis_clock_converter_0
port (
s_axis_aresetn : in std_logic;
m_axis_aresetn : in std_logic;
s_axis_aclk : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(239 downto 0);
m_axis_aclk : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(239 downto 0)
);
end component;
component axis_data_fifo_0
port (
s_axis_aresetn : in std_logic;
s_axis_aclk : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(239 downto 0);
m_axis_aclk : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(239 downto 0)
);
end component;
signal p_addr : std_logic_vector(11 downto 0);
signal p_write : std_logic;
signal p_wdata : std_logic_vector(31 downto 0);
signal p_enable : std_logic_vector(7 downto 0);
signal p_ready : std_logic_vector(7 downto 0);
type SLV_32_ARRAY is array (integer range 0 to 1) of std_logic_vector(31 downto 0);
signal p_rdata : SLV_32_ARRAY;
type SLV_4_ARRAY is array (integer range 0 to 1) of std_logic_vector(3 downto 0);
signal qsfp_rx_rxn : SLV_4_ARRAY;
signal qsfp_rx_rxp : SLV_4_ARRAY;
signal qsfp_tx_txn : SLV_4_ARRAY;
signal qsfp_tx_txp : SLV_4_ARRAY;
type SLV_240_ARRAY is array (integer range 0 to 1) of std_logic_vector(239 downto 0);
--signal tx_data_r : SLV_240_ARRAY;
--signal rx_data_r : SLV_240_ARRAY;
signal rx_data : SLV_240_ARRAY;
signal s_axis_tdata : SLV_240_ARRAY;
--signal m_axis_tdata_int : SLV_240_ARRAY;
--signal tx_fifo_m_tdata : SLV_240_ARRAY;
signal clk : std_logic_vector(1 downto 0);
--signal resetn : std_logic_vector(1 downto 0);
--signal rx_enable : std_logic_vector(1 downto 0);
signal interface_reset : std_logic_vector(1 downto 0);
signal qsfp_ref_clk_n : std_logic_vector(1 downto 0);
signal qsfp_ref_clk_p : std_logic_vector(1 downto 0);
--signal tx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
signal rx_data_en : std_logic_vector(1 downto 0);
--signal rx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
signal tx_data_ready : std_logic_vector(1 downto 0);
signal s_axis_tvalid : std_logic_vector(1 downto 0);
--signal rx_data_en_int : std_logic_vector(1 downto 0);
--signal tx_data_en_int : std_logic_vector(1 downto 0);
--signal m_axis_tvalid_int : std_logic_vector(1 downto 0);
--signal cc_overflow_tready : std_logic_vector(1 downto 0);
--signal cc_overflow_int : std_logic_vector(1 downto 0);
--signal cc_overflow_r : std_logic_vector(PORT_CNT-1 downto 0);
--signal tx_fifo_m_tvalid : std_logic_vector(1 downto 0);
--signal s_axis_tready_int : std_logic_vector(1 downto 0);
--signal tx_fifo_overflow_int : std_logic_vector(PORT_CNT-1 downto 0);
signal dig_iq_interface_ready : std_logic_vector(1 downto 0);
signal axis_0_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
signal axis_1_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
type array_32b_type is array (0 to 1) of std_logic_vector(0 to 31);
signal tx_data_channel_reset_r : array_32b_type := (others => (others => '0'));
signal tx_data_clear_r : std_logic_vector(1 downto 0) := (others => '0');
begin
p_ready(7 downto 2) <= (others => '1');
i_dig_iq_p_intfc : dig_iq_p_intfc
generic map(
SAME_CLKS => 1
)
port map(
reg_clk => clk_125_in,
reg_resetn => clk_125_resetn_in,
--
strb_in => cmd_strb_in,
addr_in => cmd_addr_in,
write_in => cmd_write_in,
sel_in => cmd_sel_in,
wdata_in => cmd_wdata_in,
ready_out => cmd_ready_out,
rdata_out => cmd_rdata_out,
--
clk_125 => clk_125_in,
clk_125_resetn => clk_125_resetn_in,
--
p_addr => p_addr,
p_write => p_write,
p_wdata => p_wdata,
p_enable => p_enable,
p_ready => p_ready,
p_rdata_0 => p_rdata(0),
p_rdata_1 => p_rdata(1),
p_rdata_2 => (others => '0'),
p_rdata_3 => (others => '0'),
p_rdata_4 => (others => '0'),
p_rdata_5 => (others => '0'),
p_rdata_6 => (others => '0'),
p_rdata_7 => (others => '0')
);
i_cdc_0 : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 2 -- DECIMAL; range: 1-1024
)
port map (
dest_out => interface_reset,
dest_clk => clk_125_in,
src_clk => '0',
src_in => dig_iq_interface_reset_in
);
-----------------------------------------------------------
dig_iq_interface_ready_out <= dig_iq_interface_ready;
axis_0_aclk_out <= clk(0);
axis_0_aresetn_out <= axis_0_aresetn_r(0);
s_axis_tdata(0) <= s0_axis_tdata_in;
s_axis_tvalid(0) <= s0_axis_tvalid_in;
s0_axis_tready_out <= tx_data_ready(0);--s_axis_tready_int(0);
m0_axis_tdata_out <= rx_data(0);--m_axis_tdata_int(0);
m0_axis_tvalid_out <= rx_data_en(0);--m_axis_tvalid_int(0);
axis_1_aclk_out <= clk(1);
axis_1_aresetn_out <= axis_1_aresetn_r(0);
s_axis_tdata(1) <= s1_axis_tdata_in;
s_axis_tvalid(1) <= s1_axis_tvalid_in;
s1_axis_tready_out <= tx_data_ready(1);--s_axis_tready_int(1);
m1_axis_tdata_out <= rx_data(1);--m_axis_tdata_int(1);
m1_axis_tvalid_out <= rx_data_en(1);--m_axis_tvalid_int(1);
qsfp_ref_clk_n(0) <= qsfp0_ref_clk_n_in;
qsfp_ref_clk_n(1) <= qsfp1_ref_clk_n_in;
qsfp_ref_clk_p(0) <= qsfp0_ref_clk_p_in;
qsfp_ref_clk_p(1) <= qsfp1_ref_clk_p_in;
qsfp_rx_rxn(0) <= qsfp0_rx_rxn_in;
qsfp_rx_rxn(1) <= qsfp1_rx_rxn_in;
qsfp_rx_rxp(0) <= qsfp0_rx_rxp_in;
qsfp_rx_rxp(1) <= qsfp1_rx_rxp_in;
qsfp0_tx_txn_out <= qsfp_tx_txn(0);
qsfp1_tx_txn_out <= qsfp_tx_txn(1);
qsfp0_tx_txp_out <= qsfp_tx_txp(0);
qsfp1_tx_txp_out <= qsfp_tx_txp(1);
process(clk(0))
begin
if (rising_edge(clk(0))) then
if (dig_iq_interface_ready(0) = '1') then
axis_0_aresetn_r <= axis_0_aresetn_r(1 to 31) & '1';
else
axis_0_aresetn_r <= (others => '0');
end if;
end if;
end process;
process(clk(1))
begin
if (rising_edge(clk(1))) then
if (dig_iq_interface_ready(1) = '1') then
axis_1_aresetn_r <= axis_1_aresetn_r(1 to 31) & '1';
else
axis_1_aresetn_r <= (others => '0');
end if;
end if;
end process;
-----------------------------------------------------------
GEN_0:
for i in 0 to 1 generate
begin
-- i_cdc_resetn : xpm_cdc_single
-- generic map (
-- DEST_SYNC_FF => 2,
-- INIT_SYNC_FF => 0,
-- SIM_ASSERT_CHK => 0,
-- SRC_INPUT_REG => 0
-- )
-- port map (
-- dest_out => resetn(i),
-- dest_clk => clk(i),
-- src_clk => '0',
-- src_in => dig_iq_resetn(i)
-- );
-- i_cdc_rx_enable : xpm_cdc_single
-- generic map (
-- DEST_SYNC_FF => 2,
-- INIT_SYNC_FF => 0,
-- SIM_ASSERT_CHK => 0,
-- SRC_INPUT_REG => 0
-- )
-- port map (
-- dest_out => rx_enable(i),
-- dest_clk => clk(i),
-- src_clk => '0',
-- src_in => dig_iq_rx_enable(i)
-- );
process(clk(i))
begin
if (rising_edge(clk(i))) then
tx_data_clear_r(i) <= tx_data_clear_in;
tx_data_channel_reset_r(i) <= tx_data_channel_reset_r(i)(1 to 31) & '0';
if (tx_data_channel_reset_in = '1') then
tx_data_channel_reset_r(i) <= (others => '1');
end if;
end if;
end process;
i_dig_iq : DIG_IQ_HS_CUSTOM1X
port map(
INIT_CLK => clk_125_in,
INTERFACE_RESET => interface_reset(i),
IntL => '1',
MGTREFCLK_N => qsfp_ref_clk_n(i),
MGTREFCLK_P => qsfp_ref_clk_p(i),
ModPrsL => '0',
PADDR => p_addr,
PCLK => clk_125_in,
PENABLE => p_enable(i),
PRESETn => clk_125_resetn_in,
PSEL => '1',
PWDATA => p_wdata,
PWRITE => p_write,
RXN => qsfp_rx_rxn(i),
RXP => qsfp_rx_rxp(i),
RX_DATA_READY => rx_data_ready_in(i),
SCL_I => '0',
SDA_I => '0',
TX_DATA_CHANNEL_RESET => tx_data_channel_reset_r(i)(0),
TX_DATA_CLEAR => tx_data_clear_r(i),
TX_DATA_DAT => s_axis_tdata(i),--tx_data_r(i),
TX_DATA_EN => s_axis_tvalid(i),--tx_data_en_r(i),
DATA_CLK => clk(i),
INTERFACE_READY => dig_iq_interface_ready(i),
ModselL => open,
PRDATA => p_rdata(i),
PREADY => p_ready(i),
RX_DATA_CHANNEL_RESET => open,
RX_DATA_DAT => rx_data(i),
RX_DATA_EN => rx_data_en(i),
SCL_O => open,
SCL_OE => open,
SDA_O => open,
SDA_OE => open,
TXN => qsfp_tx_txn(i),
TXP => qsfp_tx_txp(i),
TX_DATA_READY => tx_data_ready(i)
);
-- GEN_1:
-- for j in 0 to 239 generate
-- begin
-- i_FD_rx_data : FD --FDRE
-- generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
-- port map (
-- Q => rx_data_r(i)(j), -- 1-bit output: Data
-- C => clk(i), -- 1-bit input: Clock
-- --CE => '1', -- 1-bit input: Clock enable
-- D => rx_data(i)(j) -- 1-bit input: Data
-- --R => '0' -- 1-bit input: Synchronous reset
-- );
-- end generate;
-- rx_data_en_int(i) <= rx_data_en(i) and rx_enable(i);
-- i_FD_rx_data_en : FD --FDRE
-- generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
-- port map (
-- Q => rx_data_en_r(i), -- 1-bit output: Data
-- C => clk(i), -- 1-bit input: Clock
-- --CE => '1', -- 1-bit input: Clock enable
-- D => rx_data_en_int(i) -- 1-bit input: Data
-- --R => '0' -- 1-bit input: Synchronous reset
-- );
-- i_clock_converter : axis_clock_converter_0
-- port map(
-- s_axis_aresetn => resetn(i),
-- m_axis_aresetn => aresetn_in,
-- s_axis_aclk => clk(i),
-- s_axis_tvalid => rx_data_en_r(i),
-- s_axis_tready => cc_overflow_tready(i),
-- s_axis_tdata => rx_data_r(i),
-- m_axis_aclk => aclk_in,
-- m_axis_tvalid => m_axis_tvalid_int(i),
-- m_axis_tready => m_axis_tvalid_int(i),
-- m_axis_tdata => m_axis_tdata_int(i)
-- );
-- cc_overflow_int(i) <= not(cc_overflow_tready(i)) and rx_data_en_r(i);
-- i_FDRE_cc_overflow : FDRE
-- generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
-- port map (
-- Q => dig_iq_cc_overflow(i), -- 1-bit output: Data
-- C => clk(i), -- 1-bit input: Clock
-- CE => cc_overflow_int(i), -- 1-bit input: Clock enable
-- D => '1', -- 1-bit input: Data
-- R => resetn(i) -- 1-bit input: Synchronous reset
-- );
-----------------------------------------------------------------------------------------------
-- R&S Documentation states:
--
-- TX_DATA_READY signal -- TX channel is receptive. After the deactivation of this signal,
-- up to five more enabled data samples are allowed on the TX_DATA_DAT
-- bus.
-- Thus, we can pipeline the tx_data between the output of the FIFO and the R&S core.
--
-- ** PIPELINING IS CURRENTLY COMMENTED OUT **
-----------------------------------------------------------------------------------------------
-- i_tx_fifo : axis_data_fifo_0
-- port map(
-- s_axis_aresetn => aresetn_in,
-- s_axis_aclk => aclk_in,
-- s_axis_tvalid => s_axis_tvalid(i),
-- s_axis_tready => s_axis_tready_int(i),
-- s_axis_tdata => s_axis_tdata(i),
-- m_axis_aclk => clk(i),
-- m_axis_tvalid => tx_fifo_m_tvalid(i),
-- m_axis_tready => tx_data_ready(i),
-- m_axis_tdata => tx_fifo_m_tdata(i)
-- );
--tx_fifo_overflow_int(i) <= not(s_axis_tready_int(i)) and s_axis_tvalid(i);
-- i_FDRE_tx_overflow : FDRE
-- generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
-- port map (
-- Q => dig_iq_tx_overflow(i), -- 1-bit output: Data
-- C => aclk_in, -- 1-bit input: Clock
-- CE => tx_fifo_overflow_int(i), -- 1-bit input: Clock enable
-- D => '1', -- 1-bit input: Data
-- R => aresetn_in -- 1-bit input: Synchronous reset
-- );
-- tx_data_en_int(i) <= tx_fifo_m_tvalid(i) and tx_data_ready(i);
--i_FD_tx_data_en : FD --RE
--generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
--port map (
-- Q => tx_data_en_r(i), -- 1-bit output: Data
-- C => clk(i), -- 1-bit input: Clock
-- --CE => '1', -- 1-bit input: Clock enable
-- D => tx_data_en_int(i) -- 1-bit input: Data
-- --R => '0' -- 1-bit input: Synchronous reset
-- );
-- tx_data_en_r(i) <= tx_data_en_int(i);
--GEN_2:
--for j in 0 to 239 generate
-- begin
--
-- i_FD_tx_data : FD --RE
-- generic map (
-- INIT => '0' -- Initial value of register, '0', '1'
-- )
-- port map (
-- Q => tx_data_r(i)(j), -- 1-bit output: Data
-- C => clk(i), -- 1-bit input: Clock
-- --CE => '1', -- 1-bit input: Clock enable
-- D => tx_fifo_m_tdata(i)(j) -- 1-bit input: Data
-- --R => '0' -- 1-bit input: Synchronous reset
-- );
--
-- end generate;
-- tx_data_r(i) <= tx_fifo_m_tdata(i);
end generate;
-----------------------------------------------------------
end structural;
ip_repo/qsfp_intfc_1_0/src/ila_3/ila_3.xci
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ip_repo/qsfp_intfc_1_0/src/tick_gen.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tick_gen is
generic(
CLOCK_SPEED_MHZ : integer := 100
);
port(
clk_in : in std_logic;
tick_1us_out : out std_logic;
tick_1ms_out : out std_logic;
tick_500ms_out : out std_logic;
tick_750ms_out : out std_logic;
tick_1s_out : out std_logic;
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
prog_us_tick_out : out std_logic;
reset_in : in std_logic
);
end entity tick_gen;
architecture imp of tick_gen is
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
signal usec_cnt_r : integer range 0 to 999;
signal msec_cnt_r : integer range 0 to 499;
signal msec_cnt1_r : integer range 0 to 999;
signal tick_1us_r : std_logic;
signal tick_1ms_r : std_logic;
signal tick_500ms_r : std_logic;
signal tick_750ms_r : std_logic;
signal tick_1s_r : std_logic;
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
signal prog_us_tick_r : std_logic;
begin
tick_1us_out <= tick_1us_r;
tick_1ms_out <= tick_1ms_r;
tick_500ms_out <= tick_500ms_r;
tick_750ms_out <= tick_750ms_r;
tick_1s_out <= tick_1s_r;
prog_us_tick_out <= prog_us_tick_r;
process(clk_in, reset_in)
begin
if(reset_in = '1') then
sysclk_cnt_r <= 0;
usec_cnt_r <= 0;
msec_cnt_r <= 0;
msec_cnt1_r <= 0;
tick_1us_r <= '1';
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '0';
elsif rising_edge(clk_in) then
tick_1ms_r <= '0';
tick_500ms_r <= '0';
tick_750ms_r <= '0';
tick_1s_r <= '0';
prog_us_tick_r <= '0';
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
sysclk_cnt_r <= 0;
tick_1us_r <= '1';
else
sysclk_cnt_r <= sysclk_cnt_r + 1;
tick_1us_r <= '0';
end if;
if(tick_1us_r = '1') then
if(usec_cnt_r = 999) then -- 1000us
usec_cnt_r <= 0;
tick_1ms_r <= '1';
else
usec_cnt_r <= usec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt_r = 499) then -- 500ms
msec_cnt_r <= 0;
tick_500ms_r <= '1';
else
msec_cnt_r <= msec_cnt_r + 1;
end if;
end if;
if(tick_1ms_r = '1') then
if(msec_cnt1_r = 749) then -- 750ms
tick_750ms_r <= '1';
end if;
if(msec_cnt1_r = 999) then -- 1s
msec_cnt1_r <= 0;
tick_1s_r <= '1';
else
msec_cnt1_r <= msec_cnt1_r + 1;
end if;
end if;
if(tick_1us_r = '1') then
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
prog_usec_cnt_r <= (others => '0');
prog_us_tick_r <= '1';
else
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
end if;
end if;
end if;
end process;
end architecture imp;
ip_repo/qsfp_intfc_1_0/src/vio_0_1/vio_0_1.xci
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ip_repo/qsfp_intfc_1_0/src/vio_2_1/vio_2_1.xci
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ip_repo/qsfp_intfc_1_0/xgui/qsfp_intfc_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
ipgui::add_param $IPINST -name "MINOR_REV"
}
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to validate FPGA_REVISION_DATE
return true
}
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
# Procedure called to validate MINOR_REV
return true
}
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to validate C_S00_AXI_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
# Procedure called to validate C_S00_AXI_BASEADDR
return true
}
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
# Procedure called to validate C_S00_AXI_HIGHADDR
return true
}
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
}
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
}
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
}