moving repo from git to local repo
This commit is contained in:
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|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>iq_512b_to_240b</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">64</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">30</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">195312500</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>083caf21</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>iq_512b_to_240b</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b25fa64d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>f64a5dae</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">239</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">511</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>SCOPED_TO_REF_iq_512b_to_240b</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_3d51e471</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/iq_512b_to_240b_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>iq_512b_to_240b</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">iq_512b_to_240b_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>iq_512b_to_240b</xilinx:displayName>
|
||||
<xilinx:definitionSource>IPI</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-24T16:38:16Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5a5f56fc"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2a3456f"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c875ab87"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ca8f49ff"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component iq_512b_to_240b_dig_iq_encoder_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_512b_to_240b_dig_iq_encoder_0_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component dig_iq_encoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component dig_iq_encoder;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component dig_iq_encoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_axis_dwidth_converter_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_encoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_encoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(223 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end dig_iq_encoder;
|
||||
|
||||
architecture imp of dig_iq_encoder is
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= s_axis_tvalid;
|
||||
s_axis_tready <= m_axis_tready;
|
||||
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(16) <= '0';
|
||||
m_axis_tdata(32 downto 17 ) <= s_axis_tdata(31 downto 16 ); -- IMAG[0]
|
||||
m_axis_tdata(33) <= '0';
|
||||
m_axis_tdata(49 downto 34 ) <= s_axis_tdata(47 downto 32 ); -- REAL[1]
|
||||
m_axis_tdata(50) <= '0';
|
||||
m_axis_tdata(66 downto 51 ) <= s_axis_tdata(63 downto 48 ); -- IMAG[1]
|
||||
m_axis_tdata(67) <= '0';
|
||||
m_axis_tdata(83 downto 68 ) <= s_axis_tdata(79 downto 64 ); -- REAL[2]
|
||||
m_axis_tdata(84) <= '0';
|
||||
m_axis_tdata(100 downto 85 ) <= s_axis_tdata(95 downto 80 ); -- IMAG[2]
|
||||
m_axis_tdata(101) <= '0';
|
||||
m_axis_tdata(117 downto 102 ) <= s_axis_tdata(111 downto 96 ); -- REAL[3]
|
||||
m_axis_tdata(118) <= '0';
|
||||
m_axis_tdata(134 downto 119 ) <= s_axis_tdata(127 downto 112 ); -- IMAG[3]
|
||||
m_axis_tdata(135) <= '0';
|
||||
m_axis_tdata(151 downto 136 ) <= s_axis_tdata(143 downto 128 ); -- REAL[4]
|
||||
m_axis_tdata(152) <= '0';
|
||||
m_axis_tdata(168 downto 153 ) <= s_axis_tdata(159 downto 144 ); -- IMAG[4]
|
||||
m_axis_tdata(169) <= '0';
|
||||
m_axis_tdata(185 downto 170 ) <= s_axis_tdata(175 downto 160 ); -- REAL[5]
|
||||
m_axis_tdata(186) <= '0';
|
||||
m_axis_tdata(202 downto 187 ) <= s_axis_tdata(191 downto 176 ); -- IMAG[5]
|
||||
m_axis_tdata(203) <= '0';
|
||||
m_axis_tdata(219 downto 204 ) <= s_axis_tdata(207 downto 192 ); -- REAL[6]
|
||||
m_axis_tdata(220) <= '0';
|
||||
m_axis_tdata(236 downto 221 ) <= s_axis_tdata(223 downto 208 ); -- IMAG[6]
|
||||
m_axis_tdata(139 downto 237 ) <= (others => '0');
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_dig_iq_encoder_0_0",
|
||||
"component_reference": "xilinx.com:user:dig_iq_encoder:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_dig_iq_encoder_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user