moving repo from git to local repo

This commit is contained in:
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
127 changed files with 97045 additions and 0 deletions
@@ -0,0 +1,367 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 24 11:31:28 2024
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
--Command : generate_target iq_240b_to_512b.bd
--Design : iq_240b_to_512b
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity iq_240b_to_512b is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tready : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
overflow : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
s_axis_tvalid : in STD_LOGIC;
s_axis_tready_out : out std_logic;
sel_12b_16bn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
end iq_240b_to_512b;
architecture STRUCTURE of iq_240b_to_512b is
component iq_240b_to_512b_axis_data_fifo_0_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
);
end component iq_240b_to_512b_axis_data_fifo_0_0;
component axis_demux is
generic(
DWIDTH : integer := 512
);
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
aselect : in STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
m0_axis_tvalid : out STD_LOGIC;
m0_axis_tready : in STD_LOGIC;
m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
m1_axis_tvalid : out STD_LOGIC;
m1_axis_tready : in STD_LOGIC
);
end component axis_demux;
component iq_240b_to_512b_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
);
end component iq_240b_to_512b_xlslice_0_0;
component dig_iq_decoder is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
select_12b : in STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
s_axis_tvalid : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
m_axis_tvalid : out STD_LOGIC
);
end component dig_iq_decoder;
component axis_mux is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
aselect : in STD_LOGIC;
s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s0_axis_tvalid : in STD_LOGIC;
s0_axis_tready : out STD_LOGIC;
s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s1_axis_tvalid : in STD_LOGIC;
s1_axis_tready : out STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC
);
end component axis_mux;
component iq_240b_to_512b_axis_register_slice_28B_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
);
end component iq_240b_to_512b_axis_register_slice_28B_0;
component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
component iq_240b_to_512b_overflow_detect_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
transfer_dropped : out STD_LOGIC
);
end component iq_240b_to_512b_overflow_detect_0;
component iq_240b_to_512b_axis_register_slice_40B_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
);
end component iq_240b_to_512b_axis_register_slice_40B_0;
component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
component iq_240b_to_512b_axis_register_slice_64B_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
);
end component iq_240b_to_512b_axis_register_slice_64B_0;
signal aclk_1 : STD_LOGIC;
signal aresetn_1 : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
signal const_1b0_dout : STD_LOGIC;
signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
signal iq_240b_to_512b_overflow : STD_LOGIC;
signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
signal s_axis_1_TVALID : STD_LOGIC;
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
begin
aclk_1 <= aclk;
aresetn_1 <= aresetn;
const_1b0_dout <= sel_12b_16bn;
iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
overflow <= iq_240b_to_512b_overflow;
s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
s_axis_1_TVALID <= s_axis_tvalid;
s_axis_tready_out <= axis_data_fifo_0_M_AXIS_TREADY;
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
port map (
m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
s_axis_aclk => aclk_1,
s_axis_aresetn => aresetn_1,
s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
s_axis_tready => overflow_detect_M_AXIS_TREADY,
s_axis_tvalid => overflow_detect_M_AXIS_TVALID
);
axis_demux_16b_12b_iq: component axis_demux
generic map (
DWIDTH => 320
)
port map (
aclk => aclk_1,
aresetn => aresetn_1,
aselect => const_1b0_dout,
m0_axis_tdata => axis_demux_0_m0_axis_tdata(319 downto 0),
m0_axis_tready => axis_register_slice_0_s_axis_tready,
m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
m1_axis_tdata => axis_demux_0_m1_axis_TDATA(319 downto 0),
m1_axis_tready => axis_demux_0_m1_axis_TREADY,
m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
s_axis_tdata => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
);
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
);
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
);
axis_mux_16b_12b_iq: component axis_mux
port map (
aclk => aclk_1,
aresetn => aresetn_1,
aselect => const_1b0_dout,
m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
m_axis_tready => axis_mux_0_m_axis_TREADY,
m_axis_tvalid => axis_mux_0_m_axis_TVALID,
s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
);
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
s_axis_tready => axis_register_slice_0_s_axis_tready,
s_axis_tvalid => axis_demux_0_m0_axis_tvalid
);
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
s_axis_tready => axis_demux_0_m1_axis_TREADY,
s_axis_tvalid => axis_demux_0_m1_axis_TVALID
);
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
s_axis_tready => axis_mux_0_m_axis_TREADY,
s_axis_tvalid => axis_mux_0_m_axis_TVALID
);
iq_decoder_12b_16b: component dig_iq_decoder
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
s_axis_tvalid => s_axis_1_TVALID,
select_12b => const_1b0_dout
);
overflow_detect: component iq_240b_to_512b_overflow_detect_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
m_axis_tready => overflow_detect_M_AXIS_TREADY,
m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
transfer_dropped => iq_240b_to_512b_overflow
);
xlslice_0: component iq_240b_to_512b_xlslice_0_0
port map (
Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
);
end STRUCTURE;
@@ -0,0 +1,173 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_data_fifo_0_0",
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
"ip_revision": "11",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_data_fifo_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "11" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"S_RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axis_aresetn" } ]
}
},
"S_CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axis_aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,165 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_demux_16b_12b_iq_0",
"cell_name": "axis_demux_16b_12b_iq",
"component_reference": "xilinx.com:user:axis_demux:1.0",
"ip_revision": "2",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"DWIDTH": [ { "value": "320", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_demux_16b_12b_iq_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"DWIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplus", "usage": "all" } ],
"BASE_BOARD_PART": [ { "value": "", "usage": "all" } ],
"BOARD_CONNECTIONS": [ { "value": "", "usage": "all" } ],
"DEVICE": [ { "value": "xcvu13p", "usage": "all" } ],
"PACKAGE": [ { "value": "figd2104", "usage": "all" } ],
"PREFHDL": [ { "value": "VHDL", "usage": "all" } ],
"SILICON_REVISION": [ { "value": "", "usage": "all" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED", "usage": "all" } ],
"SPEEDGRADE": [ { "value": "-2", "usage": "all" } ],
"STATIC_POWER": [ { "value": "", "usage": "all" } ],
"TEMPERATURE_GRADE": [ { "value": "E", "usage": "all" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "2" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"aselect": [ { "direction": "in" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0" } ],
"s_axis_tvalid": [ { "direction": "in" } ],
"s_axis_tready": [ { "direction": "out" } ],
"m0_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
"m0_axis_tvalid": [ { "direction": "out" } ],
"m0_axis_tready": [ { "direction": "in", "driver_value": "1" } ],
"m1_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
"m1_axis_tvalid": [ { "direction": "out" } ],
"m1_axis_tready": [ { "direction": "in", "driver_value": "1" } ]
},
"interfaces": {
"m0_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m0_axis_tdata" } ],
"TVALID": [ { "physical_name": "m0_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m0_axis_tready" } ]
}
},
"m1_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m1_axis_tdata" } ],
"TVALID": [ { "physical_name": "m1_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m1_axis_tready" } ]
}
},
"s_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ]
}
},
"aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "m0_axis:m1_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,154 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0",
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
"ip_revision": "28",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"S_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MI_TKEEP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
"m_axis_tkeep": [ { "direction": "out", "size_left": "63", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TKEEP": [ { "physical_name": "m_axis_tkeep" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,154 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0",
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
"ip_revision": "28",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"S_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MI_TKEEP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
"m_axis_tkeep": [ { "direction": "out", "size_left": "63", "size_right": "0" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TKEEP": [ { "physical_name": "m_axis_tkeep" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,165 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_mux_16b_12b_iq_0",
"cell_name": "axis_mux_16b_12b_iq",
"component_reference": "xilinx.com:user:axis_mux:1.0",
"ip_revision": "6",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "iq_240b_to_512b_axis_mux_16b_12b_iq_0", "resolve_type": "user", "usage": "all" } ],
"DWIDTH": [ { "value": "512", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"DWIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplus", "usage": "all" } ],
"BASE_BOARD_PART": [ { "value": "", "usage": "all" } ],
"BOARD_CONNECTIONS": [ { "value": "", "usage": "all" } ],
"DEVICE": [ { "value": "xcvu13p", "usage": "all" } ],
"PACKAGE": [ { "value": "figd2104", "usage": "all" } ],
"PREFHDL": [ { "value": "VHDL", "usage": "all" } ],
"SILICON_REVISION": [ { "value": "", "usage": "all" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED", "usage": "all" } ],
"SPEEDGRADE": [ { "value": "-2", "usage": "all" } ],
"STATIC_POWER": [ { "value": "", "usage": "all" } ],
"TEMPERATURE_GRADE": [ { "value": "E", "usage": "all" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "6" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"aselect": [ { "direction": "in" } ],
"s0_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
"s0_axis_tvalid": [ { "direction": "in" } ],
"s0_axis_tready": [ { "direction": "out" } ],
"s1_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0" } ],
"s1_axis_tvalid": [ { "direction": "in" } ],
"s1_axis_tready": [ { "direction": "out" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "1" } ]
},
"interfaces": {
"m_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ]
}
},
"s0_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s0_axis_tdata" } ],
"TVALID": [ { "physical_name": "s0_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s0_axis_tready" } ]
}
},
"s1_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s1_axis_tdata" } ],
"TVALID": [ { "physical_name": "s1_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s1_axis_tready" } ]
}
},
"aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,158 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_register_slice_28B_0",
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
"ip_revision": "29",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_register_slice_28B_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "29" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
},
"interfaces": {
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
}
}
}
}
}
}
@@ -0,0 +1,158 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_register_slice_40B_0",
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
"ip_revision": "29",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_register_slice_40B_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "29" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ]
},
"interfaces": {
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
}
}
}
}
}
}
@@ -0,0 +1,158 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_axis_register_slice_64B_0",
"component_reference": "xilinx.com:ip:axis_register_slice:1.1",
"ip_revision": "29",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"REG_CONFIG": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MASTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_axis_register_slice_64B_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_REG_CONFIG": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_SLR_CROSSINGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MASTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_SLAVE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PIPELINES_MIDDLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "29" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in", "driver_value": "0x1" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tready": [ { "direction": "out" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
},
"interfaces": {
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
},
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s_axis_tready" } ],
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
}
}
}
}
}
}
@@ -0,0 +1,129 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_iq_decoder_12b_16b_0",
"cell_name": "iq_decoder_12b_16b",
"component_reference": "xilinx.com:user:dig_iq_decoder:1.0",
"ip_revision": "2",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "iq_240b_to_512b_iq_decoder_12b_16b_0", "resolve_type": "user", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplus", "usage": "all" } ],
"BASE_BOARD_PART": [ { "value": "", "usage": "all" } ],
"BOARD_CONNECTIONS": [ { "value": "", "usage": "all" } ],
"DEVICE": [ { "value": "xcvu13p", "usage": "all" } ],
"PACKAGE": [ { "value": "figd2104", "usage": "all" } ],
"PREFHDL": [ { "value": "VHDL", "usage": "all" } ],
"SILICON_REVISION": [ { "value": "", "usage": "all" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED", "usage": "all" } ],
"SPEEDGRADE": [ { "value": "-2", "usage": "all" } ],
"STATIC_POWER": [ { "value": "", "usage": "all" } ],
"TEMPERATURE_GRADE": [ { "value": "E", "usage": "all" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "2" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"select_12b": [ { "direction": "in" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0" } ],
"s_axis_tvalid": [ { "direction": "in" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
"m_axis_tvalid": [ { "direction": "out" } ]
},
"interfaces": {
"m_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"s_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "iq_240b_to_512b_aclk", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,169 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_overflow_detect_0",
"component_reference": "xilinx.com:ip:axis_subset_converter:1.1",
"ip_revision": "29",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"S_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDATA_NUM_BYTES": [ { "value": "40", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_TUSER_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_HAS_TREADY": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"S_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_HAS_TREADY": [ { "value": "1", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M_HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DEFAULT_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"TDATA_REMAP": [ { "value": "tdata[319:0]", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"TUSER_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"TID_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"TDEST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"TKEEP_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"TSTRB_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"TLAST_REMAP": [ { "value": "1'b0", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "iq_240b_to_512b_overflow_detect_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_M_AXIS_TDATA_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_M_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DEFAULT_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "29" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axis_tdata": [ { "direction": "in", "size_left": "319", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "319", "size_right": "0" } ],
"transfer_dropped": [ { "direction": "out" } ]
},
"interfaces": {
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
}
},
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "40", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
}
},
"RSTIF": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"CLKIF": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
@@ -0,0 +1,48 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_xlconstant_0_0",
"component_reference": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "8",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "iq_240b_to_512b_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xcvu37p" } ],
"PACKAGE": [ { "value": "fsvh2892" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "8" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
}
}
}
}
@@ -0,0 +1,52 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "iq_240b_to_512b_xlslice_0_0",
"component_reference": "xilinx.com:ip:xlslice:1.0",
"ip_revision": "3",
"gen_directory": "./",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "iq_240b_to_512b_xlslice_0_0", "resolve_type": "user", "usage": "all" } ],
"DIN_TO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DIN_FROM": [ { "value": "223", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DIN_WIDTH": [ { "value": "320", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DOUT_WIDTH": [ { "value": "224", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"DIN_WIDTH": [ { "value": "320", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DIN_FROM": [ { "value": "223", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DIN_TO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "3" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "./" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"Din": [ { "direction": "in", "size_left": "319", "size_right": "0" } ],
"Dout": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
}
}
}
}