moving repo from git to local repo

2026-06-02 22:12:41 -04:00
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+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:user:axis_mux:1.0
+-- IP Revision: 6
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY axis_mux_256b IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    aresetn : IN STD_LOGIC;
+    aselect : IN STD_LOGIC;
+    s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    s0_axis_tvalid : IN STD_LOGIC;
+    s0_axis_tready : OUT STD_LOGIC;
+    s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+    s1_axis_tvalid : IN STD_LOGIC;
+    s1_axis_tready : OUT STD_LOGIC;
+    m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+    m_axis_tvalid : OUT STD_LOGIC;
+    m_axis_tready : IN STD_LOGIC
+  );
+END axis_mux_256b;
+
+ARCHITECTURE axis_mux_256b_arch OF axis_mux_256b IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_mux_256b_arch: ARCHITECTURE IS "yes";
+  COMPONENT axis_mux IS
+    GENERIC (
+      DWIDTH : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      aselect : IN STD_LOGIC;
+      s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+      s0_axis_tvalid : IN STD_LOGIC;
+      s0_axis_tready : OUT STD_LOGIC;
+      s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
+      s1_axis_tvalid : IN STD_LOGIC;
+      s1_axis_tready : OUT STD_LOGIC;
+      m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
+      m_axis_tvalid : OUT STD_LOGIC;
+      m_axis_tready : IN STD_LOGIC
+    );
+  END COMPONENT axis_mux;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux,Vivado 2023.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF axis_mux_256b_arch : ARCHITECTURE IS "axis_mux_256b,axis_mux,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux_256b,axis_mux,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_mux,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DWIDTH=256}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF axis_mux_256b_arch: ARCHITECTURE IS "package_project";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s0_axis:s1_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_tdata: SIGNAL IS "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s0_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s0_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s1_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s1_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TVALID";
+BEGIN
+  U0 : axis_mux
+    GENERIC MAP (
+      DWIDTH => 256
+    )
+    PORT MAP (
+      aclk => aclk,
+      aresetn => aresetn,
+      aselect => aselect,
+      s0_axis_tdata => s0_axis_tdata,
+      s0_axis_tvalid => s0_axis_tvalid,
+      s0_axis_tready => s0_axis_tready,
+      s1_axis_tdata => s1_axis_tdata,
+      s1_axis_tvalid => s1_axis_tvalid,
+      s1_axis_tready => s1_axis_tready,
+      m_axis_tdata => m_axis_tdata,
+      m_axis_tvalid => m_axis_tvalid,
+      m_axis_tready => m_axis_tready
+    );
+END axis_mux_256b_arch;