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This commit is contained in:
Nick Santana
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
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ip_repo/axis_mux_256b/axis_mux.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/18/2021 11:43:02 AM
-- Design Name:
-- Module Name: axis_mux - imp
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_mux is
generic(
DWIDTH : integer := 512
);
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic;
s0_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
s0_axis_tvalid : in std_logic;
s0_axis_tready : out std_logic;
s1_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
s1_axis_tvalid : in std_logic;
s1_axis_tready : out std_logic;
m_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic
);
end axis_mux;
architecture imp of axis_mux is
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
-- -- Use the port name for ASSOCIATED_RESET.
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
signal aselect_int : std_logic;
begin
-- i_xpm_cdc_single_0 : xpm_cdc_single
-- generic map(
-- DEST_SYNC_FF => 4,
-- INIT_SYNC_FF => 0,
-- SIM_ASSERT_CHK => 0,
-- SRC_INPUT_REG => 0
-- )
-- port map(
-- dest_out => aselect_int,
-- dest_clk => aclk,
-- src_clk => '0',
-- src_in => aselect
-- );
aselect_int <= aselect;
m_axis_tdata <= s0_axis_tdata when aselect_int = '0' else s1_axis_tdata;
m_axis_tvalid <= s0_axis_tvalid when aselect_int = '0' else s1_axis_tvalid;
s0_axis_tready <= m_axis_tready when aselect_int = '0' else '0';
s1_axis_tready <= m_axis_tready when aselect_int = '1' else '0';
end imp;
ip_repo/axis_mux_256b/axis_mux_256b.dcp
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ip_repo/axis_mux_256b/axis_mux_256b.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axis_mux_256b",
"component_reference": "xilinx.com:user:axis_mux:1.0",
"ip_revision": "6",
"gen_directory": ".",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "axis_mux_256b", "resolve_type": "user", "usage": "all" } ],
"DWIDTH": [ { "value": "256", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"DWIDTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplus" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu19eg" } ],
"PACKAGE": [ { "value": "ffvc1760" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "6" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "." } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2023.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"aselect": [ { "direction": "in" } ],
"s0_axis_tdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
"s0_axis_tvalid": [ { "direction": "in" } ],
"s0_axis_tready": [ { "direction": "out" } ],
"s1_axis_tdata": [ { "direction": "in", "size_left": "255", "size_right": "0", "driver_value": "0" } ],
"s1_axis_tvalid": [ { "direction": "in" } ],
"s1_axis_tready": [ { "direction": "out" } ],
"m_axis_tdata": [ { "direction": "out", "size_left": "255", "size_right": "0" } ],
"m_axis_tvalid": [ { "direction": "out" } ],
"m_axis_tready": [ { "direction": "in", "driver_value": "1" } ]
},
"interfaces": {
"m_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
"TREADY": [ { "physical_name": "m_axis_tready" } ]
}
},
"s0_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s0_axis_tdata" } ],
"TVALID": [ { "physical_name": "s0_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s0_axis_tready" } ]
}
},
"s1_axis": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "32", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "s1_axis_tdata" } ],
"TVALID": [ { "physical_name": "s1_axis_tvalid" } ],
"TREADY": [ { "physical_name": "s1_axis_tready" } ]
}
},
"aresetn": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
}
},
"aclk": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s0_axis:s1_axis", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "aclk" } ]
}
}
}
}
}
}
ip_repo/axis_mux_256b/axis_mux_256b.xml
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ip_repo/axis_mux_256b/axis_mux_256b_sim_netlist.v
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ip_repo/axis_mux_256b/axis_mux_256b_sim_netlist.vhdl
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ip_repo/axis_mux_256b/axis_mux_256b_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date : Fri Sep 19 16:06:04 2025
// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
// Command : write_verilog -force -mode synth_stub -rename_top axis_mux_256b -prefix
// axis_mux_256b_ axis_mux_256b_stub.v
// Design : axis_mux_256b
// Purpose : Stub declaration of top-level module interface
// Device : xczu19eg-ffvc1760-2-i
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_mux,Vivado 2023.2" *)
module axis_mux_256b(aclk, aresetn, aselect, s0_axis_tdata,
s0_axis_tvalid, s0_axis_tready, s1_axis_tdata, s1_axis_tvalid, s1_axis_tready,
m_axis_tdata, m_axis_tvalid, m_axis_tready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready" */;
input aclk;
input aresetn;
input aselect;
input [255:0]s0_axis_tdata;
input s0_axis_tvalid;
output s0_axis_tready;
input [255:0]s1_axis_tdata;
input s1_axis_tvalid;
output s1_axis_tready;
output [255:0]m_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
endmodule
ip_repo/axis_mux_256b/axis_mux_256b_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
-- Date : Fri Sep 19 16:06:04 2025
-- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top axis_mux_256b -prefix
-- axis_mux_256b_ axis_mux_256b_stub.vhdl
-- Design : axis_mux_256b
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu19eg-ffvc1760-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity axis_mux_256b is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
aselect : in STD_LOGIC;
s0_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s0_axis_tvalid : in STD_LOGIC;
s0_axis_tready : out STD_LOGIC;
s1_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s1_axis_tvalid : in STD_LOGIC;
s1_axis_tready : out STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC
);
end axis_mux_256b;
architecture stub of axis_mux_256b is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_mux,Vivado 2023.2";
begin
end;
ip_repo/axis_mux_256b/axis_mux_ooc.xdc
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##############################################################################################
#
# Used in Out-of-Context (OOC) synthesis only
#
##############################################################################################
create_clock -period 4 [get_ports aclk]
ip_repo/axis_mux_256b/synth/axis_mux_256b.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_mux:1.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_mux_256b IS
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
aselect : IN STD_LOGIC;
s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s0_axis_tvalid : IN STD_LOGIC;
s0_axis_tready : OUT STD_LOGIC;
s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s1_axis_tvalid : IN STD_LOGIC;
s1_axis_tready : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC
);
END axis_mux_256b;
ARCHITECTURE axis_mux_256b_arch OF axis_mux_256b IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_mux_256b_arch: ARCHITECTURE IS "yes";
COMPONENT axis_mux IS
GENERIC (
DWIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
aselect : IN STD_LOGIC;
s0_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s0_axis_tvalid : IN STD_LOGIC;
s0_axis_tready : OUT STD_LOGIC;
s1_axis_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s1_axis_tvalid : IN STD_LOGIC;
s1_axis_tready : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC
);
END COMPONENT axis_mux;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux,Vivado 2023.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_mux_256b_arch : ARCHITECTURE IS "axis_mux_256b,axis_mux,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axis_mux_256b_arch: ARCHITECTURE IS "axis_mux_256b,axis_mux,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_mux,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DWIDTH=256}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF axis_mux_256b_arch: ARCHITECTURE IS "package_project";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s0_axis:s1_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_tdata: SIGNAL IS "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s0_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s0_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s0_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s0_axis TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s1_axis_tdata: SIGNAL IS "XIL_INTERFACENAME s1_axis, TDATA_NUM_BYTES 32, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s1_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s1_axis TVALID";
BEGIN
U0 : axis_mux
GENERIC MAP (
DWIDTH => 256
)
PORT MAP (
aclk => aclk,
aresetn => aresetn,
aselect => aselect,
s0_axis_tdata => s0_axis_tdata,
s0_axis_tvalid => s0_axis_tvalid,
s0_axis_tready => s0_axis_tready,
s1_axis_tdata => s1_axis_tdata,
s1_axis_tvalid => s1_axis_tvalid,
s1_axis_tready => s1_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready
);
END axis_mux_256b_arch;