moving repo from git to local repo
This commit is contained in:
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axi_regs_32 is
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generic (
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-- Width of S_AXI data bus
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C_S_AXI_DATA_WIDTH : integer := 32;
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-- Width of S_AXI address bus
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C_S_AXI_ADDR_WIDTH : integer := 7
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);
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port (
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reg0_out : out std_logic_vector(31 downto 0);
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reg1_out : out std_logic_vector(31 downto 0);
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reg2_out : out std_logic_vector(31 downto 0);
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reg3_out : out std_logic_vector(31 downto 0);
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reg4_out : out std_logic_vector(31 downto 0);
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reg5_out : out std_logic_vector(31 downto 0);
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reg6_out : out std_logic_vector(31 downto 0);
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reg7_out : out std_logic_vector(31 downto 0);
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reg8_out : out std_logic_vector(31 downto 0);
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reg9_out : out std_logic_vector(31 downto 0);
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reg10_out : out std_logic_vector(31 downto 0);
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reg11_out : out std_logic_vector(31 downto 0);
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reg12_out : out std_logic_vector(31 downto 0);
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reg13_out : out std_logic_vector(31 downto 0);
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reg14_out : out std_logic_vector(31 downto 0);
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reg15_out : out std_logic_vector(31 downto 0);
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reg16_out : out std_logic_vector(31 downto 0);
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reg17_out : out std_logic_vector(31 downto 0);
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reg18_out : out std_logic_vector(31 downto 0);
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reg19_out : out std_logic_vector(31 downto 0);
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reg20_out : out std_logic_vector(31 downto 0);
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reg21_out : out std_logic_vector(31 downto 0);
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reg22_out : out std_logic_vector(31 downto 0);
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reg23_out : out std_logic_vector(31 downto 0);
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reg24_out : out std_logic_vector(31 downto 0);
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reg25_out : out std_logic_vector(31 downto 0);
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reg26_out : out std_logic_vector(31 downto 0);
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reg27_out : out std_logic_vector(31 downto 0);
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reg28_out : out std_logic_vector(31 downto 0);
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reg29_out : out std_logic_vector(31 downto 0);
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reg30_out : out std_logic_vector(31 downto 0);
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reg31_out : out std_logic_vector(31 downto 0);
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reg0_in : in std_logic_vector(31 downto 0);
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reg1_in : in std_logic_vector(31 downto 0);
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reg2_in : in std_logic_vector(31 downto 0);
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reg3_in : in std_logic_vector(31 downto 0);
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reg4_in : in std_logic_vector(31 downto 0);
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reg5_in : in std_logic_vector(31 downto 0);
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reg6_in : in std_logic_vector(31 downto 0);
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reg7_in : in std_logic_vector(31 downto 0);
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reg8_in : in std_logic_vector(31 downto 0);
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reg9_in : in std_logic_vector(31 downto 0);
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reg10_in : in std_logic_vector(31 downto 0);
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reg11_in : in std_logic_vector(31 downto 0);
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reg12_in : in std_logic_vector(31 downto 0);
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reg13_in : in std_logic_vector(31 downto 0);
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reg14_in : in std_logic_vector(31 downto 0);
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reg15_in : in std_logic_vector(31 downto 0);
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reg16_in : in std_logic_vector(31 downto 0);
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reg17_in : in std_logic_vector(31 downto 0);
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reg18_in : in std_logic_vector(31 downto 0);
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reg19_in : in std_logic_vector(31 downto 0);
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reg20_in : in std_logic_vector(31 downto 0);
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reg21_in : in std_logic_vector(31 downto 0);
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reg22_in : in std_logic_vector(31 downto 0);
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reg23_in : in std_logic_vector(31 downto 0);
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reg24_in : in std_logic_vector(31 downto 0);
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reg25_in : in std_logic_vector(31 downto 0);
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reg26_in : in std_logic_vector(31 downto 0);
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reg27_in : in std_logic_vector(31 downto 0);
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reg28_in : in std_logic_vector(31 downto 0);
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reg29_in : in std_logic_vector(31 downto 0);
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reg30_in : in std_logic_vector(31 downto 0);
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reg31_in : in std_logic_vector(31 downto 0);
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-- Global Clock Signal
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S_AXI_ACLK : in std_logic;
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-- Global Reset Signal. This Signal is Active LOW
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S_AXI_ARESETN : in std_logic;
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-- Write address (issued by master, acceped by Slave)
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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-- Write channel Protection type. This signal indicates the
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-- privilege and security level of the transaction, and whether
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-- the transaction is a data access or an instruction access.
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S_AXI_AWPROT : in std_logic_vector(2 downto 0);
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-- Write address valid. This signal indicates that the master signaling
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-- valid write address and control information.
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S_AXI_AWVALID : in std_logic;
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-- Write address ready. This signal indicates that the slave is ready
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-- to accept an address and associated control signals.
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S_AXI_AWREADY : out std_logic;
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-- Write data (issued by master, acceped by Slave)
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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-- Write strobes. This signal indicates which byte lanes hold
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-- valid data. There is one write strobe bit for each eight
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-- bits of the write data bus.
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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-- Write valid. This signal indicates that valid write
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-- data and strobes are available.
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S_AXI_WVALID : in std_logic;
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-- Write ready. This signal indicates that the slave
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-- can accept the write data.
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S_AXI_WREADY : out std_logic;
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-- Write response. This signal indicates the status
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-- of the write transaction.
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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-- Write response valid. This signal indicates that the channel
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-- is signaling a valid write response.
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S_AXI_BVALID : out std_logic;
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-- Response ready. This signal indicates that the master
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-- can accept a write response.
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S_AXI_BREADY : in std_logic;
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-- Read address (issued by master, acceped by Slave)
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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-- Protection type. This signal indicates the privilege
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-- and security level of the transaction, and whether the
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-- transaction is a data access or an instruction access.
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S_AXI_ARPROT : in std_logic_vector(2 downto 0);
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-- Read address valid. This signal indicates that the channel
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-- is signaling valid read address and control information.
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S_AXI_ARVALID : in std_logic;
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-- Read address ready. This signal indicates that the slave is
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-- ready to accept an address and associated control signals.
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S_AXI_ARREADY : out std_logic;
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-- Read data (issued by slave)
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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-- Read response. This signal indicates the status of the
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-- read transfer.
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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-- Read valid. This signal indicates that the channel is
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-- signaling the required read data.
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S_AXI_RVALID : out std_logic;
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-- Read ready. This signal indicates that the master can
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-- accept the read data and response information.
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S_AXI_RREADY : in std_logic
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);
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end axi_regs_32;
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architecture arch_imp of axi_regs_32 is
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-- AXI4LITE signals
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signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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signal axi_awready : std_logic;
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signal axi_wready : std_logic;
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signal axi_bresp : std_logic_vector(1 downto 0);
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signal axi_bvalid : std_logic;
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signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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signal axi_arready : std_logic;
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signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal axi_rresp : std_logic_vector(1 downto 0);
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signal axi_rvalid : std_logic;
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-- Example-specific design signals
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-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
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-- ADDR_LSB is used for addressing 32/64 bit registers/memories
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-- ADDR_LSB = 2 for 32 bits (n downto 2)
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-- ADDR_LSB = 3 for 64 bits (n downto 3)
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constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
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constant OPT_MEM_ADDR_BITS : integer := 4;
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------------------------------------------------
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---- Signals for user logic register space example
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--------------------------------------------------
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---- Number of Slave Registers 32
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signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal slv_reg_rden : std_logic;
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signal slv_reg_wren : std_logic;
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signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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signal byte_index : integer;
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signal aw_en : std_logic;
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begin
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-- I/O Connections assignments
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S_AXI_AWREADY <= axi_awready;
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S_AXI_WREADY <= axi_wready;
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S_AXI_BRESP <= axi_bresp;
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S_AXI_BVALID <= axi_bvalid;
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S_AXI_ARREADY <= axi_arready;
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S_AXI_RDATA <= axi_rdata;
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S_AXI_RRESP <= axi_rresp;
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S_AXI_RVALID <= axi_rvalid;
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-- Implement axi_awready generation
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-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
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-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
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-- de-asserted when reset is low.
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_awready <= '0';
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aw_en <= '1';
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else
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if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
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-- slave is ready to accept write address when
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-- there is a valid write address and write data
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-- on the write address and data bus. This design
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-- expects no outstanding transactions.
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axi_awready <= '1';
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aw_en <= '0';
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elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
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aw_en <= '1';
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axi_awready <= '0';
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else
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axi_awready <= '0';
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end if;
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end if;
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end if;
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end process;
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-- Implement axi_awaddr latching
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-- This process is used to latch the address when both
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-- S_AXI_AWVALID and S_AXI_WVALID are valid.
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_awaddr <= (others => '0');
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else
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if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
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-- Write Address latching
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axi_awaddr <= S_AXI_AWADDR;
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end if;
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end if;
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end if;
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end process;
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-- Implement axi_wready generation
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-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
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-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
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-- de-asserted when reset is low.
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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axi_wready <= '0';
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else
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if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
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-- slave is ready to accept write data when
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-- there is a valid write address and write data
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-- on the write address and data bus. This design
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-- expects no outstanding transactions.
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axi_wready <= '1';
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else
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axi_wready <= '0';
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end if;
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end if;
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end if;
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end process;
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-- Implement memory mapped register select and write logic generation
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-- The write data is accepted and written to memory mapped registers when
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-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
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-- select byte enables of slave registers while writing.
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-- These registers are cleared when reset (active low) is applied.
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-- Slave register write enable is asserted when valid address and data are available
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-- and the slave is ready to accept the write address and write data.
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slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
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process (S_AXI_ACLK)
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variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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slv_reg0 <= (others => '0');
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slv_reg1 <= (others => '0');
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slv_reg2 <= (others => '0');
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slv_reg3 <= (others => '0');
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slv_reg4 <= (others => '0');
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slv_reg5 <= (others => '0');
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slv_reg6 <= (others => '0');
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slv_reg7 <= (others => '0');
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slv_reg8 <= (others => '0');
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slv_reg9 <= (others => '0');
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slv_reg10 <= (others => '0');
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slv_reg11 <= (others => '0');
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slv_reg12 <= (others => '0');
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slv_reg13 <= (others => '0');
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slv_reg14 <= (others => '0');
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slv_reg15 <= (others => '0');
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slv_reg16 <= (others => '0');
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slv_reg17 <= (others => '0');
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slv_reg18 <= (others => '0');
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slv_reg19 <= (others => '0');
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slv_reg20 <= (others => '0');
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slv_reg21 <= (others => '0');
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slv_reg22 <= (others => '0');
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slv_reg23 <= (others => '0');
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slv_reg24 <= (others => '0');
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slv_reg25 <= (others => '0');
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slv_reg26 <= (others => '0');
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slv_reg27 <= (others => '0');
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slv_reg28 <= (others => '0');
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slv_reg29 <= (others => '0');
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slv_reg30 <= (others => '0');
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slv_reg31 <= (others => '0');
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else
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loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
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if (slv_reg_wren = '1') then
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case loc_addr is
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when b"00000" =>
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||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
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-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
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end if;
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end loop;
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||||
when b"00001" =>
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||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"00111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"01111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"10111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 24
|
||||
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 25
|
||||
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 26
|
||||
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 27
|
||||
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 28
|
||||
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 29
|
||||
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 30
|
||||
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"11111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 31
|
||||
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
slv_reg24 <= slv_reg24;
|
||||
slv_reg25 <= slv_reg25;
|
||||
slv_reg26 <= slv_reg26;
|
||||
slv_reg27 <= slv_reg27;
|
||||
slv_reg28 <= slv_reg28;
|
||||
slv_reg29 <= slv_reg29;
|
||||
slv_reg30 <= slv_reg30;
|
||||
slv_reg31 <= slv_reg31;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (reg0_in, reg1_in, reg2_in, reg3_in, reg4_in, reg5_in, reg6_in, reg7_in, reg8_in, reg9_in, reg10_in, reg11_in, reg12_in, reg13_in, reg14_in, reg15_in, reg16_in, reg17_in, reg18_in, reg19_in, reg20_in, reg21_in, reg22_in, reg23_in, reg24_in, reg25_in, reg26_in, reg27_in, reg28_in, reg29_in, reg30_in, reg31_in, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"00000" =>
|
||||
reg_data_out <= reg0_in;
|
||||
when b"00001" =>
|
||||
reg_data_out <= reg1_in;
|
||||
when b"00010" =>
|
||||
reg_data_out <= reg2_in;
|
||||
when b"00011" =>
|
||||
reg_data_out <= reg3_in;
|
||||
when b"00100" =>
|
||||
reg_data_out <= reg4_in;
|
||||
when b"00101" =>
|
||||
reg_data_out <= reg5_in;
|
||||
when b"00110" =>
|
||||
reg_data_out <= reg6_in;
|
||||
when b"00111" =>
|
||||
reg_data_out <= reg7_in;
|
||||
when b"01000" =>
|
||||
reg_data_out <= reg8_in;
|
||||
when b"01001" =>
|
||||
reg_data_out <= reg9_in;
|
||||
when b"01010" =>
|
||||
reg_data_out <= reg10_in;
|
||||
when b"01011" =>
|
||||
reg_data_out <= reg11_in;
|
||||
when b"01100" =>
|
||||
reg_data_out <= reg12_in;
|
||||
when b"01101" =>
|
||||
reg_data_out <= reg13_in;
|
||||
when b"01110" =>
|
||||
reg_data_out <= reg14_in;
|
||||
when b"01111" =>
|
||||
reg_data_out <= reg15_in;
|
||||
when b"10000" =>
|
||||
reg_data_out <= reg16_in;
|
||||
when b"10001" =>
|
||||
reg_data_out <= reg17_in;
|
||||
when b"10010" =>
|
||||
reg_data_out <= reg18_in;
|
||||
when b"10011" =>
|
||||
reg_data_out <= reg19_in;
|
||||
when b"10100" =>
|
||||
reg_data_out <= reg20_in;
|
||||
when b"10101" =>
|
||||
reg_data_out <= reg21_in;
|
||||
when b"10110" =>
|
||||
reg_data_out <= reg22_in;
|
||||
when b"10111" =>
|
||||
reg_data_out <= reg23_in;
|
||||
when b"11000" =>
|
||||
reg_data_out <= reg24_in;
|
||||
when b"11001" =>
|
||||
reg_data_out <= reg25_in;
|
||||
when b"11010" =>
|
||||
reg_data_out <= reg26_in;
|
||||
when b"11011" =>
|
||||
reg_data_out <= reg27_in;
|
||||
when b"11100" =>
|
||||
reg_data_out <= reg28_in;
|
||||
when b"11101" =>
|
||||
reg_data_out <= reg29_in;
|
||||
when b"11110" =>
|
||||
reg_data_out <= reg30_in;
|
||||
when b"11111" =>
|
||||
reg_data_out <= reg31_in;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reg0_out <= slv_reg0;
|
||||
reg1_out <= slv_reg1;
|
||||
reg2_out <= slv_reg2;
|
||||
reg3_out <= slv_reg3;
|
||||
reg4_out <= slv_reg4;
|
||||
reg5_out <= slv_reg5;
|
||||
reg6_out <= slv_reg6;
|
||||
reg7_out <= slv_reg7;
|
||||
reg8_out <= slv_reg8;
|
||||
reg9_out <= slv_reg9;
|
||||
reg10_out <= slv_reg10;
|
||||
reg11_out <= slv_reg11;
|
||||
reg12_out <= slv_reg12;
|
||||
reg13_out <= slv_reg13;
|
||||
reg14_out <= slv_reg14;
|
||||
reg15_out <= slv_reg15;
|
||||
reg16_out <= slv_reg16;
|
||||
reg17_out <= slv_reg17;
|
||||
reg18_out <= slv_reg18;
|
||||
reg19_out <= slv_reg19;
|
||||
reg20_out <= slv_reg20;
|
||||
reg21_out <= slv_reg21;
|
||||
reg22_out <= slv_reg22;
|
||||
reg23_out <= slv_reg23;
|
||||
reg24_out <= slv_reg24;
|
||||
reg25_out <= slv_reg25;
|
||||
reg26_out <= slv_reg26;
|
||||
reg27_out <= slv_reg27;
|
||||
reg28_out <= slv_reg28;
|
||||
reg29_out <= slv_reg29;
|
||||
reg30_out <= slv_reg30;
|
||||
reg31_out <= slv_reg31;
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
|
||||
|
||||
|
||||
create_clock -period 10.000 -name S_AXI_ACLK [get_ports S_AXI_ACLK];
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user