Erisys/alinx_z19_ad9082
6
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

moving repo from git to local repo

Browse Source
This commit is contained in:
Nick Santana
2026-06-02 22:12:41 -04:00
commit 29c85ad83d
127 changed files with 97045 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ip_repo/Si5332/src/clk_gen_cfg_2.vhd
+1152
View File
File diff suppressed because it is too large Load Diff
ip_repo/Si5332/src/global_types.vhd
+13
View File
@@ -0,0 +1,13 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
package global_types is
type data_vc1_type is array (127 downto 0) of std_logic_vector(7 downto 0);
type data_vc2_type is array (127 downto 0) of std_logic_vector(7 downto 0);
type mask_vcx_type is array (127 downto 0) of std_logic_vector(7 downto 0);
type addr_si5341_type is array (511 downto 0) of std_logic_vector(15 downto 0);
type data_si5341_type is array (511 downto 0) of std_logic_vector(7 downto 0);
end global_types;
package body global_types is
end global_types;
ip_repo/Si5332/src/i2c.vhd
+305
View File
@@ -0,0 +1,305 @@
--345678901234567890123456789012345678901234567890123456789012345678901234567890
-- 1 2 3 4 5 6 7
-- Title: I2C Master Controller
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
-- Company: For HiTechGlobal
-- Project:
-- File name: i2c.vhd
--------------------------------------------------------------------------------
-- Purpose:
--------------------------------------------------------------------------------
-- Simulator: Modelsim
-- Synthesis: Xilinx ISE
--------------------------------------------------------------------------------
-- Revision: 0.65
-- Modification date: 03/05/2003
-- Limitation:
-- Notes:
--------------------------------------------------------------------------------
-- Modifications List:
--
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_signed.all;
USE ieee.numeric_std.all;
use IEEE.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity i2c is
generic (
count_div : integer range 0 to 1023:= 512 -- sysclk divide coafficien (2 to 1023 max)
);
port (
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
DAT_IN : in std_logic_vector(7 downto 0); -- write data
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
AP_EN : in std_logic; -- Enable Address Phase During Write
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
CLK : in std_logic; -- main clock
RST : in std_logic; -- system reset
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
-- SDA : inout std_logic; -- i2c data
-- SCL : out std_logic; -- i2c CLK
I_SDA_I : in std_logic;
O_SDA_O : out std_logic;
O_SDA_T : out std_logic;
I_SCL_I : in std_logic;
O_SCL_O : out std_logic;
O_SCL_T : out std_logic;
I2C_RDY : out std_logic; -- i2c ready
I2C_ACT : out std_logic; -- i2c cycle active
ACK_ERR : out std_logic -- i2c(ack) error
);
end entity i2c;
architecture translated of i2c is
component IOBUF
port
(
O : out std_ulogic;
IO : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFT
port
(
O : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component i2c_st
port (
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
WRD_DAT : in std_logic_vector(7 downto 0);
DEV_ADDR : in std_logic_vector (6 downto 0);
CONTINUE : in std_logic;
ENAPH : in std_logic; -- Enable Address Phase During Write
WR_L : in std_logic;
RST : in std_logic; -- reset
CLK : in std_logic; -- mpu CLK
SCL_TICK : in std_logic; -- 5 usec CLK tick
I2C_GO : in std_logic; -- start i2c cycle
SDA_PIN : in std_logic; -- i2c data muxed input
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
SDA : out std_logic; -- i2c data
SCL : out std_logic; -- i2c CLK
SCL_CNT_EN : out std_logic; -- SCL cntr enable
I2C_RDY : out std_logic; -- i2c ready
I2C_ACT : out std_logic; -- i2c cycle active
ACK_ERR : out std_logic -- ack error
);
end component;
---------------------------------------------------------------------------------------------------
constant sim_timescale : time := 1 ns;
function length_ct (int_length : integer) return positive is
variable conv_length : std_logic_vector(9 downto 0);
variable index : positive:= 1;
begin
conv_length := CONV_STD_LOGIC_VECTOR(int_length, 10);
for i in 9 downto 1 loop
index:= i;
exit when conv_length(i) = '1';
end loop;
return index;
end length_ct;
signal cntr : std_logic_vector(length_ct(count_div) downto 0);
signal cntr_length : std_logic_vector(length_ct(count_div) downto 0);
signal scl_tick : std_logic;
signal wrd_addr : std_logic_vector(7 downto 0);
signal wrd_dat : std_logic_vector(7 downto 0);
signal dev_addr_int : std_logic_vector(6 downto 0);
signal ENAPH : std_logic;
signal scl_cnt_en : std_logic;
signal i2c_go : std_logic;
signal sda_in : std_logic;
signal sda_o : std_logic;
signal scl_o : std_logic;
signal wr_l_int : std_logic;
signal port_switch : std_logic:= '0';
signal sda_o_spd : std_logic;
signal scl_o_spd : std_logic;
signal GND : std_logic;
begin
GND <= '0';
---------------------------------------------------------------------------------------------------
-- CLOCK DIVIDER SECTION:
---------------------------------------------------------------------------------------------------
cntr_length <= CONV_STD_LOGIC_VECTOR(count_div, (length_ct(count_div)+1));
process (CLK,RST)
begin
if (RST = '1') then
cntr <= (others => '0') after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (scl_cnt_en = '1') then
cntr <= cntr + 1 after 1 * sim_timescale;
else
cntr <= (others => '0');
end if;
end if;
end process;
process (CLK,RST)
begin
if (RST = '1') then
scl_tick <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (cntr = cntr_length) then
scl_tick <= '1' after 1 * sim_timescale;
else
scl_tick <= '0' after 1 * sim_timescale;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- ADDRESS REGISTERS SECTION:
---------------------------------------------------------------------------------------------------
process (CLK)
begin
if (CLK'event and CLK = '1') then
if WR_EN = '1'
then wrd_addr <= ADDR_IN after 1 * sim_timescale;
dev_addr_int <= DEV_ADDR after 1 * sim_timescale;
wr_l_int <= WR_OP after 1 * sim_timescale;
wrd_dat <= DAT_IN after 1 * sim_timescale;
ENAPH <= AP_EN after 1 * sim_timescale;
end if;
end if;
end process;
process (CLK)
begin
if (CLK'event and CLK = '1') then
if WR_EN = '1'
then port_switch <= (DEV_ADDR(3) and not DEV_ADDR(2) and DEV_ADDR(1) and not DEV_ADDR(0)) after 1 * sim_timescale; -- "1010" (SPD)
else null;
end if;
end if;
end process;
process (CLK, RST)
begin
-- send ack right back
if (RST = '1') then
i2c_go <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if WR_EN = '1'
then
i2c_go <= '1' after 1 * sim_timescale;
else
if (scl_cnt_en = '1') then
i2c_go <= '0' after 1 * sim_timescale;
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
ACK_L <= '1' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if WR_EN = '1'
then ACK_L <= '0' after 1 * sim_timescale;
else
ACK_L <= '1' after 1 * sim_timescale;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- I2C STATE MACHINE SECTION:
---------------------------------------------------------------------------------------------------
MAIN_FSM : i2c_st
port map(
WRD_ADD => wrd_addr,
WRD_DAT => wrd_dat,
DEV_ADDR => dev_addr_int,
CONTINUE => CONTINUE,
ENAPH => ENAPH,
WR_L => wr_l_int,
RST => RST,
CLK => CLK,
SCL_TICK => scl_tick,
I2C_GO => i2c_go,
SDA_PIN => sda_in,
I2C_RDATA => I2C_RDATA,
SDA => sda_o,
SCL => scl_o,
SCL_CNT_EN => scl_cnt_en,
I2C_RDY => I2C_RDY,
I2C_ACT => I2C_ACT,
ACK_ERR => ACK_ERR
);
sda_o_spd <= sda_o;
scl_o_spd <= scl_o;
--SDA_BUF: IOBUF
-- port map
-- (
-- O => sda_in,
-- IO => SDA,
-- I => GND,
-- T => sda_o_spd
-- );
sda_in <= I_SDA_I;
O_SDA_O <= GND;
O_SDA_T <= sda_o_spd;
--SCL_BUF: OBUFT
-- port map
-- (
-- O => SCL,
-- I => GND,
-- T => scl_o_spd
-- );
-- scl_in <= I_SCL_I
O_SCL_O <= GND;
O_SCL_T <= scl_o_spd;
end architecture translated;
ip_repo/Si5332/src/i2c_st.vhd
+435
View File
@@ -0,0 +1,435 @@
--345678901234567890123456789012345678901234567890123456789012345678901234567890
-- 1 2 3 4 5 6 7
-- Title: I2C Master Controller Top level
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
-- Company: For HiTechGlobal
-- Project:
-- File name: i2c_st.vhd
--------------------------------------------------------------------------------
-- Purpose:
--------------------------------------------------------------------------------
-- Simulator: Modelsim
-- Synthesis: Xilinx ISE
--------------------------------------------------------------------------------
-- Revision: 0.65
-- Modification date: 03/05/2003
-- Limitation:
-- Notes:
--------------------------------------------------------------------------------
-- Modifications List:
--
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_signed.all;
USE ieee.numeric_std.all;
use IEEE.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity i2c_st is
port (
WRD_ADD : in std_logic_vector(7 downto 0); -- i2c address
WRD_DAT : in std_logic_vector(7 downto 0);
DEV_ADDR : in std_logic_vector (6 downto 0);
CONTINUE : in std_logic;
ENAPH : in std_logic; -- Enable Address Phase During Write
WR_L : in std_logic;
RST : in std_logic; -- reset
CLK : in std_logic; -- mpu CLK
SCL_TICK : in std_logic; -- 5 usec CLK tick
I2C_GO : in std_logic; -- start i2c cycle
SDA_PIN : in std_logic; -- i2c data muxed input
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
SDA : out std_logic; -- i2c data
SCL : out std_logic; -- i2c CLK
SCL_CNT_EN : out std_logic; -- SCL cntr enable
I2C_RDY : out std_logic; -- i2c ready
I2C_ACT : out std_logic; -- i2c cycle active
ACK_ERR : out std_logic -- ack error
);
end entity i2c_st;
architecture translated of i2c_st is
constant sim_timescale : time := 1 ns;
---------------------------------------------------------------------
type st_type is (idle, en_clk, start1, dev_id1, ack_id1, w_add, w_dat, ack_wr, ack_add, wait1,
dis_clk1, start2, dev_id2, ack_id2, data, ack_rd, stop1, ack_rd_mult);
signal i2c_state : st_type:= idle;
signal bit_cntr : std_logic_vector(2 downto 0);
signal scl_en : std_logic;
signal en_cntr : std_logic;
signal cntr_done : std_logic;
signal sda_int : std_logic;
signal scl_int : std_logic;
signal scl_cnt_en_int : std_logic;
signal i2c_rdy_int : std_logic;
signal i2c_act_int : std_logic;
signal i2c_rdata_int : std_logic_vector(7 downto 0);
signal ack_err_int : std_logic;
signal id_sel : std_logic_vector(7 downto 0);
signal id_code_op : std_logic_vector(7 downto 0);
attribute syn_useioff : boolean;
attribute syn_useioff of translated : architecture is true;
---------------------------------------------------------------------
begin
id_sel <= DEV_ADDR & '0';
id_code_op <= DEV_ADDR & '1';
SRL16E_inst : SRL16E
generic map (
INIT => X"1111")
port map (
Q => SDA, -- SRL data output
A0 => '1', -- Select[0] input
A1 => '1', -- Select[1] input
A2 => '1', -- Select[2] input
A3 => '1', -- Select[3] input
CE => '1', -- Clock enable input
CLK => CLK, -- Clock input
D => sda_int -- SRL data input
);
-- SDA <= sda_int;
SCL <= scl_int;
SCL_CNT_EN <= scl_cnt_en_int;
I2C_RDY <= i2c_rdy_int;
I2C_ACT <= i2c_act_int;
I2C_RDATA <= i2c_rdata_int;
ACK_ERR <= ack_err_int;
---------------------------------------------------------------------
-- state machine
process (CLK, RST)
begin
if (RST = '1') then
i2c_state <= idle after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
case i2c_state is
when idle =>
if (I2C_GO = '1') then
i2c_state <= en_clk after 1 * sim_timescale;
else i2c_state <= idle;
end if;
when en_clk =>
if (SCL_TICK = '1') then
i2c_state <= start1 after 1 * sim_timescale;
else i2c_state <= en_clk;
end if;
when start1 =>
if (SCL_TICK = '1') then
i2c_state <= dev_id1 after 1 * sim_timescale;
else i2c_state <= start1;
end if;
when dev_id1 =>
if ((cntr_done and SCL_TICK) = '1') then
i2c_state <= ack_id1 after 1 * sim_timescale;
else i2c_state <= dev_id1;
end if;
when ack_id1 =>
if ((SCL_TICK and scl_int) = '1') then
if ENAPH = '1' then
i2c_state <= w_add after 1 * sim_timescale;
else
i2c_state <= w_dat after 1 * sim_timescale;
end if;
else i2c_state <= ack_id1;
end if;
when w_add =>
if ((cntr_done and SCL_TICK) = '1') then
i2c_state <= ack_add after 1 * sim_timescale;
else i2c_state <= w_add;
end if;
when ack_add =>
if ((SCL_TICK and scl_int) = '1') then
case WR_L is
when '1' => i2c_state <= dis_clk1 after 1 * sim_timescale;
when others => i2c_state <= w_dat after 1 * sim_timescale;
end case;
else i2c_state <= ack_add;
end if;
when w_dat =>
if ((cntr_done and SCL_TICK) = '1') then
i2c_state <= ack_wr after 1 * sim_timescale;
else i2c_state <= w_dat;
end if;
when ack_wr =>
if ((SCL_TICK and scl_int) = '1') then
i2c_state <= stop1 after 1 * sim_timescale;
else i2c_state <= ack_wr;
end if;
when dis_clk1 =>
if ((SCL_TICK and scl_int) = '1') then
i2c_state <= wait1 after 1 * sim_timescale;
else i2c_state <= dis_clk1;
end if;
when wait1 =>
if (SCL_TICK = '1') then
i2c_state <= start2 after 1 * sim_timescale;
else i2c_state <= wait1;
end if;
when start2 =>
if (SCL_TICK = '1') then
i2c_state <= dev_id2 after 1 * sim_timescale;
else i2c_state <= start2;
end if;
when dev_id2 =>
if ((cntr_done and SCL_TICK) = '1') then
i2c_state <= ack_id2 after 1 * sim_timescale;
else i2c_state <= dev_id2;
end if;
when ack_id2 =>
if ((SCL_TICK and scl_int) = '1') then
i2c_state <= data after 1 * sim_timescale;
else i2c_state <= ack_id2;
end if;
when data =>
if ((cntr_done and SCL_TICK) = '1') then
case CONTINUE is
when '1' => i2c_state <= ack_rd_mult after 1 * sim_timescale; --
when others => i2c_state <= ack_rd after 1 * sim_timescale;--
end case;
else i2c_state <= data;
end if;
when ack_rd =>
if ((SCL_TICK and scl_int) = '1') then
i2c_state <= stop1 after 1 * sim_timescale;
else i2c_state <= ack_rd;
end if;
when ack_rd_mult =>
if ((SCL_TICK and scl_int) = '1')
then i2c_state <= data after 1 * sim_timescale;
else i2c_state <= ack_rd_mult;
end if;
when stop1 =>
if ((SCL_TICK and scl_int) = '1') then
i2c_state <= idle after 1 * sim_timescale;
else i2c_state <= stop1;
end if;
when others =>
i2c_state <= idle after 1 * sim_timescale;
end case;
end if;
end process;
---------------------------------------------------------------------
-- bit counter
process (CLK, RST)
begin
if (RST = '1') then
bit_cntr <= "111" after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (((en_cntr and scl_int) and SCL_TICK) = '1') then
bit_cntr <= bit_cntr - "001" after 1 * sim_timescale;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
cntr_done <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if ((bit_cntr = "000") and (scl_int = '1')) then
cntr_done <= '1' after 1 * sim_timescale;
else
cntr_done <= '0' after 1 * sim_timescale;
end if;
end if;
end process;
process (CLK, RST)
begin
---------------------------------------------------------------------
-- SCL generation
-- enable CLK divider
if (RST = '1') then
en_cntr <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if ((i2c_state = dev_id1) or (i2c_state = w_add) or (i2c_state =
dev_id2) or (i2c_state = data) or (i2c_state = w_dat)) then
en_cntr <= '1' after 1 * sim_timescale;
else
if (cntr_done = '1') then
en_cntr <= '0' after 1 * sim_timescale;
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
scl_cnt_en_int <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (i2c_state = en_clk) then
scl_cnt_en_int <= '1' after 1 * sim_timescale;
else
if (i2c_state = idle) then
scl_cnt_en_int <= '0' after 1 * sim_timescale;
end if;
end if;
end if;
end process;
-- enables tick divider
--process (CLK, RST)
--begin
-- if (RST = '1') then
-- scl_en <= '0' after 1 * sim_timescale;
-- elsif (CLK'event and CLK = '1') then
-- if (i2c_state = start1) then
-- scl_en <= '1' after 1 * sim_timescale;
-- else
-- if (i2c_state = dis_clk1) and (SCL_TICK = '1') then
-- scl_en <= '0' after 1 * sim_timescale;
-- else
-- if (i2c_state = start2) then
-- scl_en <= '1' after 1 * sim_timescale;
-- else
-- if (i2c_state = stop1) and (scl_int = '1')
-- then
-- scl_en <= '0' after 1 * sim_timescale;
-- end if;
-- end if;
-- end if;
-- end if;
-- end if;
--end process;
process (CLK, RST)
begin
if (RST = '1') then
scl_en <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (i2c_state = start1) or (i2c_state = start2) then
scl_en <= '1' after 1 * sim_timescale;
else
if ((i2c_state = dis_clk1) and (SCL_TICK = '1')) or ((i2c_state = stop1) and (scl_int = '1')) then
scl_en <= '0' after 1 * sim_timescale;
else null;
end if;
end if;
end if;
end process;
-- tick divider
process (CLK, RST)
begin
if (RST = '1') then
scl_int <= '1' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if ((scl_en and SCL_TICK) = '1') then
scl_int <= not scl_int after 1 * sim_timescale;
end if;
end if;
end process;
---------------------------------------------------------------------
process (CLK, RST)
begin
if (RST = '1') then
sda_int <= '1' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if ((i2c_state = start1) or (i2c_state = start2) or (i2c_state = stop1) or (i2c_state = ack_rd_mult))
then sda_int <= '0' after 1 * sim_timescale;
else
if (i2c_state = dev_id1) then
sda_int <= id_sel(conv_integer(bit_cntr)) after 1 *
sim_timescale;
elsif (i2c_state = dev_id2) then
sda_int <= id_code_op(conv_integer(bit_cntr)) after 1 *
sim_timescale;
elsif (i2c_state = w_add) then
sda_int <= WRD_ADD(conv_integer(bit_cntr)) after 1 *
sim_timescale;
elsif (i2c_state = w_dat) then
sda_int <= WRD_DAT(conv_integer(bit_cntr)) after 1 *
sim_timescale;
else
sda_int <= '1' after 1 * sim_timescale;
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (i2c_state = data) and (scl_int = '1') then
i2c_rdata_int(conv_integer(bit_cntr)) <= SDA_PIN after 1 *
sim_timescale;
else
if (I2C_GO = '1') then
i2c_rdata_int <= "00000000" after 1 * sim_timescale;
end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
i2c_rdy_int <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (((i2c_state = stop1) and (scl_int = '1')) or
((i2c_state = ack_rd_mult) and (scl_int and not SDA_PIN and WR_L) = '1')) then
i2c_rdy_int <= '1' after 1 * sim_timescale;
else
-- if (I2C_GO = '1') then
i2c_rdy_int <= '0' after 1 * sim_timescale;
-- end if;
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
ack_err_int <= '0' after 1 * sim_timescale;
elsif (CLK'event and CLK = '1') then
if (((i2c_state = ack_id1) or (i2c_state = ack_add) or (i2c_state = ack_id2) or (i2c_state = ack_rd_mult) or (i2c_state = ack_wr))
and (scl_int and SDA_PIN) = '1') then
ack_err_int <= '1' after 1 * sim_timescale;
else
if (I2C_GO = '1') then
ack_err_int <= '0' after 1 * sim_timescale;
end if;
end if;
end if;
end process;
i2c_act_int <= '0' when i2c_state = idle else '1';
end architecture translated;
ip_repo/Si5332/src/si5332_wrapper.vhd
+126
View File
@@ -0,0 +1,126 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity si5332_wrapper is
port(
clk_100_in : in std_logic;
clk_100_areset_in : in std_logic;
sda_in : in std_logic;
sda_out : out std_logic;
sda_t_out : out std_logic;
scl_in : in std_logic;
scl_out : out std_logic;
scl_t_out : out std_logic
);
end entity si5332_wrapper;
architecture imp of si5332_wrapper is
signal tick_1ms : std_logic;
signal i2c_mux_access_ok : std_logic;
signal si5341_access_ok : std_logic;
signal si5341_config_done : std_logic;
signal si5341_config_error : std_logic;
signal man_clk_gen_en : std_logic := '0';
signal man_clk_gen_cfg_reset : std_logic := '0';
signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
-----------------------------------
i_si5341_clk_conf : entity work.si5341_clk_configurator
port map (
sys_clk100_in => clk_100_in,
tick_1ms_in => tick_1ms,
sda_in => sda_in,
sda_out => sda_out,
sda_t_out => sda_t_out,
scl_in => scl_in,
scl_out => scl_out,
scl_t_out => scl_t_out,
i2c_mux_access_ok_out => i2c_mux_access_ok,
si5341_access_ok_out => si5341_access_ok,
si5341_config_done_out => si5341_config_done,
si5341_config_error_out => si5341_config_error,
man_clk_gen_en_in => man_clk_gen_en,
man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
reset_in => clk_100_areset_in
);
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 100
)
port map (
clk_in => clk_100_in,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000_0000",
prog_us_tick_out => open,
reset_in => clk_100_areset_in
);
-- i_vio_3 : entity work.vio_3
-- port map (
-- clk => clk_100_in,
-- probe_in0(0) => i2c_mux_access_ok, -- 1
-- probe_in1(0) => si5341_access_ok, -- 1
-- probe_in2(0) => si5341_config_done, -- 1
-- probe_in3(0) => si5341_config_error, -- 1
-- probe_in4 => clk_100_freq_r, -- 32
-- probe_in5 => clk_100_cnt_r, -- 32
-- probe_in6 => qsfp2_freq_r, -- 32
-- probe_in7 => qsfp2_cnt_r, -- 32
-- probe_in8 => qsfp3_freq_r, -- 32
-- probe_in9 => qsfp3_cnt_r, -- 32
-- probe_out0(0) => man_clk_gen_en, -- 1
-- probe_out1(0) => man_clk_gen_cfg_reset -- 1
-- );
process(clk_100_in)
begin
if (rising_edge(clk_100_in)) then
clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_100_tick_1ms_r(0 to 1) = "01") then
clk_100_freq_r <= clk_100_cnt_r;
clk_100_cnt_r <= (others => '0');
else
clk_100_cnt_r <= clk_100_cnt_r + 1;
end if;
end if;
end process;
end architecture imp;
ip_repo/Si5332/src/si5341_clk_configurator.vhd
+183
View File
@@ -0,0 +1,183 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity si5341_clk_configurator is
port (
sys_clk100_in : in std_logic;
tick_1ms_in : in std_logic;
sda_in : in std_logic;
sda_out : out std_logic;
sda_t_out : out std_logic;
scl_in : in std_logic;
scl_out : out std_logic;
scl_t_out : out std_logic;
i2c_mux_access_ok_out : out std_logic;
si5341_access_ok_out : out std_logic;
si5341_config_done_out : out std_logic;
si5341_config_error_out : out std_logic;
man_clk_gen_en_in : in std_logic;
man_clk_gen_cfg_reset_in : in std_logic;
reset_in : in std_logic
);
end entity si5341_clk_configurator;
architecture imp of si5341_clk_configurator is
signal clk_gen_cfg_reset_d : std_logic := '0';
signal clk_gen_cfg_reset : std_logic;
signal i2c_mux_access_ok : std_logic;
signal si5341_access_ok : std_logic;
signal si5341_config_done : std_logic;
signal si5341_config_error : std_logic;
type fsm_state_sm is (idle_st, si5341_reset_lo_st, si5341_reset_hi_st, si5341_config_st, si5341_config_wait_st,
si5341_config_check_st, done_st);
signal state_d : fsm_state_sm := idle_st;
signal tick_cnt_d : integer;
signal state_test_r : std_logic_vector(2 downto 0) := (others => '0');
begin
clk_gen_cfg_reset <= man_clk_gen_cfg_reset_in when man_clk_gen_en_in = '1' else clk_gen_cfg_reset_d;
i_clk_gen_cfg : entity work.clk_gen_cfg
generic map (
simulation_mode => '0'
)
port map (
sys_clk_in => sys_clk100_in,
reset_in => clk_gen_cfg_reset,
i2c_mux_access_ok_out => i2c_mux_access_ok,
si5341_access_ok_out => si5341_access_ok,
si5341_config_done_out => si5341_config_done,
si5341_config_error_out => si5341_config_error,
I_SDA_I => sda_in,
O_SDA_O => sda_out,
O_SDA_T => sda_t_out,
I_SCL_I => scl_in,
O_SCL_O => scl_out,
O_SCL_T => scl_t_out
);
i2c_mux_access_ok_out <= i2c_mux_access_ok;
si5341_access_ok_out <= si5341_access_ok;
si5341_config_done_out <= si5341_config_done;
si5341_config_error_out <= si5341_config_error;
process(state_d)
begin
case state_d is
when idle_st => state_test_r <= "000";
when si5341_reset_lo_st => state_test_r <= "001";
when si5341_reset_hi_st => state_test_r <= "010";
when si5341_config_st => state_test_r <= "011";
when si5341_config_wait_st => state_test_r <= "100";
when si5341_config_check_st => state_test_r <= "101";
when done_st => state_test_r <= "110";
when others => state_test_r <= "111";
end case;
end process;
-- i_ila_0 : entity work.ila_0
-- port map (
-- clk => sys_clk100_in,
-- probe0 => state_test_r, --3
-- probe1(0) => i2c_mux_access_ok, --1
-- probe2(0) => si5341_access_ok, --1
-- probe3(0) => si5341_config_done, --1
-- probe4(0) => si5341_config_error, --1
-- probe5(0) => clk_gen_cfg_reset, --1
-- probe7(0) => clk_gen_cfg_reset_d, --1
-- probe9(0) => tick_1ms_in --1
-- );
process(sys_clk100_in)
begin
if (rising_edge(sys_clk100_in)) then
if (reset_in = '1') then
clk_gen_cfg_reset_d <= '0';
tick_cnt_d <= 500;
state_d <= idle_st;
else
if (tick_1ms_in = '1') then
tick_cnt_d <= tick_cnt_d - 1;
end if;
case state_d is
when idle_st => --0
if (tick_cnt_d = 0) then
tick_cnt_d <= 250;
state_d <= si5341_reset_lo_st;
else
state_d <= idle_st;
end if;
when si5341_reset_lo_st => --1
if (tick_cnt_d = 0) then
tick_cnt_d <= 100;
state_d <= si5341_reset_hi_st;
else
state_d <= si5341_reset_lo_st;
end if;
when si5341_reset_hi_st => --2
if (tick_cnt_d = 0) then
clk_gen_cfg_reset_d <= '1';
tick_cnt_d <= 250;
state_d <= si5341_config_st;
else
state_d <= si5341_reset_hi_st;
end if;
when si5341_config_st => --3
if (tick_cnt_d = 0) then
clk_gen_cfg_reset_d <= '0';
tick_cnt_d <= 1000;
state_d <= si5341_config_wait_st;
else
state_d <= si5341_config_st;
end if;
when si5341_config_wait_st => --4
if (tick_cnt_d = 0) then
tick_cnt_d <= 1000;
state_d <= si5341_config_check_st;
else
state_d <= si5341_config_wait_st;
end if;
when si5341_config_check_st => --5
if (tick_cnt_d = 0) then
tick_cnt_d <= 250;
state_d <= idle_st;
elsif (i2c_mux_access_ok = '1' and si5341_access_ok = '1' and si5341_config_done = '1' and si5341_config_error = '0') then
state_d <= done_st;
else
state_d <= si5341_config_check_st;
end if;
when done_st => --6
state_d <= done_st;
when others => --7
state_d <= idle_st;
end case;
end if;
end if;
end process;
end architecture imp;
ip_repo/Si5332/src/si5341_gen_cfg.vhd
+380
View File
@@ -0,0 +1,380 @@
--345678901234567890123456789012345678901234567890123456789012345678901234567890
-- 1 2 3 4 5 6 7
-- Title: Silicon Lab Si5341 Clock Generator Configuration Design
-- Engineer: Evgeny Shumilov <eugene.shumilov@gmail.com>
-- Company: For HiTechGlobal
-- Project: HTG-ZRF8
-- File name: si5341_gen_cfg.vhd
--------------------------------------------------------------------------------
-- Purpose: Configures Si5341 Clock Generators on Start-up
--------------------------------------------------------------------------------
-- Simulator: Xilinx Vivado
-- Synthesis: Xilinx Vivado
--------------------------------------------------------------------------------
-- Revision: 1.00
-- Modification date: 20/10/2018
-- Limitation: Design requires 12.5MHz input clock.
-- Change COUNT_DIV value for other bus frequency.
-- Notes:
--------------------------------------------------------------------------------
-- Modifications List:
--
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_signed.all;
USE ieee.numeric_std.all;
use IEEE.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
use work.global_types.all;
entity si5341_gen_cfg is
generic (
COUNT_DIV : integer range 0 to 1023 := 512; -- sysclk divide coefficient (Valid Values: 2 to 1023)
SIZ5341 : integer range 0 to 511 := 511; -- Real Address/Data Array Size (Valid Values: 1 to 511)
ADR5341 : addr_si5341_type := (others => (others => '0'));
DAT5341 : data_si5341_type := (others => (others => '0'));
simulation_mode : std_logic := '0'
);
port (
-- System signals
CLK : in std_logic; -- main clock
RST : in std_logic; -- system reset
-- External Operation Control
START : in std_logic; -- Run Start-Up Clock Genrators Configuration
-- Status Output
i2c_mux_access_ok_out : out std_logic;
si5341_access_ok_out : out std_logic;
si5341_config_done_out : out std_logic;
si5341_config_error_out : out std_logic;
-- I2C Bus
I_SDA_I : in std_logic;
O_SDA_O : out std_logic;
O_SDA_T : out std_logic;
I_SCL_I : in std_logic;
O_SCL_O : out std_logic;
O_SCL_T : out std_logic
);
end entity si5341_gen_cfg;
architecture si5341_gen_cfg_arch of si5341_gen_cfg is
component i2c
generic (
count_div : integer range 0 to 1023:= 512 -- sysclk divide coefficient (2 to 1023 max)
);
port (
ADDR_IN : in std_logic_vector (7 downto 0); -- word address
DAT_IN : in std_logic_vector(7 downto 0); -- write data
DEV_ADDR : in std_logic_vector (6 downto 0); -- device address
CONTINUE : in std_logic; -- continue read operation from ADDR_IN
AP_EN : in std_logic; -- Enable Address Phase During Write
WR_OP : in std_logic; -- write operation WRITE ONE WORD <= '0', RD <= '1'
WR_EN : in std_logic; -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
CLK : in std_logic; -- main clock
RST : in std_logic; -- system reset
I2C_RDATA : out std_logic_vector(7 downto 0); -- i2c read data
ACK_L : out std_logic; -- acknowledge WR_EN (active '0')
-- SDA : inout std_logic; -- i2c data
-- SCL : out std_logic; -- i2c CLK
I_SDA_I : in std_logic;
O_SDA_O : out std_logic;
O_SDA_T : out std_logic;
I_SCL_I : in std_logic;
O_SCL_O : out std_logic;
O_SCL_T : out std_logic;
I2C_RDY : out std_logic; -- i2c ready
I2C_ACT : out std_logic; -- i2c cycle active
ACK_ERR : out std_logic -- i2c(ack) error
);
end component;
constant sim_timescale : time := 1 ns;
type fsm_state is (IDLE, SI5341_NEW, SI5341_NEW_WR, SI5341_NEW_INC, FINISH, ERROR);
signal state_r : fsm_state := IDLE;
signal i2c_rdata : std_logic_vector(7 downto 0);
signal si5341_adr_arr : addr_si5341_type := ADR5341;
signal si5341_dat_arr : data_si5341_type := DAT5341;
signal dev_addr : std_logic_vector(6 downto 0);
signal new_adr : std_logic_vector(7 downto 0);
signal cur_addr : integer range 0 to 511 := 0;
signal inc_adr : std_logic;
signal new_da : std_logic_vector(6 downto 0):= (others => '0');
signal addr : std_logic_vector(8 downto 0);
signal new_dat : std_logic_vector(7 downto 0);
signal new_wr : std_logic;
signal new_op : std_logic;
signal new_apen : std_logic := '0';
signal ap_en : std_logic;
signal dat_in : std_logic_vector(7 downto 0);
signal word_addr : std_logic_vector(7 downto 0);
signal we_i2c : std_logic;
signal wr_i2c : std_logic;
signal ack_err : std_logic;
signal i2c_rdy : std_logic;
signal i2c_act : std_logic;
signal CONTINUE : std_logic;
signal ACK_L : std_logic;
signal i2c_busy : std_logic;
signal i2c_act_fall : std_logic := '0';
signal i2c_act_rg : std_logic := '0';
signal addr_itg : integer range 0 to 511;
signal si5341_size : integer range 0 to 511;
signal si5341_data : std_logic_vector(7 downto 0);
signal si5341_addr : std_logic_vector(15 downto 0);
signal si5341_addr_h : std_logic_vector(7 downto 0);
signal si5341_addr_l : std_logic_vector(7 downto 0);
signal state_test_r : std_logic_vector(3 downto 0) := (others => '0');
signal i2c_mux_access_ok_r : std_logic := '0';
signal si5341_access_ok_r : std_logic := '0';
signal si5341_config_done_r : std_logic := '0';
signal si5341_config_error_r : std_logic := '0';
begin
addr_itg <= CONV_INTEGER(cur_addr);
si5341_addr <= si5341_adr_arr(addr_itg);
si5341_data <= si5341_dat_arr(addr_itg);
si5341_size <= SIZ5341;
si5341_addr_h <= si5341_addr(15 downto 8); -- Page Number
si5341_addr_l <= si5341_addr( 7 downto 0); -- Byte Address
i2c_mux_access_ok_out <= i2c_mux_access_ok_r;
si5341_access_ok_out <= si5341_access_ok_r;
si5341_config_done_out <= si5341_config_done_r;
si5341_config_error_out <= si5341_config_error_r;
process(state_r)
begin
case state_r is
when IDLE => state_test_r <= "0000";
when SI5341_NEW => state_test_r <= "0011";
when SI5341_NEW_WR => state_test_r <= "0101";
when SI5341_NEW_INC => state_test_r <= "0110";
when FINISH => state_test_r <= "1000";
when ERROR => state_test_r <= "1001";
when others => state_test_r <= "1111";
end case;
end process;
-- i_ila_1 : entity work.ila_1
-- port map (
-- clk => CLK,
-- probe0 => state_test_r, --4
-- probe1 => new_da, --7
-- probe2 => new_dat, --8
-- probe3(0) => new_wr, --1
-- probe4(0) => i2c_busy, --1
-- probe7(0) => i2c_rdy, --1
-- probe8(0) => i2c_act, --1
-- probe9(0) => ack_err, --1
-- probe10(0) => START, --1
-- probe13 => new_adr -- 8
-- );
---------------------------------------------------------------------------------------------
-- I2C Mudule
---------------------------------------------------------------------------------------------
SPD_READ_UNIT: i2c
generic map(
count_div => COUNT_DIV -- sysclk divide coafficien (2 to 1023 max)
)
port map(
ADDR_IN => word_addr, -- word address
DAT_IN => DAT_IN, -- write data
DEV_ADDR => dev_addr, -- device address
CONTINUE => CONTINUE, -- continue read operation from ADDR_IN
AP_EN => ap_en, -- Enable Address Phase During Write
WR_OP => wr_i2c, -- write operation WRITE ONE WORD <= '0', RD <= '1'
WR_EN => we_i2c, -- enable write ADDR_IN, DAT_IN, ID_ADDR, WR_OP
CLK => CLK, -- main clock
RST => RST, -- system reset
I2C_RDATA => i2c_rdata, -- i2c read data
ACK_L => ACK_L, -- acknowledge WR_EN (active '0')
I_SDA_I => I_SDA_I,
O_SDA_O => O_SDA_O,
O_SDA_T => O_SDA_T,
I_SCL_I => I_SCL_I,
O_SCL_O => O_SCL_O,
O_SCL_T => O_SCL_T,
I2C_RDY => i2c_rdy, -- i2c ready
I2C_ACT => i2c_act, -- i2c cycle active
ACK_ERR => ack_err -- i2c(ack) error
);
CONTINUE <= '0';
word_addr <= new_adr;
dev_addr <= new_da;
we_i2c <= new_wr;
wr_i2c <= new_op;
dat_in <= new_dat;
ap_en <= new_apen;
I2C_BUSY_RG: process (RST, CLK)
begin
if RST = '1' then
i2c_busy <= '0';
elsif rising_edge(CLK) then
if i2c_act_fall = '1' then
i2c_busy <= '0';
elsif new_wr = '1' then
i2c_busy <= '1';
end if;
i2c_act_rg <= i2c_act;
i2c_act_fall <= i2c_act_rg and not i2c_act;
end if;
end process;
process(CLK, RST)
begin
if (RST = '1') then
i2c_mux_access_ok_r <= '0';
si5341_access_ok_r <= '0';
si5341_config_done_r <= '0';
si5341_config_error_r <= '0';
cur_addr <= 0;
state_r <= IDLE;
elsif (rising_edge(CLK)) then
if inc_adr = '1' then
cur_addr <= cur_addr + 1;
end if;
case state_r is
when IDLE => --0
new_adr <= si5341_addr_l;
new_dat <= X"55"; -- selects SC0/SD0 from I2C Mux U22 on ZCU208
new_op <= '0';
inc_adr <= '0';
if (START = '1') then
new_da <= "1101010"; -- 6Ah - Si5332 Access
new_apen <= '1';
new_wr <= '0';
i2c_mux_access_ok_r <= '1';
state_r <= SI5341_NEW;
else
new_wr <= '0';
state_r <= IDLE;
end if;
when SI5341_NEW => --3
new_adr <= si5341_addr_l;
new_dat <= si5341_data;
new_op <= '0';
new_wr <= '0';
inc_adr <= '0';
if (cur_addr = si5341_size) then
state_r <= FINISH;
else
state_r <= SI5341_NEW_WR;
end if;
-- Write Register Value
when SI5341_NEW_WR => --5
new_adr <= si5341_addr_l;
new_dat <= si5341_data;
new_op <= '0';
inc_adr <= '0';
if (i2c_busy = '0') then
if (ack_err = '1') then
state_r <= ERROR;
new_wr <= '0';
else
si5341_access_ok_r <= '1';
new_wr <= '1';
state_r <= SI5341_NEW_INC;
end if;
else
new_wr <= '0';
state_r <= SI5341_NEW_WR;
end if;
-- Increment Counter
when SI5341_NEW_INC => --6
new_adr <= si5341_addr_l;
new_dat <= si5341_data;
new_op <= '0';
new_wr <= '0';
if (i2c_busy = '0') then
if ack_err = '1' then
inc_adr <= '0';
state_r <= ERROR;
else
inc_adr <= '1';
state_r <= SI5341_NEW;
end if;
else
inc_adr <= '0';
state_r <= SI5341_NEW_INC;
end if;
when FINISH => --8
new_adr <= X"00";
new_dat <= X"00";
new_op <= '0';
new_wr <= '0';
inc_adr <= '0';
si5341_config_done_r <= '1';
state_r <= FINISH;
when ERROR => --9
new_adr <= X"00";
new_dat <= X"00";
new_op <= '0';
new_wr <= '0';
inc_adr <= '0';
si5341_config_error_r <= '1';
state_r <= ERROR;
when others => --f
new_adr <= X"00";
new_dat <= X"00";
new_op <= '0';
new_wr <= '0';
inc_adr <= '0';
state_r <= IDLE;
end case;
end if;
end process;
end si5341_gen_cfg_arch;
ip_repo/Si5332/src/vio_3/vio_3.xci
+1638
View File
File diff suppressed because it is too large Load Diff