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Added DDS Interface

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nsantana
2026-06-29 13:23:36 -04:00
parent 9c752152e5
commit 293d03c178
36 changed files with 38033 additions and 2371 deletions
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source/axis_mux_256b.vhd
+59
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@@ -0,0 +1,59 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_mux_256b is
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic_vector(1 downto 0);
s0_axis_tdata : in std_logic_vector(255 downto 0);
s0_axis_tvalid : in std_logic;
s0_axis_tready : out std_logic;
s1_axis_tdata : in std_logic_vector(255 downto 0);
s1_axis_tvalid : in std_logic;
s1_axis_tready : out std_logic;
s2_axis_tdata : in std_logic_vector(255 downto 0);
s2_axis_tvalid : in std_logic;
s2_axis_tready : out std_logic;
m_axis_tdata : out std_logic_vector(255 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic
);
end entity axis_mux_256b;
architecture imp of axis_mux_256b is
begin
m_axis_tdata <= s0_axis_tdata when aselect = "00" else
s1_axis_tdata when aselect = "01" else
s2_axis_tdata;
m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else
s1_axis_tvalid when aselect = "01" else
s2_axis_tvalid when aselect = "10" else
'0';
s0_axis_tready <= m_axis_tready when aselect = "00" else '0';
s1_axis_tready <= m_axis_tready when aselect = "01" else '0';
s2_axis_tready <= m_axis_tready when aselect = "10" else '0';
end imp;
source/axis_mux_512b.vhd
+49
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@@ -0,0 +1,49 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_mux_512b is
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic;
s0_axis_tdata : in std_logic_vector(511 downto 0);
s0_axis_tvalid : in std_logic;
s0_axis_tready : out std_logic;
s1_axis_tdata : in std_logic_vector(511 downto 0);
s1_axis_tvalid : in std_logic;
s1_axis_tready : out std_logic;
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic
);
end entity axis_mux_512b;
architecture imp of axis_mux_512b is
begin
m_axis_tdata <= s0_axis_tdata when aselect = '0' else
s1_axis_tdata;
m_axis_tvalid <= s0_axis_tvalid when aselect = '0' else
s1_axis_tvalid;
s0_axis_tready <= m_axis_tready when aselect = '0' else '0';
s1_axis_tready <= m_axis_tready when aselect = '1' else '0';
end imp;
source/axis_mux_chan_sel.vhd
+16 -16
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@@ -16,13 +16,13 @@ entity axis_mux_chan_sel is
port (
aselect_in : in std_logic_vector( 1 downto 0);
cmac_0_tdata_in : in std_logic_vector(127 downto 0);
cmac_0_tvalid_in : in std_logic;
cmac_0_tready_out : out std_logic;
chan_0_tdata_in : in std_logic_vector(127 downto 0);
chan_0_tvalid_in : in std_logic;
chan_0_tready_out : out std_logic;
cmac_4_tdata_in : in std_logic_vector(127 downto 0);
cmac_4_tvalid_in : in std_logic;
cmac_4_tready_out : out std_logic;
chan_1_tdata_in : in std_logic_vector(127 downto 0);
chan_1_tvalid_in : in std_logic;
chan_1_tready_out : out std_logic;
m_axis_tdata_out : out std_logic_vector(255 downto 0);
m_axis_tvalid_out : out std_logic;
@@ -35,21 +35,21 @@ architecture imp of axis_mux_chan_sel is
begin
-- adc_chan1_s3 adc_chan0_s3 adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
m_axis_tdata_out <= cmac_4_tdata_in(127 downto 96) & cmac_0_tdata_in(127 downto 96) & cmac_4_tdata_in(95 downto 64) & cmac_0_tdata_in(95 downto 64) & cmac_4_tdata_in(63 downto 32) & cmac_0_tdata_in(63 downto 32) & cmac_4_tdata_in(31 downto 0) & cmac_0_tdata_in(31 downto 0) when aselect_in = "00" else
x"FFFF_0000" & cmac_0_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_0_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_0_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_0_tdata_in(31 downto 0) when aselect_in = "01" else
cmac_4_tdata_in(127 downto 96) & x"FFFF_0000" & cmac_4_tdata_in(95 downto 64) & x"FFFF_0000" & cmac_4_tdata_in(63 downto 32) & x"FFFF_0000" & cmac_4_tdata_in(31 downto 0) & x"FFFF_0000";
m_axis_tdata_out <= chan_1_tdata_in(127 downto 96) & chan_0_tdata_in(127 downto 96) & chan_1_tdata_in(95 downto 64) & chan_0_tdata_in(95 downto 64) & chan_1_tdata_in(63 downto 32) & chan_0_tdata_in(63 downto 32) & chan_1_tdata_in(31 downto 0) & chan_0_tdata_in(31 downto 0) when aselect_in = "00" else
x"FFFF_0000" & chan_0_tdata_in(127 downto 96) & x"FFFF_0000" & chan_0_tdata_in(95 downto 64) & x"FFFF_0000" & chan_0_tdata_in(63 downto 32) & x"FFFF_0000" & chan_0_tdata_in(31 downto 0) when aselect_in = "01" else
chan_1_tdata_in(127 downto 96) & x"FFFF_0000" & chan_1_tdata_in(95 downto 64) & x"FFFF_0000" & chan_1_tdata_in(63 downto 32) & x"FFFF_0000" & chan_1_tdata_in(31 downto 0) & x"FFFF_0000";
m_axis_tvalid_out <= cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
cmac_0_tvalid_in when aselect_in = "01" else
cmac_4_tvalid_in when aselect_in = "10" else
m_axis_tvalid_out <= chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
chan_0_tvalid_in when aselect_in = "01" else
chan_1_tvalid_in when aselect_in = "10" else
'0';
cmac_0_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
m_axis_tready_in and cmac_0_tvalid_in when aselect_in = "01" else '0';
chan_0_tready_out <= m_axis_tready_in and chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
m_axis_tready_in and chan_0_tvalid_in when aselect_in = "01" else '0';
cmac_4_tready_out <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else
m_axis_tready_in and cmac_4_tvalid_in when aselect_in = "10" else '0';
chan_1_tready_out <= m_axis_tready_in and chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
m_axis_tready_in and chan_1_tvalid_in when aselect_in = "10" else '0';
end imp;
source/system_raw_eth_top.v
+365 -118
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@@ -36,7 +36,7 @@
`timescale 1ns/100ps
module system_raw_eth_top #(
parameter FPGA_REVISION_DATE = 32'h06122026,
parameter FPGA_REVISION_DATE = 32'h06272026,
parameter MINOR_REV = 8'h01,
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
@@ -369,6 +369,46 @@ module system_raw_eth_top #(
wire [3:0] M13_AXI_0_wstrb;
wire M13_AXI_0_wvalid;
wire [31:0] M14_AXI_0_araddr;
wire [2:0] M14_AXI_0_arprot;
wire M14_AXI_0_arready;
wire M14_AXI_0_arvalid;
wire [31:0] M14_AXI_0_awaddr;
wire [2:0] M14_AXI_0_awprot;
wire M14_AXI_0_awready;
wire M14_AXI_0_awvalid;
wire M14_AXI_0_bready;
wire [1:0] M14_AXI_0_bresp;
wire M14_AXI_0_bvalid;
wire [31:0] M14_AXI_0_rdata;
wire M14_AXI_0_rready;
wire [1:0] M14_AXI_0_rresp;
wire M14_AXI_0_rvalid;
wire [31:0] M14_AXI_0_wdata;
wire M14_AXI_0_wready;
wire [3:0] M14_AXI_0_wstrb;
wire M14_AXI_0_wvalid;
wire [31:0] M15_AXI_0_araddr;
wire [2:0] M15_AXI_0_arprot;
wire M15_AXI_0_arready;
wire M15_AXI_0_arvalid;
wire [31:0] M15_AXI_0_awaddr;
wire [2:0] M15_AXI_0_awprot;
wire M15_AXI_0_awready;
wire M15_AXI_0_awvalid;
wire M15_AXI_0_bready;
wire [1:0] M15_AXI_0_bresp;
wire M15_AXI_0_bvalid;
wire [31:0] M15_AXI_0_rdata;
wire M15_AXI_0_rready;
wire [1:0] M15_AXI_0_rresp;
wire M15_AXI_0_rvalid;
wire [31:0] M15_AXI_0_wdata;
wire M15_AXI_0_wready;
wire [3:0] M15_AXI_0_wstrb;
wire M15_AXI_0_wvalid;
wire sda_i;
wire sda_o;
wire sda_t;
@@ -396,10 +436,58 @@ module system_raw_eth_top #(
wire cmac_refclk_4_clk_n;
wire cmac_refclk_4_clk_p;
wire [127:0] adc_tdata_128b_chan0;
wire [127:0] adc_tdata_128b_chan1;
wire [127:0] adc_tdata_chan0_128b;
wire [127:0] adc_tdata_chan1_128b;
wire [1:0] cmac_2_dac_chan_sel;
wire [255:0] m0_dds_pulse_tdata_256b;
wire m0_dds_pulse_tvalid_256b;
wire m0_dds_pulse_tready_256b;
wire [127:0] m1_0_dds_pulse_tdata_128b;
wire m1_0_dds_pulse_tvalid_128b;
wire m1_0_dds_pulse_tready_128b;
wire [127:0] m1_1_dds_pulse_tdata_128b;
wire m1_1_dds_pulse_tvalid_128b;
wire m1_1_dds_pulse_tready_128b;
wire [255:0] dds_pulse_chan0_tdata_512b;
wire dds_pulse_chan0_tvalid_512b;
wire dds_pulse_chan0_tready_512b;
wire [255:0] dds_pulse_chan1_tdata_512b;
wire dds_pulse_chan1_tvalid_512b;
wire dds_pulse_chan1_tready_512b;
wire [511:0] dds2fiber_fifo_chan0_tdata_512b;
wire dds2fiber_fifo_chan0_tvalid_512b;
wire dds2fiber_fifo_chan0_tready_512b;
wire [511:0] dds2fiber_fifo_chan1_tdata_512b;
wire dds2fiber_fifo_chan1_tvalid_512b;
wire dds2fiber_fifo_chan1_tready_512b;
wire [511:0] adc_tdata_chan0_512b;
wire adc_tvalid_chan0_512b;
wire adc_tready_chan0_512b;
wire [511:0] adc_tdata_chan1_512b;
wire adc_tvalid_chan1_512b;
wire adc_tready_chan1_512b;
wire fiber_tx_src_data_sel;
wire [127:0] chan0_m0_dds_pulse_tdata_128b;
wire chan0_m0_dds_pulse_tvalid_128b;
wire chan0_m0_dds_pulse_tready_128b;
wire [127:0] chan1_m0_dds_pulse_tdata_128b;
wire chan1_m0_dds_pulse_tvalid_128b;
wire chan1_m0_dds_pulse_tready_128b;
wire dac_holdoff_ext;
////////////////////////////////////////////////////////////////
@@ -721,7 +809,47 @@ module system_raw_eth_top #(
.M13_AXI_0_wstrb (M13_AXI_0_wstrb),
.M13_AXI_0_wvalid (M13_AXI_0_wvalid),
.Res_0 (mxfe_rx_data_offload_s_axis_tready),
.M14_AXI_0_araddr (M14_AXI_0_araddr),
.M14_AXI_0_arprot (M14_AXI_0_arprot),
.M14_AXI_0_arready (M14_AXI_0_arready),
.M14_AXI_0_arvalid (M14_AXI_0_arvalid),
.M14_AXI_0_awaddr (M14_AXI_0_awaddr),
.M14_AXI_0_awprot (M14_AXI_0_awprot),
.M14_AXI_0_awready (M14_AXI_0_awready),
.M14_AXI_0_awvalid (M14_AXI_0_awvalid),
.M14_AXI_0_bready (M14_AXI_0_bready),
.M14_AXI_0_bresp (M14_AXI_0_bresp),
.M14_AXI_0_bvalid (M14_AXI_0_bvalid),
.M14_AXI_0_rdata (M14_AXI_0_rdata),
.M14_AXI_0_rready (M14_AXI_0_rready),
.M14_AXI_0_rresp (M14_AXI_0_rresp),
.M14_AXI_0_rvalid (M14_AXI_0_rvalid),
.M14_AXI_0_wdata (M14_AXI_0_wdata),
.M14_AXI_0_wready (M14_AXI_0_wready),
.M14_AXI_0_wstrb (M14_AXI_0_wstrb),
.M14_AXI_0_wvalid (M14_AXI_0_wvalid),
.M15_AXI_0_araddr (M15_AXI_0_araddr),
.M15_AXI_0_arprot (M15_AXI_0_arprot),
.M15_AXI_0_arready (M15_AXI_0_arready),
.M15_AXI_0_arvalid (M15_AXI_0_arvalid),
.M15_AXI_0_awaddr (M15_AXI_0_awaddr),
.M15_AXI_0_awprot (M15_AXI_0_awprot),
.M15_AXI_0_awready (M15_AXI_0_awready),
.M15_AXI_0_awvalid (M15_AXI_0_awvalid),
.M15_AXI_0_bready (M15_AXI_0_bready),
.M15_AXI_0_bresp (M15_AXI_0_bresp),
.M15_AXI_0_bvalid (M15_AXI_0_bvalid),
.M15_AXI_0_rdata (M15_AXI_0_rdata),
.M15_AXI_0_rready (M15_AXI_0_rready),
.M15_AXI_0_rresp (M15_AXI_0_rresp),
.M15_AXI_0_rvalid (M15_AXI_0_rvalid),
.M15_AXI_0_wdata (M15_AXI_0_wdata),
.M15_AXI_0_wready (M15_AXI_0_wready),
.M15_AXI_0_wstrb (M15_AXI_0_wstrb),
.M15_AXI_0_wvalid (M15_AXI_0_wvalid),
.Res_0 (mxfe_rx_data_offload_s_axis_tready),
.pl_clk1_clk250_out (clk_250),
.pl_clk1_clk250_aresetn_out (clk_250_aresetn),
@@ -737,29 +865,7 @@ module system_raw_eth_top #(
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
assign clk_100_areset = ~clk_100_aresetn;
// ila_5 i_ila_rx (
// .clk (rx_device_clk_1),
// .probe0 (adc_tdata_256b[15:0]), // 16
// .probe1 (adc_tdata_256b[31:16]), // 16
// .probe2 (adc_tdata_256b[47:32]), // 16
// .probe3 (adc_tdata_256b[63:48]), // 16
// .probe4 (adc_tdata_256b[79:64]), // 16
// .probe5 (adc_tdata_256b[95:80]), // 16
// .probe6 (adc_tdata_256b[111:96]), // 16
// .probe7 (adc_tdata_256b[127:112]), // 16
// .probe8 (adc_tdata_256b[143:128]), // 16
// .probe9 (adc_tdata_256b[159:144]), // 16
// .probe10 (adc_tdata_256b[175:160]), // 16
// .probe11 (adc_tdata_256b[191:176]), // 16
// .probe12 (adc_tdata_256b[207:192]), // 16
// .probe13 (adc_tdata_256b[223:208]), // 16
// .probe14 (adc_tdata_256b[239:224]), // 16
// .probe15 (adc_tdata_256b[255:240]), // 16
// .probe16 (adc_tvalid_256b), // 1
// .probe17 (adc_fifo_tready_256b) // 1
// );
///////////////////////////////////////////////////////////////////////////
qsfp_intfc_v1_1 #(
.FPGA_REVISION_DATE (FPGA_REVISION_DATE),
@@ -859,31 +965,11 @@ module system_raw_eth_top #(
//assign = slv_reg10[14:13];
//assign = slv_reg10[15];
assign cmac_2_dac_chan_sel = slv_reg10[17:16];
//assign = slv_reg10[30:18];
//assign = slv_reg10[23:18];
assign fiber_tx_src_data_sel = slv_reg10[24];
//assign = slv_reg10[30:25];
assign playback_path_data_enable_n = slv_reg10[31];
//ila_5 i_ila_rx (
// .clk (tx_device_clk_1),
// .probe0 (cmac_rx_tdata_256b[15:0]), // 16
// .probe1 (cmac_rx_tdata_256b[31:16]), // 16
// .probe2 (cmac_rx_tdata_256b[47:32]), // 16
// .probe3 (cmac_rx_tdata_256b[63:48]), // 16
// .probe4 (cmac_rx_tdata_256b[79:64]), // 16
// .probe5 (cmac_rx_tdata_256b[95:80]), // 16
// .probe6 (cmac_rx_tdata_256b[111:96]), // 16
// .probe7 (cmac_rx_tdata_256b[127:112]), // 16
// .probe8 (cmac_rx_tdata_256b[143:128]), // 16
// .probe9 (cmac_rx_tdata_256b[159:144]), // 16
// .probe10 (cmac_rx_tdata_256b[175:160]), // 16
// .probe11 (cmac_rx_tdata_256b[191:176]), // 16
// .probe12 (cmac_rx_tdata_256b[207:192]), // 16
// .probe13 (cmac_rx_tdata_256b[223:208]), // 16
// .probe14 (cmac_rx_tdata_256b[239:224]), // 16
// .probe15 (cmac_rx_tdata_256b[255:240]), // 16
// .probe16 (cmac_rx_tvalid_256b), // 1
// .probe17 (cmac_rx_tready_256b) // 1
// );
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
@@ -959,24 +1045,46 @@ module system_raw_eth_top #(
.s_axis_tready (cmac_0_tx_tready_512b) // out
);
assign adc_tdata_128b_chan0 = {adc_tdata_256b[223:192], adc_tdata_256b[159:128], adc_tdata_256b[95:64], adc_tdata_256b[31:0]}; // adc_chan0_s3, adc_chan0_s2, adc_chan0_s1, adc_chan0_s0
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign adc_tdata_chan0_128b = {adc_tdata_256b[223:192], adc_tdata_256b[159:128], adc_tdata_256b[95:64], adc_tdata_256b[31:0]}; // adc_chan0_s3, adc_chan0_s2, adc_chan0_s1, adc_chan0_s0
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_cmac_0 (
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_chan0 (
.aclk (rx_device_clk_1), // in
.aresetn (rx_device_clk_aresetn), // in
.s_axis_tdata (adc_tdata_128b_chan0), // in
.s_axis_tdata (adc_tdata_chan0_128b), // in
.s_axis_tvalid (adc_tvalid_256b), // in
.s_axis_tready ( ), // out
.m_axis_tdata (cmac_0_tx_tdata_512b), // out
.m_axis_tvalid (cmac_0_tx_tvalid_512b), // out
.m_axis_tready (cmac_0_tx_tready_512b_en) // in
.m_axis_tdata (adc_tdata_chan0_512b), // out
.m_axis_tvalid (adc_tvalid_chan0_512b), // out
.m_axis_tready (adc_tready_chan0_512b) // in
);
axis_mux_512b i_axis_mux_512b_chan0 (
.aclk (rx_device_clk_1), // input
.aresetn (rx_device_clk_aresetn), // input
.aselect (fiber_tx_src_data_sel), // input
.s0_axis_tdata (adc_tdata_chan0_512b), // input
.s0_axis_tvalid (adc_tvalid_chan0_512b), // input
.s0_axis_tready (adc_tready_chan0_512b), // output
.s1_axis_tdata (chan0_dds_pulse_fifo_tdata_512b), // input
.s1_axis_tvalid (chan0_dds_pulse_fifo_tvalid_512b), // input
.s1_axis_tready (chan0_dds_pulse_fifo_tready_512b), // output
.m_axis_tdata (cmac_0_tx_tdata_512b), // output
.m_axis_tvalid (cmac_0_tx_tvalid_512b), // output
.m_axis_tready (cmac_0_tx_tready_512b_en) // input
);
assign cmac_0_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0;
assign cmac_0_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0;
///////////
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign cmac_0_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0;
assign cmac_0_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0;
@@ -993,9 +1101,6 @@ module system_raw_eth_top #(
.m_axis_tready (cmac_0_rx_tready_128b) // in
);
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
@@ -1071,24 +1176,45 @@ module system_raw_eth_top #(
.s_axis_tready (cmac_4_tx_tready_512b) // out
);
assign adc_tdata_128b_chan1 = {adc_tdata_256b[255:224], adc_tdata_256b[191:160], adc_tdata_256b[127:96], adc_tdata_256b[63:32]}; // adc_chan1_s3, adc_chan1_s2, adc_chan1_s1, adc_chan1_s0
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign adc_tdata_chan1_128b = {adc_tdata_256b[255:224], adc_tdata_256b[191:160], adc_tdata_256b[127:96], adc_tdata_256b[63:32]}; // adc_chan1_s3, adc_chan1_s2, adc_chan1_s1, adc_chan1_s0
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_cmac4 (
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_chan1 (
.aclk (rx_device_clk_1), // in
.aresetn (rx_device_clk_aresetn), // in
.s_axis_tdata (adc_tdata_128b_chan1), // in
.s_axis_tdata (adc_tdata_chan1_128b), // in
.s_axis_tvalid (adc_tvalid_256b), // in
.s_axis_tready ( ), // out
.m_axis_tdata (cmac_4_tx_tdata_512b), // out
.m_axis_tvalid (cmac_4_tx_tvalid_512b), // out
.m_axis_tready (cmac_4_tx_tready_512b_en) // in
.m_axis_tdata (adc_tdata_chan1_512b), // out
.m_axis_tvalid (adc_tvalid_chan1_512b), // out
.m_axis_tready (adc_tready_chan1_512b) // in
);
axis_mux_512b i_axis_mux_512b_chan1 (
.aclk (rx_device_clk_1), // input
.aresetn (rx_device_clk_aresetn), // input
.aselect (fiber_tx_src_data_sel), // input
.s0_axis_tdata (adc_tdata_chan1_512b), // input
.s0_axis_tvalid (adc_tvalid_chan1_512b), // input
.s0_axis_tready (adc_tready_chan1_512b), // output
.s1_axis_tdata (chan1_dds_pulse_fifo_tdata_512b), // input
.s1_axis_tvalid (chan1_dds_pulse_fifo_tvalid_512b), // input
.s1_axis_tready (chan1_dds_pulse_fifo_tready_512b), // output
.m_axis_tdata (cmac_4_tx_tdata_512b), // output
.m_axis_tvalid (cmac_4_tx_tvalid_512b), // output
.m_axis_tready (cmac_4_tx_tready_512b_en) // input
);
assign cmac_4_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_4_tx_tvalid_512b : 1'b0;
assign cmac_4_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_4_tx_tready_512b : 1'b0;
///////////
//////////////////////////////////////////////////////////////
assign cmac_4_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_4_rx_tvalid_512b : 1'b0;
assign cmac_4_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_4_rx_tready_512b : 1'b0;
@@ -1107,66 +1233,42 @@ module system_raw_eth_top #(
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b, cmac_0_rx_tdata_128b};
// adc_chan1_s3 adc_chan0_s3 //adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
// assign cmac_rx_tdata_256b = {cmac_4_rx_tdata_128b[127:96], cmac_0_rx_tdata_128b[127:96], cmac_4_rx_tdata_128b[95:64], cmac_0_rx_tdata_128b[95:64], cmac_4_rx_tdata_128b[63:32], cmac_0_rx_tdata_128b[63:32], cmac_4_rx_tdata_128b[31:0], cmac_0_rx_tdata_128b[31:0]};
axis_mux_chan_sel i_axis_mux_chan_sel (
.aselect_in (cmac_2_dac_chan_sel),
.cmac_0_tdata_in (cmac_0_rx_tdata_128b), // in
.cmac_0_tvalid_in (cmac_0_rx_tvalid_128b), // in
.cmac_0_tready_out (cmac_0_rx_tready_128b), // out
.aselect_in (cmac_2_dac_chan_sel),
.cmac_4_tdata_in (cmac_4_rx_tdata_128b), // in
.cmac_4_tvalid_in (cmac_4_rx_tvalid_128b), // in
.cmac_4_tready_out (cmac_4_rx_tready_128b), // out
.chan_0_tdata_in (cmac_0_rx_tdata_128b), // in
.chan_0_tvalid_in (cmac_0_rx_tvalid_128b), // in
.chan_0_tready_out (cmac_0_rx_tready_128b), // out
.m_axis_tdata_out (cmac_rx_tdata_256b), // out
.m_axis_tvalid_out (cmac_rx_tvalid_256b), // out
.m_axis_tready_in (cmac_rx_tready_256b) // in
.chan_1_tdata_in (cmac_4_rx_tdata_128b), // in
.chan_1_tvalid_in (cmac_4_rx_tvalid_128b), // in
.chan_1_tready_out (cmac_4_rx_tready_128b), // out
.m_axis_tdata_out (cmac_rx_tdata_256b), // out
.m_axis_tvalid_out (cmac_rx_tvalid_256b), // out
.m_axis_tready_in (cmac_rx_tready_256b) // in
);
ila_5 i_ila_rx (
.clk (tx_device_clk_1),
.probe0 (cmac_rx_tdata_256b[15:0]), // 16
.probe1 (cmac_rx_tdata_256b[31:16]), // 16
.probe2 (cmac_rx_tdata_256b[47:32]), // 16
.probe3 (cmac_rx_tdata_256b[63:48]), // 16
.probe4 (cmac_rx_tdata_256b[79:64]), // 16
.probe5 (cmac_rx_tdata_256b[95:80]), // 16
.probe6 (cmac_rx_tdata_256b[111:96]), // 16
.probe7 (cmac_rx_tdata_256b[127:112]), // 16
.probe8 (cmac_rx_tdata_256b[143:128]), // 16
.probe9 (cmac_rx_tdata_256b[159:144]), // 16
.probe10 (cmac_rx_tdata_256b[175:160]), // 16
.probe11 (cmac_rx_tdata_256b[191:176]), // 16
.probe12 (cmac_rx_tdata_256b[207:192]), // 16
.probe13 (cmac_rx_tdata_256b[223:208]), // 16
.probe14 (cmac_rx_tdata_256b[239:224]), // 16
.probe15 (cmac_rx_tdata_256b[255:240]), // 16
.probe16 (cmac_rx_tvalid_256b), // 1
.probe17 (cmac_rx_tready_256b) // 1
);
axis_mux_256b i_dac_axis_mux_256b (
.aclk (tx_device_clk_1), // input
.aresetn (tx_device_clk_aresetn), // input
.aselect (dac_src_data_sel[0]), // input
.aclk (tx_device_clk_1), // input
.aresetn (tx_device_clk_aresetn), // input
.aselect (dac_src_data_sel), // input
.s0_axis_tdata (mem_xfer_tx_upload_tdata_256b), // input
.s0_axis_tvalid (mem_xfer_tx_upload_tvalid_256b), // input
.s0_axis_tready (mem_xfer_tx_upload_tready_256b), // output
.s0_axis_tdata (mem_xfer_tx_upload_tdata_256b), // input
.s0_axis_tvalid (mem_xfer_tx_upload_tvalid_256b), // input
.s0_axis_tready (mem_xfer_tx_upload_tready_256b), // output
.s1_axis_tdata (cmac_rx_tdata_256b), // input
.s1_axis_tvalid (cmac_rx_tvalid_256b), // input
.s1_axis_tready (cmac_rx_tready_256b), // output
.s1_axis_tdata (cmac_rx_tdata_256b), // input
.s1_axis_tvalid (cmac_rx_tvalid_256b), // input
.s1_axis_tready (cmac_rx_tready_256b), // output
.m_axis_tdata (dac_tdata_256b), // output
.m_axis_tvalid (dac_tvalid_256b), // output
.m_axis_tready (dac_tready_256b) // input
.s2_axis_tdata (m0_dds_pulse_tdata_256b), // input
.s2_axis_tvalid (m0_dds_pulse_tvalid_256b), // input
.s2_axis_tready (m0_dds_pulse_tready_256b), // output
.m_axis_tdata (dac_tdata_256b), // output
.m_axis_tvalid (dac_tvalid_256b), // output
.m_axis_tready (dac_tready_256b) // input
);
axis_register_slice_256b i_util_mxfe_upack_reg_slice_256b (
@@ -1248,6 +1350,151 @@ module system_raw_eth_top #(
cmac_4_tx_tvalid_512b_cnt_r <= cmac_4_tx_tvalid_512b_cnt_r + 1;
end
//////////////////////////
dds_pulse_intfc_v1_0 i_dds_pulse_intfc_v1_0_chan0 (
.m_axis_aclk_in (tx_device_clk_1),
.m_axis_aresetn_in (tx_device_clk_aresetn),
.m0_axis_tdata_out (chan0_m0_dds_pulse_tdata_128b), // out
.m0_axis_tvalid_out (chan0_m0_dds_pulse_tvalid_128b), // out
.m0_axis_tready_in (chan0_m0_dds_pulse_tready_128b), // in
.m1_axis_tdata_out (chan0_m1_dds_pulse_tdata_128b), // out
.m1_axis_tvalid_out (chan0_m1_dds_pulse_tvalid_128b), // out
.m1_axis_tready_in (chan0_m1_dds_pulse_tready_128b), // in
.dac_holdoff_ext_en_in (1'b0),
.dac_holdoff_ext_in (1'b0),
.dac_holdoff_ext_out (dac_holdoff_ext),
.s00_axi_aclk_in (clk_100),
.s00_axi_aresetn_in (clk_100_aresetn),
.s00_axi_awaddr (M14_AXI_0_awaddr[7:0]),
.s00_axi_awprot (M14_AXI_0_awprot),
.s00_axi_awvalid (M14_AXI_0_awvalid),
.s00_axi_awready (M14_AXI_0_awready),
.s00_axi_wdata (M14_AXI_0_wdata),
.s00_axi_wstrb (M14_AXI_0_wstrb),
.s00_axi_wvalid (M14_AXI_0_wvalid),
.s00_axi_wready (M14_AXI_0_wready),
.s00_axi_bresp (M14_AXI_0_bresp),
.s00_axi_bvalid (M14_AXI_0_bvalid),
.s00_axi_bready (M14_AXI_0_bready),
.s00_axi_araddr (M14_AXI_0_araddr[7:0]),
.s00_axi_arprot (M14_AXI_0_arprot),
.s00_axi_arvalid (M14_AXI_0_arvalid),
.s00_axi_arready (M14_AXI_0_arready),
.s00_axi_rdata (M14_AXI_0_rdata),
.s00_axi_rresp (M14_AXI_0_rresp),
.s00_axi_rvalid (M14_AXI_0_rvalid),
.s00_axi_rready (M14_AXI_0_rready)
);
//////////////////////////
dds_pulse_intfc_v1_0 i_dds_pulse_intfc_v1_0_chan1 (
.m_axis_aclk_in (tx_device_clk_1),
.m_axis_aresetn_in (tx_device_clk_aresetn),
.m0_axis_tdata_out (chan1_m0_dds_pulse_tdata_128b), // out
.m0_axis_tvalid_out (chan1_m0_dds_pulse_tvalid_128b), // out
.m0_axis_tready_in (chan1_m0_dds_pulse_tready_128b), // in
.m1_axis_tdata_out (chan1_m1_dds_pulse_tdata_128b), // out
.m1_axis_tvalid_out (chan1_m1_dds_pulse_tvalid_128b), // out
.m1_axis_tready_in (chan1_m1_dds_pulse_tready_128b), // in
.dac_holdoff_ext_en_in (1'b1),
.dac_holdoff_ext_in (dac_holdoff_ext),
.dac_holdoff_ext_out (),
.s00_axi_aclk_in (clk_100),
.s00_axi_aresetn_in (clk_100_aresetn),
.s00_axi_awaddr (M15_AXI_0_awaddr[7:0]),
.s00_axi_awprot (M15_AXI_0_awprot),
.s00_axi_awvalid (M15_AXI_0_awvalid),
.s00_axi_awready (M15_AXI_0_awready),
.s00_axi_wdata (M15_AXI_0_wdata),
.s00_axi_wstrb (M15_AXI_0_wstrb),
.s00_axi_wvalid (M15_AXI_0_wvalid),
.s00_axi_wready (M15_AXI_0_wready),
.s00_axi_bresp (M15_AXI_0_bresp),
.s00_axi_bvalid (M15_AXI_0_bvalid),
.s00_axi_bready (M15_AXI_0_bready),
.s00_axi_araddr (M15_AXI_0_araddr[7:0]),
.s00_axi_arprot (M15_AXI_0_arprot),
.s00_axi_arvalid (M15_AXI_0_arvalid),
.s00_axi_arready (M15_AXI_0_arready),
.s00_axi_rdata (M15_AXI_0_rdata),
.s00_axi_rresp (M15_AXI_0_rresp),
.s00_axi_rvalid (M15_AXI_0_rvalid),
.s00_axi_rready (M15_AXI_0_rready)
);
assign m0_dds_pulse_tdata_256b[255:224] = (chan1_m0_dds_pulse_tvalid_128b == 1'b1) ? chan1_m0_dds_pulse_tdata_128b[127:96] : 32'hFFFF0000; // adc_chan1_s3
assign m0_dds_pulse_tdata_256b[223:192] = (chan0_m0_dds_pulse_tvalid_128b == 1'b1) ? chan0_m0_dds_pulse_tdata_128b[127:96] : 32'hFFFF0000; // adc_chan0_s3
assign m0_dds_pulse_tdata_256b[191:160] = (chan1_m0_dds_pulse_tvalid_128b == 1'b1) ? chan1_m0_dds_pulse_tdata_128b[95:64] : 32'hFFFF0000; // adc_chan1_s2
assign m0_dds_pulse_tdata_256b[159:128] = (chan0_m0_dds_pulse_tvalid_128b == 1'b1) ? chan0_m0_dds_pulse_tdata_128b[95:64] : 32'hFFFF0000; // adc_chan0_s2
assign m0_dds_pulse_tdata_256b[127:96] = (chan1_m0_dds_pulse_tvalid_128b == 1'b1) ? chan1_m0_dds_pulse_tdata_128b[63:32] : 32'hFFFF0000; // adc_chan1_s1
assign m0_dds_pulse_tdata_256b[95:64] = (chan0_m0_dds_pulse_tvalid_128b == 1'b1) ? chan0_m0_dds_pulse_tdata_128b[63:32] : 32'hFFFF0000; // adc_chan0_s1
assign m0_dds_pulse_tdata_256b[63:32] = (chan1_m0_dds_pulse_tvalid_128b == 1'b1) ? chan1_m0_dds_pulse_tdata_128b[31:0] : 32'hFFFF0000; // adc_chan1_s0
assign m0_dds_pulse_tdata_256b[31:0] = (chan0_m0_dds_pulse_tvalid_128b == 1'b1) ? chan0_m0_dds_pulse_tdata_128b[31:0] : 32'hFFFF0000; // adc_chan0_s0
assign m0_dds_pulse_tvalid_256b = chan1_m0_dds_pulse_tvalid_128b || chan0_m0_dds_pulse_tvalid_128b;
assign chan0_m0_dds_pulse_tready_128b = m0_dds_pulse_tready_256b;
assign chan1_m0_dds_pulse_tready_128b = m0_dds_pulse_tready_256b;
/////////////////////////////////////////
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_dds_chan0 (
.aclk (tx_device_clk_1), // in
.aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (chan0_m1_dds_pulse_tdata_128b), // in
.s_axis_tvalid (chan0_m1_dds_pulse_tvalid_128b), // in
.s_axis_tready (chan0_m1_dds_pulse_tready_128b), // out
.m_axis_tdata (chan0_dds_pulse_tdata_512b), // out
.m_axis_tvalid (chan0_dds_pulse_tvalid_512b), // out
.m_axis_tready (chan0_dds_pulse_tready_512b) // in
);
axis_afifo_64x512 i_dds2fiber_fifo_chan0 (
.s_axis_aclk (tx_device_clk_1), // in
.s_axis_aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (chan0_dds_pulse_tdata_512b), // in
.s_axis_tvalid (chan0_dds_pulse_tvalid_512b), // in
.s_axis_tready (chan0_dds_pulse_tready_512b), // out
.m_axis_aclk (rx_device_clk_1), // in
.m_axis_tdata (chan0_dds_pulse_fifo_tdata_512b), // out
.m_axis_tvalid (chan0_dds_pulse_fifo_tvalid_512b), // out
.m_axis_tready (chan0_dds_pulse_fifo_tready_512b) // in
);
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b_dds_chan1 (
.aclk (tx_device_clk_1), // in
.aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (chan1_m1_dds_pulse_tdata_128b), // in
.s_axis_tvalid (chan1_m1_dds_pulse_tvalid_128b), // in
.s_axis_tready (chan1_m1_dds_pulse_tready_128b), // out
.m_axis_tdata (chan1_dds_pulse_tdata_512b), // out
.m_axis_tvalid (chan1_dds_pulse_tvalid_512b), // out
.m_axis_tready (chan1_dds_pulse_tready_512b) // in
);
axis_afifo_64x512 i_dds2fiber_fifo_chan1 (
.s_axis_aclk (tx_device_clk_1), // in
.s_axis_aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (chan1_dds_pulse_tdata_512b), // in
.s_axis_tvalid (chan1_dds_pulse_tvalid_512b), // in
.s_axis_tready (chan1_dds_pulse_tready_512b), // out
.m_axis_aclk (rx_device_clk_1), // in
.m_axis_tdata (chan1_dds_pulse_fifo_tdata_512b), // out
.m_axis_tvalid (chan1_dds_pulse_fifo_tvalid_512b), // out
.m_axis_tready (chan1_dds_pulse_fifo_tready_512b) // in
);
//////////////////////////
si5332_wrapper i_si5332_wrapper (
.clk_100_in (clk_100),