56 lines
3.0 KiB
VHDL
56 lines
3.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity axis_mux_chan_sel is
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port (
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aselect_in : in std_logic_vector( 1 downto 0);
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chan_0_tdata_in : in std_logic_vector(127 downto 0);
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chan_0_tvalid_in : in std_logic;
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chan_0_tready_out : out std_logic;
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chan_1_tdata_in : in std_logic_vector(127 downto 0);
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chan_1_tvalid_in : in std_logic;
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chan_1_tready_out : out std_logic;
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m_axis_tdata_out : out std_logic_vector(255 downto 0);
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m_axis_tvalid_out : out std_logic;
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m_axis_tready_in : in std_logic
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);
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end entity axis_mux_chan_sel;
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architecture imp of axis_mux_chan_sel is
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begin
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-- adc_chan1_s3 adc_chan0_s3 adc_chan1_s2 adc_chan0_s2 adc_chan1_s1 adc_chan0_s1 adc_chan1_s0 adc_chan0_s0
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m_axis_tdata_out <= chan_1_tdata_in(127 downto 96) & chan_0_tdata_in(127 downto 96) & chan_1_tdata_in(95 downto 64) & chan_0_tdata_in(95 downto 64) & chan_1_tdata_in(63 downto 32) & chan_0_tdata_in(63 downto 32) & chan_1_tdata_in(31 downto 0) & chan_0_tdata_in(31 downto 0) when aselect_in = "00" else
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x"FFFF_0000" & chan_0_tdata_in(127 downto 96) & x"FFFF_0000" & chan_0_tdata_in(95 downto 64) & x"FFFF_0000" & chan_0_tdata_in(63 downto 32) & x"FFFF_0000" & chan_0_tdata_in(31 downto 0) when aselect_in = "01" else
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chan_1_tdata_in(127 downto 96) & x"FFFF_0000" & chan_1_tdata_in(95 downto 64) & x"FFFF_0000" & chan_1_tdata_in(63 downto 32) & x"FFFF_0000" & chan_1_tdata_in(31 downto 0) & x"FFFF_0000";
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m_axis_tvalid_out <= chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
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chan_0_tvalid_in when aselect_in = "01" else
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chan_1_tvalid_in when aselect_in = "10" else
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'0';
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chan_0_tready_out <= m_axis_tready_in and chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
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m_axis_tready_in and chan_0_tvalid_in when aselect_in = "01" else '0';
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chan_1_tready_out <= m_axis_tready_in and chan_0_tvalid_in and chan_1_tvalid_in when aselect_in = "00" else
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m_axis_tready_in and chan_1_tvalid_in when aselect_in = "10" else '0';
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end imp;
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