216 lines
11 KiB
VHDL
216 lines
11 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity qsfp4_playback_intfc is
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port (
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rx_device_clk_in : in std_logic;
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rx_device_clk_aresetn_in : in std_logic;
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rx_tdata_256b_in : in std_logic_vector(255 downto 0);
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rx_tvalid_256b_in : in std_logic;
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rx_tready_256b_out : out std_logic;
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rx_tvalid_256b_cnt_out : out std_logic_vector( 31 downto 0);
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rx_tvalid_256b_en_cnt_out : out std_logic_vector( 31 downto 0);
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playback_data_path_enable_n_in : in std_logic;
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qsfp4_playback_aclk_in : in std_logic;
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qsfp4_playback_aresetn_in : in std_logic;
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qsfp4_playback_tdata_240b_out : out std_logic_vector(239 downto 0);
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qsfp4_playback_tvalid_240b_out : out std_logic;
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qsfp4_playback_tready_240b_in : in std_logic;
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qsfp4_playback_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
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cnt_reset_in : in std_logic
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);
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end entity qsfp4_playback_intfc;
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architecture arch_imp of qsfp4_playback_intfc is
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signal playback_data_path_enable_r : std_logic_vector(0 to 31) := (others => '0');
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signal rx_path_fifo_rst_n : std_logic;
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signal qsfp4_fifo_rst_n : std_logic;
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signal iq_512b_to_240b_rst_n : std_logic;
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signal playback_data_path_enable : std_logic;
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signal rx_tvalid_256b_en : std_logic;
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signal rx_tvalid_256b_en_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal rx_tvalid_256b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal rx_tready_256b : std_logic;
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signal rx_tdata_256b_pipe : std_logic_vector(255 downto 0);
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signal rx_tvalid_256b_pipe : std_logic;
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signal axis_dwidth_converter_tdata_256b_to_512b : std_logic_vector(511 downto 0);
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signal axis_dwidth_converter_tvalid_256b_to_512b : std_logic;
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signal axis_dwidth_converter_tready_256b_to_512b : std_logic;
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signal rx_tdata_512b_pipe : std_logic_vector(511 downto 0);
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signal rx_tvalid_512b_pipe : std_logic;
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signal rx_tready_512b_pipe : std_logic;
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signal iq_512b_to_240b_tdata : std_logic_vector(239 downto 0);
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signal iq_512b_to_240b_tvalid : std_logic;
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signal iq_512b_to_240b_tready : std_logic;
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signal rx_tready_240b : std_logic;
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signal rx_tdata_240b_pipe : std_logic_vector(239 downto 0);
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signal rx_tvalid_240b_pipe : std_logic;
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signal rx_fifo_tready_240b : std_logic;
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signal qsfp4_playback_tvalid_240b : std_logic;
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signal qsfp4_playback_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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begin
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qsfp4_playback_tvalid_240b_out <= qsfp4_playback_tvalid_240b;
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qsfp4_playback_tvalid_240b_cnt_out <= qsfp4_playback_tvalid_240b_cnt_r;
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rx_tvalid_256b_cnt_out <= rx_tvalid_256b_cnt_r;
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rx_tvalid_256b_en_cnt_out <= rx_tvalid_256b_en_cnt_r;
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rx_tready_256b_out <= rx_tready_256b;
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process(rx_device_clk_in, rx_device_clk_aresetn_in)
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begin
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if (rx_device_clk_aresetn_in = '0') then
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playback_data_path_enable_r <= (others => '0');
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elsif (rising_edge(rx_device_clk_in)) then
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if (playback_data_path_enable_n_in = '1') then
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playback_data_path_enable_r <= (others => '0');
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else
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playback_data_path_enable_r <= playback_data_path_enable_r(1 to 31) & '1';
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end if;
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end if;
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end process;
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rx_path_fifo_rst_n <= playback_data_path_enable_r(27);
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qsfp4_fifo_rst_n <= playback_data_path_enable_r(20);
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iq_512b_to_240b_rst_n <= playback_data_path_enable_r(16);
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playback_data_path_enable <= playback_data_path_enable_r(0);
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process(rx_device_clk_in)
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begin
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if (rising_edge(rx_device_clk_in)) then
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if (cnt_reset_in = '1') then
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rx_tvalid_256b_cnt_r <= (others => '0');
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elsif (rx_tvalid_256b_in = '1') then
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rx_tvalid_256b_cnt_r <= rx_tvalid_256b_cnt_r + 1;
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end if;
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end if;
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end process;
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rx_tvalid_256b_en <= rx_tvalid_256b_in when playback_data_path_enable = '1' else '0';
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i_rx_register_slice_256b : entity work.axis_register_slice_256b
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port map (
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aclk => rx_device_clk_in,
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aresetn => rx_path_fifo_rst_n,
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s_axis_tdata => rx_tdata_256b_in, -- in
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s_axis_tvalid => rx_tvalid_256b_en, -- in
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s_axis_tready => rx_tready_256b, -- out
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m_axis_tdata => rx_tdata_256b_pipe, -- out
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m_axis_tvalid => rx_tvalid_256b_pipe, -- out
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m_axis_tready => axis_dwidth_converter_tready_256b_to_512b -- in
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);
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-- i_ila_4 : entity work.ila_4
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-- port map (
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-- clk => rx_device_clk_in,
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-- probe0 => rx_tdata_256b_in, -- 128
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-- probe1 => rx_tvalid_256b_en, -- 1
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-- probe2 => rx_tready_256b, -- 1
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-- probe3 => rx_tvalid_256b_cnt_r -- 32
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-- );
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process(rx_device_clk_in)
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begin
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if (rising_edge(rx_device_clk_in)) then
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if (rx_path_fifo_rst_n = '0' or cnt_reset_in = '1') then
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rx_tvalid_256b_en_cnt_r <= (others => '0');
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elsif (rx_tvalid_256b_pipe = '1' and axis_dwidth_converter_tready_256b_to_512b = '1') then
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rx_tvalid_256b_en_cnt_r <= rx_tvalid_256b_en_cnt_r + 1;
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end if;
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end if;
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end process;
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i_axis_dwidth_converter_256b_to_512b : entity work.axis_dwidth_converter_256b_to_512b
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port map (
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aclk => rx_device_clk_in, -- in
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aresetn => rx_path_fifo_rst_n, -- in
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s_axis_tdata => rx_tdata_256b_pipe, -- in
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s_axis_tvalid => rx_tvalid_256b_pipe, -- in
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s_axis_tready => axis_dwidth_converter_tready_256b_to_512b, -- out
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m_axis_tdata => axis_dwidth_converter_tdata_256b_to_512b, -- out
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m_axis_tvalid => axis_dwidth_converter_tvalid_256b_to_512b, -- out
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m_axis_tready => rx_tready_512b_pipe -- in
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);
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i_qsfp4_reg_slice_512b : entity work.axis_register_slice_512b
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port map (
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aclk => rx_device_clk_in, -- in
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aresetn => rx_path_fifo_rst_n, -- in
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s_axis_tdata => axis_dwidth_converter_tdata_256b_to_512b, -- in
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s_axis_tvalid => axis_dwidth_converter_tvalid_256b_to_512b, -- in
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s_axis_tready => rx_tready_512b_pipe, -- out
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m_axis_tdata => rx_tdata_512b_pipe, -- out
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m_axis_tvalid => rx_tvalid_512b_pipe, -- out
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m_axis_tready => iq_512b_to_240b_tready -- in
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);
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i_iq_512b_to_240b : entity work.iq_512b_to_240b
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port map (
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aclk => rx_device_clk_in, -- in
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aresetn => iq_512b_to_240b_rst_n, -- in
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s_axis_tdata => rx_tdata_512b_pipe, -- in
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s_axis_tvalid => rx_tvalid_512b_pipe, -- in
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s_axis_tready => iq_512b_to_240b_tready, -- out
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m_axis_tdata => iq_512b_to_240b_tdata, -- out
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m_axis_tvalid => iq_512b_to_240b_tvalid, -- out
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m_axis_tready => rx_fifo_tready_240b --rx_tready_240b -- in
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);
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-- i_qsfp4_reg_slice_240b : entity work.axis_register_slice_240b
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-- port map (
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-- aclk => rx_device_clk_in, -- in
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-- aresetn => rx_path_fifo_rst_n, -- in
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-- s_axis_tdata => iq_512b_to_240b_tdata, -- in
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-- s_axis_tvalid => iq_512b_to_240b_tvalid, -- in
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-- s_axis_tready => rx_tready_240b, -- out
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-- m_axis_tdata => rx_tdata_240b_pipe, -- out
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-- m_axis_tvalid => rx_tvalid_240b_pipe, -- out
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-- m_axis_tready => rx_fifo_tready_240b -- in
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-- );
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-- this fifo is actually 32 words deep
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i_qsfp4_fifo : entity work.axis_data_fifo_32x240
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port map (
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s_axis_aclk => rx_device_clk_in, -- in
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s_axis_aresetn => qsfp4_fifo_rst_n, -- in
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s_axis_tdata => iq_512b_to_240b_tdata, --rx_tdata_240b_pipe, -- in
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s_axis_tvalid => iq_512b_to_240b_tvalid, --rx_tvalid_240b_pipe, -- in
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s_axis_tready => rx_fifo_tready_240b, -- out
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m_axis_aclk => qsfp4_playback_aclk_in, -- in
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m_axis_tdata => qsfp4_playback_tdata_240b_out, -- out
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m_axis_tvalid => qsfp4_playback_tvalid_240b, -- out
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m_axis_tready => qsfp4_playback_tready_240b_in -- in
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);
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process(qsfp4_playback_aclk_in)
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begin
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if (rising_edge(qsfp4_playback_aclk_in)) then
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if (qsfp4_fifo_rst_n = '0' or cnt_reset_in = '1') then
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qsfp4_playback_tvalid_240b_cnt_r <= (others => '0');
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elsif (qsfp4_playback_tvalid_240b = '1' and qsfp4_playback_tready_240b_in = '1') then
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qsfp4_playback_tvalid_240b_cnt_r <= qsfp4_playback_tvalid_240b_cnt_r + 1;
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end if;
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end if;
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end process;
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end architecture arch_imp;
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