moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,86 @@
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proc init { cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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set full_sbusif_list [list ]
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foreach busif $all_busif {
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if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
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set busif_param_list [list]
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set busif_name [get_property NAME $busif]
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if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
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continue
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}
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foreach tparam $axi_standard_param_list {
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lappend busif_param_list "C_${busif_name}_${tparam}"
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}
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bd::mark_propagate_only $cell_handle $busif_param_list
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}
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}
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}
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proc pre_propagate {cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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foreach busif $all_busif {
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if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
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continue
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}
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if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
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continue
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}
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set busif_name [get_property NAME $busif]
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foreach tparam $axi_standard_param_list {
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set busif_param_name "C_${busif_name}_${tparam}"
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set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
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set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
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if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
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if { $val_on_cell != "" } {
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set_property CONFIG.${tparam} $val_on_cell $busif
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}
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}
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}
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}
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}
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proc propagate {cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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foreach busif $all_busif {
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if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
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continue
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}
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if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
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continue
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}
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set busif_name [get_property NAME $busif]
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foreach tparam $axi_standard_param_list {
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set busif_param_name "C_${busif_name}_${tparam}"
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set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
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set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
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if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
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#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
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if { $val_on_cell_intf_pin != "" } {
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set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
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}
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}
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
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OPTION psf_version = 2.1;
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BEGIN DRIVER qsfp_intfc
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OPTION supported_peripherals = (qsfp_intfc);
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OPTION copyfiles = all;
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OPTION VERSION = 1.0;
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OPTION NAME = qsfp_intfc;
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END DRIVER
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@@ -0,0 +1,5 @@
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "qsfp_intfc" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
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}
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@@ -0,0 +1,26 @@
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COMPILER=
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ARCHIVER=
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CP=cp
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COMPILER_FLAGS=
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EXTRA_COMPILER_FLAGS=
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LIB=libxil.a
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RELEASEDIR=../../../lib
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INCLUDEDIR=../../../include
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INCLUDES=-I./. -I${INCLUDEDIR}
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INCLUDEFILES=*.h
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LIBSOURCES=*.c
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OUTS = *.o
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libs:
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echo "Compiling qsfp_intfc..."
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$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
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$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
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make clean
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include:
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${CP} $(INCLUDEFILES) $(INCLUDEDIR)
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clean:
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rm -rf ${OUTS}
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@@ -0,0 +1,6 @@
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/***************************** Include Files *******************************/
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#include "qsfp_intfc.h"
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/************************** Function Definitions ***************************/
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@@ -0,0 +1,107 @@
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#ifndef QSFP_INTFC_H
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#define QSFP_INTFC_H
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/****************** Include Files ********************/
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#include "xil_types.h"
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#include "xstatus.h"
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#define QSFP_INTFC_S00_AXI_SLV_REG0_OFFSET 0
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#define QSFP_INTFC_S00_AXI_SLV_REG1_OFFSET 4
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#define QSFP_INTFC_S00_AXI_SLV_REG2_OFFSET 8
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#define QSFP_INTFC_S00_AXI_SLV_REG3_OFFSET 12
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#define QSFP_INTFC_S00_AXI_SLV_REG4_OFFSET 16
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#define QSFP_INTFC_S00_AXI_SLV_REG5_OFFSET 20
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#define QSFP_INTFC_S00_AXI_SLV_REG6_OFFSET 24
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#define QSFP_INTFC_S00_AXI_SLV_REG7_OFFSET 28
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#define QSFP_INTFC_S00_AXI_SLV_REG8_OFFSET 32
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#define QSFP_INTFC_S00_AXI_SLV_REG9_OFFSET 36
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#define QSFP_INTFC_S00_AXI_SLV_REG10_OFFSET 40
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#define QSFP_INTFC_S00_AXI_SLV_REG11_OFFSET 44
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#define QSFP_INTFC_S00_AXI_SLV_REG12_OFFSET 48
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#define QSFP_INTFC_S00_AXI_SLV_REG13_OFFSET 52
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#define QSFP_INTFC_S00_AXI_SLV_REG14_OFFSET 56
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#define QSFP_INTFC_S00_AXI_SLV_REG15_OFFSET 60
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#define QSFP_INTFC_S00_AXI_SLV_REG16_OFFSET 64
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#define QSFP_INTFC_S00_AXI_SLV_REG17_OFFSET 68
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#define QSFP_INTFC_S00_AXI_SLV_REG18_OFFSET 72
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#define QSFP_INTFC_S00_AXI_SLV_REG19_OFFSET 76
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#define QSFP_INTFC_S00_AXI_SLV_REG20_OFFSET 80
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#define QSFP_INTFC_S00_AXI_SLV_REG21_OFFSET 84
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#define QSFP_INTFC_S00_AXI_SLV_REG22_OFFSET 88
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#define QSFP_INTFC_S00_AXI_SLV_REG23_OFFSET 92
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#define QSFP_INTFC_S00_AXI_SLV_REG24_OFFSET 96
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#define QSFP_INTFC_S00_AXI_SLV_REG25_OFFSET 100
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#define QSFP_INTFC_S00_AXI_SLV_REG26_OFFSET 104
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#define QSFP_INTFC_S00_AXI_SLV_REG27_OFFSET 108
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#define QSFP_INTFC_S00_AXI_SLV_REG28_OFFSET 112
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#define QSFP_INTFC_S00_AXI_SLV_REG29_OFFSET 116
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#define QSFP_INTFC_S00_AXI_SLV_REG30_OFFSET 120
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#define QSFP_INTFC_S00_AXI_SLV_REG31_OFFSET 124
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/**************************** Type Definitions *****************************/
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/**
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*
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* Write a value to a QSFP_INTFC register. A 32 bit write is performed.
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* If the component is implemented in a smaller width, only the least
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* significant data is written.
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*
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* @param BaseAddress is the base address of the QSFP_INTFCdevice.
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* @param RegOffset is the register offset from the base to write to.
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* @param Data is the data written to the register.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void QSFP_INTFC_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
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*
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*/
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#define QSFP_INTFC_mWriteReg(BaseAddress, RegOffset, Data) \
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Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
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/**
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*
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* Read a value from a QSFP_INTFC register. A 32 bit read is performed.
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* If the component is implemented in a smaller width, only the least
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* significant data is read from the register. The most significant data
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* will be read as 0.
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*
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* @param BaseAddress is the base address of the QSFP_INTFC device.
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* @param RegOffset is the register offset from the base to write to.
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*
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* @return Data is the data from the register.
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*
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* @note
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* C-style signature:
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* u32 QSFP_INTFC_mReadReg(u32 BaseAddress, unsigned RegOffset)
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*
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*/
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#define QSFP_INTFC_mReadReg(BaseAddress, RegOffset) \
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Xil_In32((BaseAddress) + (RegOffset))
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/************************** Function Prototypes ****************************/
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/**
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*
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* Run a self-test on the driver/device. Note this may be a destructive test if
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* resets of the device are performed.
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*
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* If the hardware system is not built correctly, this function may never
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* return to the caller.
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*
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* @param baseaddr_p is the base address of the QSFP_INTFC instance to be worked on.
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*
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* @return
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*
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* - XST_SUCCESS if all self-test code passed
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* - XST_FAILURE if any self-test code failed
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*
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* @note Caching must be turned off for this function to work.
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* @note Self test may fail if data memory and device are not on the same bus.
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*
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*/
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XStatus QSFP_INTFC_Reg_SelfTest(void * baseaddr_p);
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#endif // QSFP_INTFC_H
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@@ -0,0 +1,60 @@
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/***************************** Include Files *******************************/
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#include "qsfp_intfc.h"
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#include "xparameters.h"
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#include "stdio.h"
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#include "xil_io.h"
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/************************** Constant Definitions ***************************/
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#define READ_WRITE_MUL_FACTOR 0x10
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/************************** Function Definitions ***************************/
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/**
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*
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* Run a self-test on the driver/device. Note this may be a destructive test if
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* resets of the device are performed.
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*
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||||
* If the hardware system is not built correctly, this function may never
|
||||
* return to the caller.
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*
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* @param baseaddr_p is the base address of the QSFP_INTFCinstance to be worked on.
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*
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* @return
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||||
*
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* - XST_SUCCESS if all self-test code passed
|
||||
* - XST_FAILURE if any self-test code failed
|
||||
*
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||||
* @note Caching must be turned off for this function to work.
|
||||
* @note Self test may fail if data memory and device are not on the same bus.
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||||
*
|
||||
*/
|
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XStatus QSFP_INTFC_Reg_SelfTest(void * baseaddr_p)
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{
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u32 baseaddr;
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int write_loop_index;
|
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int read_loop_index;
|
||||
int Index;
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||||
|
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baseaddr = (u32) baseaddr_p;
|
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|
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xil_printf("******************************\n\r");
|
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xil_printf("* User Peripheral Self Test\n\r");
|
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xil_printf("******************************\n\n\r");
|
||||
|
||||
/*
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* Write to user logic slave module register(s) and read back
|
||||
*/
|
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xil_printf("User logic slave module test...\n\r");
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for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
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QSFP_INTFC_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
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||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
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||||
if ( QSFP_INTFC_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
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xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
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return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf(" - slave register write/read passed\n\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
proc create_ipi_design { offsetfile design_name } {
|
||||
create_bd_design $design_name
|
||||
open_bd_design $design_name
|
||||
|
||||
# Create Clock and Reset Ports
|
||||
set ACLK [ create_bd_port -dir I -type clk ACLK ]
|
||||
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
|
||||
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
|
||||
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
|
||||
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
|
||||
|
||||
# Create instance: qsfp_intfc_0, and set properties
|
||||
set qsfp_intfc_0 [ create_bd_cell -type ip -vlnv user.org:user:qsfp_intfc:1.0 qsfp_intfc_0]
|
||||
|
||||
# Create instance: master_0, and set properties
|
||||
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
|
||||
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins qsfp_intfc_0/S00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins qsfp_intfc_0/S00_AXI_ACLK]
|
||||
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins qsfp_intfc_0/S00_AXI_ARESETN]
|
||||
set_property target_simulator XSim [current_project]
|
||||
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
|
||||
|
||||
# Auto assign address
|
||||
assign_bd_address
|
||||
|
||||
# Copy all address to interface_address.vh file
|
||||
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
|
||||
upvar 1 $offsetfile offset_file
|
||||
set offset_file "${bd_path}/qsfp_intfc_v1_0_tb_include.svh"
|
||||
set fp [open $offset_file "w"]
|
||||
puts $fp "`ifndef qsfp_intfc_v1_0_tb_include_vh_"
|
||||
puts $fp "`define qsfp_intfc_v1_0_tb_include_vh_\n"
|
||||
puts $fp "//Configuration current bd names"
|
||||
puts $fp "`define BD_NAME ${design_name}"
|
||||
puts $fp "`define BD_INST_NAME ${design_name}_i"
|
||||
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
|
||||
puts $fp "//Configuration address parameters"
|
||||
|
||||
puts $fp "`endif"
|
||||
close $fp
|
||||
}
|
||||
|
||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:qsfp_intfc:1.0]]]]
|
||||
set test_bench_file ${ip_path}/example_designs/bfm_design/qsfp_intfc_v1_0_tb.sv
|
||||
set interface_address_vh_file ""
|
||||
|
||||
# Set IP Repository and Update IP Catalogue
|
||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
||||
update_ip_catalog
|
||||
}
|
||||
|
||||
set design_name ""
|
||||
set all_bd {}
|
||||
set all_bd_files [get_files *.bd -quiet]
|
||||
foreach file $all_bd_files {
|
||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
||||
lappend all_bd $bd_name
|
||||
}
|
||||
|
||||
for { set i 1 } { 1 } { incr i } {
|
||||
set design_name "qsfp_intfc_v1_0_bfm_${i}"
|
||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
create_ipi_design interface_address_vh_file ${design_name}
|
||||
validate_bd_design
|
||||
|
||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
||||
import_files -force -norecurse $wrapper_file
|
||||
|
||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
||||
import_files -fileset sim_1 -norecurse -force $test_bench_file
|
||||
remove_files -quiet -fileset sim_1 qsfp_intfc_v1_0_tb_include.vh
|
||||
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
|
||||
set_property top qsfp_intfc_v1_0_tb [get_filesets sim_1]
|
||||
set_property top_lib {} [get_filesets sim_1]
|
||||
set_property top_file {} [get_filesets sim_1]
|
||||
launch_simulation -simset sim_1 -mode behavioral
|
||||
@@ -0,0 +1,197 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
`include "qsfp_intfc_v1_0_tb_include.svh"
|
||||
|
||||
import axi_vip_pkg::*;
|
||||
import qsfp_intfc_v1_0_bfm_1_master_0_0_pkg::*;
|
||||
|
||||
module qsfp_intfc_v1_0_tb();
|
||||
|
||||
|
||||
xil_axi_uint error_cnt = 0;
|
||||
xil_axi_uint comparison_cnt = 0;
|
||||
axi_transaction wr_transaction;
|
||||
axi_transaction rd_transaction;
|
||||
axi_monitor_transaction mst_monitor_transaction;
|
||||
axi_monitor_transaction master_moniter_transaction_queue[$];
|
||||
xil_axi_uint master_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction mst_scb_transaction;
|
||||
axi_monitor_transaction passthrough_monitor_transaction;
|
||||
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
|
||||
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction passthrough_mst_scb_transaction;
|
||||
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
|
||||
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction passthrough_slv_scb_transaction;
|
||||
axi_monitor_transaction slv_monitor_transaction;
|
||||
axi_monitor_transaction slave_moniter_transaction_queue[$];
|
||||
xil_axi_uint slave_moniter_transaction_queue_size =0;
|
||||
axi_monitor_transaction slv_scb_transaction;
|
||||
xil_axi_uint mst_agent_verbosity = 0;
|
||||
xil_axi_uint slv_agent_verbosity = 0;
|
||||
xil_axi_uint passthrough_agent_verbosity = 0;
|
||||
bit clock;
|
||||
bit reset;
|
||||
integer result_slave;
|
||||
bit [31:0] S00_AXI_test_data[3:0];
|
||||
localparam LC_AXI_BURST_LENGTH = 8;
|
||||
localparam LC_AXI_DATA_WIDTH = 32;
|
||||
task automatic COMPARE_DATA;
|
||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
|
||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
|
||||
begin
|
||||
if (expected === 'hx || actual === 'hx) begin
|
||||
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
|
||||
result_slave = 0; $stop;
|
||||
end
|
||||
if (actual != expected) begin
|
||||
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
|
||||
result_slave = 0;
|
||||
$stop;
|
||||
end
|
||||
else
|
||||
begin
|
||||
$display("TESTBENCH Passed! Data expected is equal to actual.",
|
||||
" expected = 0x%h",expected, " actual = 0x%h",actual);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
integer i;
|
||||
integer j;
|
||||
xil_axi_uint trans_cnt_before_switch = 48;
|
||||
xil_axi_uint passthrough_cmd_switch_cnt = 0;
|
||||
event passthrough_mastermode_start_event;
|
||||
event passthrough_mastermode_end_event;
|
||||
event passthrough_slavemode_end_event;
|
||||
xil_axi_uint mtestID;
|
||||
xil_axi_ulong mtestADDR;
|
||||
xil_axi_len_t mtestBurstLength;
|
||||
xil_axi_size_t mtestDataSize;
|
||||
xil_axi_burst_t mtestBurstType;
|
||||
xil_axi_lock_t mtestLOCK;
|
||||
xil_axi_cache_t mtestCacheType = 0;
|
||||
xil_axi_prot_t mtestProtectionType = 3'b000;
|
||||
xil_axi_region_t mtestRegion = 4'b000;
|
||||
xil_axi_qos_t mtestQOS = 4'b000;
|
||||
xil_axi_data_beat dbeat;
|
||||
xil_axi_data_beat [255:0] mtestWUSER;
|
||||
xil_axi_data_beat mtestAWUSER = 'h0;
|
||||
xil_axi_data_beat mtestARUSER = 0;
|
||||
xil_axi_data_beat [255:0] mtestRUSER;
|
||||
xil_axi_uint mtestBUSER = 0;
|
||||
xil_axi_resp_t mtestBresp;
|
||||
xil_axi_resp_t[255:0] mtestRresp;
|
||||
bit [63:0] mtestWDataL;
|
||||
bit [63:0] mtestRDataL;
|
||||
axi_transaction pss_wr_transaction;
|
||||
axi_transaction pss_rd_transaction;
|
||||
axi_transaction reactive_transaction;
|
||||
axi_transaction rd_payload_transaction;
|
||||
axi_transaction wr_rand;
|
||||
axi_transaction rd_rand;
|
||||
axi_transaction wr_reactive;
|
||||
axi_transaction rd_reactive;
|
||||
axi_transaction wr_reactive2;
|
||||
axi_transaction rd_reactive2;
|
||||
axi_ready_gen bready_gen;
|
||||
axi_ready_gen rready_gen;
|
||||
axi_ready_gen awready_gen;
|
||||
axi_ready_gen wready_gen;
|
||||
axi_ready_gen arready_gen;
|
||||
axi_ready_gen bready_gen2;
|
||||
axi_ready_gen rready_gen2;
|
||||
axi_ready_gen awready_gen2;
|
||||
axi_ready_gen wready_gen2;
|
||||
axi_ready_gen arready_gen2;
|
||||
xil_axi_payload_byte data_mem[xil_axi_ulong];
|
||||
qsfp_intfc_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
|
||||
|
||||
`BD_WRAPPER DUT(
|
||||
.ARESETN(reset),
|
||||
.ACLK(clock)
|
||||
);
|
||||
|
||||
initial begin
|
||||
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
|
||||
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
|
||||
mst_agent_0.set_agent_tag("Master VIP");
|
||||
mst_agent_0.set_verbosity(mst_agent_verbosity);
|
||||
mst_agent_0.start_master();
|
||||
$timeformat (-12, 1, " ps", 1);
|
||||
end
|
||||
initial begin
|
||||
reset <= 1'b0;
|
||||
#200ns;
|
||||
reset <= 1'b1;
|
||||
repeat (5) @(negedge clock);
|
||||
end
|
||||
always #5 clock <= ~clock;
|
||||
initial begin
|
||||
S_AXI_TEST ( );
|
||||
|
||||
#1ns;
|
||||
$finish;
|
||||
end
|
||||
task automatic S_AXI_TEST;
|
||||
begin
|
||||
#1;
|
||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
|
||||
mtestID = 0;
|
||||
mtestADDR = 64'h00000000;
|
||||
mtestBurstLength = 0;
|
||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
||||
mtestCacheType = 0;
|
||||
mtestProtectionType = 0;
|
||||
mtestRegion = 0;
|
||||
mtestQOS = 0;
|
||||
result_slave = 1;
|
||||
mtestWDataL[31:0] = 32'h00000001;
|
||||
for(int i = 0; i < 4;i++) begin
|
||||
S00_AXI_test_data[i] <= mtestWDataL[31:0];
|
||||
mst_agent_0.AXI4LITE_WRITE_BURST(
|
||||
mtestADDR,
|
||||
mtestProtectionType,
|
||||
mtestWDataL,
|
||||
mtestBresp
|
||||
);
|
||||
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
|
||||
mtestADDR = mtestADDR + 64'h4;
|
||||
end
|
||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
|
||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
|
||||
mtestID = 0;
|
||||
mtestADDR = 64'h00000000;
|
||||
mtestBurstLength = 0;
|
||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
||||
mtestCacheType = 0;
|
||||
mtestProtectionType = 0;
|
||||
mtestRegion = 0;
|
||||
mtestQOS = 0;
|
||||
for(int i = 0; i < 4;i++) begin
|
||||
mst_agent_0.AXI4LITE_READ_BURST(
|
||||
mtestADDR,
|
||||
mtestProtectionType,
|
||||
mtestRDataL,
|
||||
mtestRresp
|
||||
);
|
||||
mtestADDR = mtestADDR + 64'h4;
|
||||
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
|
||||
end
|
||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
|
||||
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
|
||||
$display("---------------------------------------------------------");
|
||||
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
|
||||
if ( result_slave ) begin
|
||||
$display("PTGEN_TEST: PASSED!");
|
||||
end else begin
|
||||
$display("PTGEN_TEST: FAILED!");
|
||||
end
|
||||
$display("---------------------------------------------------------");
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
|
||||
proc create_ipi_design { offsetfile design_name } {
|
||||
|
||||
create_bd_design $design_name
|
||||
open_bd_design $design_name
|
||||
|
||||
# Create and configure Clock/Reset
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
|
||||
|
||||
#Constraints will be provided manually while pin planning.
|
||||
create_bd_port -dir I -type rst reset_rtl
|
||||
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
|
||||
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
|
||||
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
|
||||
set external_reset_port reset_rtl
|
||||
create_bd_port -dir I -type clk clock_rtl
|
||||
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
|
||||
set external_clock_port clock_rtl
|
||||
|
||||
#Avoid IPI DRC, make clock port synchronous to reset
|
||||
if { $external_clock_port ne "" && $external_reset_port ne "" } {
|
||||
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
|
||||
}
|
||||
|
||||
# Connect other sys_reset pins
|
||||
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
|
||||
|
||||
# Create instance: qsfp_intfc_0, and set properties
|
||||
set qsfp_intfc_0 [ create_bd_cell -type ip -vlnv user.org:user:qsfp_intfc:1.0 qsfp_intfc_0 ]
|
||||
|
||||
# Create instance: jtag_axi_0, and set properties
|
||||
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
|
||||
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
|
||||
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
# Create instance: axi_peri_interconnect, and set properties
|
||||
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
|
||||
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
|
||||
|
||||
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
# Connect all clock & reset of qsfp_intfc_0 slave interfaces..
|
||||
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins qsfp_intfc_0/S00_AXI]
|
||||
connect_bd_net [get_bd_pins qsfp_intfc_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
|
||||
connect_bd_net [get_bd_pins qsfp_intfc_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
||||
|
||||
|
||||
# Auto assign address
|
||||
assign_bd_address
|
||||
|
||||
# Copy all address to qsfp_intfc_v1_0_include.tcl file
|
||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
||||
upvar 1 $offsetfile offset_file
|
||||
set offset_file "${bd_path}/qsfp_intfc_v1_0_include.tcl"
|
||||
set fp [open $offset_file "w"]
|
||||
puts $fp "# Configuration address parameters"
|
||||
|
||||
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_qsfp_intfc_0_S00_AXI_* ]]
|
||||
puts $fp "set s00_axi_addr ${offset}"
|
||||
|
||||
close $fp
|
||||
}
|
||||
|
||||
# Set IP Repository and Update IP Catalogue
|
||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:qsfp_intfc:1.0]]]]
|
||||
set hw_test_file ${ip_path}/example_designs/debug_hw_design/qsfp_intfc_v1_0_hw_test.tcl
|
||||
|
||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
||||
update_ip_catalog
|
||||
}
|
||||
|
||||
set design_name ""
|
||||
set all_bd {}
|
||||
set all_bd_files [get_files *.bd -quiet]
|
||||
foreach file $all_bd_files {
|
||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
||||
lappend all_bd $bd_name
|
||||
}
|
||||
|
||||
for { set i 1 } { 1 } { incr i } {
|
||||
set design_name "qsfp_intfc_v1_0_hw_${i}"
|
||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
||||
break
|
||||
}
|
||||
}
|
||||
|
||||
set intf_address_include_file ""
|
||||
create_ipi_design intf_address_include_file ${design_name}
|
||||
save_bd_design
|
||||
validate_bd_design
|
||||
|
||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
||||
import_files -force -norecurse $wrapper_file
|
||||
|
||||
puts "-------------------------------------------------------------------------------------------------"
|
||||
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
|
||||
puts " please perform following steps to test design in targeted board."
|
||||
puts "1. Generate bitstream"
|
||||
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
|
||||
puts "3. Download generated bitstream"
|
||||
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
|
||||
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
|
||||
puts " : source -notrace ${hw_test_file}"
|
||||
puts "-------------------------------------------------------------------------------------------------"
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
# Runtime Tcl commands to interact with - qsfp_intfc_v1_0
|
||||
|
||||
# Sourcing design address info tcl
|
||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
||||
source ${bd_path}/qsfp_intfc_v1_0_include.tcl
|
||||
|
||||
# jtag axi master interface hardware name, change as per your design.
|
||||
set jtag_axi_master hw_axi_1
|
||||
set ec 0
|
||||
|
||||
# hw test script
|
||||
# Delete all previous axis transactions
|
||||
if { [llength [get_hw_axi_txns -quiet]] } {
|
||||
delete_hw_axi_txn [get_hw_axi_txns -quiet]
|
||||
}
|
||||
|
||||
|
||||
# Test all lite slaves.
|
||||
set wdata_1 abcd1234
|
||||
|
||||
# Test: S00_AXI
|
||||
# Create a write transaction at s00_axi_addr address
|
||||
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
|
||||
# Create a read transaction at s00_axi_addr address
|
||||
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
|
||||
# Initiate transactions
|
||||
run_hw_axi r_s00_axi_addr
|
||||
run_hw_axi w_s00_axi_addr
|
||||
run_hw_axi r_s00_axi_addr
|
||||
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
|
||||
# Compare read data
|
||||
if { $rdata_tmp == $wdata_1 } {
|
||||
puts "Data comparison test pass for - S00_AXI"
|
||||
} else {
|
||||
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
|
||||
inc ec
|
||||
}
|
||||
|
||||
# Check error flag
|
||||
if { $ec == 0 } {
|
||||
puts "PTGEN_TEST: PASSED!"
|
||||
} else {
|
||||
puts "PTGEN_TEST: FAILED!"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,240 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_unsigned.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity qsfp_init_fsm is
|
||||
port(
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_aresetn_in : in std_logic;
|
||||
|
||||
mode_50g_40g_n_in : in std_logic;
|
||||
qsfp1_reset_n_in : in std_logic;
|
||||
qsfp4_reset_n_in : in std_logic;
|
||||
|
||||
cmd_strb_out : out std_logic;
|
||||
cmd_addr_out : out std_logic_vector(11 downto 0);
|
||||
cmd_write_out : out std_logic;
|
||||
cmd_sel_out : out std_logic_vector( 2 downto 0);
|
||||
cmd_wdata_out : out std_logic_vector(31 downto 0);
|
||||
cmd_ready_in : in std_logic;
|
||||
fsm_running_out : out std_logic
|
||||
);
|
||||
end entity qsfp_init_fsm;
|
||||
|
||||
architecture imp of qsfp_init_fsm is
|
||||
|
||||
type fsm_state is (IDLE, QSFP1_INIT_WAIT, QSFP1_INIT, QSFP4_INIT_WAIT, QSFP4_INIT, DONE, ERROR);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
signal qsfp1_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp1_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp4_reset_n : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_b : std_logic_vector(0 to 0);
|
||||
signal qsfp4_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
|
||||
|
||||
signal qsfp1_reset_r : std_logic := '0';
|
||||
|
||||
signal qsfp4_reset_r : std_logic := '0';
|
||||
|
||||
signal cmd_addr_r : std_logic_vector (11 downto 0) := (others => '0');
|
||||
signal cmd_sel_r : std_logic_vector ( 2 downto 0) := (others => '0');
|
||||
signal cmd_strb_r : std_logic := '0';
|
||||
signal cmd_wdata_r : std_logic_vector (31 downto 0) := (others => '0');
|
||||
signal cmd_write_r : std_logic := '0';
|
||||
|
||||
signal fsm_running_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
cmd_strb_out <= cmd_strb_r;
|
||||
cmd_addr_out <= cmd_addr_r;
|
||||
cmd_write_out <= cmd_write_r;
|
||||
cmd_sel_out <= cmd_sel_r;
|
||||
cmd_wdata_out <= cmd_wdata_r;
|
||||
fsm_running_out <= fsm_running_r;
|
||||
|
||||
--
|
||||
qsfp1_reset_n(0) <= qsfp1_reset_n_in;
|
||||
|
||||
i_cdc_qsfp1_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp1_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp1_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp1_reset_n_r <= qsfp1_reset_n_r(1 to 31) & qsfp1_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
qsfp4_reset_n(0) <= qsfp4_reset_n_in;
|
||||
|
||||
i_cdc_qsfp4_reset_n : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 1 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => qsfp4_reset_b,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => qsfp4_reset_n
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
qsfp4_reset_n_r <= qsfp4_reset_n_r(1 to 31) & qsfp4_reset_b(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (clk_125_aresetn_in = '0') then
|
||||
qsfp1_reset_r <= '0';
|
||||
qsfp4_reset_r <= '0';
|
||||
|
||||
cmd_sel_r <= (others => '0');
|
||||
cmd_addr_r <= (others => '0');
|
||||
cmd_wdata_r <= (others => '0');
|
||||
cmd_write_r <= '0';
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
state_cnt_r <= 0;
|
||||
state_r <= IDLE;
|
||||
elsif (rising_edge(clk_125_in)) then
|
||||
cmd_strb_r <= '0';
|
||||
|
||||
if (qsfp1_reset_n_r(1) = '1' and qsfp1_reset_n_r(0) = '0') then
|
||||
qsfp1_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
if (qsfp4_reset_n_r(1) = '1' and qsfp4_reset_n_r(0) = '0') then
|
||||
qsfp4_reset_r <= '1';
|
||||
end if;
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (qsfp1_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "000";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
elsif (qsfp4_reset_r = '1') then
|
||||
fsm_running_r <= '1';
|
||||
cmd_sel_r <= "001";
|
||||
cmd_addr_r <= x"001";
|
||||
if (mode_50g_40g_n_in = '1') then
|
||||
cmd_wdata_r <= x"0000_0001";
|
||||
else
|
||||
cmd_wdata_r <= x"0000_0011";
|
||||
end if;
|
||||
cmd_write_r <= '1';
|
||||
cmd_strb_r <= '1';
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
else
|
||||
fsm_running_r <= '0';
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP1_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP1_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP1_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp1_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP1_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT_WAIT =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_cnt_r <= 0;
|
||||
state_r <= QSFP4_INIT;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= QSFP4_INIT_WAIT;
|
||||
end if;
|
||||
|
||||
when QSFP4_INIT =>
|
||||
if (state_cnt_r = 32) then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= ERROR;
|
||||
else
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
if (cmd_ready_in = '1') then
|
||||
qsfp4_reset_r <= '0';
|
||||
state_r <= DONE;
|
||||
else
|
||||
state_r <= QSFP4_INIT;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when ERROR =>
|
||||
cmd_write_r <= '0';
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,933 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
--use ieee.numeric_std.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
entity qsfp_intfc_v1_0 is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0603_2024";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXI
|
||||
C_S00_AXI_DATA_WIDTH : integer := 32;
|
||||
C_S00_AXI_ADDR_WIDTH : integer := 7
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
clk_125_in : in std_logic;
|
||||
clk_125_reset_n_in : in std_logic;
|
||||
|
||||
clk_250_in : in std_logic;
|
||||
clk_250_reset_n_in : in std_logic;
|
||||
|
||||
rx_device_clk_in : in std_logic;
|
||||
tx_device_clk_in : in std_logic;
|
||||
|
||||
clkin8_in : in std_logic;
|
||||
-- sysref_in : in std_logic;
|
||||
ref_clk_div2_in : in std_logic;
|
||||
qsfp2_clk_in : in std_logic;
|
||||
qsfp3_clk_in : in std_logic;
|
||||
pl_clk3_0 : in std_logic;
|
||||
|
||||
QSFP1_SI570_CLOCK_P : in std_logic;
|
||||
QSFP1_SI570_CLOCK_N : in std_logic;
|
||||
QSFP1_TX1_P : out std_logic;
|
||||
QSFP1_TX1_N : out std_logic;
|
||||
QSFP1_RX1_P : in std_logic;
|
||||
QSFP1_RX1_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX2_P : out std_logic;
|
||||
QSFP1_TX2_N : out std_logic;
|
||||
QSFP1_RX2_P : in std_logic;
|
||||
QSFP1_RX2_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX3_P : out std_logic;
|
||||
QSFP1_TX3_N : out std_logic;
|
||||
QSFP1_RX3_P : in std_logic;
|
||||
QSFP1_RX3_N : in std_logic;
|
||||
--
|
||||
QSFP1_TX4_P : out std_logic;
|
||||
QSFP1_TX4_N : out std_logic;
|
||||
QSFP1_RX4_P : in std_logic;
|
||||
QSFP1_RX4_N : in std_logic;
|
||||
|
||||
QSFP1_RESETL_LS : out std_logic;
|
||||
QSFP1_MODPRSL_LS : in std_logic;
|
||||
QSFP1_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP4_SI570_CLOCK_P : in std_logic;
|
||||
QSFP4_SI570_CLOCK_N : in std_logic;
|
||||
QSFP4_TX1_P : out std_logic;
|
||||
QSFP4_TX1_N : out std_logic;
|
||||
QSFP4_RX1_P : in std_logic;
|
||||
QSFP4_RX1_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX2_P : out std_logic;
|
||||
QSFP4_TX2_N : out std_logic;
|
||||
QSFP4_RX2_P : in std_logic;
|
||||
QSFP4_RX2_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX3_P : out std_logic;
|
||||
QSFP4_TX3_N : out std_logic;
|
||||
QSFP4_RX3_P : in std_logic;
|
||||
QSFP4_RX3_N : in std_logic;
|
||||
--
|
||||
QSFP4_TX4_P : out std_logic;
|
||||
QSFP4_TX4_N : out std_logic;
|
||||
QSFP4_RX4_P : in std_logic;
|
||||
QSFP4_RX4_N : in std_logic;
|
||||
|
||||
QSFP4_RESETL_LS : out std_logic;
|
||||
QSFP4_MODPRSL_LS : in std_logic;
|
||||
QSFP4_INTL_LS : in std_logic;
|
||||
|
||||
qsfp1_capture_aclk_out : out std_logic;
|
||||
qsfp1_capture_aresetn_out : out std_logic;
|
||||
qsfp1_capture_tdata_240b_out : out std_logic_vector(239 downto 0);
|
||||
qsfp1_capture_tvalid_240b_out : out std_logic;
|
||||
qsfp1_capture_rx_data_ready_in : in std_logic;
|
||||
|
||||
qsfp4_playback_aclk_out : out std_logic;
|
||||
qsfp4_playback_aresetn_out : out std_logic;
|
||||
qsfp4_playback_tdata_240b_in : in std_logic_vector(239 downto 0);
|
||||
qsfp4_playback_tvalid_240b_in : in std_logic;
|
||||
qsfp4_playback_tready_240b_out : out std_logic;
|
||||
|
||||
qsfp1_capture_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_overflow_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_fifo_aempty_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0);
|
||||
tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
adc_rx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp4_playback_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cnt_reset_out : out std_logic;
|
||||
|
||||
slv_reg9_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg21_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg22_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg23_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg24_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg25_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg26_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg27_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg28_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg29_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg30_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg31_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg32_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg33_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg34_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg35_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg36_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg37_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg38_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg39_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg40_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg41_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg42_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg43_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg44_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg45_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg46_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg47_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg48_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg49_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg50_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg51_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg52_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Ports of Axi Slave Bus Interface S00_AXI
|
||||
sys_cpu_clk_in : in std_logic;
|
||||
s00_axi_aresetn : in std_logic;
|
||||
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_awprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_awvalid : in std_logic;
|
||||
s00_axi_awready : out std_logic;
|
||||
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
s00_axi_wvalid : in std_logic;
|
||||
s00_axi_wready : out std_logic;
|
||||
s00_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_bvalid : out std_logic;
|
||||
s00_axi_bready : in std_logic;
|
||||
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
|
||||
s00_axi_arprot : in std_logic_vector(2 downto 0);
|
||||
s00_axi_arvalid : in std_logic;
|
||||
s00_axi_arready : out std_logic;
|
||||
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
|
||||
s00_axi_rresp : out std_logic_vector(1 downto 0);
|
||||
s00_axi_rvalid : out std_logic;
|
||||
s00_axi_rready : in std_logic
|
||||
);
|
||||
end qsfp_intfc_v1_0;
|
||||
|
||||
architecture arch_imp of qsfp_intfc_v1_0 is
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal dig_iq_cmd_addr_i : std_logic_vector (11 downto 0);
|
||||
signal dig_iq_cmd_sel_i : std_logic_vector ( 2 downto 0);
|
||||
signal dig_iq_cmd_strb_i : std_logic;
|
||||
signal dig_iq_cmd_wdata_i : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_write_i : std_logic;
|
||||
|
||||
signal dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal dig_iq_cmd_rdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_ready : std_logic;
|
||||
signal dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal dig_iq_cmd_strb : std_logic;
|
||||
signal dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_cmd_write : std_logic;
|
||||
signal dig_iq_interface_ready : std_logic_vector ( 1 downto 0);
|
||||
signal dig_iq_interface_reset : std_logic_vector ( 1 downto 0);
|
||||
|
||||
signal vio_dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal vio_dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal vio_dig_iq_cmd_strb : std_logic;
|
||||
signal vio_dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal vio_dig_iq_cmd_write : std_logic;
|
||||
signal vio_enable : std_logic;
|
||||
|
||||
--
|
||||
signal qsfp1_axis_aclk : std_logic;
|
||||
signal qsfp1_axis_aresetn : std_logic;
|
||||
|
||||
signal qsfp1_rx_rxn : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_rx_rxp : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_tx_txn : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_tx_txp : std_logic_vector(3 downto 0);
|
||||
signal qsfp1_reset_n : std_logic;
|
||||
signal vio_qsfp1_reset_n : std_logic;
|
||||
signal qsfp1_reset_n_i : std_logic;
|
||||
signal qsfp1_modprsl : std_logic;
|
||||
signal qsfp1_intl : std_logic;
|
||||
|
||||
signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0);
|
||||
signal qsfp1_m_axis_tvalid : std_logic;
|
||||
|
||||
signal qsfp1_axis_aresetn_i : std_logic;
|
||||
signal vio_qsfp1_axis_aresetn : std_logic;
|
||||
--
|
||||
signal qsfp4_axis_aclk : std_logic;
|
||||
signal qsfp4_axis_aresetn : std_logic;
|
||||
|
||||
signal qsfp4_rx_rxn : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_rx_rxp : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_tx_txn : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_tx_txp : std_logic_vector(3 downto 0);
|
||||
signal qsfp4_reset_n : std_logic;
|
||||
signal vio_qsfp4_reset_n : std_logic;
|
||||
signal qsfp4_reset_n_i : std_logic;
|
||||
signal qsfp4_modprsl : std_logic;
|
||||
signal qsfp4_intl : std_logic;
|
||||
|
||||
signal qsfp4_s_axis_tready : std_logic;
|
||||
|
||||
signal qsfp4_axis_aresetn_i : std_logic;
|
||||
signal vio_qsfp4_axis_aresetn : std_logic;
|
||||
|
||||
--
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp1_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp1_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp1_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp4_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp4_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp4_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal rx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal rx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal rx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal tx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal tx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal clkin8_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clkin8_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clkin8_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal sys_cpu_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal sys_cpu_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal sys_cpu_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal ref_clk_div2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal ref_clk_div2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal ref_clk_div2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp2_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg3 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg4 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg5 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg6 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg7 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg8 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal vio_cnt_reset : std_logic;
|
||||
signal cnt_rst : std_logic;
|
||||
|
||||
signal fsm_dig_iq_cmd_strb : std_logic;
|
||||
signal fsm_dig_iq_cmd_addr : std_logic_vector (11 downto 0);
|
||||
signal fsm_dig_iq_cmd_write : std_logic;
|
||||
signal fsm_dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
|
||||
signal fsm_dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
|
||||
signal dig_iq_mode_50g_40g_n : std_logic;
|
||||
signal dig_iq_mode_50g_40g_n_i : std_logic;
|
||||
signal vio_dig_iq_mode_50g_40g_n : std_logic;
|
||||
|
||||
signal fsm_running : std_logic;
|
||||
|
||||
signal clk_50 : std_logic;
|
||||
signal clk_50_reset : std_logic_vector(0 to 15) := (others => '1');
|
||||
|
||||
signal pl_clk3_0_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal pl_clk3_0_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pl_clk3_0_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
cnt_reset_out <= vio_cnt_reset when vio_enable = '1' else cnt_rst;
|
||||
|
||||
i_bufgce_div : BUFGCE_DIV
|
||||
generic map (
|
||||
BUFGCE_DIVIDE => 2, -- 1-8
|
||||
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
IS_CE_INVERTED => '0', -- Optional inversion for CE
|
||||
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
|
||||
IS_I_INVERTED => '0', -- Optional inversion for I
|
||||
SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS
|
||||
)
|
||||
port map (
|
||||
O => clk_50, -- 1-bit output: Buffer
|
||||
CE => '1', -- 1-bit input: Buffer enable
|
||||
CLR => '0', -- 1-bit input: Asynchronous clear
|
||||
I => sys_cpu_clk_in -- 1-bit input: Buffer
|
||||
);
|
||||
|
||||
process(clk_50)
|
||||
begin
|
||||
if (rising_edge(clk_50)) then
|
||||
clk_50_reset <= clk_50_reset(1 to 15) & '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
|
||||
slv_reg0_in => slv_reg0, -- 0x44a0_0000
|
||||
slv_reg1_in => slv_reg1, -- 0x44a0_0004
|
||||
slv_reg2_in => slv_reg2, -- 0x44a0_0008
|
||||
slv_reg3_out => slv_reg3, -- 0x44a0_000C
|
||||
slv_reg4_out => slv_reg4, -- 0x44a0_0010
|
||||
slv_reg5_out => slv_reg5, -- 0x44a0_0014
|
||||
slv_reg6_out => slv_reg6, -- 0x44a0_0018
|
||||
slv_reg7_out => slv_reg7, -- 0x44a0_001C
|
||||
slv_reg8_out => slv_reg8, -- 0x44a0_0020
|
||||
|
||||
slv_reg9_out => slv_reg9_out, -- 0x44a0_0024
|
||||
slv_reg10_out => slv_reg10_out, -- 0x44a0_0028
|
||||
|
||||
slv_reg11_in => qsfp1_s_axis_aclk_freq_r, -- 0x44a0_002C
|
||||
slv_reg12_in => qsfp1_s_axis_aclk_cnt_r, -- 0x44a0_0030
|
||||
slv_reg13_in => qsfp4_s_axis_aclk_freq_r, -- 0x44a0_0034
|
||||
slv_reg14_in => qsfp4_s_axis_aclk_cnt_r, -- 0x44a0_0038
|
||||
slv_reg15_in => rx_device_clk_freq_r, -- 0x44a0_003C
|
||||
slv_reg16_in => tx_device_clk_freq_r, -- 0x44a0_0040
|
||||
slv_reg17_in => clk_125_freq_r, -- 0x44a0_0044
|
||||
slv_reg18_in => clk_125_cnt_r, -- 0x44a0_0048
|
||||
slv_reg19_in => clk_250_freq_r, -- 0x44a0_004C
|
||||
slv_reg20_in => clk_250_cnt_r, -- 0x44a0_0050
|
||||
|
||||
slv_reg21_out => slv_reg21_out, -- 0x44a0_0054
|
||||
slv_reg22_out => slv_reg22_out, -- 0x44a0_0058
|
||||
slv_reg23_out => slv_reg23_out, -- 0x44a0_005C *
|
||||
slv_reg24_out => slv_reg24_out, -- 0x44a0_0060
|
||||
slv_reg25_out => slv_reg25_out, -- 0x44a0_0064 *
|
||||
slv_reg26_out => slv_reg26_out, -- 0x44a0_0068 *
|
||||
slv_reg27_out => slv_reg27_out, -- 0x44a0_006C
|
||||
slv_reg28_out => slv_reg28_out, -- 0x44a0_0070
|
||||
|
||||
slv_reg29_out => slv_reg29_out, -- 0x44a0_0074
|
||||
slv_reg30_out => slv_reg30_out, -- 0x44a0_0078
|
||||
slv_reg31_out => slv_reg31_out, -- 0x44a0_007C *
|
||||
slv_reg32_out => slv_reg32_out, -- 0x44a0_0080
|
||||
slv_reg33_out => slv_reg33_out, -- 0x44a0_0084 *
|
||||
slv_reg34_out => slv_reg34_out, -- 0x44a0_0088 *
|
||||
slv_reg35_out => slv_reg35_out, -- 0x44a0_008C
|
||||
slv_reg36_out => slv_reg36_out, -- 0x44a0_0090
|
||||
|
||||
slv_reg37_out => slv_reg37_out, -- 0x44a0_0094
|
||||
slv_reg38_out => slv_reg38_out, -- 0x44a0_0098
|
||||
slv_reg39_out => slv_reg39_out, -- 0x44a0_009C *
|
||||
slv_reg40_out => slv_reg40_out, -- 0x44a0_00A0
|
||||
slv_reg41_out => slv_reg41_out, -- 0x44a0_00A4 *
|
||||
slv_reg42_out => slv_reg42_out, -- 0x44a0_00A8 *
|
||||
slv_reg43_out => slv_reg43_out, -- 0x44a0_00AC
|
||||
slv_reg44_out => slv_reg44_out, -- 0x44a0_00B0
|
||||
|
||||
slv_reg45_out => slv_reg45_out, -- 0x44a0_00B4
|
||||
slv_reg46_out => slv_reg46_out, -- 0x44a0_00B8
|
||||
slv_reg47_out => slv_reg47_out, -- 0x44a0_00BC *
|
||||
slv_reg48_out => slv_reg48_out, -- 0x44a0_00C0
|
||||
slv_reg49_out => slv_reg49_out, -- 0x44a0_00C4 *
|
||||
slv_reg50_out => slv_reg50_out, -- 0x44a0_00C8 *
|
||||
slv_reg51_out => slv_reg51_out, -- 0x44a0_00CC
|
||||
slv_reg52_out => slv_reg52_out, -- 0x44a0_00D0
|
||||
|
||||
slv_reg53_in => qsfp4_playback_tvalid_240b_cnt_in, -- 0x44a0_00D4
|
||||
slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x44a0_00D8
|
||||
|
||||
slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x44a0_00DC
|
||||
slv_reg56_in => tx_tvalid_128b_cnt_in, -- 0x44a0_00E0
|
||||
slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x44a0_00E4
|
||||
slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x44a0_00E8
|
||||
slv_reg59_in => (others => '0'), -- 0x44a0_00EC
|
||||
slv_reg60_in => dac_tx_tvalid_128b_cnt_in, -- 0x44a0_00F0
|
||||
slv_reg61_in => qsfp1_capture_tvalid_240b_cnt_in, -- 0x44a0_00F4
|
||||
slv_reg62_in => qsfp1_capture_fifo_aempty_512b_cnt_in, -- 0x44a0_00F8
|
||||
slv_reg63_in => qsfp1_capture_rx_data_ready_cnt_in, -- 0x44a0_00FC
|
||||
|
||||
S_AXI_ACLK => sys_cpu_clk_in,
|
||||
S_AXI_ARESETN => s00_axi_aresetn,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
--
|
||||
slv_reg0 <= fpga_revision_date_r; -- 0x44a0_0000
|
||||
--
|
||||
slv_reg1(31 downto 24) <= minor_rev_r; -- 0x44a0_0004
|
||||
slv_reg1(23 downto 9) <= (others => '0');
|
||||
slv_reg1(8) <= dig_iq_cmd_ready;
|
||||
slv_reg1( 7 downto 2) <= (others => '0');
|
||||
slv_reg1( 1 downto 0) <= dig_iq_interface_ready;
|
||||
--
|
||||
slv_reg2 <= dig_iq_cmd_rdata; -- 0x44a0_0008
|
||||
--
|
||||
dig_iq_cmd_addr_i <= slv_reg3(11 downto 0); -- 0x44a0_000C
|
||||
dig_iq_cmd_sel_i <= slv_reg4( 2 downto 0); -- 0x44a0_0010
|
||||
--
|
||||
dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x44a0_0014
|
||||
qsfp1_reset_n_i <= slv_reg5(16);
|
||||
qsfp4_reset_n_i <= slv_reg5(24);
|
||||
--
|
||||
dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x44a0_0018
|
||||
--
|
||||
dig_iq_cmd_write_i <= slv_reg7(0); -- 0x44a0_001C
|
||||
--
|
||||
dig_iq_mode_50g_40g_n_i <= slv_reg8(0); -- 0x44a0_0020
|
||||
-- <= slv_reg8(24);
|
||||
-- <= slv_reg8(28);
|
||||
cnt_rst <= slv_reg8(31);
|
||||
|
||||
-- Add user logic here
|
||||
QSFP1_TX1_P <= qsfp1_tx_txp(0);
|
||||
QSFP1_TX1_N <= qsfp1_tx_txn(0);
|
||||
qsfp1_rx_rxp(0) <= QSFP1_RX1_P;
|
||||
qsfp1_rx_rxn(0) <= QSFP1_RX1_N;
|
||||
|
||||
QSFP1_TX2_P <= qsfp1_tx_txp(1);
|
||||
QSFP1_TX2_N <= qsfp1_tx_txn(1);
|
||||
qsfp1_rx_rxp(1) <= QSFP1_RX2_P;
|
||||
qsfp1_rx_rxn(1) <= QSFP1_RX2_N;
|
||||
|
||||
QSFP1_TX3_P <= qsfp1_tx_txp(2);
|
||||
QSFP1_TX3_N <= qsfp1_tx_txn(2);
|
||||
qsfp1_rx_rxp(2) <= QSFP1_RX3_P;
|
||||
qsfp1_rx_rxn(2) <= QSFP1_RX3_N;
|
||||
|
||||
QSFP1_TX4_P <= qsfp1_tx_txp(3);
|
||||
QSFP1_TX4_N <= qsfp1_tx_txn(3);
|
||||
qsfp1_rx_rxp(3) <= QSFP1_RX4_P;
|
||||
qsfp1_rx_rxn(3) <= QSFP1_RX4_N;
|
||||
|
||||
QSFP1_RESETL_LS <= qsfp1_reset_n;
|
||||
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
|
||||
qsfp1_intl <= QSFP1_INTL_LS;
|
||||
-------
|
||||
QSFP4_TX1_P <= qsfp4_tx_txp(0);
|
||||
QSFP4_TX1_N <= qsfp4_tx_txn(0);
|
||||
qsfp4_rx_rxp(0) <= QSFP4_RX1_P;
|
||||
qsfp4_rx_rxn(0) <= QSFP4_RX1_N;
|
||||
|
||||
QSFP4_TX2_P <= qsfp4_tx_txp(1);
|
||||
QSFP4_TX2_N <= qsfp4_tx_txn(1);
|
||||
qsfp4_rx_rxp(1) <= QSFP4_RX2_P;
|
||||
qsfp4_rx_rxn(1) <= QSFP4_RX2_N;
|
||||
|
||||
QSFP4_TX3_P <= qsfp4_tx_txp(2);
|
||||
QSFP4_TX3_N <= qsfp4_tx_txn(2);
|
||||
qsfp4_rx_rxp(2) <= QSFP4_RX3_P;
|
||||
qsfp4_rx_rxn(2) <= QSFP4_RX3_N;
|
||||
|
||||
QSFP4_TX4_P <= qsfp4_tx_txp(3);
|
||||
QSFP4_TX4_N <= qsfp4_tx_txn(3);
|
||||
qsfp4_rx_rxp(3) <= QSFP4_RX4_P;
|
||||
qsfp4_rx_rxn(3) <= QSFP4_RX4_N;
|
||||
|
||||
QSFP4_RESETL_LS <= qsfp4_reset_n;
|
||||
qsfp4_modprsl <= QSFP4_MODPRSL_LS;
|
||||
qsfp4_intl <= QSFP4_INTL_LS;
|
||||
|
||||
i_vio_2 : entity work.vio_2_1
|
||||
port map (
|
||||
clk => clk_50,
|
||||
probe_in0(0) => dig_iq_cmd_ready, -- 1
|
||||
probe_in1 => dig_iq_cmd_rdata, -- 32
|
||||
probe_in2 => dig_iq_interface_ready, -- 2
|
||||
|
||||
probe_in3(0) => qsfp1_modprsl, -- 1
|
||||
probe_in4(0) => qsfp1_intl, -- 1
|
||||
probe_in5(0) => qsfp4_modprsl, -- 1
|
||||
probe_in6(0) => qsfp4_intl, -- 1
|
||||
probe_in7 => qsfp1_capture_tvalid_240b_cnt_in, -- 32
|
||||
probe_in8 => qsfp1_capture_rx_data_ready_cnt_in, -- 32
|
||||
probe_in9 => qsfp1_capture_fifo_aempty_512b_cnt_in, -- 32
|
||||
|
||||
probe_in10 => tx_tvalid_128b_cnt_in, -- 32
|
||||
probe_in11 => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 32
|
||||
probe_in12 => dac_tx_tvalid_128b_cnt_in, -- 32
|
||||
probe_in13 => qsfp1_capture_rx_data_ready_in, -- 1
|
||||
|
||||
probe_in14 => qsfp1_capture_overflow_240b_cnt_in, -- 32
|
||||
probe_in15 => qsfp4_playback_tvalid_128b_cnt_in, -- 32
|
||||
probe_in16 => qsfp4_playback_tvalid_240b_cnt_in, -- 32
|
||||
probe_in17 => adc_rx_tvalid_128b_cnt_in, -- 32
|
||||
|
||||
probe_out0(0) => vio_dig_iq_cmd_strb, -- 1
|
||||
probe_out1 => vio_dig_iq_cmd_addr, -- 12
|
||||
probe_out2(0) => vio_dig_iq_cmd_write, -- 1
|
||||
probe_out3 => vio_dig_iq_cmd_sel, -- 3
|
||||
probe_out4 => vio_dig_iq_cmd_wdata, -- 32
|
||||
probe_out5 => vio_dig_iq_mode_50g_40g_n, -- 1
|
||||
probe_out6(0) => vio_enable, -- 1
|
||||
|
||||
probe_out7(0) => vio_qsfp1_reset_n, -- 1
|
||||
probe_out8(0) => vio_qsfp4_reset_n, -- 1
|
||||
probe_out9(0) => vio_qsfp1_axis_aresetn, -- 1
|
||||
probe_out10(0) => vio_qsfp4_axis_aresetn, -- 1
|
||||
probe_out11(0) => vio_cnt_reset -- 1
|
||||
);
|
||||
|
||||
dig_iq_cmd_strb <= fsm_dig_iq_cmd_strb when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_strb when vio_enable = '1' else dig_iq_cmd_strb_i;
|
||||
dig_iq_cmd_addr <= fsm_dig_iq_cmd_addr when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_addr when vio_enable = '1' else dig_iq_cmd_addr_i;
|
||||
dig_iq_cmd_write <= fsm_dig_iq_cmd_write when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_write when vio_enable = '1' else dig_iq_cmd_write_i;
|
||||
dig_iq_cmd_sel <= fsm_dig_iq_cmd_sel when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_sel when vio_enable = '1' else dig_iq_cmd_sel_i;
|
||||
dig_iq_cmd_wdata <= fsm_dig_iq_cmd_wdata when fsm_running = '1' else
|
||||
vio_dig_iq_cmd_wdata when vio_enable = '1' else dig_iq_cmd_wdata_i;
|
||||
dig_iq_mode_50g_40g_n <= vio_dig_iq_mode_50g_40g_n when vio_enable = '1' else dig_iq_mode_50g_40g_n_i;
|
||||
|
||||
qsfp1_reset_n <= vio_qsfp1_reset_n when vio_enable = '1' else qsfp1_reset_n_i;
|
||||
dig_iq_interface_reset(0) <= not qsfp1_reset_n;
|
||||
qsfp4_reset_n <= vio_qsfp4_reset_n when vio_enable = '1' else qsfp4_reset_n_i;
|
||||
dig_iq_interface_reset(1) <= not qsfp4_reset_n;
|
||||
|
||||
i_qsfp_int_fsm : entity work.qsfp_init_fsm
|
||||
port map (
|
||||
clk_125_in => clk_125_in,
|
||||
clk_125_aresetn_in => clk_125_reset_n_in,
|
||||
|
||||
mode_50g_40g_n_in => dig_iq_mode_50g_40g_n,
|
||||
qsfp1_reset_n_in => qsfp1_reset_n,
|
||||
qsfp4_reset_n_in => qsfp4_reset_n,
|
||||
|
||||
cmd_strb_out => fsm_dig_iq_cmd_strb,
|
||||
cmd_addr_out => fsm_dig_iq_cmd_addr,
|
||||
cmd_write_out => fsm_dig_iq_cmd_write,
|
||||
cmd_sel_out => fsm_dig_iq_cmd_sel,
|
||||
cmd_wdata_out => fsm_dig_iq_cmd_wdata,
|
||||
cmd_ready_in => dig_iq_cmd_ready,
|
||||
fsm_running_out => fsm_running
|
||||
);
|
||||
|
||||
------------------------------------------------------
|
||||
i_dig_iq_x2 : entity work.dig_iq_x2
|
||||
port map(
|
||||
--
|
||||
clk_125_resetn_in => clk_125_reset_n_in,
|
||||
clk_125_in => clk_125_in,
|
||||
--
|
||||
aclk_in => clk_250_in,
|
||||
aresetn_in => clk_250_reset_n_in,
|
||||
cmd_strb_in => dig_iq_cmd_strb,
|
||||
cmd_addr_in => dig_iq_cmd_addr,
|
||||
cmd_write_in => dig_iq_cmd_write,
|
||||
cmd_sel_in => dig_iq_cmd_sel,
|
||||
cmd_wdata_in => dig_iq_cmd_wdata,
|
||||
cmd_ready_out => dig_iq_cmd_ready,
|
||||
cmd_rdata_out => dig_iq_cmd_rdata,
|
||||
dig_iq_interface_reset_in => dig_iq_interface_reset,
|
||||
--
|
||||
dig_iq_interface_ready_out => dig_iq_interface_ready,
|
||||
--
|
||||
rx_data_ready_in => qsfp1_capture_rx_data_ready_in,
|
||||
|
||||
axis_0_aclk_out => qsfp1_axis_aclk,
|
||||
axis_0_aresetn_out => qsfp1_axis_aresetn,
|
||||
m0_axis_tdata_out => qsfp1_m_axis_tdata,
|
||||
m0_axis_tvalid_out => qsfp1_m_axis_tvalid,
|
||||
s0_axis_tdata_in => (others =>'0'),
|
||||
s0_axis_tvalid_in => '0',
|
||||
s0_axis_tready_out => open,
|
||||
--
|
||||
axis_1_aclk_out => qsfp4_axis_aclk,
|
||||
axis_1_aresetn_out => qsfp4_axis_aresetn,
|
||||
m1_axis_tdata_out => open,
|
||||
m1_axis_tvalid_out => open,
|
||||
s1_axis_tdata_in => qsfp4_playback_tdata_240b_in,
|
||||
s1_axis_tvalid_in => qsfp4_playback_tvalid_240b_in,
|
||||
s1_axis_tready_out => qsfp4_s_axis_tready,
|
||||
|
||||
tx_data_channel_reset_in => '0',
|
||||
tx_data_clear_in => '0',
|
||||
|
||||
--
|
||||
qsfp0_ref_clk_p_in => QSFP1_SI570_CLOCK_P,
|
||||
qsfp0_ref_clk_n_in => QSFP1_SI570_CLOCK_N,
|
||||
qsfp0_rx_rxp_in => qsfp1_rx_rxp,
|
||||
qsfp0_rx_rxn_in => qsfp1_rx_rxn,
|
||||
qsfp0_tx_txp_out => qsfp1_tx_txp,
|
||||
qsfp0_tx_txn_out => qsfp1_tx_txn,
|
||||
--
|
||||
qsfp1_ref_clk_p_in => QSFP4_SI570_CLOCK_P,
|
||||
qsfp1_ref_clk_n_in => QSFP4_SI570_CLOCK_N,
|
||||
qsfp1_rx_rxp_in => qsfp4_rx_rxp,
|
||||
qsfp1_rx_rxn_in => qsfp4_rx_rxn,
|
||||
qsfp1_tx_txp_out => qsfp4_tx_txp,
|
||||
qsfp1_tx_txn_out => qsfp4_tx_txn
|
||||
);
|
||||
|
||||
qsfp1_axis_aresetn_i <= qsfp1_axis_aresetn and vio_qsfp1_axis_aresetn;
|
||||
qsfp1_capture_aclk_out <= qsfp1_axis_aclk;
|
||||
qsfp1_capture_aresetn_out <= qsfp1_axis_aresetn_i;
|
||||
qsfp1_capture_tdata_240b_out <= qsfp1_m_axis_tdata;
|
||||
qsfp1_capture_tvalid_240b_out <= qsfp1_m_axis_tvalid;
|
||||
|
||||
-- i_ila_3_qsfp1 : entity work.ila_3
|
||||
-- port map (
|
||||
-- clk => qsfp1_axis_aclk,
|
||||
-- probe0(0) => qsfp1_m_axis_tvalid, --1
|
||||
-- probe1(0) => '0', --1
|
||||
-- probe2 => qsfp1_m_axis_tdata(31 downto 0), --32
|
||||
-- probe3 => qsfp1_m_axis_tdata(63 downto 32), --32
|
||||
-- probe4 => qsfp1_m_axis_tdata(95 downto 64), --32
|
||||
-- probe5 => qsfp1_m_axis_tdata(127 downto 96), --32
|
||||
-- probe6 => qsfp1_m_axis_tdata(159 downto 128), --32
|
||||
-- probe7 => qsfp1_m_axis_tdata(191 downto 160), --32
|
||||
-- probe8 => qsfp1_m_axis_tdata(223 downto 192), --32
|
||||
-- probe9 => qsfp1_m_axis_tdata(239 downto 224) --16
|
||||
-- );
|
||||
|
||||
--------------------------------------------------------------------------------------------
|
||||
qsfp4_axis_aresetn_i <= qsfp4_axis_aresetn and vio_qsfp4_axis_aresetn;
|
||||
qsfp4_playback_aclk_out <= qsfp4_axis_aclk;
|
||||
qsfp4_playback_tready_240b_out <= qsfp4_s_axis_tready;
|
||||
qsfp4_playback_aresetn_out <= qsfp4_axis_aresetn_i;
|
||||
|
||||
-- i_ila_3_qsfp4 : entity work.ila_3
|
||||
-- port map (
|
||||
-- clk => qsfp4_axis_aclk,
|
||||
-- probe0(0) => qsfp4_playback_tvalid_240b_in, --1
|
||||
-- probe1(0) => qsfp4_s_axis_tready, --1
|
||||
-- probe2 => qsfp4_playback_tdata_240b_in(31 downto 0), --32
|
||||
-- probe3 => qsfp4_playback_tdata_240b_in(63 downto 32), --32
|
||||
-- probe4 => qsfp4_playback_tdata_240b_in(95 downto 64), --32
|
||||
-- probe5 => qsfp4_playback_tdata_240b_in(127 downto 96), --32
|
||||
-- probe6 => qsfp4_playback_tdata_240b_in(159 downto 128), --32
|
||||
-- probe7 => qsfp4_playback_tdata_240b_in(191 downto 160), --32
|
||||
-- probe8 => qsfp4_playback_tdata_240b_in(223 downto 192), --32
|
||||
-- probe9 => qsfp4_playback_tdata_240b_in(239 downto 224) --16
|
||||
-- );
|
||||
|
||||
------------------------------------------------
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 50
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_50,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_50_reset(0)
|
||||
);
|
||||
|
||||
process(clk_50)
|
||||
begin
|
||||
if (rising_edge(clk_50)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_vio_0 : entity work.vio_0_1
|
||||
port map (
|
||||
clk => clk_50,
|
||||
probe_in0 => fpga_revision_date_r, -- 32
|
||||
probe_in1 => minor_rev_r, -- 8
|
||||
probe_in2 => clk_125_freq_r, -- 32
|
||||
probe_in3 => clk_125_cnt_r, -- 32
|
||||
probe_in4 => clk_250_freq_r, -- 32
|
||||
probe_in5 => clk_250_cnt_r, -- 32
|
||||
probe_in6 => qsfp1_s_axis_aclk_freq_r, -- 32
|
||||
probe_in7 => qsfp1_s_axis_aclk_cnt_r, -- 32
|
||||
probe_in8 => qsfp4_s_axis_aclk_freq_r, -- 32
|
||||
probe_in9 => qsfp4_s_axis_aclk_cnt_r, -- 32
|
||||
probe_in10 => rx_device_clk_freq_r, -- 32
|
||||
probe_in11 => rx_device_clk_cnt_r, -- 32
|
||||
probe_in12 => tx_device_clk_freq_r, -- 32
|
||||
probe_in13 => tx_device_clk_cnt_r, -- 32
|
||||
probe_in14 => clkin8_freq_r, -- 32
|
||||
probe_in15 => clkin8_cnt_r, -- 32
|
||||
probe_in16 => sys_cpu_clk_freq_r, -- 32
|
||||
probe_in17 => sys_cpu_clk_cnt_r, -- 32
|
||||
probe_in18 => ref_clk_div2_freq_r, -- 32
|
||||
probe_in19 => ref_clk_div2_cnt_r, -- 32
|
||||
probe_in20 => qsfp2_clk_freq_r, -- 32
|
||||
probe_in21 => qsfp2_clk_cnt_r, -- 32
|
||||
probe_in22 => qsfp3_clk_freq_r, -- 32
|
||||
probe_in23 => qsfp3_clk_cnt_r, -- 32
|
||||
probe_in24 => pl_clk3_0_freq_r -- 32
|
||||
);
|
||||
|
||||
process(clk_125_in)
|
||||
begin
|
||||
if (rising_edge(clk_125_in)) then
|
||||
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_125_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_125_freq_r <= clk_125_cnt_r;
|
||||
clk_125_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_125_cnt_r <= clk_125_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_250_in)
|
||||
begin
|
||||
if (rising_edge(clk_250_in)) then
|
||||
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_250_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_250_freq_r <= clk_250_cnt_r;
|
||||
clk_250_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_250_cnt_r <= clk_250_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp1_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(qsfp1_axis_aclk)) then
|
||||
qsfp1_s_axis_aclk_tick_1ms_r <= qsfp1_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp1_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp1_s_axis_aclk_freq_r <= qsfp1_s_axis_aclk_cnt_r;
|
||||
qsfp1_s_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp1_s_axis_aclk_cnt_r <= qsfp1_s_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp4_axis_aclk)
|
||||
begin
|
||||
if (rising_edge(qsfp4_axis_aclk)) then
|
||||
qsfp4_s_axis_aclk_tick_1ms_r <= qsfp4_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp4_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp4_s_axis_aclk_freq_r <= qsfp4_s_axis_aclk_cnt_r;
|
||||
qsfp4_s_axis_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp4_s_axis_aclk_cnt_r <= qsfp4_s_axis_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(rx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(rx_device_clk_in)) then
|
||||
rx_device_clk_tick_1ms_r <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
rx_device_clk_freq_r <= rx_device_clk_cnt_r;
|
||||
rx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
rx_device_clk_cnt_r <= rx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(tx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(tx_device_clk_in)) then
|
||||
tx_device_clk_tick_1ms_r <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
tx_device_clk_freq_r <= tx_device_clk_cnt_r;
|
||||
tx_device_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
tx_device_clk_cnt_r <= tx_device_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clkin8_in)
|
||||
begin
|
||||
if (rising_edge(clkin8_in)) then
|
||||
clkin8_tick_1ms_r <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clkin8_tick_1ms_r(0 to 1) = "01") then
|
||||
clkin8_freq_r <= clkin8_cnt_r;
|
||||
clkin8_cnt_r <= (others => '0');
|
||||
else
|
||||
clkin8_cnt_r <= clkin8_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(sys_cpu_clk_in)
|
||||
begin
|
||||
if (rising_edge(sys_cpu_clk_in)) then
|
||||
sys_cpu_clk_tick_1ms_r <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
sys_cpu_clk_freq_r <= sys_cpu_clk_cnt_r;
|
||||
sys_cpu_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
sys_cpu_clk_cnt_r <= sys_cpu_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(ref_clk_div2_in)
|
||||
begin
|
||||
if (rising_edge(ref_clk_div2_in)) then
|
||||
ref_clk_div2_tick_1ms_r <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then
|
||||
ref_clk_div2_freq_r <= ref_clk_div2_cnt_r;
|
||||
ref_clk_div2_cnt_r <= (others => '0');
|
||||
else
|
||||
ref_clk_div2_cnt_r <= ref_clk_div2_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp2_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp2_clk_in)) then
|
||||
qsfp2_clk_tick_1ms_r <= qsfp2_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp2_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp2_clk_freq_r <= qsfp2_clk_cnt_r;
|
||||
qsfp2_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp2_clk_cnt_r <= qsfp2_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp3_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp3_clk_in)) then
|
||||
qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp3_clk_freq_r <= qsfp3_clk_cnt_r;
|
||||
qsfp3_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(pl_clk3_0)
|
||||
begin
|
||||
if (rising_edge(pl_clk3_0)) then
|
||||
pl_clk3_0_tick_1ms_r <= pl_clk3_0_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (pl_clk3_0_tick_1ms_r(0 to 1) = "01") then
|
||||
pl_clk3_0_freq_r <= pl_clk3_0_cnt_r;
|
||||
pl_clk3_0_cnt_r <= (others => '0');
|
||||
else
|
||||
pl_clk3_0_cnt_r <= pl_clk3_0_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_1kx240_1",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "2048", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_1kx240_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241650", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../vcu128/ad9081_fmca_ebz_vcu128.tmp/qsfp_intfc_v1_0_project/qsfp_intfc_v1_0_project.gen/sources_1/ip/axis_data_fifo_1kx240_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"prog_full": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_data_fifo_32x240",
|
||||
"cell_name": "i_qsfp0_to_qsfp1_fifo",
|
||||
"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
|
||||
"ip_revision": "11",
|
||||
"gen_directory": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_DEPTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_AEMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_EMPTY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_AFULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_data_fifo_32x240", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "virtexuplusHBM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AXIS_TDATA_WIDTH": [ { "value": "240", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"C_FIFO_DEPTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FIFO_MEMORY_TYPE": [ { "value": "auto", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "11" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_data_fifo_32x240" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "239", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axis_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"S_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axis_aclk" } ]
|
||||
}
|
||||
},
|
||||
"M_CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_axis_aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,337 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/08/2023
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_p_intfc
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
--
|
||||
--p_enable_in_0 : out std_logic;
|
||||
--p_enable_in_1 : out std_logic;
|
||||
--p_enable_in_2 : out std_logic;
|
||||
--p_enable_in_3 : out std_logic;
|
||||
--p_enable_out_0 : out std_logic;
|
||||
--p_enable_out_1 : out std_logic;
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
--
|
||||
--p_ready_in_0 : in std_logic;
|
||||
--p_ready_in_1 : in std_logic;
|
||||
--p_ready_in_2 : in std_logic;
|
||||
--p_ready_in_3 : in std_logic;
|
||||
--p_ready_out_0 : in std_logic;
|
||||
--p_ready_out_1 : in std_logic;
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
--
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end dig_iq_p_intfc;
|
||||
|
||||
architecture arch_imp of dig_iq_p_intfc is
|
||||
|
||||
--signal p_ready : std_logic_vector(7 downto 0);
|
||||
signal strb_in_r : std_logic := '0';
|
||||
signal strb_int : std_logic;
|
||||
signal addr_int : std_logic_vector(11 downto 0);
|
||||
signal sel_int : std_logic_vector(2 downto 0);
|
||||
signal write_int : std_logic;
|
||||
signal wdata_int : std_logic_vector(31 downto 0);
|
||||
signal p_addr_r : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal p_write_r : std_logic := '0';
|
||||
signal p_wdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal p_enable_r : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_enable_r1 : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal p_strb_r : std_logic := '0';
|
||||
signal p_ready_r : std_logic := '0';
|
||||
signal p_rdata_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
SAME_CLKS_FALSE_GEN :
|
||||
if SAME_CLKS = 0 generate
|
||||
begin
|
||||
|
||||
i_cdc_pulse_strb : xpm_cdc_pulse
|
||||
generic map (
|
||||
DEST_SYNC_FF => 7, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
REG_OUTPUT => 1, -- DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
RST_USED => 0, -- DECIMAL; 0=no reset, 1=implement reset
|
||||
SIM_ASSERT_CHK => 0 -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
)
|
||||
port map (
|
||||
dest_rst => '0',
|
||||
dest_pulse => strb_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => reg_clk,
|
||||
src_pulse => strb_in,
|
||||
src_rst => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_addr : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 12 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => addr_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => addr_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_sel : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 3 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => sel_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => sel_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_array_wdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => wdata_int,
|
||||
dest_clk => clk_125,
|
||||
src_in => wdata_in,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
i_cdc_single_write : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => write_int,
|
||||
dest_clk => clk_125,
|
||||
src_clk => '0',
|
||||
src_in => write_in
|
||||
);
|
||||
|
||||
i_cdc_single_ready : xpm_cdc_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4,
|
||||
INIT_SYNC_FF => 0,
|
||||
SIM_ASSERT_CHK => 0,
|
||||
SRC_INPUT_REG => 0
|
||||
)
|
||||
port map (
|
||||
dest_out => ready_out,
|
||||
dest_clk => reg_clk,
|
||||
src_clk => '0',
|
||||
src_in => p_ready_r
|
||||
);
|
||||
|
||||
i_cdc_array_rdata : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 32 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => rdata_out,
|
||||
dest_clk => reg_clk,
|
||||
src_in => p_rdata_r,
|
||||
src_clk => '0'
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
SAME_CLKS_TRUE_GEN :
|
||||
if SAME_CLKS = 1 generate
|
||||
begin
|
||||
|
||||
strb_int <= not(strb_in_r) and strb_in;
|
||||
addr_int <= addr_in;
|
||||
sel_int <= sel_in;
|
||||
wdata_int <= wdata_in;
|
||||
write_int <= write_in;
|
||||
ready_out <= p_ready_r;
|
||||
rdata_out <= p_rdata_r;
|
||||
|
||||
end generate;
|
||||
---------------------------------------
|
||||
|
||||
|
||||
|
||||
-- APB Interface Ports
|
||||
p_addr <= p_addr_r;
|
||||
p_write <= p_write_r;
|
||||
p_wdata <= p_wdata_r;
|
||||
|
||||
p_enable <= p_enable_r1;
|
||||
--p_enable_in_0 <= p_enable_r1(0);
|
||||
--p_enable_in_1 <= p_enable_r1(1);
|
||||
--p_enable_in_2 <= p_enable_r1(2);
|
||||
--p_enable_in_3 <= p_enable_r1(3);
|
||||
--p_enable_out_0 <= p_enable_r1(4);
|
||||
--p_enable_out_1 <= p_enable_r1(5);
|
||||
|
||||
--p_ready(0) <= p_ready_in_0;
|
||||
--p_ready(1) <= p_ready_in_1;
|
||||
--p_ready(2) <= p_ready_in_2;
|
||||
--p_ready(3) <= p_ready_in_3;
|
||||
--p_ready(4) <= p_ready_out_0;
|
||||
--p_ready(5) <= p_ready_out_1;
|
||||
|
||||
|
||||
process(clk_125)
|
||||
begin
|
||||
if(rising_edge(clk_125))then
|
||||
if(clk_125_resetn = '0')then
|
||||
strb_in_r <= '0';
|
||||
p_addr_r <= (others => '0');
|
||||
p_write_r <= '0';
|
||||
p_wdata_r <= (others => '0');
|
||||
p_enable_r <= (others => '0');
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_strb_r <= '0';
|
||||
p_ready_r <= '0';
|
||||
p_rdata_r <= (others => '0');
|
||||
else
|
||||
strb_in_r <= strb_in;
|
||||
|
||||
p_strb_r <= strb_int;
|
||||
|
||||
if(strb_int = '1')then
|
||||
p_addr_r <= addr_int;
|
||||
p_write_r <= write_int;
|
||||
p_wdata_r <= wdata_int;
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_enable_r <= "00000001";
|
||||
when "001" =>
|
||||
p_enable_r <= "00000010";
|
||||
when "010" =>
|
||||
p_enable_r <= "00000100";
|
||||
when "011" =>
|
||||
p_enable_r <= "00001000";
|
||||
when "100" =>
|
||||
p_enable_r <= "00010000";
|
||||
when "101" =>
|
||||
p_enable_r <= "00100000";
|
||||
when "110" =>
|
||||
p_enable_r <= "01000000";
|
||||
when "111" =>
|
||||
p_enable_r <= "10000000";
|
||||
when others =>
|
||||
p_enable_r <= "00000000";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
if(p_strb_r = '1')then
|
||||
|
||||
p_enable_r1 <= p_enable_r;
|
||||
if(p_enable_r /= "00000000")then
|
||||
p_ready_r <= '0';
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
if(p_ready = "11111111")then
|
||||
p_enable_r1 <= (others => '0');
|
||||
p_ready_r <= '1';
|
||||
|
||||
case sel_int is
|
||||
when "000" =>
|
||||
p_rdata_r <= p_rdata_0;
|
||||
when "001" =>
|
||||
p_rdata_r <= p_rdata_1;
|
||||
when "010" =>
|
||||
p_rdata_r <= p_rdata_2;
|
||||
when "011" =>
|
||||
p_rdata_r <= p_rdata_3;
|
||||
when "100" =>
|
||||
p_rdata_r <= p_rdata_4;
|
||||
when "101" =>
|
||||
p_rdata_r <= p_rdata_5;
|
||||
when "110" =>
|
||||
p_rdata_r <= p_rdata_6;
|
||||
when "111" =>
|
||||
p_rdata_r <= p_rdata_7;
|
||||
when others =>
|
||||
p_rdata_r <= x"DEADBEEF";
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,596 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/02/2023 02:07:25 PM
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_x2 - structural
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
Library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_x2 is
|
||||
port (
|
||||
clk_125_resetn_in : in std_logic;
|
||||
clk_125_in : in std_logic;
|
||||
|
||||
aclk_in : in std_logic;
|
||||
aresetn_in : in std_logic;
|
||||
cmd_strb_in : in std_logic;
|
||||
cmd_addr_in : in std_logic_vector(11 downto 0);
|
||||
cmd_write_in : in std_logic;
|
||||
cmd_sel_in : in std_logic_vector(2 downto 0);
|
||||
cmd_wdata_in : in std_logic_vector(31 downto 0);
|
||||
cmd_ready_out : out std_logic;
|
||||
cmd_rdata_out : out std_logic_vector(31 downto 0);
|
||||
dig_iq_interface_reset_in : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_resetn : in std_logic_vector(1 downto 0);
|
||||
--dig_iq_rx_enable : in std_logic_vector(1 downto 0);
|
||||
--
|
||||
dig_iq_interface_ready_out : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_cc_overflow : out std_logic_vector(1 downto 0); --async
|
||||
--dig_iq_tx_overflow : out std_logic_vector(PORT_CNT-1 downto 0);
|
||||
rx_data_ready_in : in std_logic;
|
||||
|
||||
axis_0_aclk_out : out std_logic;
|
||||
axis_0_aresetn_out : out std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
s0_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s0_axis_tvalid_in : in std_logic;
|
||||
s0_axis_tready_out : out std_logic;
|
||||
|
||||
axis_1_aclk_out : out std_logic;
|
||||
axis_1_aresetn_out : out std_logic;
|
||||
m1_axis_tdata_out : out std_logic_vector(239 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
s1_axis_tdata_in : in std_logic_vector(239 downto 0);
|
||||
s1_axis_tvalid_in : in std_logic;
|
||||
s1_axis_tready_out : out std_logic;
|
||||
|
||||
tx_data_channel_reset_in : in std_logic;
|
||||
tx_data_clear_in : in std_logic;
|
||||
|
||||
qsfp0_ref_clk_n_in : in std_logic;
|
||||
qsfp0_ref_clk_p_in : in std_logic;
|
||||
qsfp0_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp0_tx_txp_out : out std_logic_vector(3 downto 0);
|
||||
|
||||
qsfp1_ref_clk_n_in : in std_logic;
|
||||
qsfp1_ref_clk_p_in : in std_logic;
|
||||
qsfp1_rx_rxn_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_rx_rxp_in : in std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txn_out : out std_logic_vector(3 downto 0);
|
||||
qsfp1_tx_txp_out : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end dig_iq_x2;
|
||||
|
||||
architecture structural of dig_iq_x2 is
|
||||
|
||||
component DIG_IQ_HS_CUSTOM1X is
|
||||
port(
|
||||
INIT_CLK : in std_logic := '0';
|
||||
INTERFACE_RESET : in std_logic := '1';
|
||||
IntL : in std_logic := '1';
|
||||
MGTREFCLK_N : in std_logic := '1';
|
||||
MGTREFCLK_P : in std_logic := '0';
|
||||
ModPrsL : in std_logic := '1';
|
||||
PADDR : in std_logic_vector (11 downto 0) := (others => '0');
|
||||
PCLK : in std_logic := '0';
|
||||
PENABLE : in std_logic := '0';
|
||||
PRESETn : in std_logic := '0';
|
||||
PSEL : in std_logic := '0';
|
||||
PWDATA : in std_logic_vector (31 downto 0) := (others => '0');
|
||||
PWRITE : in std_logic := '0';
|
||||
RXN : in std_logic_vector (3 downto 0) := (others => '1');
|
||||
RXP : in std_logic_vector (3 downto 0) := (others => '0');
|
||||
RX_DATA_READY : in std_logic := '1';
|
||||
SCL_I : in std_logic := '0';
|
||||
SDA_I : in std_logic := '0';
|
||||
TX_DATA_CLEAR : in std_logic := '0';
|
||||
TX_DATA_DAT : in std_logic_vector (239 downto 0) := (others => '0');
|
||||
TX_DATA_EN : in std_logic := '0';
|
||||
TX_DATA_CHANNEL_RESET : in std_logic := '0';
|
||||
RX_DATA_CHANNEL_RESET : out std_logic;
|
||||
DATA_CLK : out std_logic ;
|
||||
INTERFACE_READY : out std_logic ;
|
||||
ModselL : out std_logic ;
|
||||
PRDATA : out std_logic_vector (31 downto 0);
|
||||
PREADY : out std_logic ;
|
||||
RX_DATA_DAT : out std_logic_vector (239 downto 0);
|
||||
RX_DATA_EN : out std_logic ;
|
||||
SCL_O : out std_logic ;
|
||||
SCL_OE : out std_logic ;
|
||||
SDA_O : out std_logic ;
|
||||
SDA_OE : out std_logic ;
|
||||
TXN : out std_logic_vector (3 downto 0);
|
||||
TXP : out std_logic_vector (3 downto 0);
|
||||
TX_DATA_READY : out std_logic
|
||||
);
|
||||
end component DIG_IQ_HS_CUSTOM1X;
|
||||
|
||||
component dig_iq_p_intfc is
|
||||
generic(
|
||||
SAME_CLKS : natural range 0 to 1 := 0
|
||||
);
|
||||
port (
|
||||
reg_clk : in std_logic;
|
||||
reg_resetn : in std_logic;
|
||||
--
|
||||
strb_in : in std_logic;
|
||||
addr_in : in std_logic_vector(11 downto 0);
|
||||
write_in : in std_logic;
|
||||
sel_in : in std_logic_vector(2 downto 0);
|
||||
wdata_in : in std_logic_vector(31 downto 0);
|
||||
ready_out : out std_logic;
|
||||
rdata_out : out std_logic_vector(31 downto 0);
|
||||
----------------------------------------------------------
|
||||
clk_125 : in std_logic;
|
||||
clk_125_resetn : in std_logic;
|
||||
--
|
||||
p_addr : out std_logic_vector(11 downto 0);
|
||||
p_write : out std_logic;
|
||||
p_wdata : out std_logic_vector(31 downto 0);
|
||||
p_enable : out std_logic_vector(7 downto 0);
|
||||
p_ready : in std_logic_vector(7 downto 0);
|
||||
p_rdata_0 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_1 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_2 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_3 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_4 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_5 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_6 : in std_logic_vector(31 downto 0);
|
||||
p_rdata_7 : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component dig_iq_p_intfc;
|
||||
|
||||
component axis_clock_converter_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
m_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component axis_data_fifo_0
|
||||
port (
|
||||
s_axis_aresetn : in std_logic;
|
||||
s_axis_aclk : in std_logic;
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
m_axis_aclk : in std_logic;
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic;
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal p_addr : std_logic_vector(11 downto 0);
|
||||
signal p_write : std_logic;
|
||||
signal p_wdata : std_logic_vector(31 downto 0);
|
||||
signal p_enable : std_logic_vector(7 downto 0);
|
||||
signal p_ready : std_logic_vector(7 downto 0);
|
||||
|
||||
type SLV_32_ARRAY is array (integer range 0 to 1) of std_logic_vector(31 downto 0);
|
||||
signal p_rdata : SLV_32_ARRAY;
|
||||
|
||||
type SLV_4_ARRAY is array (integer range 0 to 1) of std_logic_vector(3 downto 0);
|
||||
signal qsfp_rx_rxn : SLV_4_ARRAY;
|
||||
signal qsfp_rx_rxp : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txn : SLV_4_ARRAY;
|
||||
signal qsfp_tx_txp : SLV_4_ARRAY;
|
||||
|
||||
type SLV_240_ARRAY is array (integer range 0 to 1) of std_logic_vector(239 downto 0);
|
||||
--signal tx_data_r : SLV_240_ARRAY;
|
||||
--signal rx_data_r : SLV_240_ARRAY;
|
||||
signal rx_data : SLV_240_ARRAY;
|
||||
signal s_axis_tdata : SLV_240_ARRAY;
|
||||
--signal m_axis_tdata_int : SLV_240_ARRAY;
|
||||
--signal tx_fifo_m_tdata : SLV_240_ARRAY;
|
||||
|
||||
signal clk : std_logic_vector(1 downto 0);
|
||||
--signal resetn : std_logic_vector(1 downto 0);
|
||||
--signal rx_enable : std_logic_vector(1 downto 0);
|
||||
signal interface_reset : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_n : std_logic_vector(1 downto 0);
|
||||
signal qsfp_ref_clk_p : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal rx_data_en : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal tx_data_ready : std_logic_vector(1 downto 0);
|
||||
signal s_axis_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal rx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_data_en_int : std_logic_vector(1 downto 0);
|
||||
--signal m_axis_tvalid_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_tready : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_int : std_logic_vector(1 downto 0);
|
||||
--signal cc_overflow_r : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
--signal tx_fifo_m_tvalid : std_logic_vector(1 downto 0);
|
||||
--signal s_axis_tready_int : std_logic_vector(1 downto 0);
|
||||
--signal tx_fifo_overflow_int : std_logic_vector(PORT_CNT-1 downto 0);
|
||||
|
||||
signal dig_iq_interface_ready : std_logic_vector(1 downto 0);
|
||||
signal axis_0_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
signal axis_1_aresetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
|
||||
type array_32b_type is array (0 to 1) of std_logic_vector(0 to 31);
|
||||
signal tx_data_channel_reset_r : array_32b_type := (others => (others => '0'));
|
||||
signal tx_data_clear_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
signal rx_data_ready : std_logic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
rx_data_ready <= '1' & rx_data_ready_in;
|
||||
|
||||
p_ready(7 downto 2) <= (others => '1');
|
||||
|
||||
i_dig_iq_p_intfc : dig_iq_p_intfc
|
||||
generic map(
|
||||
SAME_CLKS => 1
|
||||
)
|
||||
port map(
|
||||
reg_clk => clk_125_in,
|
||||
reg_resetn => clk_125_resetn_in,
|
||||
--
|
||||
strb_in => cmd_strb_in,
|
||||
addr_in => cmd_addr_in,
|
||||
write_in => cmd_write_in,
|
||||
sel_in => cmd_sel_in,
|
||||
wdata_in => cmd_wdata_in,
|
||||
ready_out => cmd_ready_out,
|
||||
rdata_out => cmd_rdata_out,
|
||||
--
|
||||
clk_125 => clk_125_in,
|
||||
clk_125_resetn => clk_125_resetn_in,
|
||||
--
|
||||
p_addr => p_addr,
|
||||
p_write => p_write,
|
||||
p_wdata => p_wdata,
|
||||
p_enable => p_enable,
|
||||
p_ready => p_ready,
|
||||
p_rdata_0 => p_rdata(0),
|
||||
p_rdata_1 => p_rdata(1),
|
||||
p_rdata_2 => (others => '0'),
|
||||
p_rdata_3 => (others => '0'),
|
||||
p_rdata_4 => (others => '0'),
|
||||
p_rdata_5 => (others => '0'),
|
||||
p_rdata_6 => (others => '0'),
|
||||
p_rdata_7 => (others => '0')
|
||||
);
|
||||
|
||||
i_cdc_0 : xpm_cdc_array_single
|
||||
generic map (
|
||||
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
|
||||
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
|
||||
WIDTH => 2 -- DECIMAL; range: 1-1024
|
||||
)
|
||||
port map (
|
||||
dest_out => interface_reset,
|
||||
dest_clk => clk_125_in,
|
||||
src_clk => '0',
|
||||
src_in => dig_iq_interface_reset_in
|
||||
);
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
dig_iq_interface_ready_out <= dig_iq_interface_ready;
|
||||
|
||||
axis_0_aclk_out <= clk(0);
|
||||
axis_0_aresetn_out <= axis_0_aresetn_r(0);
|
||||
s_axis_tdata(0) <= s0_axis_tdata_in;
|
||||
s_axis_tvalid(0) <= s0_axis_tvalid_in;
|
||||
s0_axis_tready_out <= tx_data_ready(0);--s_axis_tready_int(0);
|
||||
m0_axis_tdata_out <= rx_data(0);--m_axis_tdata_int(0);
|
||||
m0_axis_tvalid_out <= rx_data_en(0);--m_axis_tvalid_int(0);
|
||||
|
||||
axis_1_aclk_out <= clk(1);
|
||||
axis_1_aresetn_out <= axis_1_aresetn_r(0);
|
||||
s_axis_tdata(1) <= s1_axis_tdata_in;
|
||||
s_axis_tvalid(1) <= s1_axis_tvalid_in;
|
||||
s1_axis_tready_out <= tx_data_ready(1);--s_axis_tready_int(1);
|
||||
m1_axis_tdata_out <= rx_data(1);--m_axis_tdata_int(1);
|
||||
m1_axis_tvalid_out <= rx_data_en(1);--m_axis_tvalid_int(1);
|
||||
|
||||
qsfp_ref_clk_n(0) <= qsfp0_ref_clk_n_in;
|
||||
qsfp_ref_clk_n(1) <= qsfp1_ref_clk_n_in;
|
||||
|
||||
qsfp_ref_clk_p(0) <= qsfp0_ref_clk_p_in;
|
||||
qsfp_ref_clk_p(1) <= qsfp1_ref_clk_p_in;
|
||||
|
||||
qsfp_rx_rxn(0) <= qsfp0_rx_rxn_in;
|
||||
qsfp_rx_rxn(1) <= qsfp1_rx_rxn_in;
|
||||
|
||||
qsfp_rx_rxp(0) <= qsfp0_rx_rxp_in;
|
||||
qsfp_rx_rxp(1) <= qsfp1_rx_rxp_in;
|
||||
|
||||
qsfp0_tx_txn_out <= qsfp_tx_txn(0);
|
||||
qsfp1_tx_txn_out <= qsfp_tx_txn(1);
|
||||
|
||||
qsfp0_tx_txp_out <= qsfp_tx_txp(0);
|
||||
qsfp1_tx_txp_out <= qsfp_tx_txp(1);
|
||||
|
||||
|
||||
process(clk(0))
|
||||
begin
|
||||
if (rising_edge(clk(0))) then
|
||||
if (dig_iq_interface_ready(0) = '1') then
|
||||
axis_0_aresetn_r <= axis_0_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_0_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk(1))
|
||||
begin
|
||||
if (rising_edge(clk(1))) then
|
||||
if (dig_iq_interface_ready(1) = '1') then
|
||||
axis_1_aresetn_r <= axis_1_aresetn_r(1 to 31) & '1';
|
||||
else
|
||||
axis_1_aresetn_r <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
GEN_0:
|
||||
for i in 0 to 1 generate
|
||||
begin
|
||||
|
||||
|
||||
-- i_cdc_resetn : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => resetn(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_resetn(i)
|
||||
-- );
|
||||
|
||||
-- i_cdc_rx_enable : xpm_cdc_single
|
||||
-- generic map (
|
||||
-- DEST_SYNC_FF => 2,
|
||||
-- INIT_SYNC_FF => 0,
|
||||
-- SIM_ASSERT_CHK => 0,
|
||||
-- SRC_INPUT_REG => 0
|
||||
-- )
|
||||
-- port map (
|
||||
-- dest_out => rx_enable(i),
|
||||
-- dest_clk => clk(i),
|
||||
-- src_clk => '0',
|
||||
-- src_in => dig_iq_rx_enable(i)
|
||||
-- );
|
||||
|
||||
|
||||
process(clk(i))
|
||||
begin
|
||||
if (rising_edge(clk(i))) then
|
||||
tx_data_clear_r(i) <= tx_data_clear_in;
|
||||
tx_data_channel_reset_r(i) <= tx_data_channel_reset_r(i)(1 to 31) & '0';
|
||||
|
||||
if (tx_data_channel_reset_in = '1') then
|
||||
tx_data_channel_reset_r(i) <= (others => '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
i_dig_iq : DIG_IQ_HS_CUSTOM1X
|
||||
port map(
|
||||
INIT_CLK => clk_125_in,
|
||||
INTERFACE_RESET => interface_reset(i),
|
||||
IntL => '1',
|
||||
MGTREFCLK_N => qsfp_ref_clk_n(i),
|
||||
MGTREFCLK_P => qsfp_ref_clk_p(i),
|
||||
ModPrsL => '0',
|
||||
PADDR => p_addr,
|
||||
PCLK => clk_125_in,
|
||||
PENABLE => p_enable(i),
|
||||
PRESETn => clk_125_resetn_in,
|
||||
PSEL => '1',
|
||||
PWDATA => p_wdata,
|
||||
PWRITE => p_write,
|
||||
RXN => qsfp_rx_rxn(i),
|
||||
RXP => qsfp_rx_rxp(i),
|
||||
RX_DATA_READY => rx_data_ready(i),
|
||||
SCL_I => '0',
|
||||
SDA_I => '0',
|
||||
TX_DATA_CHANNEL_RESET => tx_data_channel_reset_r(i)(0),
|
||||
TX_DATA_CLEAR => tx_data_clear_r(i),
|
||||
TX_DATA_DAT => s_axis_tdata(i),--tx_data_r(i),
|
||||
TX_DATA_EN => s_axis_tvalid(i),--tx_data_en_r(i),
|
||||
DATA_CLK => clk(i),
|
||||
INTERFACE_READY => dig_iq_interface_ready(i),
|
||||
ModselL => open,
|
||||
PRDATA => p_rdata(i),
|
||||
PREADY => p_ready(i),
|
||||
RX_DATA_CHANNEL_RESET => open,
|
||||
RX_DATA_DAT => rx_data(i),
|
||||
RX_DATA_EN => rx_data_en(i),
|
||||
SCL_O => open,
|
||||
SCL_OE => open,
|
||||
SDA_O => open,
|
||||
SDA_OE => open,
|
||||
TXN => qsfp_tx_txn(i),
|
||||
TXP => qsfp_tx_txp(i),
|
||||
TX_DATA_READY => tx_data_ready(i)
|
||||
);
|
||||
|
||||
-- GEN_1:
|
||||
-- for j in 0 to 239 generate
|
||||
-- begin
|
||||
|
||||
-- i_FD_rx_data : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
-- end generate;
|
||||
|
||||
-- rx_data_en_int(i) <= rx_data_en(i) and rx_enable(i);
|
||||
|
||||
-- i_FD_rx_data_en : FD --FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => rx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => rx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- i_clock_converter : axis_clock_converter_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => resetn(i),
|
||||
-- m_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => clk(i),
|
||||
-- s_axis_tvalid => rx_data_en_r(i),
|
||||
-- s_axis_tready => cc_overflow_tready(i),
|
||||
-- s_axis_tdata => rx_data_r(i),
|
||||
-- m_axis_aclk => aclk_in,
|
||||
-- m_axis_tvalid => m_axis_tvalid_int(i),
|
||||
-- m_axis_tready => m_axis_tvalid_int(i),
|
||||
-- m_axis_tdata => m_axis_tdata_int(i)
|
||||
-- );
|
||||
|
||||
-- cc_overflow_int(i) <= not(cc_overflow_tready(i)) and rx_data_en_r(i);
|
||||
|
||||
-- i_FDRE_cc_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_cc_overflow(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- CE => cc_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => resetn(i) -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- R&S Documentation states:
|
||||
--
|
||||
-- TX_DATA_READY signal -- TX channel is receptive. After the deactivation of this signal,
|
||||
-- up to five more enabled data samples are allowed on the TX_DATA_DAT
|
||||
-- bus.
|
||||
-- Thus, we can pipeline the tx_data between the output of the FIFO and the R&S core.
|
||||
--
|
||||
-- ** PIPELINING IS CURRENTLY COMMENTED OUT **
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
-- i_tx_fifo : axis_data_fifo_0
|
||||
-- port map(
|
||||
-- s_axis_aresetn => aresetn_in,
|
||||
-- s_axis_aclk => aclk_in,
|
||||
-- s_axis_tvalid => s_axis_tvalid(i),
|
||||
-- s_axis_tready => s_axis_tready_int(i),
|
||||
-- s_axis_tdata => s_axis_tdata(i),
|
||||
-- m_axis_aclk => clk(i),
|
||||
-- m_axis_tvalid => tx_fifo_m_tvalid(i),
|
||||
-- m_axis_tready => tx_data_ready(i),
|
||||
-- m_axis_tdata => tx_fifo_m_tdata(i)
|
||||
-- );
|
||||
|
||||
--tx_fifo_overflow_int(i) <= not(s_axis_tready_int(i)) and s_axis_tvalid(i);
|
||||
|
||||
-- i_FDRE_tx_overflow : FDRE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => dig_iq_tx_overflow(i), -- 1-bit output: Data
|
||||
-- C => aclk_in, -- 1-bit input: Clock
|
||||
-- CE => tx_fifo_overflow_int(i), -- 1-bit input: Clock enable
|
||||
-- D => '1', -- 1-bit input: Data
|
||||
-- R => aresetn_in -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_int(i) <= tx_fifo_m_tvalid(i) and tx_data_ready(i);
|
||||
|
||||
--i_FD_tx_data_en : FD --RE
|
||||
--generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
--port map (
|
||||
-- Q => tx_data_en_r(i), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_data_en_int(i) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
|
||||
-- tx_data_en_r(i) <= tx_data_en_int(i);
|
||||
|
||||
--GEN_2:
|
||||
--for j in 0 to 239 generate
|
||||
-- begin
|
||||
--
|
||||
-- i_FD_tx_data : FD --RE
|
||||
-- generic map (
|
||||
-- INIT => '0' -- Initial value of register, '0', '1'
|
||||
-- )
|
||||
-- port map (
|
||||
-- Q => tx_data_r(i)(j), -- 1-bit output: Data
|
||||
-- C => clk(i), -- 1-bit input: Clock
|
||||
-- --CE => '1', -- 1-bit input: Clock enable
|
||||
-- D => tx_fifo_m_tdata(i)(j) -- 1-bit input: Data
|
||||
-- --R => '0' -- 1-bit input: Synchronous reset
|
||||
-- );
|
||||
--
|
||||
-- end generate;
|
||||
|
||||
-- tx_data_r(i) <= tx_fifo_m_tdata(i);
|
||||
|
||||
end generate;
|
||||
|
||||
-----------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
end structural;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,90 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "FPGA_REVISION_DATE"
|
||||
ipgui::add_param $IPINST -name "MINOR_REV"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to update FPGA_REVISION_DATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_REVISION_DATE { PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to validate FPGA_REVISION_DATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to update MINOR_REV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MINOR_REV { PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to validate MINOR_REV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_REVISION_DATE { MODELPARAM_VALUE.FPGA_REVISION_DATE PARAM_VALUE.FPGA_REVISION_DATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_REVISION_DATE}] ${MODELPARAM_VALUE.FPGA_REVISION_DATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MINOR_REV { MODELPARAM_VALUE.MINOR_REV PARAM_VALUE.MINOR_REV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MINOR_REV}] ${MODELPARAM_VALUE.MINOR_REV}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user