moving repo from git to local repo
This commit is contained in:
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|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>SCOPED_TO_REF_iq_512b_to_240b</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_3d51e471</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_axis_dwidth_converter_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
<spirit:userFileType>CELL_NAME_dig_iq_encoder_0</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/iq_512b_to_240b.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_dwidth_converter" xilinx:version="1.1">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="user" xilinx:name="dig_iq_encoder" xilinx:version="1.0">
|
||||
<xilinx:mode xilinx:name="create_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/iq_512b_to_240b_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>iq_512b_to_240b</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">iq_512b_to_240b_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>iq_512b_to_240b</xilinx:displayName>
|
||||
<xilinx:definitionSource>IPI</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-24T16:38:16Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5a5f56fc"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2a3456f"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c875ab87"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ca8f49ff"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component iq_512b_to_240b_dig_iq_encoder_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component iq_512b_to_240b_dig_iq_encoder_0_0;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Jan 24 11:37:59 2024
|
||||
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
|
||||
--Command : generate_target iq_512b_to_240b.bd
|
||||
--Design : iq_512b_to_240b
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity iq_512b_to_240b is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
|
||||
end iq_512b_to_240b;
|
||||
|
||||
architecture STRUCTURE of iq_512b_to_240b is
|
||||
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
component dig_iq_encoder is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC
|
||||
);
|
||||
end component dig_iq_encoder;
|
||||
signal aclk_1 : STD_LOGIC;
|
||||
signal aresetn_1 : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
|
||||
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
|
||||
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
|
||||
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
|
||||
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
signal s_axis_1_TREADY : STD_LOGIC;
|
||||
signal s_axis_1_TVALID : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
aclk_1 <= aclk;
|
||||
aresetn_1 <= aresetn;
|
||||
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
|
||||
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
|
||||
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
|
||||
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
|
||||
s_axis_1_TVALID <= s_axis_tvalid;
|
||||
s_axis_tready <= s_axis_1_TREADY;
|
||||
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
|
||||
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
|
||||
s_axis_tready => s_axis_1_TREADY,
|
||||
s_axis_tvalid => s_axis_1_TVALID
|
||||
);
|
||||
dig_iq_encoder_0: component dig_iq_encoder
|
||||
port map (
|
||||
aclk => aclk_1,
|
||||
aresetn => aresetn_1,
|
||||
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
|
||||
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
|
||||
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
|
||||
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
|
||||
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
|
||||
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1169
File diff suppressed because it is too large
Load Diff
+336
@@ -0,0 +1,336 @@
|
||||
// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
// f_clogb2
|
||||
// f_gcd
|
||||
// f_lcm
|
||||
// f_get_tdata_indx
|
||||
// f_get_tstrb_indx
|
||||
// f_get_tkeep_indx
|
||||
// f_get_tlast_indx
|
||||
// f_get_tid_indx
|
||||
// f_get_tdest_indx
|
||||
// f_get_tuser_indx
|
||||
// f_payload_width
|
||||
// Tasks:
|
||||
// t_display_tdata_error
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Define Signal Set indices
|
||||
localparam G_INDX_SS_TREADY = 0;
|
||||
localparam G_INDX_SS_TDATA = 1;
|
||||
localparam G_INDX_SS_TSTRB = 2;
|
||||
localparam G_INDX_SS_TKEEP = 3;
|
||||
localparam G_INDX_SS_TLAST = 4;
|
||||
localparam G_INDX_SS_TID = 5;
|
||||
localparam G_INDX_SS_TDEST = 6;
|
||||
localparam G_INDX_SS_TUSER = 7;
|
||||
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
|
||||
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
|
||||
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
|
||||
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
|
||||
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
|
||||
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
|
||||
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
|
||||
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
|
||||
|
||||
// Task DRC error levels
|
||||
localparam G_TASK_SEVERITY_ERR = 2;
|
||||
localparam G_TASK_SEVERITY_WARNING = 1;
|
||||
localparam G_TASK_SEVERITY_INFO = 0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Functions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
// Calculates the Greatest Common Divisor between two integers using the
|
||||
// euclidean algorithm.
|
||||
function automatic integer f_gcd (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
if (a == 0) begin
|
||||
f_gcd = b;
|
||||
end else if (b == 0) begin
|
||||
f_gcd = a;
|
||||
end else if (a > b) begin
|
||||
f_gcd = f_gcd(a % b, b);
|
||||
end else begin
|
||||
f_gcd = f_gcd(a, b % a);
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Calculates the Lowest Common Denominator between two integers
|
||||
function integer f_lcm (
|
||||
input integer a,
|
||||
input integer b
|
||||
);
|
||||
begin : main
|
||||
f_lcm = ( a / f_gcd(a, b)) * b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdata_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
f_get_tdata_indx = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tstrb_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
|
||||
// If TDATA exists, then add its width to its base to get the tstrb index
|
||||
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tkeep_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tlast_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tid_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tdest_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
|
||||
// signal is not enabled.
|
||||
function integer f_get_tuser_indx (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// Payload is the sum of all the AXIS signals present except for
|
||||
// TREADY/TVALID
|
||||
function integer f_payload_width (
|
||||
input integer DAW, // TDATA Width
|
||||
input integer IDW, // TID Width
|
||||
input integer DEW, // TDEST Width
|
||||
input integer USW, // TUSER Width
|
||||
input [31:0] SST // Signal Set
|
||||
);
|
||||
begin : main
|
||||
integer cur_indx;
|
||||
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
|
||||
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
|
||||
// Ensure that the return value is never less than 1
|
||||
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
|
||||
end
|
||||
endfunction
|
||||
|
||||
task t_check_tdata_width(
|
||||
input integer data_width,
|
||||
input [8*80-1:0] var_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tdata_width
|
||||
if (data_width%8 != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
|
||||
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
|
||||
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
|
||||
$display(" information.");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task t_check_tuser_width(
|
||||
input integer tuser_width,
|
||||
input [8*80-1:0] tuser_name,
|
||||
input integer tdata_width,
|
||||
input [8*80-1:0] tdata_name,
|
||||
input [8*80-1:0] inst_name,
|
||||
input integer severity_lvl,
|
||||
output integer ret_val
|
||||
);
|
||||
// Severity levels:
|
||||
// 0 = INFO
|
||||
// 1 = WARNING
|
||||
// 2 = ERROR
|
||||
begin : t_check_tuser_width
|
||||
integer tdata_bytes;
|
||||
tdata_bytes = tdata_width/8;
|
||||
if ((tuser_width%tdata_bytes) != 0) begin
|
||||
// 000 1 2 3 4 5 6 7 8
|
||||
// 012 0 0 0 0 0 0 0 0
|
||||
if (severity_lvl >= 2) begin
|
||||
$display("ERROR: %m::%s", inst_name);
|
||||
end else if (severity_lvl == 1) begin
|
||||
$display("WARNING: %m::%s", inst_name);
|
||||
end else begin
|
||||
$display("INFO: %m::%s", inst_name);
|
||||
end
|
||||
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
|
||||
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
|
||||
$display(" TUSER width in this module is only defined when the TUSER is the");
|
||||
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
|
||||
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
|
||||
ret_val = 1;
|
||||
end else begin
|
||||
ret_val = 0;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
+1318
File diff suppressed because it is too large
Load Diff
+2998
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
+152
@@ -0,0 +1,152 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_axis_dwidth_converter_0_0",
|
||||
"component_reference": "xilinx.com:ip:axis_dwidth_converter:1.1",
|
||||
"ip_revision": "28",
|
||||
"gen_directory": "./",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"S_TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_TDATA_NUM_BYTES": [ { "value": "28", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MI_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_axis_dwidth_converter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_S_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TDATA_WIDTH": [ { "value": "224", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_M_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "28" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "./" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "223", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"RSTIF": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLKIF": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "195312500", "value_src": "user_prop", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1403
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 5.120 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+99512
File diff suppressed because it is too large
Load Diff
+130586
File diff suppressed because it is too large
Load Diff
+30
@@ -0,0 +1,30 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
// Date : Fri Mar 28 20:50:13 2025
|
||||
// Host : Ubuntu-Dev running 64-bit Ubuntu 22.04.5 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top iq_512b_to_240b_axis_dwidth_converter_0_0 -prefix
|
||||
// iq_512b_to_240b_axis_dwidth_converter_0_0_ iq_512b_to_240b_axis_dwidth_converter_0_0_stub.v
|
||||
// Design : iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xczu19eg-ffvc1760-2-i
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2" *)
|
||||
module iq_512b_to_240b_axis_dwidth_converter_0_0(aclk, aresetn, s_axis_tvalid, s_axis_tready,
|
||||
s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[511:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[223:0]" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [511:0]s_axis_tdata;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [223:0]m_axis_tdata;
|
||||
endmodule
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
-- Date : Fri Mar 28 20:50:13 2025
|
||||
-- Host : Ubuntu-Dev running 64-bit Ubuntu 22.04.5 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top iq_512b_to_240b_axis_dwidth_converter_0_0 -prefix
|
||||
-- iq_512b_to_240b_axis_dwidth_converter_0_0_ iq_512b_to_240b_axis_dwidth_converter_0_0_stub.vhdl
|
||||
-- Design : iq_512b_to_240b_axis_dwidth_converter_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xczu19eg-ffvc1760-2-i
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axis_tvalid : in STD_LOGIC;
|
||||
s_axis_tready : out STD_LOGIC;
|
||||
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
|
||||
m_axis_tvalid : out STD_LOGIC;
|
||||
m_axis_tready : in STD_LOGIC;
|
||||
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
|
||||
);
|
||||
|
||||
end iq_512b_to_240b_axis_dwidth_converter_0_0;
|
||||
|
||||
architecture stub of iq_512b_to_240b_axis_dwidth_converter_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[511:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[223:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2";
|
||||
begin
|
||||
end;
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axis_dwidth_converter_v1_1_28_axis_dwidth_converter,Vivado 2023.2" *)
|
||||
(* CHECK_LICENSE_TYPE = "iq_512b_to_240b_axis_dwidth_converter_0_0,axis_dwidth_converter_v1_1_28_axis_dwidth_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "iq_512b_to_240b_axis_dwidth_converter_0_0,axis_dwidth_converter_v1_1_28_axis_dwidth_converter,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_dwidth_converter,x_ipVersion=1.1,x_ipCoreRevision=28,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_S_AXIS_TDATA_WIDTH=512,C_M_AXIS_TDATA_WIDTH=224,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_S_AXIS_TUSER_WIDTH=1,C_M_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module iq_512b_to_240b_axis_dwidth_converter_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axis_tvalid,
|
||||
s_axis_tready,
|
||||
s_axis_tdata,
|
||||
m_axis_tvalid,
|
||||
m_axis_tready,
|
||||
m_axis_tdata
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire s_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire s_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [511 : 0] s_axis_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire m_axis_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire m_axis_tready;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 28, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [223 : 0] m_axis_tdata;
|
||||
|
||||
axis_dwidth_converter_v1_1_28_axis_dwidth_converter #(
|
||||
.C_FAMILY("zynquplus"),
|
||||
.C_S_AXIS_TDATA_WIDTH(512),
|
||||
.C_M_AXIS_TDATA_WIDTH(224),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_S_AXIS_TUSER_WIDTH(1),
|
||||
.C_M_AXIS_TUSER_WIDTH(1),
|
||||
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.aclken(1'H1),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tdata(s_axis_tdata),
|
||||
.s_axis_tstrb(64'HFFFFFFFFFFFFFFFF),
|
||||
.s_axis_tkeep(64'HFFFFFFFFFFFFFFFF),
|
||||
.s_axis_tlast(1'H1),
|
||||
.s_axis_tid(1'H0),
|
||||
.s_axis_tdest(1'H0),
|
||||
.s_axis_tuser(1'H0),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(m_axis_tready),
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,88 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_encoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_encoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(223 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
s_axis_tready : out std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(239 downto 0);
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tready : in std_logic
|
||||
);
|
||||
end dig_iq_encoder;
|
||||
|
||||
architecture imp of dig_iq_encoder is
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= s_axis_tvalid;
|
||||
s_axis_tready <= m_axis_tready;
|
||||
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(16) <= '0';
|
||||
m_axis_tdata(32 downto 17 ) <= s_axis_tdata(31 downto 16 ); -- IMAG[0]
|
||||
m_axis_tdata(33) <= '0';
|
||||
m_axis_tdata(49 downto 34 ) <= s_axis_tdata(47 downto 32 ); -- REAL[1]
|
||||
m_axis_tdata(50) <= '0';
|
||||
m_axis_tdata(66 downto 51 ) <= s_axis_tdata(63 downto 48 ); -- IMAG[1]
|
||||
m_axis_tdata(67) <= '0';
|
||||
m_axis_tdata(83 downto 68 ) <= s_axis_tdata(79 downto 64 ); -- REAL[2]
|
||||
m_axis_tdata(84) <= '0';
|
||||
m_axis_tdata(100 downto 85 ) <= s_axis_tdata(95 downto 80 ); -- IMAG[2]
|
||||
m_axis_tdata(101) <= '0';
|
||||
m_axis_tdata(117 downto 102 ) <= s_axis_tdata(111 downto 96 ); -- REAL[3]
|
||||
m_axis_tdata(118) <= '0';
|
||||
m_axis_tdata(134 downto 119 ) <= s_axis_tdata(127 downto 112 ); -- IMAG[3]
|
||||
m_axis_tdata(135) <= '0';
|
||||
m_axis_tdata(151 downto 136 ) <= s_axis_tdata(143 downto 128 ); -- REAL[4]
|
||||
m_axis_tdata(152) <= '0';
|
||||
m_axis_tdata(168 downto 153 ) <= s_axis_tdata(159 downto 144 ); -- IMAG[4]
|
||||
m_axis_tdata(169) <= '0';
|
||||
m_axis_tdata(185 downto 170 ) <= s_axis_tdata(175 downto 160 ); -- REAL[5]
|
||||
m_axis_tdata(186) <= '0';
|
||||
m_axis_tdata(202 downto 187 ) <= s_axis_tdata(191 downto 176 ); -- IMAG[5]
|
||||
m_axis_tdata(203) <= '0';
|
||||
m_axis_tdata(219 downto 204 ) <= s_axis_tdata(207 downto 192 ); -- REAL[6]
|
||||
m_axis_tdata(220) <= '0';
|
||||
m_axis_tdata(236 downto 221 ) <= s_axis_tdata(223 downto 208 ); -- IMAG[6]
|
||||
m_axis_tdata(139 downto 237 ) <= (others => '0');
|
||||
|
||||
|
||||
|
||||
end imp;
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "iq_512b_to_240b_dig_iq_encoder_0_0",
|
||||
"component_reference": "xilinx.com:user:dig_iq_encoder:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "iq_512b_to_240b_dig_iq_encoder_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "virtexuplusHBM" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "xilinx.com:vcu128:part0:1.0" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xcvu37p" } ],
|
||||
"PACKAGE": [ { "value": "fsvh2892" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2L" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "E" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "223", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "239", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "30", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "28", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user