287 lines
10 KiB
VHDL
287 lines
10 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:53:22 03/24/2017
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-- Design Name:
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-- Module Name:
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-- Project Name: xem7350
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: dac_interface
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.STD_LOGIC_arith.ALL;
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USE IEEE.STD_LOGIC_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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entity tb_cap_plybk is
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end tb_cap_plybk;
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architecture behavior of tb_cap_plybk is
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constant C_M_AXI_DATA_WIDTH : integer := 32;
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constant C_M_AXI_ADDR_WIDTH : integer := 32;
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-- Clock period definitions
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constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
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constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
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constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
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constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
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constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
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constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
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signal clk_125 : std_logic := '0';
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signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0');
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signal clk_125_reset : std_logic;
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signal clk_250 : std_logic := '0';
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signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0');
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signal clk_250_areset : std_logic;
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signal tx_device_clk_1 : std_logic := '0';
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signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
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signal tx_device_clk_aresetn : std_logic;
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signal rx_device_clk_1 : std_logic := '0';
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signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
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signal rx_device_clk_aresetn : std_logic;
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signal rx_device_clk_areset : std_logic;
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signal qsfp4_playback_aclk : std_logic := '0';
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signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
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signal qsfp4_playback_aresetn : std_logic;
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signal qsfp1_capture_aclk : std_logic;
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signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
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signal qsfp1_capture_aresetn : std_logic;
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--
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signal tick_1ms : std_logic;
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signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0');
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signal adc_rx_tvalid_128b : std_logic := '0';
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signal adc_rx_tready_128b : std_logic;
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signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0);
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signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0);
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signal qsfp4_playback_tvalid_240b : std_logic;
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signal qsfp4_playback_tready_240b : std_logic := '1';
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signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0);
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signal qsfp1_capture_tvalid_240b : std_logic;
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signal tx_tdata_128b : std_logic_vector(127 downto 0);
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signal tx_tvalid_128b : std_logic;
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signal tx_tready_128b : std_logic := '1';
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signal qsfp1_capture_rx_data_ready : std_logic;
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signal playback_data_path_enable_n : std_logic := '1';
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signal adc_rx_tvalid_128b_ena : std_logic;
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begin
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clk_125 <= not clk_125 after CLK_125_PERIOD/2;
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clk_250 <= not clk_250 after CLK_250_PERIOD/2;
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tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2;
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rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2;
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qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2;
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-- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2;
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--
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process(clk_125)
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begin
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if (rising_edge(clk_125)) then
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clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
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end if;
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end process;
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process(clk_125)
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begin
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if (rising_edge(clk_125)) then
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clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
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end if;
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end process;
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clk_125_reset <= not clk_125_aresetn(0);
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--
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process(clk_250)
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begin
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if (rising_edge(clk_250)) then
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clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1';
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end if;
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end process;
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clk_250_areset <= not clk_250_aresetn(0);
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--
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process(tx_device_clk_1)
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begin
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if (rising_edge(tx_device_clk_1)) then
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tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1';
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end if;
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end process;
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tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0);
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--
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process(rx_device_clk_1)
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begin
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if (rising_edge(rx_device_clk_1)) then
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rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1';
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end if;
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end process;
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rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0);
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--
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process(qsfp4_playback_aclk)
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begin
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if (rising_edge(qsfp4_playback_aclk)) then
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qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1';
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end if;
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end process;
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qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0);
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--
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process(rx_device_clk_1)
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begin
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if (rising_edge(rx_device_clk_1)) then
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adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008";
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end if;
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end process;
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--
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process(qsfp1_capture_aclk)
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begin
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if (rising_edge(qsfp1_capture_aclk)) then
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qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1';
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end if;
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end process;
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qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0);
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adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready;
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i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc
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port map (
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rx_device_clk_in => rx_device_clk_1,
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rx_device_clk_aresetn_in => rx_device_clk_aresetn,
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rx_tdata_128b_in => adc_rx_tdata_128b,
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rx_tvalid_128b_in => adc_rx_tvalid_128b_ena,
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rx_tready_128b_out => adc_rx_tready_128b,
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rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt,
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rx_tvalid_128b_en_cnt_out => open,
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playback_data_path_enable_n_in => playback_data_path_enable_n,
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qsfp4_playback_aclk_in => qsfp4_playback_aclk,
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qsfp4_playback_aresetn_in => qsfp4_playback_aresetn,
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qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b,
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qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b,
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qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b,
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qsfp4_playback_tvalid_240b_cnt_out => open,
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cnt_reset_in => '0'
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);
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--///////////////////////////////
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qsfp1_capture_aclk <= qsfp4_playback_aclk; --
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qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; --
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qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; --
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--///////////////////////////////
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--// ****>>>> FROM QSFP1 CAPTURE INTERFACE
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i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc
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port map (
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qsfp1_capture_aclk_in => qsfp1_capture_aclk,
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qsfp1_capture_aresetn_in => qsfp1_capture_aresetn,
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qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b,
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qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b,
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qsfp1_capture_tvalid_240b_cnt_out => open,
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qsfp1_capture_fifo_aempty_512b_cnt_out => open,
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qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open,
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qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready,
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qsfp1_capture_rx_data_ready_cnt_out => open,
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tx_device_clk_in => tx_device_clk_1,
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tx_device_clk_aresetn_in => tx_device_clk_aresetn,
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tx_tdata_128b_out => tx_tdata_128b, -- out
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tx_tvalid_128b_out => tx_tvalid_128b, -- out
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tx_tready_128b_in => tx_tready_128b, -- in
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tx_tvalid_128b_cnt_out => open,
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cnt_reset_in => '0'
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);
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-- Stimulus process
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stim_proc: process
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begin
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wait until rx_device_clk_aresetn = '1';
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wait for 200 ns;
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wait until rising_edge(rx_device_clk_1);
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adc_rx_tvalid_128b <= '1';
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wait for 500 ns;
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wait until rising_edge(rx_device_clk_1);
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playback_data_path_enable_n <= '0';
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wait for 5 us;
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wait until rising_edge(qsfp4_playback_aclk);
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playback_data_path_enable_n <='0';
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wait for 5 us;
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wait until rising_edge(qsfp4_playback_aclk);
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qsfp4_playback_tready_240b <='1';
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wait; -- wait here forever
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end process;
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end;
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