317 lines
12 KiB
VHDL
317 lines
12 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:53:22 03/24/2017
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-- Design Name:
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-- Module Name:
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-- Project Name: xem7350
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: dac_interface
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.STD_LOGIC_arith.ALL;
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USE IEEE.STD_LOGIC_unsigned.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity dds_wrapper_tb is
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end dds_wrapper_tb;
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architecture behavior of dds_wrapper_tb is
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-- Clock period definitions
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constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
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constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
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constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz
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constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
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constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
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constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
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constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
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signal clk_100 : std_logic := '0';
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signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0');
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signal clk_250 : std_logic := '0';
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signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0');
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signal m_axis_tready_r : std_logic := '0';
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signal m_axis_tdata : std_logic_vector(127 downto 0);
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signal m_axis_tvalid : std_logic;
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signal m_axis_tready : std_logic;
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signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0);
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signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic;
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signal m_axis_tdata_1 : std_logic_vector(127 downto 0);
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signal m_axis_tvalid_1 : std_logic;
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signal m_axis_tready_1 : std_logic;
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signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0');
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signal dac_holdoff_r : std_logic := '1';
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signal chan1_i : std_logic_vector(15 downto 0);
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signal chan1_q : std_logic_vector(15 downto 0);
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signal chan2_i : std_logic_vector(15 downto 0);
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signal chan2_q : std_logic_vector(15 downto 0);
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signal chan3_i : std_logic_vector(15 downto 0);
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signal chan3_q : std_logic_vector(15 downto 0);
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signal chan4_i : std_logic_vector(15 downto 0);
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signal chan4_q : std_logic_vector(15 downto 0);
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signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0');
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signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0');
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signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0');
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signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0');
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signal cnt_reset : std_logic := '0';
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begin
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clk_100 <= not clk_100 after CLK_100_PERIOD/2;
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clk_250 <= not clk_250 after CLK_250_PERIOD/2;
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--
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process(clk_100)
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begin
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if (rising_edge(clk_100)) then
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clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1';
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end if;
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end process;
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--
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process(clk_250)
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begin
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if (rising_edge(clk_250)) then
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clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1';
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end if;
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end process;
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process (clk_100)
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begin
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if rising_edge(clk_100) then
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if (cmd_send_i(0) = '1') then
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cmd_send_0_r <= "111";
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else
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cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0';
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end if;
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if (cmd_send_i(1) = '1') then
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cmd_send_1_r <= "111";
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else
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cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0';
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end if;
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if (cmd_send_i(2) = '1') then
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cmd_send_2_r <= "111";
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else
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cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0';
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end if;
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if (cmd_send_i(3) = '1') then
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cmd_send_3_r <= "111";
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else
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cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0';
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end if;
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end if;
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end process;
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i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
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port map (
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s_axi_aclk_in => clk_100,
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s_axi_aresetn_in => clk_100_aresetn(0),
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cmd_idx_in => "000",
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dac_holdoff_in => dac_holdoff_r,
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dds_chan_en_in => "1111",
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cmd_send_0_in => cmd_send_0_r(0),
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scale_0_in => x"8000",
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dds_phase_inc_dwell_time_0_in => x"00000000",
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dds_phase_inc_step_size_0_in => x"0000D6BF",
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idle_samples_0_in => x"00000000",
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dds_samples_0_in => x"000004E2",
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phase_inc_0_in => x"010624DD",
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phase_off_0_in => x"00000000",
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swap_sf_0_in => x"00008000",
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cmd_send_1_in => cmd_send_1_r(0),
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scale_1_in => x"8000",
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dds_phase_inc_dwell_time_1_in => x"00000000",
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dds_phase_inc_step_size_1_in => x"0000D6BF",
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idle_samples_1_in => x"00000000",
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dds_samples_1_in => x"000014E2", --x"000004E2",
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phase_inc_1_in => x"010624DD",
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phase_off_1_in => x"00000000",
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swap_sf_1_in => x"00008000",
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cmd_send_2_in => cmd_send_2_r(0),
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scale_2_in => x"8000",
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dds_phase_inc_dwell_time_2_in => x"00000000",
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dds_phase_inc_step_size_2_in => x"0000D6BF",
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idle_samples_2_in => x"00000000",
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dds_samples_2_in => x"000004E2",
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phase_inc_2_in => x"010624DD",
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phase_off_2_in => x"00000000",
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swap_sf_2_in => x"00008000",
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cmd_send_3_in => cmd_send_3_r(0),
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scale_3_in => x"8000",
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dds_phase_inc_dwell_time_3_in => x"00000000",
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dds_phase_inc_step_size_3_in => x"0000D6BF",
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idle_samples_3_in => x"00000000",
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dds_samples_3_in => x"000004E2",
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phase_inc_3_in => x"010624DD",
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phase_off_3_in => x"00000000",
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swap_sf_3_in => x"00008000",
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m_axis_aclk_in => clk_250,
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m_axis_aresetn_in => clk_250_aresetn(0),
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m_axis_tdata_out => m_axis_tdata,
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m_axis_tvalid_out => m_axis_tvalid,
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m_axis_tready_in => m_axis_tready,
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cnt_reset_in => cnt_reset,
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m_axis_tvalid_cnt_out => open,
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dds_pulse_data_cnt_out => open
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);
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-- big FIFO before JESD TX PORT
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i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128
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port map (
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s_axis_aclk => clk_250, -- in
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s_axis_aresetn => clk_250_aresetn(0), -- in
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s_axis_tdata => m_axis_tdata, -- in
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s_axis_tvalid => m_axis_tvalid, -- in
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s_axis_tready => m_axis_tready, -- out
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m_axis_tdata => m_axis_tdata_1, -- out
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m_axis_tvalid => m_axis_tvalid_1, -- out
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m_axis_tready => m_axis_tready_1 -- in
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);
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-- big FIFO before JESD TX PORT
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i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128
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port map (
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s_axis_aclk => clk_250, -- in
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s_axis_aresetn => clk_250_aresetn(0), -- in
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s_axis_tdata => m_axis_tdata_1, -- in
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s_axis_tvalid => m_axis_tvalid_1, -- in
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s_axis_tready => m_axis_tready_1, -- out
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m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out
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m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out
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m_axis_tready => m_axis_tready_r -- in
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);
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chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0);
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chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16);
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chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32);
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chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48);
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chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64);
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chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80);
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chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96);
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chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112);
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-- Stimulus process
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stim_proc: process
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begin
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wait until clk_100_aresetn(0) = '1';
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-- wait for 24 us;
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wait until rising_edge(clk_250);
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m_axis_tready_r <= '1';
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wait for 1 us;
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wait until rising_edge(clk_100);
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cmd_send_i(0) <= '1';
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wait for 200 ns;
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wait until rising_edge(clk_100);
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cmd_send_i(0) <= '0';
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wait for 1 us;
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wait until rising_edge(clk_100);
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cmd_send_i(1) <= '1';
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wait for 200 ns;
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wait until rising_edge(clk_100);
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cmd_send_i(1) <= '0';
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wait for 1 us;
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wait until rising_edge(clk_100);
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cmd_send_i(2) <= '1';
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wait for 200 ns;
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wait until rising_edge(clk_100);
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cmd_send_i(2) <= '0';
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wait for 1 us;
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wait until rising_edge(clk_100);
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cmd_send_i(3) <= '1';
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wait for 200 ns;
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wait until rising_edge(clk_100);
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cmd_send_i(3) <= '0';
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wait for 1 us;
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wait until rising_edge(clk_100);
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dac_holdoff_r <= '0';
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wait for 8 us;
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cnt_reset <= '1';
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wait until rising_edge(clk_100);
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cnt_reset <= '0';
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-- m_axis_tready_r <= '0';
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-- wait until rising_edge(clk_250);
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-- m_axis_tready_r <= '1';
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-- wait until rising_edge(clk_250);
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-- m_axis_tready_r <= '0';
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-- wait until rising_edge(clk_250);
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-- m_axis_tready_r <= '1';
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wait until rising_edge(clk_100);
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wait; -- wait here forever
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end process;
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end;
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